TWI519881B - Array substrate and method of fabricating the same - Google Patents

Description

Array substrate and method of manufacturing same

The present disclosure relates to an array substrate, and in particular to an array substrate and a method of fabricating the same, the array substrate comprising a thin film transistor having an oxide semiconductor layer.

With the rapid development of information technology, display devices for displaying a large amount of information have been rapidly developed. More particularly, flat panel display (FPD) devices having a thin profile, light weight, and low power consumption, such as organic electroluminescent display (OLED) devices and liquid crystal display (LCD) devices, have been actively advanced and are replacing cathode ray tubes (CRT). ).

In a liquid crystal display device, active matrix type liquid crystal display devices including thin film transistors for controlling on/off of respective pixels have been subjected to their high resolution, color expression ability, and superiority in displaying moving images. Widely used.

In addition, organic electroluminescent display devices have recently attracted attention due to the following advantages: organic electroluminescent display devices have high luminance and low driving voltage; since they self-illuminate, organic electroluminescent display devices have excellent contrast and are already ultra-thin Thickness; organic electroluminescent display device has a response time of a few microseconds, and has the advantage of displaying moving images; the organic electroluminescent display device has a wide viewing angle and is stable at low temperatures; since the organic electroluminescent display device transmits a low voltage of 5V to 15V through direct current (DC) The voltage is driven, so that it is easy to design and manufacture the driving circuit; and since only the deposition and packaging steps are required, the manufacturing process of the organic electroluminescence display device is simple. Among organic electroluminescent display devices, active matrix type display devices are also widely used because of low power consumption, high resolution, and large size.

The active matrix type liquid crystal display device and the active matrix type organic electroluminescence display device each include an array substrate having thin film transistors that control their respective pixel on/off as switching elements.

The "figure 1" is a cross-sectional view of an array substrate of a liquid crystal display device or an organic electroluminescence display device according to one of the prior art. "Fig. 1" shows a cross-sectional view of a pixel region having a thin film transistor in an array substrate.

In the "Fig. 1", a gate line (not shown) and a data line (not shown) are formed on a substrate 11 and intersect each other to define a pixel region P. A gate 15 is formed in a switching region TrA of the pixel region P. A gate insulating layer 18 is formed on the gate electrode 15, and a semiconductor layer 28 including an active layer 22 of intrinsic amorphous germanium and an ohmic contact layer 26 doped with amorphous germanium is formed on the gate insulating layer 18. Source and drain electrodes 36 and 38 are formed on ohmic contact layer 26. Source and drain electrodes 36 and 38 correspond to gates 15 and are spaced apart from one another. Shun The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are formed in the switching region TrA, constitute a thin film transistor Tr.

A passivation layer 42 is formed over the substrate 11 over the source and drain electrodes 36 and 38 and the exposed active layer 22. The passivation layer 42 has a drain contact hole 45 that exposes a portion of the drain 38. A pixel electrode 50 is independently formed in each of the pixel regions P on the passivation layer 42. The pixel electrode 50 is in contact with the drain electrode 38 through the drain contact hole 45.

Here, although not shown, a semiconductor pattern is formed under the data line. The semiconductor pattern has a two-layer structure having a first pattern of the same material as the ohmic contact layer 26 and a second pattern of the same material as the active layer 22.

In the semiconductor layer 28 formed in the switching region TrA of the conventional technology array substrate, the active layer 22 of the intrinsic amorphous germanium has different thicknesses depending on the deposition. That is, a portion of the active layer 22 exposed by selectively removing the ohmic contact layer 26 has a first thickness t1 and a portion of the active layer 22 below the ohmic contact layer 26 has a second thickness t2, the second thickness T2 is thicker than the first thickness t1. The different thicknesses of the different portions of the active layer 22 are produced by a manufacturing method, and this reduces the output characteristics of the thin film transistor Tr and negatively affects the characteristics of the thin film transistor Tr because the source and the drains 36 and 38 become thin film The active layer 22 of one channel of the crystal Tr has a reduced thickness.

In order to solve this problem, a single layer oxide has been developed. A thin film transistor of a semiconductor layer which does not require an ohmic contact layer of the prior art and uses an oxide semiconductor layer as an active layer.

"Fig. 2" is a plan view of a portion of a pixel region of an array substrate including a thin film transistor having such an oxide semiconductor layer according to the prior art, and "Fig. 3" is along "2nd" A cross-sectional view of the line III-III of the figure.

In "Fig. 2" and "Fig. 3", the oxide semiconductor layer 63 is formed on each of the pixel regions on a transparent insulating layer such as the substrate 61. The oxide semiconductor layer 63 has a bar shape. A gate 69 is formed corresponding to a central portion of the oxide semiconductor layer 63, and a gate insulating layer 66 is disposed between the oxide semiconductor layer 63 and the gate 69.

At the same time, the oxide semiconductor layer 63 includes an active region 63a and source and drain regions 63b and 63c. The active region 63a corresponds to the gate 69 and has a half conductivity. The source and drain regions 63b and 63c are exposed on both sides of the gate insulating layer 66 and have different contact properties from the active region 63a.

A gate line 68 is also formed on the gate insulating layer 66. Gate line 68 is coupled to gate 69 and extends in a first direction. Here, the gate 69 extends from the gate line 68 along a second direction.

An interlayer insulating layer 72 of an inorganic insulating material is formed on the gate 69 and the gate insulating layer 66. The interlayer insulating layer 72 includes first and second semiconductor contact holes 74a and 74b on both sides of the gate 69, and the first and second semiconductor connections The contact holes 74a and 74b expose the source and drain regions 63b and 63c of the oxide semiconductor layer 63, respectively. The first and second semiconductor contact holes 74a and 74b are formed in the same pixel region and arranged in a line along the first direction, wherein the first direction is a pixel shorter than a length of the pixel region P A direction of a width of the region P.

Source and drain electrodes 76 and 77 are formed on the interlayer insulating layer 72. Source and drain electrodes 76 and 77 are in contact with source and drain regions 63b and 63c via first and second semiconductor contact holes 74a and 74b, respectively.

A data line 75 is also formed on the interlayer insulating layer 72 connected to the source 76. The data line 75 extends in a second direction and intersects the gate line 68 to thereby define a pixel region P. The source 76 extends from the data line 75 along the first direction.

A passivation layer 78 is formed on the source and drain electrodes 76 and 77, and a pixel electrode 85 is formed on the passivation layer in the pixel region P. The pixel electrode 85 is in contact with the drain electrode 77 through a drain contact hole 80 of the passivation layer 78.

In the array substrate including the thin film transistor Tr in "Fig. 2" and "Fig. 3" having the oxide semiconductor layer 63, the oxide semiconductor layer 63 has a single layer structure without an ohmic contact layer. Therefore, the oxide semiconductor layer 63 is not exposed to the etching gas used in the dry etching process of the ohmic contact layer 26 forming the "Fig. 1". Therefore, the output characteristics of the thin film transistor Tr are prevented from being lowered and minimized.

At the same time, recently, products with sufficient high definition, such as a TV with 1080 by 1920 high definition, have been the first choice. A high definition display is also required compared to a relatively small personal portable device such as a laptop or a cellular telephone.

Although a television has a high definition of 1080 by 1920, the television has a relatively large pixel size. However, a personal portable device such as a laptop or a cellular phone has a relatively small pixel size for high definition because of its display size of a few inches.

The array substrate shown in "Fig. 2" can be applied to a television. Here, the pixel region P has a relatively large size such that the oxide thin film transistor Tr having the first and second semiconductor contact holes 74a and 74b can be formed in one pixel region P, wherein the first and second The semiconductor contact holes 74a and 74b are disposed in a direction parallel to a width of the pixel region P.

However, when the array substrate shown in "Fig. 2" is applied to a device having a relatively small display size such as a laptop or a cellular phone, since the width of the pixel region is relatively narrow, along the pixel An oxide thin film transistor having two contact holes in one width direction of the region may not be formed in one pixel region.

That is, the oxide thin film transistor having a coplanar structure includes the first and second semiconductor contact holes exposing the source and the drain region of the oxide semiconductor layer, and the semiconductor contact hole needs to be in contact with the oxide semiconductor layer. A minimum size of a predetermined area. Therefore, when considering the minimum size, a width of the oxide thin film transistor can be larger than the width of the pixel region, and it is difficult to form the coplanar structure in each pixel region of an array substrate of a high definition device. Oxide film transistor.

Moreover, although an oxide thin film transistor having this coplanar structure is formed in each pixel region, there is a problem that the aperture ratio is reduced due to the relatively large size of the oxide thin film transistor.

Accordingly, the present invention is directed to an array substrate comprising a thin film transistor and a method of fabricating the same, thereby overcoming one or more problems due to limitations and disadvantages of the prior art.

One of the objects of the present invention is to provide an array substrate including a thin film transistor and a method of fabricating the same, which can be applied to a high definition device.

One of the objects of the present invention is to provide an array substrate including a thin film transistor and a method of manufacturing the same, which can increase the aperture ratio.

Other advantages, objects, and features of the invention will be set forth in part in the description which follows, It is understood or can be derived from the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the <RTI

In order to obtain the object and other features of the present invention, the present invention is embodied and described in detail. An array substrate of the present invention comprises: a substrate; an oxide semiconductor layer on the substrate, and an oxide semiconductor layer comprising An active region and a source and a drain region on both sides of the active region; a gate insulating layer and a gate are sequentially located on the active region of the oxide semiconductor layer; and an interlayer insulating layer is located on the gate and has a respective exposure source and The first and second semiconductor contact holes of the drain region; and the source and the drain are located on the interlayer insulating layer and are in contact with the source and the drain region through the first and second semiconductor contact holes, respectively, wherein the first and second The semiconductor contact holes are disposed in two regions.

Preferably, the oxide semiconductor layer may have a bent portion, and both ends of the bent portion correspond to the first and second semiconductor contact holes, respectively.

Preferably, the curved portion may have an L-like shape.

Preferably, the array substrate further comprises: a gate line on the gate insulating layer along a first direction and connected to the gate; and a data line on the interlayer insulating layer along a second direction The data line intersects the gate line to define a plurality of pixel regions, wherein the two regions straddle two pixels adjacent to each other along the second direction in a direction parallel to a length of one pixel region The locale, wherein the length of the one pixel region is longer than a width of the one pixel region.

Preferably, the array substrate further comprises: a gate line on the gate insulating layer along a first direction and connected to the gate; and a data a line along a second direction on the interlayer insulating layer, the data line intersecting the gate line to define a plurality of pixel regions, wherein the two regions are adjacent to each other along the second direction and one of the two regions Is the last pixel region connected to the last gate line, wherein the last pixel region of the last gate line forms the second semiconductor contact hole of the last pixel region, and the other of the two regions The first semiconductor contact hole, which is the last pixel region connected to the last gate line, is formed to correspond to an area of the data line extending in a non-display area.

Preferably, the array substrate further comprises: a gate line on the gate insulating layer along a first direction; and a data line on the interlayer insulating layer along a second direction, the data line The gate line is crossed to define a first pixel region and a second pixel region adjacent to each other along the second direction, wherein a portion of the gate line is a gate and a portion of the data line is a source.

Preferably, the drain may be located in the first pixel region and the source may be located in the data line next to the second pixel region.

Preferably, the oxide semiconductor layer is formed of an oxide semiconductor material when one or more selected from the group consisting of helium (He), argon (Ar), and hydrogen (H) is exposed to the plasma. Has an increased conductivity.

Preferably, the oxide semiconductor material may comprise indium gallium zinc oxide One of (IGZO), zinc tin oxide (ZTO) or zinc indium oxide (ZIO).

Preferably, the active region is a portion of the oxide semiconductor layer that overlaps the gate and is not plasma-treated, and the source and drain regions are not overlapped with the gate and are treated by plasma to have improved conductivity. Part of the performance of the oxide semiconductor layer.

Preferably, the array substrate further comprises: a passivation layer on the source and the drain and having a drain contact hole and a pixel contact hole on the passivation layer and through the drain contact hole and the germanium The pole contact is in contact with the second semiconductor contact hole.

In another aspect, a method of fabricating an array substrate includes: forming an oxide semiconductor layer on a substrate, the oxide semiconductor layer including an active region and source and drain regions on both sides of the active region; a gate insulating layer and a gate on the active region of the oxide semiconductor layer; and a source for processing the oxide semiconductor layer using one or more plasmas selected from the group consisting of helium (He), argon (Ar), and hydrogen (H) And a drain region, thereby increasing a conductive property of the source and the drain region; forming an interlayer insulating layer on the gate and having first and second semiconductor contact holes respectively exposing the source and the drain region; and forming a source and a drain The first and the second semiconductor contact holes are in contact with the source and the drain, respectively, on the interlayer insulating layer, and the first and second semiconductor contact holes are disposed in the two regions.

Preferably, the oxide semiconductor layer may have a bent portion, and both ends of the bent portion correspond to the first and second semiconductor contact holes, respectively.

Preferably, the curved portion may have a similar L shape.

Preferably, forming the gate may include forming a gate line along a first direction and connecting to the gate, wherein forming the source and the drain comprises forming a data line on the interlayer insulating layer along a second direction, The line intersects the gate line to define a plurality of pixel regions, and wherein the two regions span two pixel regions adjacent to each other along the second direction in a direction parallel to a length of one pixel region It is set that the length of one of the pixel regions is longer than the width of one of the pixel regions.

Preferably, forming the gate may include forming a gate line along a first direction and connecting to the gate, wherein forming the source and the drain comprises forming a data line on the interlayer insulating layer along a second direction, The line intersects the gate line to define a plurality of pixel regions, and the two regions are adjacent to each other along the second direction and one of the regions is the last pixel region connected to the last gate line. Wherein the last pixel region of the last gate line forms a second semiconductor contact hole of the last pixel region, and the other of the two regions is connected to the last pixel region of the last gate line. The first semiconductor contact hole is formed to correspond to an area of the data line extending in a non-display area.

Preferably, forming the gate electrode comprises forming a gate line along a first direction, wherein forming the source and the drain comprises forming a data line, a data line and a gate line on the interlayer insulating layer along a second direction Intersect to define along the second The first and second pixel regions are adjacent to each other, and a portion of the gate line is a gate, and a portion of the data line is a source.

Preferably, the drain may be located in the first pixel region and the source may be located in the data line next to the second pixel region.

Preferably, the oxide semiconductor material may comprise one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO).

Preferably, the active region may be part of an oxide semiconductor layer overlapping the gate and not being plasma-treated, and the source and drain regions may be overlapped with the gate and treated by plasma treatment to have an improved A portion of an oxide semiconductor layer of electrically conductive properties.

Preferably, the method for fabricating the array substrate further comprises: forming a passivation layer on the source and the drain and having a drain contact hole exposing the drain, and forming a pixel electrode on the passivation layer and contacting through the drain The hole is in contact with the drain, wherein the drain contact hole overlaps the second semiconductor contact hole.

It is to be understood that the foregoing general description of the invention and the claims

11‧‧‧Substrate

15‧‧‧ gate

18‧‧‧ gate insulation

22‧‧‧Active layer

26‧‧‧Ohm contact layer

28‧‧‧Semiconductor layer

36‧‧‧ source

38‧‧‧汲polar

42‧‧‧ Passivation layer

45‧‧‧汲 contact hole

50‧‧‧ pixel electrodes

61‧‧‧Substrate

63‧‧‧Oxide semiconductor layer

63a‧‧‧Active Area

63b‧‧‧ source area

63c‧‧‧Bungee Area

66‧‧‧ gate insulation

68‧‧ ‧ gate line

69‧‧‧ gate

72‧‧‧Interlayer insulation

74a‧‧‧First semiconductor contact hole

74b‧‧‧Second semiconductor contact hole

75‧‧‧Information line

76‧‧‧ source

77‧‧‧汲polar

78‧‧‧ Passivation layer

80‧‧‧Bungee contact hole

85‧‧‧pixel electrodes

101‧‧‧Substrate

105‧‧‧Oxide semiconductor layer

105a‧‧‧active area

105b‧‧‧ source area

105c‧‧‧Bungee Area

108‧‧‧First insulation

109‧‧‧ gate insulation

113‧‧‧ gate line

115‧‧‧First metal layer

116‧‧‧ gate

120‧‧‧Interlayer insulation

122a‧‧‧First semiconductor contact hole

122b‧‧‧Second semiconductor contact hole

130‧‧‧Information line

133‧‧‧ source

136‧‧‧汲

140‧‧‧ Passivation layer

143‧‧‧Bare contact hole

150‧‧‧pixel electrodes

191‧‧‧First photoresist pattern

195‧‧‧vacuum chamber

P‧‧‧ pixel area

T1‧‧‧first thickness

T2‧‧‧second thickness

P1‧‧‧ first pixel area

P2‧‧‧Second pixel area

TrA‧‧‧Switching area

Tr‧‧‧thin film transistor

Fig. 1 is a cross-sectional view showing an array substrate of a liquid crystal display device or an organic electroluminescence display device according to one of the prior art.

Figure 2 is a thin film comprising such an oxide semiconductor layer according to the prior art. A plan view of a portion of a pixel region of an array of substrates of a film transistor.

Fig. 3 is a cross-sectional view taken along line III-III of Fig. 2.

Figure 4 is a plan view showing a portion of an array substrate according to an embodiment of the present invention, wherein the array substrate comprises an oxide thin film transistor having an oxide semiconductor layer.

Fig. 5 is a cross-sectional view taken along line V-V of Fig. 4.

6A to 6I are cross-sectional views of the array substrate in the steps of the method of fabricating an array substrate according to an embodiment of the present invention, and show a cross section along the line V-V of Fig. 4.

Reference will now be made in detail be made to the embodiments of the invention Throughout the drawings, the same reference numerals will be used to refer to the same or the like.

Fig. 4 is a plan view showing a portion of an array substrate according to an embodiment of the present invention, wherein the array substrate comprises an oxide thin film transistor having an oxide semiconductor layer. For ease of explanation, a region of the oxide film transistor positioning is defined as a switching region TrA.

In FIG. 4, a gate line 113 in a first direction and a data line 130 in a second direction intersect each other to thereby define first and second pictures adjacent to each other along the second direction. Prime areas P1 and P2.

An oxide thin film transistor Tr as a switching element is connected to an intersection portion of the gate line 113 and the data line 130. Oxide thin film transistor Tr is set to intersect the first and second pixel regions P1 and P2. The oxide thin film transistor Tr includes an oxide semiconductor layer 105, and the oxide semiconductor layer 105 may have a bent portion and one end is disposed in the first pixel region P1 and the other end is disposed in the second pixel region P2 or the second In the data line next to the pixel area P2.

The oxide thin film transistor Tr includes an oxide semiconductor layer 105, a gate 116, and source and drain electrodes 133 and 136. The oxide semiconductor layer 105 is formed on a substrate (not shown), and the gate 116 is formed over the oxide semiconductor layer 105. The oxide semiconductor layer 105 on both sides of the gate 116 is exposed through the first and second semiconductor contact holes 122a and 122b. The source and drain electrodes 133 and 136 are in contact with the oxide semiconductor layer 105 through the first and second semiconductor contact holes 122a and 122b, respectively. The oxide thin film transistor Tr has a coplanar structure.

In the oxide thin film transistor Tr, the oxide semiconductor layer 105 may have any shape formed between both ends thereof. In this case, one source of one oxide thin film transistor Tr and one drain of the other oxide thin film transistor Tr can be disposed in one pixel region along a length longer than a width of the pixel region (including In the data line next to the pixel area). Therefore, although the sizes of the first and second pixel regions P1 and P2 are reduced for high definition, the oxide thin film transistor Tr having a coplanar structure can be formed to switch the first and second pixel regions P1. And the on/off of each of P2. Preferably, the oxide semiconductor layer 105 comprises at least one curved portion, such as an L-like The shape is such that a portion of the data line 130 is the source 133 and a portion of the gate line 113 is the gate 116.

Further, the source 133 of the oxide thin film transistor Tr of the first pixel region P1 is switched, and the second pixel disposed in the second pixel region P2 or adjacent to the first pixel region P1 along the second direction In the data line next to the area P2. The drain 136 of the oxide thin film transistor Tr of the first pixel region P1 is switched and disposed in the first pixel region P1.

Meanwhile, the first semiconductor contact hole 122a corresponds to the source electrode 133, and the second semiconductor contact hole 122b corresponds to the drain electrode 136. The source electrode 133 contacts a source region of the oxide semiconductor layer 105 through the first semiconductor contact hole 122a, and the drain electrode 136 contacts a drain region of the oxide semiconductor layer 105 through the second semiconductor contact hole 122b.

In the present invention, the first and second semiconductor contact holes 122a and 122b of a certain size are required in a line along a first direction parallel to a short length of the first or second pixel region P1 or P2. It is not set in one pixel area, for example, in the first pixel area P1. That is, the first and second semiconductor contact holes 122a and 122b are respectively disposed in the second and first pixel regions P2 (including a data line of the second pixel region P2) and P1, the first and second semiconductors. The contact holes 122a and 122b are adjacent to each other along a second direction parallel to a long length of the first or second pixel region P1 or P2. Therefore, although the sizes of the first and second pixel regions P1 and P2 are for a full high definition display The arrangement is reduced, but the oxide thin film transistor Tr can be formed to have a coplanar structure.

Meanwhile, in the oxide thin film transistor Tr expanded in the first and second pixel regions P1 and P2, the oxide semiconductor layer 105 includes an active layer and a source and a drain region. The active region overlaps the gate 116 and is not plasma treated. The source and drain regions are disposed on both sides of the active region and do not overlap the gate 116. The source and drain are treated by plasma and have improved contact properties.

A single pixel electrode 150 is formed in each of the first and second pixel regions P1 and P2. The pixel electrode 150 in the first pixel region P1 is connected to the drain electrode 136 of the oxide film transistor Tr, and the pixel electrode 150 in the second pixel region P2 is connected to another oxide film transistor (Fig. Show a bungee.

When the array substrate is used in a liquid crystal display device, a common electrode may be further formed on the array substrate. In order to supply a common voltage to the common electrode, a common line may also be formed on the array substrate, and the common line may be formed on the same layer as the same material as the gate line 113 or the data line 130.

For example, when the array substrate is used for a planar switching type liquid crystal display device, a common electrode may be formed on the same layer or a different layer as the pixel electrode, and each of the common electrode and the pixel electrode 150 may have A rod-shaped pattern alternating with each other.

Or when the array substrate is used for a fringe field switching type liquid crystal display In the device, a common electrode can be formed on a layer different from the pixel electrode and overlaps the pixel electrode. One of the common electrode and the pixel electrode may have a rod-shaped opening in each of the first and second pixel regions P1 and P2.

Meanwhile, when the array substrate is used in an organic electroluminescence display device, the pixel electrode 150 has a size corresponding to each of the first and second pixel regions P1 and P2 and is an organic light emitting diode. A first electrode, the first electrode can serve as a cathode or an anode.

In the array substrate, since a pixel region connected to the last gate line in a display region does not have a neighboring pixel region along the second direction, it seems to be a picture connected to the last gate line. The prime area does not have a switching area.

However, the data line 130 extends into a non-display area outside the display area and is connected to a data connection line or a data pad electrode in the non-display area, or has a virtual pixel area in the non-display area.

Therefore, the first semiconductor contact hole 122a connected to the pixel region of the last gate line 113 is formed to correspond to the data line 130 extending in the non-display region. And the source 133 of the pixel region connected to the last gate line 113 is formed to correspond to the first semiconductor contact hole 122a.

In the above array substrate, the switching region TrA is disposed in a direction parallel to the data line 130 so as to span the first and second pixel regions P1 and P2 of the two pixel regions adjacent to each other, and respectively expose the oxide semiconductor Floor The first and second semiconductor contact holes 122a and 122b of the source and drain regions 105b and 105c of 105 are larger than the first and second pixel regions P1 and P2 of the width of the first and second pixel regions P1 and P2. The sides of the parallel length are arranged upwards. Therefore, although the sizes of the first and second pixel regions P1 and P2 are reduced due to high definition, for example, 1080 by 1920, the oxide thin film transistor Tr having a coplanar structure can be formed to switch the first and second paintings. On/off of each of the prime regions P1 and P2.

Moreover, since a portion of the gate line 113 serves as the gate 116 and a portion of the data line 130 serves as a source, the size of the oxide thin film transistor Tr is reduced, and each of the first and second pixel regions P1 and P2 The aperture ratio in one increases.

A cross-sectional structure of an array substrate according to an embodiment of the present invention will hereinafter be described.

"5th drawing" is a cross-sectional view taken along the line V-V in "Fig. 4". For ease of explanation, a region where the oxide film is positioned is defined as a switching region TrA.

In the array substrate of the present invention, the oxide semiconductor layer 105 is formed in the switching region TrA on a transparent insulating substrate 101. The substrate 101 may be formed of glass or plastic. The oxide semiconductor layer 105 includes an active region 105a and source and drain regions 105b and 105c. The active region 105a overlaps the gate and is not plasma treated. Source and drain regions 105b and 105c are respectively disposed in the active region Both sides of 105a are treated by plasma to have electrical conductivity. The oxide semiconductor layer 105 has a bent portion in a plan view and has an L-like shape.

The oxide semiconductor layer 105 is formed of an oxide semiconductor material such as Indium gallium zinc oxide (IGZO), Zinc Tin Oxide (ZTO) or Zinc Indium Oxide (ZIO). When plasma treatment is performed using one or more selected from the group consisting of helium (He), argon (Ar), and hydrogen (H), the electrical conductivity of the oxide semiconductor material is improved.

That is, a portion of the oxide semiconductor material having no plasma treatment functions as a semiconductor which transmits a current by forming a channel according to an on/off operation of the gate 116 or an insulating property when a channel is not formed. A portion of the plasma treated oxide semiconductor material has improved electrical conductivity and functions as a conductor.

Meanwhile, a buffer layer (not shown) may be further formed between the substrate 101 and the oxide semiconductor layer 105. For example, the buffer layer may be formed of an inorganic insulating material such as hafnium oxide or tantalum nitride.

A gate insulating layer 109 is formed on the oxide semiconductor layer 105 having the active region 105a and the source and drain regions 105b and 105c. The gate insulating layer 109 corresponds to the active region 105a. For example, the gate insulating layer 109 may be formed of an inorganic insulating material such as hafnium oxide or tantalum nitride.

A gate 116 is formed on the gate insulating layer 109 corresponding to the active region 105a of the oxide semiconductor layer 105.

Although not shown, a gate line 113 of "Fig. 4" is formed together with the gate 116, and a gate insulating layer 109 is formed under the gate line 113 of "Fig. 4". A part of the gate line 113 of "Fig. 4" is the gate 116.

The gate insulating layer 109, the gate line 113 of FIG. 4, and the gate 116 are patterned and formed by the same mask process, and the gate insulating layer 109 has the gate line 113 as shown in FIG. The gate 116 has the same planar structure.

This is to form the source of the oxide semiconductor layer 105 and the drain electrodes 105b and 105c. That is, the gate insulating layer 109, the gate line 113 of "Fig. 4", and the gate 116 are patterned by the same mask process, and one surface of the oxide semiconductor layer 105 is exposed on both sides of the gate insulating layer 109. . Then, a plasma treatment process is performed on the exposed surface of the oxide semiconductor layer 105 to thereby form the source and drain regions 105b and 105c of the oxide semiconductor layer 105.

Then, the interlayer insulating layer 120 is formed on the gate line 113 and the gate 116 of the "Fig. 4" over the substrate 101. For example, the interlayer insulating layer 120 may be formed of an inorganic insulating material such as hafnium oxide or tantalum nitride.

The interlayer insulating layer 120 has first and second semiconductor contact holes 122a and 122b of the exposed source and drain regions 105b and 105c, respectively. Here, the first and second semiconductor contact holes 122a and 122b are disposed in different pixel regions (in a data line containing these pixel areas). That is, the first semiconductor contact hole 122a is disposed in a second pixel region P2 or adjacent to a data line adjacent to the second pixel region P2 of the first pixel region P1, and the second semiconductor contact hole 122b is disposed in the first pixel area P1.

A source 133 and a drain 136 are formed in the switching region TrA on the interlayer insulating layer 120. The source and drain electrodes 133 and 136 are spaced apart from each other. The source electrode 133 is in contact with the source region 105b of the oxide semiconductor layer 105 through the first semiconductor contact hole 122a, and the drain electrode 136 is in contact with the drain region 105c of the oxide semiconductor layer 105 through the second semiconductor contact hole 122b.

Meanwhile, a data line 130 of "FIG. 4" is formed on the interlayer insulating layer 120. The data line 130 of "Fig. 4" intersects with the gate line 113 of "Fig. 4" to define the first and second pixel regions P1 and P2. A part of the data line 130 of "Fig. 4" is the source 133.

The oxide semiconductor layer 105, the gate insulating layer 109, the gate 116, the interlayer insulating layer 120 having the first and second semiconductor contact holes 122a and 122b, and the source and drain electrodes 133 and 136 are sequentially formed in the switching region Tr. The oxide thin film transistor Tr is formed, that is, a switching element.

A passivation layer 140 is formed over the oxide film transistor Tr over a total surface of the substrate 101. The passivation layer 140 is formed of an inorganic insulating material such as hafnium oxide or tantalum nitride, or an organic insulating material such as benzocyclobutene (BCB) and photo propylene.

The passivation layer 140 has a drain contact hole 143 that exposes the drain 136. The drain contact hole 143 overlaps with the second semiconductor contact hole 122b. This causes an increase in the aperture ratio of the first and second pixel regions P1 and P2.

A pixel electrode 150 is formed on the passivation layer 140 having the drain contact holes 143 in each of the pixel regions P1 and P2. The pixel electrode 150 is in contact with the drain 136 through the drain contact hole 143.

Although not shown, according to one mode of a liquid crystal display device, a common line can be further formed on the same layer as the gate line 113 of "Fig. 4" or the data line 130 of "Fig. 4" and with The gate line 113 of Fig. 4 or the data line 130 of "Fig. 4" are parallel. A common electrode can be formed and connected to a common line.

A method of manufacturing an array substrate according to the present invention will be described.

6A to 6I are cross-sectional views of the array substrate in the steps of the method of manufacturing an array substrate according to an embodiment of the present invention, and show the VV line along the "Fig. 4". section. For ease of explanation, a region in which an oxide thin film transistor is formed is defined as a switching region TrA. Here, the switching region TrA traverses the two pixel regions first and second pixel regions P1 and P2 adjacent to each other in a direction parallel to a data line.

In FIG. 6A, a layer of an oxide semiconductor material (not shown) is formed on a transparent insulating substrate 101 by deposition or application of an oxide semiconductor material. Oxide semiconductor materials must pass through the use of certain gases The plasma treatment of time may have an increased electrical conductivity and, for example, may be selected from indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO).

A buffer layer (not shown) may be further formed on the substrate 101 by depositing yttrium oxide or tantalum nitride before forming the oxide semiconductor material layer.

Then, the oxide semiconductor material layer is patterned by performing a mask process including the following steps: applying a photoresist, exposing, developing, and etching, thereby forming an oxide semiconductor layer 105 in each of the switching regions TrA. . The oxide semiconductor layer 105 has a curved pattern and has an L-like shape.

Then, in FIG. 6B, a first insulating layer 108 is formed on the oxide semiconductor layer 105 having an L-like shape by depositing an inorganic insulating material such as hafnium oxide or tantalum nitride, and then a first metal layer. 115 is formed on the first insulating layer 108 by depositing a first metal material. The first metal material may be one or more selected from the group consisting of copper (Cu), copper alloy, aluminum (Al), aluminum alloy such as aluminum-niobium alloy (AlNd), molybdenum (Mo), and molybdenum alloy such as molybdenum-titanium alloy (MoTi). And the first metal layer 115 may have a single layer structure or a multilayer structure.

In FIG. 6C, a photoresist layer (not shown) is formed on the first metal layer 115 by applying a photoresist and forming a pattern, thereby forming a first photoresist pattern 191. The first photoresist pattern 191 corresponds to the formation of "figure 4" A gate line 113 and a portion of a gate 116 of "Fig. 6D".

In the "Picture 6D", the gate line 113 and the gate 116 of the "Fig. 4" are removed from the first metal layer 115 in the "6Cth" by using the first photoresist pattern 191 as an etching mask. It is formed on the first insulating layer 108 of FIG. 6C. The gate line 113 of "Fig. 4" extends in a first direction, and the gate 116 is located in the switching region TrA and is connected to the gate line 113 of Fig. 4.

Here, a portion of the gate line 113 of the "fourth diagram" overlapping the oxide semiconductor layer 105 becomes the gate 116.

Subsequently, the first insulating layer 108 of the "FIG. 6C" exposed by the removal of the first metal layer of "FIG. 6C" is etched and removed, thereby forming a gate insulating layer 109. The gate insulating layer 109 has the same shape as the gate line 113 and the gate 116 of FIG. 4 in a planar structure.

After the gate insulating layer 109 is formed, the first photoresist pattern 191 and the gate 116 of the "FIG. 6C" on the gate line 113 of FIG. 4 are removed by performing a peeling and ashing process.

Therefore, the oxide semiconductor layer 105 having an island shape and disposed in the switching region TrA is exposed except for a portion overlapping the gate 116. The first insulating layer 108 of "FIG. 6C" is selectively removed and the oxide semiconductor layer 105 is partially exposed to increase the conductivity of a portion of the oxide semiconductor 105 by a plasma process performed later.

Next, in FIG. 6E, the substrate 101 including the gate line 113, the gate 116, and the partially exposed oxide semiconductor layer 105 of FIG. 4 is placed in a vacuum chamber 195 and exposed to plasma. A predetermined time, such as 30 seconds to 150 seconds, wherein the plasma is provided in the vacuum chamber 195 using one or more selected from the group consisting of helium (He), argon (Ar), and hydrogen (H). The oxide semiconductor layer 105 exposed to the plasma for a predetermined time has an increased electrical conductivity to thereby function as a conductor and have an ohmic property.

Here, the oxide semiconductor layer 105 has an active region 105a and source and drain regions 105b and 105c. Active region 105a is located below gate 116 and is not exposed to plasma. Source and drain regions 105b and 105c are disposed on both sides of active region 105a and exposed to the plasma.

For example, indium gallium zinc oxide (IGZO) for the oxide semiconductor layer 105 usually has a sheet resistance of several thousands to several tens of ohms/sq, and indium gallium zinc oxide (IGZO) exposed to plasma may have one A sheet resistance of 30 to 1000 ohm/sq.

Next, in FIG. 6F, an interlayer insulating layer 120 is formed on the entire surface of the substrate 101 by depositing an inorganic insulating material such as hafnium oxide or tantalum nitride, and is formed in the gate line of FIG. 113 and gate 116.

Then, the interlayer insulating layer 120 is patterned by a photomask process, thereby forming the first and second semiconductor contact holes 122a and 122b. First and The second semiconductor contact holes 122a and 122b are exposed to the source and drain regions 105b and 105c of the oxide semiconductor layer 105 of the switching region TrA, respectively.

Meanwhile, the first semiconductor contact hole 122a is disposed in the second pixel region P2 (including a data line beside the second pixel region P2) of the source region 105b of the oxide semiconductor layer 105 having the bent portion, and The second semiconductor contact hole 122b is disposed in the first pixel region P1 of the drain region 105c of the positioning oxide semiconductor layer 105.

In the "6G", a second metal layer (not shown) is formed on the interlayer insulating layer 120 having the first and second semiconductor contact holes 122a and 122b by depositing a second metal material. The second metal material may be one or more selected from the group consisting of copper (Cu), copper alloy, aluminum (Al), aluminum alloy such as aluminum-niobium alloy (AlNd), molybdenum (Mo), and molybdenum alloy such as molybdenum-titanium alloy (MoTi). And the second metal layer may have a single layer structure or a multilayer structure.

Next, the second metal layer is patterned by a photomask process, whereby the data line 130 of "Fig. 4" and the source and drain electrodes 133 and 136 are formed on the interlayer insulating layer 120. The data line 130 of "Fig. 4" extends in a second direction and intersects the gate line 113 in "Fig. 4" to define the first and second pixel regions P1 and P2. The source 133 and the drain 136 are disposed in the switching region TrA. The source 133 is connected to the data line 130 of "Fig. 4" and is in contact with the source region 105b through the first semiconductor contact hole 122a. The drain 136 is in contact with the drain region 105c through the second semiconductor contact hole 122b.

Here, a part of the data line 130 of "Fig. 4" becomes the source 133.

Formed in the switching region TrA, the oxide semiconductor layer 105 including the active region 105a and the source and drain regions 105b and 105c, the gate insulating layer 109, the gate 116, and the first and second semiconductor contact holes 122a and 122b are formed. The interlayer insulating layer 120, and the source and drain electrodes 133 and 136 constitute an oxide thin film transistor Tr which is a switching element.

As described above, the source electrode 133 of the oxide thin film transistor Tr is disposed in the data line beside the second pixel region P2, and the drain electrode 136 of the oxide thin film transistor Tr is disposed in the first pixel region P1. The oxide thin film transistor Tr is formed to straddle the first and second pixel regions P1 and P2 of the two pixel regions.

In "6H", a passivation layer 140 is formed on the data line 130 of "Fig. 4" and the source and drain electrodes 133 by depositing an inorganic insulating material on substantially the entire surface of the substrate 101 or applying an organic insulating material. And 136. For example, the inorganic insulating material may be tantalum oxide or tantalum nitride, and the organic insulating material may be benzocyclobutene (BCB) and photo propylene.

The passivation layer 140 is patterned by a photomask process, thereby forming a drain contact hole 143. The drain contact hole 143 exposes the drain 136 and overlaps the second semiconductor contact hole 122b.

Then, in "Picture 6I", by depositing a third metal material or a transparent conductive material and forming a pattern through a mask process, a pixel The electrode 150 is formed on each of the first and second pixel regions P1 and P2 on the passivation layer 140 having the drain contact hole 143. The pixel electrode 150 is in contact with the drain 136 through the drain contact hole 143. For example, the third metal material may be molybdenum (Mo) or molybdenum titanium alloy (MoTi), and the transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO).

Thus, the array substrate according to an embodiment of the present invention is completed. Meanwhile, although not shown, the gate line 113 forming "Fig. 4" or the data line 130 forming "Fig. 4" may include forming a common line which is parallel to the gate line of "Fig. 4". 113 or the data line 130 of FIG. 4, the formation of the drain contact hole 143 may include forming a common contact hole exposing the common line, and forming the pixel electrode 150 may include forming a common electrode, the common electrode passing through the common contact hole It is in contact with the common line and alternates with the pixel electrode 150, wherein each of the pixel electrode 150 and the common electrode has a pattern of a plurality of rod shapes.

In the array substrate of the present invention, the oxide thin film transistor Tr is formed to intersect the first and second pixel regions P1 and P2 adjacent to each other along the second direction, and expose the source of the oxide semiconductor layer 105 and The first and second semiconductor contact holes 122a and 122b of the drain regions 105b and 105c are arranged along a first direction parallel to a length of the first and second pixel regions P1 and P2, wherein the first and second pixels The length of the regions P1 and P2 is longer than the width of the first and second pixel regions P1 and P2. Therefore, although the first and second pixels One size of the domains P1 and P2 is reduced due to high definition, but it is possible to form an oxide thin film transistor Tr having a coplanar structure.

Further, the oxide thin film transistor Tr includes a gate line 113 of "Fig. 4" as a portion of the gate 116 and a data line 130 of "Fig. 4" as a portion of the source 133. Therefore, the area for the oxide thin film transistor Tr can be reduced, and the aperture ratio in each of the first and second pixel regions P1 and P2 can be increased.

The above oxide thin film transistor Tr can be applied not only to an array of substrates of a human portable device such as a laptop computer or a cellular phone capable of displaying a sufficiently high definition image, but also can be applied to include a coplanar structure. Any array of thin film transistors.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

101‧‧‧Substrate

105‧‧‧Oxide semiconductor layer

105a‧‧‧active area

105b‧‧‧ source area

105c‧‧‧Bungee Area

109‧‧‧ gate insulation

116‧‧‧ gate

120‧‧‧Interlayer insulation

122a‧‧‧First semiconductor contact hole

122b‧‧‧Second semiconductor contact hole

133‧‧‧ source

136‧‧‧汲

140‧‧‧ Passivation layer

143‧‧‧Bare contact hole

150‧‧‧pixel electrodes

P‧‧‧ pixel area

P1‧‧‧ first pixel area

P2‧‧‧Second pixel area

TrA‧‧‧Switching area

Tr‧‧‧thin film transistor

Claims (21)

An array substrate comprising: a substrate; an oxide semiconductor layer disposed on the substrate, the oxide semiconductor layer comprising an active region and a source region and a drain region on both sides of the active region; and a gate insulation a layer and a gate are sequentially disposed on the active region of the oxide semiconductor layer; an interlayer insulating layer is disposed on the gate and has a first semiconductor contact hole respectively exposing the source region and the drain region a second semiconductor contact hole; and a source and a drain are disposed on the interlayer insulating layer and are in contact with the source region and the drain region through the first semiconductor contact hole and the second semiconductor contact hole, respectively, wherein The first semiconductor contact hole and the second semiconductor contact hole are disposed in two regions, wherein the oxide is treated using one or more plasma selected from the group consisting of helium (He), argon (Ar), and hydrogen (H) The source region of the semiconductor layer and the drain region thereby increasing a conductive property of the source region and the drain region. The array substrate according to claim 1, wherein the oxide semiconductor layer has a bent portion, and both ends of the bent portion correspond to the first semiconductor contact hole and the second semiconductor contact hole, respectively. The array substrate of claim 2, wherein the curved portion has an L-like shape. The array substrate according to claim 1, further comprising: a gate line on the gate insulating layer along a first direction and connected to the gate; and a data line on the interlayer insulating layer along a second direction, the data line and the The gate lines intersect to define a plurality of pixel regions, wherein the two regions are disposed across two pixel regions adjacent to each other along the second direction in a direction parallel to a length of one pixel region, The length of the one pixel region is longer than a width of the one pixel region. The array substrate of claim 1, further comprising: a gate line on the gate insulating layer along a first direction and connected to the gate; and a data line along a second The direction is on the interlayer insulating layer, and the data line intersects the gate line to define a plurality of pixel regions, wherein the two regions are adjacent to each other along the second direction and one of the two regions is connected a final pixel region to the last gate line, wherein the last pixel region of the last gate line forms the second semiconductor contact hole of the last pixel region, and the other of the two regions A first semiconductor contact hole that is connected to the last pixel region of the last gate line is formed to correspond to an area of the data line extending in a non-display area. The array substrate of claim 1, further comprising: a gate line located on the gate insulating layer along a first direction; a data line is disposed on the interlayer insulating layer along a second direction, the data line intersecting the gate line to define a first pixel region and a second pixel adjacent to each other along the second direction a region, wherein a portion of the gate line is the gate, and a portion of the data line is the source. The array substrate of claim 6, wherein the drain is located in the first pixel region and the source is located in the data line beside the second pixel region. The array substrate according to claim 1, wherein the oxide semiconductor layer is formed of an oxide semiconductor material. The array substrate according to claim 8, wherein the oxide semiconductor material comprises one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO). The array substrate of claim 8, wherein the active region is a portion of the oxide semiconductor layer that overlaps the gate and is not plasma-treated, and the source region and the drain region are not A portion of the oxide semiconductor layer that overlaps the gate and is plasma treated to have improved electrical conductivity. The array substrate of claim 1, further comprising: a passivation layer on the source and the drain and having a drain contact hole exposing the drain, and a pixel electrode located in the passivation layer And contacting the drain through the drain contact hole, wherein the drain contact hole overlaps the second semiconductor contact hole. A method for manufacturing an array substrate, comprising: Forming an oxide semiconductor layer on a substrate, the oxide semiconductor layer comprising an active region and a source region and a drain region on both sides of the active region; sequentially forming a gate insulating layer and a gate On the active region of the oxide semiconductor layer; treating the source region and the drain of the oxide semiconductor layer using one or more plasmas selected from the group consisting of helium (He), argon (Ar), and hydrogen (H) a region, thereby increasing a conductive property of the source region and the drain region; forming an interlayer insulating layer on the gate and having a first semiconductor contact hole and a first semiconductor contact hole respectively exposing the source region and the drain region a second semiconductor contact hole; and forming a source and a drain on the interlayer insulating layer and contacting the source region and the drain region through the first semiconductor contact hole and the second semiconductor contact hole, respectively, wherein The first semiconductor contact hole and the second semiconductor contact hole are disposed in two regions. The method of manufacturing an array substrate according to claim 12, wherein the oxide semiconductor layer has a bent portion, and both ends of the bent portion correspond to the first semiconductor contact hole and the second semiconductor contact hole, respectively. The method of manufacturing an array substrate according to claim 13, wherein the curved portion has a similar L shape. The method of fabricating an array substrate according to claim 12, wherein the forming the gate comprises forming a gate line along a first direction and connecting to the gate. Forming the source and the drain includes forming a data line on the interlayer insulating layer along a second direction, the data line crossing the gate line to define a plurality of pixel regions, and wherein the two The region is disposed across two pixel regions adjacent to each other along the second direction in a direction parallel to a length of one pixel region, wherein the length of the one pixel region is compared to the one pixel region One has a longer width. The method of fabricating an array substrate according to claim 12, wherein the forming the gate comprises forming a gate line along a first direction and connecting to the gate, wherein the source and the drain are formed along a a second direction forming a data line on the interlayer insulating layer, the data line crossing the gate line to define a plurality of pixel regions, and wherein the two regions are adjacent to each other along the second direction and the two One of the regions is the last pixel region connected to the last gate line, wherein the last pixel region of the last gate line forms the second semiconductor contact hole of the last pixel region, And the other of the two regions is the first semiconductor contact hole connected to the last pixel region of the last gate line formed to correspond to an area of the data line extending in a non-display area . The method of fabricating an array substrate according to claim 12, wherein the forming the gate comprises forming a gate line along a first direction, wherein the source is formed and the drain comprises a layer along the second direction Forming a data line on the insulating layer, the data line intersecting the gate line to determine a first pixel region and a second pixel region adjacent to each other along the second direction, and wherein a portion of the gate line is the gate, and a portion of the data line is the source . The method of fabricating an array substrate according to claim 17, wherein the drain is located in the first pixel region and the source is located in the data line beside the second pixel region. The method of manufacturing an array substrate according to claim 12, wherein the oxide semiconductor layer is formed of an oxide semiconductor material comprising indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc oxide. One of indium (ZIO). The method of fabricating an array substrate according to claim 12, wherein the active region is a portion of the oxide semiconductor layer overlapping the gate and not plasma-treated, and the source region and the drain region It is a portion of the oxide semiconductor layer that does not overlap the gate and is plasma-treated to have improved conductivity. The method for fabricating an array substrate according to claim 17, further comprising: forming a passivation layer on the source and the drain and having a drain contact hole exposing the drain, and forming a pixel electrode for the passivation And contacting the drain electrode through the drain contact hole, wherein the drain contact hole overlaps the second semiconductor contact hole.