TW200810123A - Thin film transistors and displays including the same - Google Patents
Thin film transistors and displays including the same Download PDFInfo
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- TW200810123A TW200810123A TW95128282A TW95128282A TW200810123A TW 200810123 A TW200810123 A TW 200810123A TW 95128282 A TW95128282 A TW 95128282A TW 95128282 A TW95128282 A TW 95128282A TW 200810123 A TW200810123 A TW 200810123A
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- 239000010409 thin film Substances 0.000 title claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000013078 crystal Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 claims description 4
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 129
- 239000000463 material Substances 0.000 description 13
- 229910052732 germanium Inorganic materials 0.000 description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 239000002356 single layer Substances 0.000 description 4
- 229910052735 hafnium Inorganic materials 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910052684 Cerium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- BEQNOZDXPONEMR-UHFFFAOYSA-N cadmium;oxotin Chemical compound [Cd].[Sn]=O BEQNOZDXPONEMR-UHFFFAOYSA-N 0.000 description 2
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 206010011469 Crying Diseases 0.000 description 1
- 241000238631 Hexapoda Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- CQMUOFGWJSNFPX-UHFFFAOYSA-N [O].[Sn].[Sn] Chemical compound [O].[Sn].[Sn] CQMUOFGWJSNFPX-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- FJMNNXLGOUYVHO-UHFFFAOYSA-N aluminum zinc Chemical compound [Al].[Zn] FJMNNXLGOUYVHO-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- -1 sharp Chemical compound 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
200810123 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構，特別是有關於一種 薄膜電晶體及包含此薄膜電晶體之顯示器。 【先前技#ί】 在面板製造過程中，很容易有靜電放電（BSD)的情形 發生，此對元件與電路會造成極大損害，遂在面板設計 時，常於面板最外圍加設靜電放電防護元件及電路，以降 _ 低製程中靜電放電的影響。一個「堅固耐用（robust)」的 靜電放電元件是必要的，然而，生產過程中仍不時見到被 靜電放電損害的靜電放電防護元件，一旦靜電放電防護元 件被損毁，即無法發揮該有效能保護内部畫素電路。 其次，一個好的靜電放電防護元件必須具備「穿透 (transparency)」的特性，意即在正常條件操作下，靜電放 電防護元件必須是關閉且不工作的，若關閉特性不良即會 有額外漏電流及功率的損耗，此種情形特別不允許在可攜 φ 式的電子產品上出現，例如手機或PDA等。針對靜電放 電防護元件的「穿透（transparency)」特性，美國專利第 6,081，307 及 6，175,394 號提出浮置閘極式（floating gate)的 薄膜電晶體結構，其與二極體式（diode-type)的薄膜電晶體 結構相比，靜電放電防護元件的起始電壓較大，而漏電流 及所佔面積較小。目前，此兩種薄膜電晶體連接方式都廣 泛使用中。 【發明内容】200810123 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure, and more particularly to a thin film transistor and a display comprising the same. [Previous technology #ί] In the panel manufacturing process, it is easy to have electrostatic discharge (BSD), which will cause great damage to components and circuits. When the panel is designed, it is often installed with electrostatic discharge protection at the outermost periphery of the panel. Components and circuits to reduce the effects of electrostatic discharge in the low process. A "robust" electrostatic discharge component is necessary. However, electrostatic discharge protection components damaged by electrostatic discharge are still seen from time to time during production. Once the electrostatic discharge protection component is damaged, the effective energy cannot be achieved. Protect the internal pixel circuit. Secondly, a good ESD protection component must have "transparency" characteristics, meaning that under normal operating conditions, the ESD protection component must be turned off and not working. If the shutdown characteristics are poor, there will be additional leakage. Current and power loss, especially in portable φ-type electronic products, such as cell phones or PDAs. U.S. Patent Nos. 6,081,307 and 6,175,394, the disclosure of which is incorporated herein by reference to U.S. Pat. Compared with the thin film transistor structure of the type), the initial voltage of the electrostatic discharge protection element is large, and the leakage current and the occupied area are small. Currently, both types of thin film transistor connections are widely used. [Summary of the Invention]
Clientf s Docket No.:AU0511067 TT's Docket No: 0632-A50689TW/final/david 5 200810123 本發明提供一種薄膜電晶體，包括一閘極，形成於一 基板上；一絕緣層，形成於該基板上並覆蓋該閘極；一半 導體層，形成於該絕緣層上；以及一源極與一没極，形成 於該半導禮層上，該源極與該汲極之間具有一間隔，且該 源極與該汲極之至少之一者，係未延伸至該閘極正上方之 區域内。 本發明提供一種薄膜電晶體，包括一閘極，形成於一 基板上；一絕緣層，形成於該基板上並覆蓋該閘極；一半 導體層，形成於該絕緣層上；以及一源極與一没極，形成 _ 於該半導體層上，該源極與該汲極之間具有一間隔，且該 源極與該汲極之至少之一者，係延伸至該閘極正上方之區 域内。 本發明另提供一種顯示器，包括一定義有一顯示區之 基底；複數條閘極線（gate lines)，設置於該基底上；複數 條資料線（data lines)，設置於該基底上’該等閘極線與該 等資料線彼此相交，以定義出複數個晝素區，且每一晝素 區具有至少一開關元件（switch device);至少一短路桿 ⑩ （shorting bar)，設置於該顯示區週邊；以及複數個源極與 汲極之至少之一者未延伸至該閘極正上方區域内之薄膜 電晶體，設置於該顯示區外，其中每一薄膜電晶體係分別 電性連接於該等閘極線之一與該短路桿及/或該等資料線 之一與該短路桿。 本發明再提供一種顯示器，包括一定義有一顯示區之 基底；複數條閘極線（gate lines)，設置於該基底上；複數 條資料線（data lines)，設置於該基底上，該等閘極線與該 等資料線彼此相交，以定義出複數個晝素區，且每一晝素Clientf s Docket No.: AU0511067 TT's Docket No: 0632-A50689TW/final/david 5 200810123 The present invention provides a thin film transistor comprising a gate formed on a substrate; an insulating layer formed on the substrate and covering a gate electrode; a semiconductor layer formed on the insulating layer; and a source and a gate formed on the semiconductor layer, the source and the drain have a space therebetween, and the source At least one of the bungee poles does not extend into the area directly above the gate. The present invention provides a thin film transistor comprising a gate formed on a substrate; an insulating layer formed on the substrate and covering the gate; a semiconductor layer formed on the insulating layer; and a source and a stepless manner, forming a gap between the source and the drain, and at least one of the source and the drain extends to a region directly above the gate . The invention further provides a display comprising a substrate defining a display area; a plurality of gate lines disposed on the substrate; and a plurality of data lines disposed on the substrate The polar line and the data lines intersect each other to define a plurality of pixel regions, and each of the pixel regions has at least one switch device; at least one shorting bar 10 is disposed in the display region a peripheral film; and a plurality of thin film transistors extending in the region directly above the gate, at least one of the source and the drain, disposed outside the display region, wherein each of the thin film electro-crystal systems is electrically connected to the One of the gate lines and one of the shorting bars and/or one of the data lines and the shorting bar. The present invention further provides a display comprising a substrate defining a display area; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, the gates The polar line and the data lines intersect each other to define a plurality of halogen regions, and each element
Client^ s Docket No.:AU0511067 6 TTf s Docket No: 0632-Α5Ό689TW/final/david 200810123 區具有至少一開關元件（switch device);至少一短路桿 (shorting bar)，設置於該顯示區週邊；以及複數個源極與 汲極之至少之一者延伸至該閘極正上方區域内之薄膜電 晶體，設置於該顯示區外，其中每一薄膜電晶體係分別電 性連接於該等閘極線之一與該短路桿及/或該等資料線之 一與該短路桿。 為讓本發明之上述目的、特徵及優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 【實施方式】 本發明提供一種薄膜電晶體，包括一閘極，形成於一 基板上；一絕緣層，形成於基板上並覆蓋閘極；一半導體 層，形成於絕緣層上；以及一源極與一汲極，形成於半導 體層上’源極與没極之間具有一間隔’且源極與没極至少 之一者，未延伸至閘極正上方的區域内。 上述半導體層可包括一通道層與一分別接觸源極與 汲極的歐姆接觸層。位於源極與汲極間的通道層可定義為 一通道區，其長度大約介於4〜12微米。源/汲極與閘極間 形成有一電阻値大於5Μω的壓搶電阻(ballast resistor)。而 上述未延伸至閘極正上方區域内的源極或汲極，其與閘極 的水平距離大約介於〇〜2微米。 閘極與源/汲極的材質可為相同或不同，包括透明材 質或反射材質。適用的透明材質例如氧化銦錫（indium tin oxide，ITO)、氧化銦鋅（indium zinc oxide，IZO)、氧化錫錫Client^ s Docket No.: AU0511067 6 TTf s Docket No: 0632-Α5Ό689TW/final/david 200810123 zone has at least one switch device; at least one shorting bar is disposed around the display area; a thin film transistor extending in at least one of the source and the drain to the region directly above the gate is disposed outside the display region, wherein each of the thin film electro-crystal systems is electrically connected to the gate lines One of the shorting bars and/or one of the data lines and the shorting bar. The above-mentioned objects, features and advantages of the present invention will become more apparent from the following description. a gate is formed on a substrate; an insulating layer is formed on the substrate and covers the gate; a semiconductor layer is formed on the insulating layer; and a source and a drain are formed on the semiconductor layer. There is a gap between the pole and the pole, and at least one of the source and the pole is not extended to the area directly above the gate. The semiconductor layer may include a channel layer and an ohmic contact layer respectively contacting the source and the drain. The channel layer between the source and the drain can be defined as a channel region having a length of approximately 4 to 12 microns. A ballast resistor having a resistance 値 greater than 5 Μ ω is formed between the source/drain and the gate. The source or drain, which does not extend to the region directly above the gate, has a horizontal distance from the gate of about 〇2 μm. The material of the gate and source/drain can be the same or different, including transparent or reflective materials. Suitable transparent materials such as indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide tin
Client's Docket No.:AU0511067 η TTfs Docket No: 〇632-A5〇689TW/final/david 200810123 (cadmium tin oxide, CTO)、其他具有類似性質的材料或上 述之組合。適用的反射材質例如銀、金、銅、I呂、欽、组、 鶬、錮、銳、氮化鈦、氮化组、氧化銘、氮化铭或上述材 質組成的合金或組合。閘極與源/汲極可為單層或多層結 構。 絕緣層的材質包括氮化矽、氧化矽、氮氧化矽或其組 合物，且可為單層或多層結構。另通道層與歐姆接觸層的 材質可包括非晶矽、多晶矽、微晶矽、單晶矽或其組合物， 其中歐姆接觸層的摻雜型態可為η型或p型摻雜。更甚 _ 者，為了能讓歐姆接觸層及通道層之電阻較低或讓電子流 通較為順暢，通道層可摻雜濃度較低於歐姆接觸層之掺雜 型態，且通道層所摻雜之摻雜型態可單層或多層，而可能 地更保留一層未摻雜層。 請參閱第1Α圖，說明本發明薄膜電晶體的剖面結 構。薄膜電晶體10包括一閘極14、一絕緣層16、一半導 體層24以及一源極26與一汲極28。閘極14形成於一基 板U上，絕緣層16形成於基板12上並覆蓋閘極14，半 • 導體層24形成於絕緣層16上，源極26與汲極28形成於 、半導體層24上。半導體層24由一通道層20與一歐姆接 觸層22所構成，其中歐姆接觸層22與源極26、汲極28 接觸。源極26與汲極28之間形成有一間隔30，間隔30 中的通道層20定義為一通道區32。此薄膜電晶體的結構 特徵在於源極26與汲極28至少之一者，未延伸至閘極 14正上方的區域34内，其源極26或汲極28與閘極14 · ' 令 的水平距離為零。換句話說，源極26或汲極28並未與閘 極14有重豐區域存在。Client's Docket No.: AU0511067 η TTfs Docket No: 〇632-A5〇689TW/final/david 200810123 (cadmium tin oxide, CTO), other materials having similar properties or combinations thereof. Suitable reflective materials such as silver, gold, copper, Ilu, chin, group, tantalum, niobium, sharp, titanium nitride, nitrided, oxidized, nitrided or alloys or combinations of the above materials. The gate and source/drain can be single or multi-layer structures. The material of the insulating layer includes tantalum nitride, cerium oxide, cerium oxynitride or a combination thereof, and may be a single layer or a multilayer structure. The material of the other channel layer and the ohmic contact layer may include amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium or a combination thereof, wherein the doping type of the ohmic contact layer may be n-type or p-type doping. Even more, in order to make the resistance of the ohmic contact layer and the channel layer lower or to make the electron flow smoother, the channel layer can be doped to a lower doping type than the ohmic contact layer, and the channel layer is doped. The doped form may be a single layer or multiple layers, while possibly retaining an additional layer of undoped layers. Referring to Fig. 1, a sectional structure of a thin film transistor of the present invention will be described. The thin film transistor 10 includes a gate 14, an insulating layer 16, a half conductor layer 24, and a source 26 and a drain 28. The gate electrode 14 is formed on a substrate U. The insulating layer 16 is formed on the substrate 12 and covers the gate electrode 14. The semiconductor layer 24 is formed on the insulating layer 16. The source electrode 26 and the drain electrode 28 are formed on the semiconductor layer 24. . The semiconductor layer 24 is composed of a channel layer 20 and an ohmic contact layer 22, wherein the ohmic contact layer 22 is in contact with the source electrode 26 and the drain electrode 28. A space 30 is formed between the source 26 and the drain 28, and the channel layer 20 in the space 30 is defined as a channel region 32. The thin film transistor is characterized by at least one of source 26 and drain 28, not extending into region 34 directly above gate 14, and its source 26 or drain 28 and gate 14' The distance is zero. In other words, source 26 or drain 28 is not present in a region of overlap with gate 14.
Clients Docket No. :AU0511067 ΤΤ,s Docket No : 0632-A5068?TW/final/david 8 200810123 請參閱第1B及1C圖，說明本發明另一薄膜電晶體 的剖面結構。薄膜電晶體50包括一閘極54、一絕緣層56、 一半導體層64以及一源極66與一汲極68。閘極54形成 於一基板52上，絕緣層56形成於基板52上並覆蓋閘極 54，半導體層64形成於絕緣層56上，源極66與汲極68 形成於半導體層64上。半導體層64由一通道層60與一 歐姆接觸層62所構成，其中歐姆接觸層62與源極66、 汲極68接觸。源極66與汲極68之間形成有一間隔70， 間隔70中的通道層60定義為一通道區72。此薄膜電晶 _ 體的結構特徵在於源極66與汲極68至少之一者（第1B圖） 或兩者(第1C圖），未延伸至閘極54正上方的區域74内， 其源極66或汲極68與閘極54有一水平距離W1。需要注 意的是，第1C圖所示的二個水平距離W1在實施例為相 等，然而，二個水平距離W1亦可不相等。 第1A.圖與1B圖結構上的差異在於1A圖中，源極 * - - * 、 26或汲極28與閘極14的水平距離為零，而1B圖的源極 66或汲極68與閘極54有一水平距離W1。兩者相同的是 A 結構中的源極或汲極至少之一者未延伸至閘極正上方的 馨 區域内。 、， 本發明提供一種薄膜電晶體，包括一閘極，形成於一 基板上；一絕緣層，形成於基板上並覆蓋閘極；一半導體 層，形成於絕緣層上；以及一源極與一汲極，形成於半導 體層上，源極與汲極之間具有一間隔，且源極與汲極至少 之一者，延伸至閘極正上方的區域内。 上述半·導體層可包括一通道層與一分別接觸源極與 汲極的歐姆接觸層。位於源極與汲極間的通道層可定義為Clients Docket No. : AU0511067 ΤΤ, s Docket No : 0632-A5068? TW/final/david 8 200810123 Please refer to FIGS. 1B and 1C for a cross-sectional structure of another thin film transistor of the present invention. The thin film transistor 50 includes a gate 54, an insulating layer 56, a semiconductor layer 64, and a source 66 and a drain 68. The gate 54 is formed on a substrate 52. The insulating layer 56 is formed on the substrate 52 and covers the gate. The semiconductor layer 64 is formed on the insulating layer 56, and the source 66 and the drain 68 are formed on the semiconductor layer 64. The semiconductor layer 64 is composed of a channel layer 60 and an ohmic contact layer 62, wherein the ohmic contact layer 62 is in contact with the source 66 and the drain 68. A gap 70 is formed between the source 66 and the drain 68, and the channel layer 60 in the space 70 is defined as a channel region 72. The thin film transistor is characterized by at least one of the source 66 and the drain 68 (Fig. 1B) or both (Fig. 1C), not extending into the region 74 directly above the gate 54, the source thereof. The pole 66 or the drain 68 has a horizontal distance W1 from the gate 54. It should be noted that the two horizontal distances W1 shown in Fig. 1C are equal in the embodiment, however, the two horizontal distances W1 may not be equal. The difference between the structure of the 1A. and 1B is that in the 1A diagram, the horizontal distance between the source * - - * , 26 or the drain 28 and the gate 14 is zero, and the source 66 or the drain 68 of the 1B diagram is The gate 54 has a horizontal distance W1. The same is true for at least one of the source or drain in the A structure does not extend into the fragrant area directly above the gate. The present invention provides a thin film transistor comprising a gate formed on a substrate, an insulating layer formed on the substrate and covering the gate, a semiconductor layer formed on the insulating layer, and a source and a gate The drain is formed on the semiconductor layer, and has a space between the source and the drain, and at least one of the source and the drain extends into a region directly above the gate. The semi-conductor layer may include a channel layer and an ohmic contact layer respectively contacting the source and the drain. The channel layer between the source and the drain can be defined as
Clientr s. Docket No.:AU0511067 9 TT's Docket No: 0632-A50689TW/final/david 200810123 一通道區，其長度大約介於4〜12微米。源/汲極與閘極間 形成有一電阻値大於5Μω的壓艙電阻(baiiast resistor)。而 上述延伸至閘極正上方區域内的源極或汲極，其與閘極的 重疊寬度不大於0.5微米。 閘極與源/汲極的材質可為相同或不同，包括透明材 質或反射材質。適用的透明材質例如氧化銦錫（indium tin oxide，ITO)、氧化銦鋅（indium zinc 〇xide，IZ〇)、氧化鎘錫 (cadmium tin oxide，CTO)、氧化鋁鋅（aluminum zinc，AZ〇)Clientr s. Docket No.: AU0511067 9 TT's Docket No: 0632-A50689TW/final/david 200810123 A channel zone with a length of approximately 4 to 12 microns. A baiiast resistor having a resistance 値 greater than 5 Μ ω is formed between the source/drain and the gate. The source or drain extending to the region directly above the gate has an overlap width with the gate of no more than 0.5 μm. The material of the gate and source/drain can be the same or different, including transparent or reflective materials. Suitable transparent materials such as indium tin oxide (ITO), indium zinc 〇xide (IZ〇), cadmium tin oxide (CTO), aluminum zinc (AZ〇)
或其他具有類似性質的材料。適用的反射材質例如銀、 金、銅、鋁、鈦、斂、鈕、鎢、鉬，、氮化鈦、、氮化鈕、 氧化鋁、氮化IS或上述材質組成的合金或組合物。閘極與 源/汲極可為單層或多層結構。 絕緣層的材質，包括氮化矽、氧化矽、氮氧化矽或其 組合物，且可為單層或多層結構。另通道層與歐姆接觸層 的材質可包括非晶矽、多晶矽、微晶矽、單晶矽或其組： 物，其中歐姆接觸層的摻雜型態可為n型或p型摻雜。更 甚者，為了能讓歐姆接觸層及通道層之電阻較低或讓電子 流通，為順暢，通道層可摻雜濃度較低於歐姆接觸層之摻 雜型態’且通道層所摻雜之摻雜型態可單層或多層γ而可 能地更保留一層未摻雜層。 ’ —請參閱第2圖，說明本發明薄膜電晶體的剖面結構。 薄膜電晶體100包括一閘極14〇、一絕緣層16〇、一蝕列 終止層18〇、一半導體層240以及一源極26〇與一汲極 280。閘極140形成於一基板12〇上，絕緣層16〇形成於 基板120上並覆蓋閘極14〇,半導體層24〇形成於絕緣層 160上，源極260與汲極280形成於半導體層24〇上。^Or other materials with similar properties. Suitable reflective materials such as silver, gold, copper, aluminum, titanium, condensed, button, tungsten, molybdenum, titanium nitride, nitrided nitride, alumina, nitrided IS or alloys or compositions of the foregoing. The gate and source/drain can be single or multi-layer structures. The material of the insulating layer includes tantalum nitride, cerium oxide, cerium oxynitride or a combination thereof, and may be a single layer or a multilayer structure. The material of the channel layer and the ohmic contact layer may include amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium or a group thereof, wherein the doped state of the ohmic contact layer may be n-type or p-type doped. Moreover, in order to make the resistance of the ohmic contact layer and the channel layer lower or allow electrons to flow, the channel layer can be doped to a lower doping type than the ohmic contact layer and the channel layer is doped. The doped form may be a single layer or multiple layers of gamma and possibly more of an undoped layer. ─ - Please refer to Fig. 2 to illustrate the cross-sectional structure of the thin film transistor of the present invention. The thin film transistor 100 includes a gate 14A, an insulating layer 16A, an etch stop layer 18A, a semiconductor layer 240, and a source 26 and a drain 280. The gate 140 is formed on a substrate 12, the insulating layer 16 is formed on the substrate 120 and covers the gate 14A, the semiconductor layer 24 is formed on the insulating layer 160, and the source 260 and the drain 280 are formed on the semiconductor layer 24. 〇上. ^
Clients Docket No. :AU0511067 , TTfs Docket No: 0632-A50689TW/final/david 10 200810123 導體層240由一通道層200與一歐姆接觸層220所構成， 其中歐姆接觸層220與源極260、汲極280接觸。源極260 與汲極280之間形成有一間隔300，間隔300中的通道層 200定義為一通道區320。此薄膜電晶體的結構特徵在於 源極260與汲極280至少之一者，延伸至閘極140正上方 的區域340内，其源極260或汲極280與閘極140有一重 疊寬度W2。 本發明設計的靜電放電（ESD)防護元件具有一大的壓 艙電阻(ballast resistor)，可有效減輕靜電放電造成的直接 _ 損害，又不會增加額外的layout面積。壓艙電阻(ballast resistor)是藉由控制源/汲極與閘極之間的重疊面積來改 變其數值。此外，由於寄生串聯電阻的設計，靜電放電防 護元件的漏電流及功率損耗極低，提供了一有效電壓降以 增強靜電放電防護元件的「堅固财用性（robustness)」。 本發明除可應用在如第1A、1B及第2圖所示的 BCE(back channel etched)元件外，亦可應用於具有 I-stopper(ion-stopper)結構的元件。以下即以第3A、3B及 • 第4圖說明本發明I-stopper薄膜電晶體。 請參閱第3A圖，說明本發明（I-stopper)薄膜電晶體的 剖面結構。薄膜電晶體101包括一閘極141、——絕緣層 161、一半導體層241以及一源極261與一汲極281。閘 極141形成於一基板121上，絕緣層161形成於基板121 上並覆蓋閘極141，半導體層241形成於絕緣層161上， 源極261與汲極281形成於半導體層241上。半導體層 241由一通道層201與一歐姆接觸層221所構成，其中通 道層201與蝕刻終止層181接觸，歐姆接觸層221與源極Clients Docket No. : AU0511067 , TTfs Docket No : 0632-A50689TW/final/david 10 200810123 The conductor layer 240 is composed of a channel layer 200 and an ohmic contact layer 220, wherein the ohmic contact layer 220 and the source 260 and the drain 280 contact. A gap 300 is formed between the source 260 and the drain 280, and the channel layer 200 in the space 300 is defined as a channel region 320. The thin film transistor is characterized in that at least one of the source 260 and the drain 280 extends into the region 340 directly above the gate 140, and the source 260 or the drain 280 and the gate 140 have an overlapping width W2. The electrostatic discharge (ESD) protection element designed by the present invention has a large ballast resistor, which can effectively reduce the direct damage caused by electrostatic discharge without adding additional layout area. The ballast resistor changes its value by controlling the area of overlap between the source/drain and the gate. In addition, due to the design of the parasitic series resistance, the leakage current and power loss of the ESD protection component are extremely low, providing an effective voltage drop to enhance the "robustness" of the ESD protection component. The present invention can be applied to an element having an I-stopper (ion-stopper) structure in addition to the BCE (back channel etched) element as shown in Figs. 1A, 1B, and 2 . Hereinafter, the I-stopper thin film transistor of the present invention will be described with reference to Figs. 3A, 3B and Fig. 4. Referring to Figure 3A, the cross-sectional structure of the (I-stopper) thin film transistor of the present invention will be described. The thin film transistor 101 includes a gate 141, an insulating layer 161, a semiconductor layer 241, and a source 261 and a drain 281. The gate electrode 141 is formed on a substrate 121. The insulating layer 161 is formed on the substrate 121 and covers the gate electrode 141. The semiconductor layer 241 is formed on the insulating layer 161, and the source electrode 261 and the drain electrode 281 are formed on the semiconductor layer 241. The semiconductor layer 241 is composed of a channel layer 201 and an ohmic contact layer 221, wherein the channel layer 201 is in contact with the etch stop layer 181, and the ohmic contact layer 221 and the source are
Client's Docket No.:AU0511067 TTf s Docket No: 0632-A50689TW/final/david 11 200810123 261、汲極281接觸。 源極261與汲極281之間的通道層201上更包括形成 有一蝕刻終止層211，以避免電晶體關閉時，源極261與 没極281之間的漏電流。姓刻終止層211可由例如氮化 矽、氧化矽、氮氧化矽等絕緣材料所構成。源極261與汲 極281之間形成有一間隔301，間隔301中的通道層201 定義為一通道區321。源極261與汲極281至少之一者， 未延伸至閘極141正上方的區域341内，其源極261或汲 極281與閘極141的水平距離為零。換句話說，源極26 _ 或汲極28並未與閘極14有重疊區域存在。 請參閱第3B及3C圖，說明本發明另一蝕刻終止 (I-stopper)薄膜電晶體的剖面結構。薄膜電晶體501包括 一閘極541、一絕緣層561、一半導體層641以及一源極 661與一汲極681。閘極541形成於一基板521上，絕緣 層561形成於基板521上並覆蓋閘極541，半導體層641 形成於絕緣層561上，源極661與汲極681形成於半導體 層641上。半導體層641由一通道層601與一歐姆接觸層 A 621所構成，其中歐姆接觸層62ί與源極661、汲極681 接觸。 源極661與没極681之間的通道層601上更包括形成 有一钱刻終止層611，以避免電晶體關閉時，源極6 61與 没極681之間的漏電流。I虫刻終止層611可由例如氮化 矽、氧化矽、氮氧化矽等絕緣材料所構成。源極661與汲 極681之間形成有一間隔701，間隔701中的通道層601 定義為一通道區721。源極661與汲極681至少之一者（第 3Β圖）或兩者（第3C圖），未延伸至閘極541正上方的區域Client's Docket No.: AU0511067 TTf s Docket No: 0632-A50689TW/final/david 11 200810123 261, bungee 281 contact. The channel layer 201 between the source 261 and the drain 281 further includes an etch stop layer 211 formed to prevent leakage current between the source 261 and the gate 281 when the transistor is turned off. The surname termination layer 211 may be composed of an insulating material such as tantalum nitride, hafnium oxide, or hafnium oxynitride. A gap 301 is formed between the source 261 and the drain 281, and the channel layer 201 in the space 301 is defined as a channel region 321 . At least one of the source 261 and the drain 281 does not extend into the region 341 directly above the gate 141, and the horizontal distance between the source 261 or the drain 281 and the gate 141 is zero. In other words, the source 26 _ or the drain 28 does not overlap the gate 14 . Referring to Figures 3B and 3C, a cross-sectional structure of another I-stopper film transistor of the present invention is illustrated. The thin film transistor 501 includes a gate 541, an insulating layer 561, a semiconductor layer 641, and a source 661 and a drain 681. The gate electrode 541 is formed on a substrate 521. The insulating layer 561 is formed on the substrate 521 and covers the gate electrode 541. The semiconductor layer 641 is formed on the insulating layer 561, and the source electrode 661 and the drain electrode 681 are formed on the semiconductor layer 641. The semiconductor layer 641 is composed of a channel layer 601 and an ohmic contact layer A 621, wherein the ohmic contact layer 62ί is in contact with the source electrode 661 and the drain electrode 681. The channel layer 601 between the source 661 and the gate 681 further includes a stop layer 611 formed to prevent leakage current between the source 6 61 and the gate 681 when the transistor is turned off. The insect engraving stop layer 611 may be composed of an insulating material such as tantalum nitride, hafnium oxide or hafnium oxynitride. A gap 701 is formed between the source 661 and the drain 681, and the channel layer 601 in the gap 701 is defined as a channel region 721. At least one of the source 661 and the drain 681 (Fig. 3) or both (Fig. 3C) does not extend to the area directly above the gate 541.
Clientf s Docket No.:AU0511067 TT's Docket No: 0632-A50689TW/final/david 12 200810123 741内，其源極661或汲極681與閘極541有一水平距離 W1。需要注意的是，第3C圖所示的二個水平距離W1在 實施例為相等’然而，二個水平距離W1亦可不相等。 第3A圖與3B调結構上的差異在於3A圖中，源極261 或没極281與閘極141的水平距離為零，而3B圖的源極 661或汲極681與閘極541有一水平距離W1。兩者相同 的是結構中的源極或没極至少之一者未延伸至閘極正上 方的區域内。 请參閱弟4圖’說明本發明钱刻終止（i_st〇pper)薄膜 • 電晶體的剖面結構。薄膜電晶體1〇〇1包括一閘極1401、 一絕緣層1601、一半導體層2401以及一源極2601與一 汲極2801。閘極1401形成於一基板12〇1上，絕緣層1601 形成於基板1201上並覆蓋閘極14〇1，半導體層2401形 成於絕緣層1601上，源極2601與汲極2801形成於半導 體層2401上。半導體層2401由一通道層2001與一歐姆 接觸層2201所構成，其中歐姆接觸層22〇1與源極26〇1、 汲極2801接觸。 _ 源極2601與汲極2801之間的通道層2〇〇1上更包括 开> 成有一餘刻終止層2101，以避免電晶體關閉時，源極 2601與/及極2801之間的漏電流。茲刻終止層21Q1可由 例如氮化矽、氮氧化矽或氧化矽等絕緣材料所構成。源極 2601與/及極2801之間形成有一間隔3〇〇1，間隔3001中 的通道層2001疋義為一通道區3201。源極2601與汲極 2801至少之一者，延伸至閘極14〇1正上方的區域'34〇1 内，其源極2601或汲極2801與閘極14〇ι有一重疊寬度 W2。 且、又Clientf s Docket No.: AU0511067 TT's Docket No: 0632-A50689TW/final/david 12 200810123 In 741, its source 661 or drain 681 has a horizontal distance W1 from the gate 541. It should be noted that the two horizontal distances W1 shown in Fig. 3C are equal in the embodiment. However, the two horizontal distances W1 may not be equal. The difference between the 3A and 3B modulation structures is that in the 3A diagram, the horizontal distance between the source 261 or the pole 281 and the gate 141 is zero, and the source 661 or the drain 681 of the 3B diagram has a horizontal distance from the gate 541. W1. The same is true for at least one of the source or the immersion in the structure that does not extend into the area directly above the gate. Please refer to the figure 4 to illustrate the cross-sectional structure of the invention. The thin film transistor 101 includes a gate 1401, an insulating layer 1601, a semiconductor layer 2401, and a source 2601 and a drain 2801. The gate 1401 is formed on a substrate 12〇1, the insulating layer 1601 is formed on the substrate 1201 and covers the gate 14〇1, the semiconductor layer 2401 is formed on the insulating layer 1601, and the source 2601 and the drain 2801 are formed on the semiconductor layer 2401. on. The semiconductor layer 2401 is composed of a channel layer 2001 and an ohmic contact layer 2201, wherein the ohmic contact layer 22〇1 is in contact with the source 26〇1 and the drain 2801. _ The channel layer 2〇〇1 between the source 2601 and the drain 2801 further includes an opening layer 2101 to avoid leakage between the source 2601 and/or the pole 2801 when the transistor is turned off. Current. The stopper layer 21Q1 may be composed of an insulating material such as tantalum nitride, hafnium oxynitride or hafnium oxide. A gap 3〇〇1 is formed between the source 2601 and/or the pole 2801, and the channel layer 2001 in the interval 3001 is referred to as a channel region 3201. At least one of the source 2601 and the drain 2801 extends into the region '34〇1 directly above the gate 14〇1, and the source 2601 or the drain 2801 and the gate 14〇 have an overlapping width W2. And again
Client’s Docket No.:AU0511067 TT^s Docket No: 0632-A50689TW/final/david 13 200810123 本f明另提供一種顯示器，包括一定義有一顯示區的 基底；複數條閘極線(gate lines)，設置於基底上；複數佟 資料線（data lines) ’設置於基底上’上述閘極線與資料各复 彼此相交，以定義出複數個畫素區，且每一晝素區具有至 少一開關元件（switch device);至少一短路桿（sh〇rtin bar)，設置於顯示區週邊；以及複數個源極與汲極至少= 一者未延伸至閘極正上方區域内的薄膜電晶體，設置於顯 示區外，其中每一薄膜電晶體分別電性連接於上述閘極= 之一與短路桿及/或上述資料線之一與短路桿。此顯示哭 • 更包括一共用線，設置於顯示區週邊，且電性連接於短路 桿。 本發明再提供一種顯示器，包括一定義有一顯示區的 基底；複數條閘極線(gate lines)，設置於基底上；複數修 資料線(data lines)，設置於基底上，上述閘極線與資料線 彼此相交，以定義出複數個晝素區，且每一書素區具有至 少一開關元件（switch device)至少一短路桿（sh〇rtin bar)，設置於顯示區週邊；以及複數個源極與汲極之至少 之一者延伸至閘極正上方區域內的薄膜電晶體，設置於^ 示區外’其中每一薄膜電晶體分別電性連接於上述閘極線 之一與短路桿及/或上述資料線之一與短路桿。此顯示器 更包括一共用線，設置於顯示區週邊，且電性連接於短: 桿。Client's Docket No.: AU0511067 TT^s Docket No: 0632-A50689TW/final/david 13 200810123 The present invention further provides a display comprising a substrate defining a display area; a plurality of gate lines arranged at On the substrate; a plurality of data lines are disposed on the substrate. The gate lines and the data intersect each other to define a plurality of pixel regions, and each of the pixel regions has at least one switching element (switch Device); at least one shorting bar (sh〇rtin bar) disposed at the periphery of the display area; and a plurality of source and drain electrodes at least one of the thin film transistors not extending to the upper portion of the gate, disposed in the display area In addition, each of the thin film transistors is electrically connected to one of the above gates = one of the shorting bars and/or one of the above data lines and the shorting bar. This display is crying • It also includes a common line, which is placed around the display area and electrically connected to the shorting bar. The invention further provides a display comprising a substrate defining a display area; a plurality of gate lines disposed on the substrate; a plurality of data lines disposed on the substrate, the gate lines and The data lines intersect each other to define a plurality of pixel regions, and each of the pixel regions has at least one switch device at least one shorting bar (sh〇rtin bar) disposed at a periphery of the display area; and a plurality of sources At least one of the pole and the drain extends to the thin film transistor in the region directly above the gate, and is disposed outside the display region, wherein each of the thin film transistors is electrically connected to one of the gate lines and the shorting rod and / or one of the above data lines with a shorting rod. The display further includes a common line disposed around the display area and electrically connected to the short: rod.
本發明之顯示器可包括電激發光顯示署 (electroluminescence disPlay)、發光二極體顯示多 (light-emitting diode display)、場發射顯示罗 (field-emission display)、奈米碳管顯示器（nan〇_carb〇BThe display of the present invention may include an electroluminescence disPlay, a light-emitting diode display, a field-emission display, and a carbon nanotube display (nan〇_ Carb〇B
Clientrs Docket No.:AU0511067 TTf s Docket No: 0632-A50689TW/final/david 14 200810123 tube display)、液晶顯示器（HqUid crystal display)或電聚顯 示器（plasma display)等。 本發明薄膜電晶體可連接成二極體式（diode-type)的 薄膜電sa體亦可連接成浮置閘極式（fi〇ating gate)的薄膜 電晶體。以下即以第5及第6圖分別作說明。請參閱第5 圖，說明本發明包含二極體式薄膜電晶體的顯示器電路設 计示意圖。複數條閘極線4與資料線5彼此垂直相交設置 於基底9上，以定義出複數個晝素區n並分別耦接至位 於顯示區週邊的驅動電路6及7。開關元件2，設置於晝 ⑩素區11内並耦接至構成該晝素區的閘極線及資料線。晝 素έ 11内更包括與開關元件2耦接的電容元件3。 複數個源極與汲極至少之一者未延伸或延伸至閘極 正上方區域内的薄膜電晶體1與短路桿13，設置於顯示 區週邊，其中每一薄膜電晶體1分別電性連接於上述複數 條閘極線4之一、另一薄膜電晶體1與短路桿j 3及/或上 述複數條資料線5之一、另一薄臈電晶體丨與短路桿13。 上述二極體式薄膜電晶體的起始電壓大約介於2〇〜4〇 參伏特，其漏電流低於1E_6安培，.功率消耗低於2E-5瓦。 請參閱第6圖，說明本發明包含浮置閘極式薄膜電晶 體的顯示器電路設計示意圖。複數條閘極線4盎資料線5 彼此垂直相交設置於基底9上，以定義出複數個晝素區 11並分別麵接至位於顯示區週邊的驅動電路6及7。開關 元件2 ’没置於晝素H 11内並耦接至構成該晝素區的閘 極線及資料、線。晝素區11 Θ i包括與開關元件2輕接的 電容元件3 〇 複數個源極與汲極至少之一者未延伸或延伸至，閑極Clientrs Docket No.: AU0511067 TTf s Docket No: 0632-A50689TW/final/david 14 200810123 tube display), liquid crystal display (HqUid crystal display) or plasma display. The thin film transistor of the present invention can be connected as a diode-type thin film electric sa body or as a floating gate transistor. The following is a description of each of the fifth and sixth figures. Referring to Figure 5, there is shown a schematic diagram of a display circuit design comprising a diode thin film transistor of the present invention. The plurality of gate lines 4 and the data lines 5 are perpendicularly intersected with each other on the substrate 9 to define a plurality of pixel regions n and are respectively coupled to the driving circuits 6 and 7 located around the periphery of the display region. The switching element 2 is disposed in the NMOS region 11 and coupled to the gate line and the data line constituting the pixel region. The capacitor element 3 coupled to the switching element 2 is further included in the anode 11 . a plurality of thin film transistors 1 and shorting bars 13 which are not extended or extended to a region directly above the gate, and are disposed at a periphery of the display region, wherein each of the thin film transistors 1 is electrically connected to each other One of the plurality of gate lines 4, the other thin film transistor 1 and the shorting rod j 3 and/or one of the plurality of data lines 5, the other thin transistor 丨 and the shorting bar 13. The starting voltage of the above-mentioned diode-type thin film transistor is about 2 〇 to 4 参 volts, and the leakage current is lower than 1E_6 amps, and the power consumption is less than 2E-5 watts. Referring to Figure 6, there is shown a schematic diagram of a display circuit design of the present invention comprising a floating gate thin film transistor. A plurality of gate lines 4 angstrom data lines 5 are vertically intersected with each other and disposed on the substrate 9 to define a plurality of pixel regions 11 and respectively face the drive circuits 6 and 7 located around the periphery of the display region. The switching element 2' is not placed in the halogen H 11 and is coupled to the gate lines and data and lines constituting the pixel region. The halogen element 11 Θ i includes a capacitive element 3 that is lightly connected to the switching element 2 〇 at least one of the plurality of sources and the drain is not extended or extended to the idle pole
Clientfs Docket No.:AU0511067 TTrs Docket No: 0632-A50689TW/final/david 15 200810123 正上方區域内的薄膜電晶體1與短路桿13，設置於顯示 區週邊，其中每一薄膜電晶體1分別電性連接於上述複數 條閘極線4之一與短路桿13及/或上述複數條資料線5之 一與短路桿13。 上述浮置閘極式薄膜電晶體的起始電壓大約介於 60〜100伏特，其漏電流低於1£-7安培，功率消耗低於 6E-6 瓦。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 • 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Clientfs Docket No.: AU0511067 TTrs Docket No: 0632-A50689TW/final/david 15 200810123 The thin film transistor 1 and the shorting bar 13 in the upper area are disposed around the display area, and each of the thin film transistors 1 is electrically connected And one of the plurality of gate lines 4 and the shorting bar 13 and/or one of the plurality of data lines 5 and the shorting bar 13. The floating gate type thin film transistor has an initial voltage of about 60 to 100 volts, a leakage current of less than 1 -7 amps, and a power consumption of less than 6E-6 watts. While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
Clients Docket -No. :AU0511067 16 TT/s Docket No: 0632-A50689TW/final/david 200810123 【圖式簡單說明】 第1A〜1C及第2圖係為本發明BCE薄膜電晶體*士構 之剖面示意圖。 第3A〜3C及第4圖係為本發明姓刻終止薄 膜電晶體結構之剖面示意圖。 " 第5圖係為本發明包含二極體式薄膜電晶體之顯示界 電路設計示意圖。 ^ 弟6圖係為本發明包含浮置閘極式薄膜電晶體之顯矛 φ 器電路設計示意圖。 ' 【主要元件符號說明】 10、50、100、101、501、1001 〜薄膜電晶體； 12、52、120、121、521、1201 〜基板； 14、54、140、141、541、1401 〜閘極； 16、56、160、161、561、1601 〜絕緣層； 20、60、200、201、601、2001〜通道層； 22、62、220、221、62卜2201〜歐姆接觸層； 馨 24、64、240、241、641、2401〜半導體層； 26、66、260、261、661、2601〜源極； 28、68、280、281、681、2801〜没極； 30、70、300、301、701、3001〜間隔； 32、72、320、321、721、3201〜通道區； 34、74、340、341、74卜3401〜閘極正上方區域； 211、611、2101〜蝕刻終止層； W1〜源/没極與閘極之水平距離；Clients Docket -No. :AU0511067 16 TT/s Docket No: 0632-A50689TW/final/david 200810123 [Simplified Schematic] 1A to 1C and 2 are schematic cross-sectional views of the BCE thin film transistor of the present invention. . 3A to 3C and Fig. 4 are schematic cross-sectional views showing the structure of the electrode film of the invention. " Fig. 5 is a schematic view showing the circuit design of the display boundary including the diode type thin film transistor of the present invention. ^Di 6 is a schematic diagram of the circuit design of the display φ φ device including the floating gate thin film transistor of the present invention. ' [Main component symbol description] 10, 50, 100, 101, 501, 1001 ~ thin film transistor; 12, 52, 120, 121, 521, 1201 ~ substrate; 14, 54, 140, 141, 541, 1401 ~ gate Pole; 16, 56, 160, 161, 561, 1601 ~ insulating layer; 20, 60, 200, 201, 601, 2001 ~ channel layer; 22, 62, 220, 221, 62 b 2201 ~ ohmic contact layer; , 64, 240, 241, 641, 2401 ~ semiconductor layer; 26, 66, 260, 261, 661, 2601 ~ source; 28, 68, 280, 281, 681, 2801 ~ no pole; 30, 70, 300, 301, 701, 3001~interval; 32, 72, 320, 321, 721, 3201~channel area; 34, 74, 340, 341, 74b 3401~ directly above the gate; 211, 611, 2101~ etch stop layer ; W1 ~ source / no pole and the horizontal distance of the gate;
Clientf s Docket No.:AU0511067 TTfs Docket No: 0632-A50689TW/final/david 17 200810123 W2〜源/汲極與閘極之重疊寬度; 1、15〜薄膜電晶體； 2〜開關元件； 3〜電容元件； 4〜閘極線； 5〜貢料線， 6、7〜驅動電路； 8〜共用線； 9〜基底； 11〜晝素區； 13〜短路桿。Clientf s Docket No.: AU0511067 TTfs Docket No: 0632-A50689TW/final/david 17 200810123 W2 ~ source / drain and gate overlap width; 1, 15 ~ thin film transistor; 2 ~ switching element; 3 ~ capacitive element ; 4 ~ gate line; 5 ~ tribute line, 6, 7 ~ drive circuit; 8 ~ shared line; 9 ~ base; 11 ~ 昼 区 area; 13 ~ shorting rod.
Clientf s Docket No.:AU0511067 TT^ s Docket No : 0632-A50 68 9TW/final/davidClientf s Docket No.: AU0511067 TT^ s Docket No : 0632-A50 68 9TW/final/david
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI450398B (en) * | 2011-12-30 | 2014-08-21 | Hon Hai Prec Ind Co Ltd | Thin film transistor |
| TWI667780B (en) * | 2018-08-02 | 2019-08-01 | 友達光電股份有限公司 | Display panel |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI450398B (en) * | 2011-12-30 | 2014-08-21 | Hon Hai Prec Ind Co Ltd | Thin film transistor |
| TWI667780B (en) * | 2018-08-02 | 2019-08-01 | 友達光電股份有限公司 | Display panel |
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| TWI301671B (en) | 2008-10-01 |
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