WO2018205332A1 - 液晶显示面板及液晶显示装置 - Google Patents

液晶显示面板及液晶显示装置 Download PDF

Info

Publication number
WO2018205332A1
WO2018205332A1 PCT/CN2017/087783 CN2017087783W WO2018205332A1 WO 2018205332 A1 WO2018205332 A1 WO 2018205332A1 CN 2017087783 W CN2017087783 W CN 2017087783W WO 2018205332 A1 WO2018205332 A1 WO 2018205332A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
sub
row
liquid crystal
scan line
Prior art date
Application number
PCT/CN2017/087783
Other languages
English (en)
French (fr)
Inventor
陈宥烨
何振伟
吴宇
何涛
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2018205332A1 publication Critical patent/WO2018205332A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel and a liquid crystal display device having the same.
  • the existing liquid crystal display panel In order to reduce the cost, the existing liquid crystal display panel often adopts a three-dimensional transistor (Tri-gate) structure. As shown in FIG. 1 , the existing liquid crystal display panel includes a plurality of sub-pixels arranged in an array, and the sub-pixel includes a red sub-pixel.
  • the pixel R, the green sub-pixel G, and the blue sub-pixel B, the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R in each column sub-pixel are alternately and repeatedly arranged in an order, and when the architecture is driven, the second row is used.
  • the N-5 row sub-pixel, the N-3th row sub-pixel, the N-4th row sub-pixel, the N-2th row sub-pixel, and the N-th row sub-pixel are sequentially driven in sequence, and the liquid crystal display panel adopting the driving method , can reduce the high and low level switching frequency of the scan line.
  • FIG. 2 is a schematic diagram of a sub-pixel structure of a conventional liquid crystal display panel. As shown in FIG. 2, when driving is performed, the second row of sub-pixels is first driven. At this time, the scanning line Gn corresponding to the third row of sub-pixels connected to the other end of the liquid crystal capacitor Cst of the second row of sub-pixels is turned off.
  • the charge in the sub-pixel of the second row is conserved, and then when the sub-pixel is driven for the third row, the scan line Gn corresponding to the sub-pixel of the third row is turned on, and the coupling function of the storage capacitor Cst of the sub-pixel of the second row is made.
  • the voltage of the second row of sub-pixels is pulled down, which in turn causes flicker or image afterimage (image) Abnormal display of sticking), and this phenomenon is repeated in the second row subpixel, the fifth row subpixel, the eighth row subpixel, ..., the N-5th row subpixel, and the N-2th row subpixel Up, thereby affecting the display quality of the liquid crystal display panel.
  • the invention provides a liquid crystal display panel, which reduces the storage capacitor value corresponding to the abnormal display row, thereby reducing the degree that the voltage is pulled down, so as to solve the coupling effect of the storage capacitor in the sub-pixel of the existing liquid crystal display panel, so that the voltage The technical problem that is pulled down, which in turn affects the display effect.
  • the present invention provides a liquid crystal display panel including a data line, a scan line, and a pixel unit formed by intersection of a data line and a scan line, the pixel unit including a first sub-pixel row driven by a high level scan and a low level scan driving a second sub-pixel row, the first sub-pixel row and the second sub-pixel row being staggered;
  • the scanning order of the scan lines is the 3n+2th row, the 3n+1th row, and the 3n+3th row, and n is an increasing integer starting from 0 to reduce the high-low level switching frequency of the scan line;
  • Each of the sub-pixels includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor.
  • the gate of the thin film transistor is connected to a corresponding scan line.
  • the source of the thin film transistor is connected to a corresponding data line.
  • the drain of the transistor is connected to one end of the liquid crystal capacitor and one end of the storage capacitor, and the other end of the liquid crystal capacitor is connected to the common electrode, and the other end of the storage capacitor corresponds to the next sub-pixel.
  • the capacitance value of the storage capacitor corresponding to the 3n+2th row scan line is smaller than the capacitance value of the storage capacitor corresponding to the 3n+1th row and the 3n+3th row scan line;
  • the distance between the pixel electrode of the sub-pixel corresponding to the 3n+2th scan line and the corresponding scan line is greater than the distance between the pixel electrode of the other sub-pixel and the corresponding scan line.
  • the area of the pixel electrode of the sub-pixel corresponding to the 3n+2th row scan line is smaller than the area of the pixel electrode corresponding to the 3n+1th row and the 3n+3th row of scan lines.
  • the sub-pixel corresponding to the 3n+2th row scan line has a pixel electrode close to the side of the storage capacitor, and converges inward to form a circular arc side.
  • each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that are longitudinally distributed.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially driven. Scan sequentially.
  • the first sub-pixel is a blue sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a red sub-pixel
  • the present invention also provides another liquid crystal display panel including a data line, a scan line, and a pixel unit formed by intersection of a data line and a scan line, the pixel unit including a first sub-pixel row driven by a high level scan and a low level Scanning a second sub-pixel row of the driving, the first sub-pixel row and the second sub-pixel row being staggered;
  • the scanning order of the scan lines is the 3n+2th row, the 3n+1th row, and the 3n+3th row, and n is an increasing integer starting from 0 to reduce the high-low level switching frequency of the scan line;
  • Each of the sub-pixels includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor.
  • the gate of the thin film transistor is connected to a corresponding scan line.
  • the source of the thin film transistor is connected to a corresponding data line.
  • the drain of the transistor is connected to one end of the liquid crystal capacitor and one end of the storage capacitor, and the other end of the liquid crystal capacitor is connected to the common electrode, and the other end of the storage capacitor corresponds to the next sub-pixel.
  • the capacitance value of the storage capacitor corresponding to the 3n+2th row scan line is smaller than the capacitance value of the storage capacitor corresponding to the 3n+1th row and the 3n+3th row scan line.
  • the area of the pixel electrode of the sub-pixel corresponding to the 3n+2th row scan line is smaller than the area of the pixel electrode corresponding to the 3n+1th row and the 3n+3th row of scan lines.
  • the sub-pixel corresponding to the 3n+2th row scan line has a pixel electrode close to the side of the storage capacitor, and converges inward to form a circular arc side.
  • each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that are longitudinally distributed.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially driven. Scan sequentially.
  • the first sub-pixel is a blue sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a red sub-pixel
  • a liquid crystal display device includes a backlight module and a liquid crystal display panel disposed opposite to each other;
  • the liquid crystal display panel includes: a data line, a scan line, and a pixel unit formed by crossing the data line and the scan line, the pixel unit including a first sub-pixel row driven by a high level scan and a second sub-pixel row driven by a low level scan a sub-pixel row, the first sub-pixel row and the second sub-pixel row are staggered;
  • the scanning order of the scan lines is the 3n+2th row, the 3n+1th row, and the 3n+3th row, and n is an increasing integer starting from 0 to reduce the high-low level switching frequency of the scan line;
  • Each of the sub-pixels includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor.
  • the gate of the thin film transistor is connected to a corresponding scan line.
  • the source of the thin film transistor is connected to a corresponding data line.
  • the drain of the transistor is connected to one end of the liquid crystal capacitor and one end of the storage capacitor, and the other end of the liquid crystal capacitor is connected to the common electrode, and the other end of the storage capacitor corresponds to the next sub-pixel.
  • the capacitance value of the storage capacitor corresponding to the 3n+2th row scan line is smaller than the capacitance value of the storage capacitor corresponding to the 3n+1th row and the 3n+3th row scan line.
  • the area of the pixel electrode of the sub-pixel corresponding to the 3n+2th row scan line is smaller than the area of the pixel electrode corresponding to the 3n+1th row and the 3n+3th row of scan lines.
  • the sub-pixel corresponding to the 3n+2th row scan line has a pixel electrode close to the side of the storage capacitor, and converges inward to form a circular arc side.
  • the distance between the pixel electrode of the sub-pixel corresponding to the 3n+2th scan line and the corresponding scan line is greater than the distance between the pixel electrode of the other sub-pixel and the corresponding scan line.
  • the invention has the beneficial effects that the liquid crystal display panel of the present invention solves the existing liquid crystal by reducing the storage capacitor value corresponding to the abnormal display row and further reducing the voltage being pulled lower than the conventional liquid crystal display panel.
  • the storage capacitors in the sub-pixels of the display panel are coupled such that the corresponding sub-pixel voltages are pulled low, thereby affecting the technical problem of the display effect.
  • FIG. 1 is a schematic structural view of a conventional liquid crystal display panel
  • FIG. 2 is a schematic structural view of a sub-pixel of a conventional liquid crystal display panel
  • FIG. 3 is a schematic structural view of a sub-pixel of a liquid crystal display panel of the present invention.
  • FIG. 4 is another schematic structural view of a sub-pixel of a liquid crystal display panel of the present invention.
  • the present invention is directed to a conventional liquid crystal display panel.
  • the voltage of a portion of the row of sub-pixels is pulled down due to the coupling effect of the storage capacitors of the partial row of sub-pixels, thereby causing an abnormality of image flicker or image sticking.
  • the embodiment of the present invention can solve the technical defect.
  • the present invention provides a liquid crystal display panel comprising a plurality of data lines, scan lines, and pixel units formed by intersections of data lines and scan lines, the pixel units including a first sub-pixel row driven by a high level scan and a low level scan Driving the second sub-pixel row, the first sub-pixel row and the second sub-pixel row are alternately arranged; the scan line scanning order is 3n+2 rows, 3n+1 rows, and 3n+3 In the row, n is an increasing integer starting from 0; wherein the 3n+2th row is used to indicate row-level scan lines of 2, 5, 8, ..., 32, and the 3n+1th row is used to indicate 1, 4, 7, ..., 31 and other row-level scan lines, the 3n + 3 lines are used to indicate the row-level scan lines of 3, 6, 9, ..., 33, etc., when driving, first scan the second row of sub-pixels, and then follow Scan 1, 3, 5, and then scan the 4, 6, 8 sequential misalignment scan; divide the sub-pixel into several sub-pixel
  • Each of the sub-pixels includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor.
  • the gate of the thin film transistor is connected to a corresponding scan line.
  • the source of the thin film transistor is connected to a corresponding data line.
  • the drain of the transistor is connected to one end of the liquid crystal capacitor and one end of the storage capacitor, and the other end of the liquid crystal capacitor is connected to the common electrode, and the other end of the storage capacitor corresponds to the next sub-pixel. Scan line connection.
  • the storage capacitor in each sub-pixel is connected to the scan line of the next sub-pixel.
  • the Gn+1 line of the scan line is turned off before Gn, and when Gn is turned off, the connection is connected to Gn. Due to the coupling effect, the capacitor pulls down the pixel voltage of Gn+1. These phenomena appear on the pixel corresponding to the 3n+2th scan line, and the positive and negative voltages are pulled low, causing these scan lines to correspond to the common electrode of the pixel. The optimum voltage value is shifted down, which causes the problem of flicker and afterimage.
  • the capacitance value of the storage capacitor corresponding to the 3n+2th row of scan lines the pixel voltage of Gn+1 can be lowered to a lower degree, thereby avoiding The above problems have arisen.
  • a schematic diagram of a sub-pixel structure provided by the embodiment reduces the capacitance value of the corresponding storage capacitor by reducing the pixel electrode area of the pixel.
  • the first sub-pixel 302 and the second sub-pixel 303 are formed by the data line 301 and the scan line, and include a first scan line 304, a second scan line 305 and a third scan line 306.
  • the first thin film transistor T1 The gate is connected to the first scan line 304, the source is connected to the data line 301, the drain is connected to the first pixel electrode 307, and the first storage capacitor 308 is connected between the first pixel electrode 307 and the second scan line 305.
  • the second thin film transistor is connected. T2, the gate is connected to the second scan line 305, the source is connected to the data line 301, the drain is connected to the second pixel electrode 310, and the second storage capacitor 311 is connected between the second pixel electrode 310 and the third scan line 306.
  • the two sub-pixels 303 correspond to the 3n+2th row scan line, and the pixel electrode area in the second sub-pixel 303 is smaller than the pixel electrode area in the other sub-pixels.
  • the second pixel electrode 310 is closer to the side of the second storage capacitor 311, and converges inward to form a circular arc side, thereby reducing the The area of the two-pixel electrode 310 reduces the capacitance value of the storage capacitor.
  • FIG. 4 another schematic diagram of the sub-pixel structure provided by the embodiment reduces the capacitance value of the corresponding storage capacitor by increasing the distance between the pixel electrode and the corresponding scan line.
  • the first sub-pixel 402 and the second sub-pixel 403 are formed by the data line 401 and the scan line, and include a first scan line 404, a second scan line 405 and a third scan line 406.
  • the first thin film transistor T1 The gate is connected to the first scan line 404, the source is connected to the data line 401, the drain is connected to the first pixel electrode 407, and the first storage capacitor 408 is connected between the first pixel electrode 407 and the second scan line 405.
  • the second thin film transistor is connected. T2, the gate is connected to the second scan line 405, the source is connected to the data line 401, the drain is connected to the second pixel electrode 410, and the second storage electrode 411 is connected between the second pixel electrode 410 and the third scan line 406.
  • the two sub-pixels 403 correspond to the 3n+2th row of scan lines, the pixel electrodes of the second sub-pixels 403 are disposed away from the third scan line 406, and further, the second pixel electrode 410 is moved away from the third scan line 406.
  • the direction is offset by a certain distance, thereby increasing the distance between the pixel electrode and the corresponding scan line, and reducing the capacitance value of the corresponding storage capacitor.
  • the present invention further provides a liquid crystal display device including a backlight module and a liquid crystal display panel disposed opposite to each other; the liquid crystal display panel includes: a data line, a scan line, and a pixel formed by the intersection of the data line and the scan line.
  • the pixel unit includes a first sub-pixel row driven by a high level scan and a second sub-pixel row driven by a low level scan, the first sub-pixel row and the second sub-pixel row being staggered;
  • the scan order of the scan lines is the 3n+2th row, the 3n+1th row, and the 3n+3th row, and n is an increasing integer starting from 0 to reduce the high-low transition frequency of the scan line;
  • each sub- Each of the pixels includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor.
  • the gate of the thin film transistor is connected to a corresponding scan line, and a source of the thin film transistor is connected to a corresponding data line, and a drain of the thin film transistor Connected to one end of the liquid crystal capacitor and one end of the storage capacitor, the other end of the liquid crystal capacitor is connected to the common electrode, and the other end of the storage capacitor is next to the next Corresponding to the pixel connected to the scan line; wherein the first capacitor 3n + 2 scan line value corresponding to the storage capacitor, the capacitance value smaller than 3n + 3n + 1 row. 3 and second scanning lines corresponding to the storage capacitor.
  • the working principle of the liquid crystal display device of the preferred embodiment is the same as that of the liquid crystal display panel of the preferred embodiment.
  • the invention has the beneficial effects that the liquid crystal display panel of the present invention solves the existing liquid crystal by reducing the storage capacitor value corresponding to the abnormal display row and further reducing the voltage being pulled lower than the conventional liquid crystal display panel.
  • the storage capacitors in the sub-pixels of the display panel are coupled such that the corresponding sub-pixel voltages are pulled low, thereby affecting the technical problem of the display effect.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶显示面板，其包括高电平扫描驱动的第一子像素行及低电平扫描驱动的第二子像素行，第一子像素行与第二子像素行交错设置，扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，其中第3n+2行扫描线对应的存储电容（311,411）的电容值，小于其他扫描线对应的存储电容（308,408）的电容值。通过降低异常显示行对应的存储电容（311,411）的电容值，进而降低电压被拉低的程度，避免了画面闪烁或图像残影。

Description

液晶显示面板及液晶显示装置 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示面板及具有所述液晶显示面板的液晶显示装置。
 背景技术
现有的液晶显示面板为了降低成本常常采用三维晶体管（Tri-gate）架构，如图1所示，为现有的液晶显示面板，包括阵列排布的多个子像素，所述子像素包括红色子像素R、绿色子像素G以及蓝色子像素B，每一列子像素中蓝色子像素B、绿色子像素G、及红色子像素R依次交替重复排列，该架构驱动时，采用第2行子像素、第1行子像素、第3行子像素、第5行子像素、第4行子像素、第6行子像素、第8行子像素、……、第N-7行子像素、第N-5行子像素、第N-3行子像素、第N-4行子像素、第N-2行子像素、及第N行子像素的顺序依次驱动，采用此驱动方式的液晶显示面板，可以降低扫描线的高低电平转换频率。
而为了进一步提升该架构的液晶显示面板的穿透率，通常会采用Cst on gate的像素设计，参阅图2，图2为现有的液晶显示面板的子像素结构示意图。如图2所示，在进行驱动时，首先对第2行子像素进行驱动，此时，与第2行子像素的液晶电容Cst的另一端相连的第3行子像素对应的扫描线Gn关闭，此时第2行子像素内的电荷守恒，随后对第3行子像素驱动时，打开第3行子像素对应的扫描线Gn，由于第2行子像素的存储电容Cst的耦合作用，使得第2行子像素的电压被拉低，进而带来画面闪烁（Flicker）或图像残影（image sticking）的异常显示，而这种现象都重复出现在第2行子像素、第5行子像素、第8行子像素、……、第N-5行子像素以及第N-2行子像素上，从而影响液晶显示面板的显示品质。
综上所述，需要提供一种新的液晶显示面板以解决上述技术缺陷。
 技术问题
本发明提供一种液晶显示面板，通过降低异常显示行对应的存储电容值，进而降低电压被拉低的程度，以解决现有的液晶显示面板的子像素中的存储电容受耦合作用，使得电压被拉低，进而影响显示效果的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种液晶显示面板，包括数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；
所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；
每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接；
其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值；
所述第3n+2行扫描线对应的子像素的像素电极与相应的扫描线之间的距离，大于其他子像素的像素电极与相应的扫描线之间的距离。。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素的像素电极的面积，小于第3n+1行以及第3n+3行扫描线对应的像素电极的面积。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素，其像素电极靠近所述存储电容的一侧，向内收敛形成圆弧边。
根据本发明一优选实施例，每一像素包括纵向分布的第一子像素、第二子像素以及第三子像素，驱动时，按照第一子像素、第二子像素、第三子像素的顺序逐次进行扫描。
根据本发明一优选实施例，所述第一子像素为蓝色子像素，所述第二子像素为绿色子像素，所述第三子像素为红色子像素。
本发明还提供另一种液晶显示面板，包括数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；
所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；
每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接；
其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素的像素电极的面积，小于第3n+1行以及第3n+3行扫描线对应的像素电极的面积。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素，其像素电极靠近所述存储电容的一侧，向内收敛形成圆弧边。
根据本发明一优选实施例，每一像素包括纵向分布的第一子像素、第二子像素以及第三子像素，驱动时，按照第一子像素、第二子像素、第三子像素的顺序逐次进行扫描。
根据本发明一优选实施例，所述第一子像素为蓝色子像素，所述第二子像素为绿色子像素，所述第三子像素为红色子像素。
依据本发明的上述目的，提出一种液晶显示装置，包括相对设置的背光模组及液晶显示面板；
所述液晶显示面板包括：数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；
所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；
每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接；
其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素的像素电极的面积，小于第3n+1行以及第3n+3行扫描线对应的像素电极的面积。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素，其像素电极靠近所述存储电容的一侧，向内收敛形成圆弧边。
根据本发明一优选实施例，所述第3n+2行扫描线对应的子像素的像素电极与相应的扫描线之间的距离，大于其他子像素的像素电极与相应的扫描线之间的距离。
 有益效果
本发明的有益效果为：相较于现有的液晶显示面板，本发明的液晶显示面板，通过降低异常显示行对应的存储电容值，进而降低电压被拉低的程度，解决了现有的液晶显示面板的子像素中的存储电容受耦合作用，使得相应子像素电压被拉低，进而影响显示效果的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有液晶显示面板结构示意图；
图2为现有液晶显示面板子像素结构示意图；
图3为本发明液晶显示面板子像素一结构示意图；
图4为本发明液晶显示面板子像素又一结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的液晶显示面板，在特定扫描方式下，由于部分行子像素的存储电容的耦合作用，使得部分行子像素的电压被拉低，进而带来画面闪烁或图像残影的异常显示问题，本发明实施例能够解决该技术缺陷。
本发明提供一种液晶显示面板，包括若干数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数；其中，第3n+2行用于指示2、5、8、……、32等行级扫描线，第3n+1行用于指示1、4、7、……、31等行级扫描线，第3n+3行用于指示3、6、9、……、33等行级扫描线，在驱动时，先扫描第2行子像素，随后按照先扫描1、3、5，然后扫描4、6、8的顺序错位扫描；将子像素分成若干子像素组进行扫描，像素的充放电频率降为之前的三分之一，从而降低所述扫描线的高低电平的转换频率。
每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接。
在Cst on gate像素结构中，每一个子像素中的存储电容连接下一子像素的扫描线，当采用上述扫描方式时，扫描线的Gn+1行先于Gn关闭，当Gn关闭时，连接于Gn的存储电容因耦合作用，将Gn+1的像素电压拉低，这些现象会出现在第3n+2行扫描线对应的像素上，正负电压都被拉低，导致这些扫描线对应像素的公共电极的最佳电压值下移，导致出现闪烁和残影的问题，通过降低第3n+2行扫描线对应的存储电容的电容值，可使得Gn+1的像素电压被拉低的程度降低，进而避免上述问题出现。
如图3所示，为本实施例提供的一子像素结构示意图，通过减小像素的像素电极面积来降低相应的存储电容的电容值。
图中包括由数据线301与扫描线围合成的第一子像素302及第二子像素303，包括有第一扫描线304、第二扫描线305及第三扫描线306，第一薄膜晶体管T1，其栅极连接第一扫描线304，源极连接数据线301，漏极连接第一像素电极307，第一像素电极307与第二扫描线305间连接第一存储电容308；第二薄膜晶体管T2，其栅极连接第二扫描线305，源极连接数据线301，漏极连接第二像素电极310，第二像素电极310与第三扫描线306间连接第二存储电容311，所述第二子像素303对应于第3n+2行扫描线，所述第二子像素303中的像素电极面积小于其他子像素中的像素电极面积。
进一步，为了减小像素电极面积，并尽可能地保证开口率的情况下，将第二像素电极310靠近所述第二存储电容311的一侧，向内收敛形成圆弧边，进而减小第二像素电极310的面积，降低存储电容的电容值。
如图4所示，为本实施例提供的又一子像素结构示意图，通过增大像素电极与相应的扫描线之间的距离，来降低相应的存储电容的电容值。
图中包括由数据线401与扫描线围合成的第一子像素402及第二子像素403，包括有第一扫描线404、第二扫描线405及第三扫描线406，第一薄膜晶体管T1，其栅极连接第一扫描线404，源极连接数据线401，漏极连接第一像素电极407，第一像素电极407与第二扫描线405间连接第一存储电容408；第二薄膜晶体管T2，其栅极连接第二扫描线405，源极连接数据线401，漏极连接第二像素电极410，第二像素电极410与第三扫描线406间连接第二存储电容411，所述第二子像素403对应于第3n+2行扫描线，所述第二子像素403中的像素电极远离第三扫描线406设置，进一步，将所述第二像素电极410向远离第三扫描线406的方向偏移一定距离，从而增大像素电极与相应的扫描线之间的距离，降低相应的存储电容的电容值。
依据上述发明目的，本发明还提出一种液晶显示装置，包括相对设置的背光模组及液晶显示面板；所述液晶显示面板包括：数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的扫描线连接，所述薄膜晶体管的源极与相应的数据线连接，所述薄膜晶体管的漏极与所述液晶电容的一端以及所述存储电容的一端连接，所述液晶电容的另一端与所述公共电极连接，所述存储电容的另一端与下一个子像素所对应的扫描线连接；其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值。
本优选实施例的液晶显示装置的工作原理跟上述优选实施例的液晶显示面板的工作原理一致，具体可参考上述优选实施例的液晶显示面板的工作原理，此处不再做赘述。
本发明的有益效果为：相较于现有的液晶显示面板，本发明的液晶显示面板，通过降低异常显示行对应的存储电容值，进而降低电压被拉低的程度，解决了现有的液晶显示面板的子像素中的存储电容受耦合作用，使得相应子像素电压被拉低，进而影响显示效果的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种液晶显示面板，其包括数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；
    所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；
    每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接；
    其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值；
    所述第3n+2行扫描线对应的子像素的像素电极与相应的一所述扫描线之间的距离，大于其他子像素的像素电极与相应的扫描线之间的距离。
  2. 根据权利要求1所述的液晶显示面板，其中，所述第3n+2行扫描线对应的子像素的像素电极的面积，小于第3n+1行以及第3n+3行扫描线对应的像素电极的面积。
  3. 根据权利要求2所述的液晶显示面板，其中，所述第3n+2行扫描线对应的子像素，其像素电极靠近所述存储电容的一侧，向内收敛形成圆弧边。
  4. 根据权利要求1所述的液晶显示面板，其中，每一像素包括纵向分布的第一子像素、第二子像素以及第三子像素，驱动时，按照第一子像素、第二子像素以及第三子像素的顺序逐次进行扫描。
  5. 根据权利要求4所述的液晶显示面板，其中，所述第一子像素为蓝色子像素，所述第二子像素为绿色子像素，所述第三子像素为红色子像素。
  6. 一种液晶显示面板，其包括数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；
    所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；
    每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接；
    其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值。
  7. 根据权利要求6所述的液晶显示面板，其中，所述第3n+2行扫描线对应的子像素的像素电极的面积，小于第3n+1行以及第3n+3行扫描线对应的像素电极的面积。
  8. 根据权利要求7所述的液晶显示面板，其中，所述第3n+2行扫描线对应的子像素，其像素电极靠近所述存储电容的一侧，向内收敛形成圆弧边。
  9. 根据权利要求6所述的液晶显示面板，其中，每一像素包括纵向分布的第一子像素、第二子像素以及第三子像素，驱动时，按照第一子像素、第二子像素以及第三子像素的顺序逐次进行扫描。
  10. 根据权利要求9所述的液晶显示面板，其中，所述第一子像素为蓝色子像素，所述第二子像素为绿色子像素，所述第三子像素为红色子像素。
  11. 一种液晶显示装置，其中，包括相对设置的背光模组及液晶显示面板；
    所述液晶显示面板包括：数据线、扫描线以及由数据线和扫描线交叉构成的像素单元，所述像素单元包括高电平扫描驱动的第一子像素行以及低电平扫描驱动的第二子像素行，所述第一子像素行和所述第二子像素行交错设置；
    所述扫描线的扫描顺序为第3n+2行、第3n+1行以及第3n+3行，n为从0开始的递增的整数，以降低所述扫描线的高低电平转换频率；
    每个子像素均包括一薄膜晶体管、一液晶电容以及一存储电容，所述薄膜晶体管的栅极与相应的一扫描线连接，所述薄膜晶体管的源极与相应的一数据线连接，所述薄膜晶体管的漏极与一所述液晶电容的一端以及一所述存储电容的一端连接，所述液晶电容的另一端与公共电极连接，所述存储电容的另一端与下一个子像素所对应的一扫描线连接；
    其中，第3n+2行扫描线对应的存储电容的电容值，小于第3n+1行以及第3n+3行扫描线对应的存储电容的电容值。
  12. 根据权利要求11所述的液晶显示装置，其中，所述第3n+2行扫描线对应的子像素的像素电极的面积，小于第3n+1行以及第3n+3行扫描线对应的像素电极的面积。
  13. 根据权利要求12所述的液晶显示装置，其中，所述第3n+2行扫描线对应的子像素，其像素电极靠近所述存储电容的一侧，向内收敛形成圆弧边。
  14. 根据权利要求11所述的液晶显示装置，其中，所述第3n+2行扫描线对应的子像素的像素电极与相应的扫描线之间的距离，大于其他子像素的像素电极与相应的扫描线之间的距离。
PCT/CN2017/087783 2017-05-08 2017-06-09 液晶显示面板及液晶显示装置 WO2018205332A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710318327.7 2017-05-08
CN201710318327.7A CN106940505B (zh) 2017-05-08 2017-05-08 液晶显示面板及液晶显示装置

Publications (1)

Publication Number Publication Date
WO2018205332A1 true WO2018205332A1 (zh) 2018-11-15

Family

ID=59463464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/087783 WO2018205332A1 (zh) 2017-05-08 2017-06-09 液晶显示面板及液晶显示装置

Country Status (2)

Country Link
CN (1) CN106940505B (zh)
WO (1) WO2018205332A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113205747A (zh) * 2021-04-30 2021-08-03 惠科股份有限公司 阵列基板、显示面板和显示设备

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983369A (zh) * 2005-12-13 2007-06-20 群康科技(深圳)有限公司 液晶显示面板驱动电路和采用该驱动电路的液晶显示面板
US20090009673A1 (en) * 2005-03-15 2009-01-08 Sharp Kabushiki Kaisha Active Matrix Substance and Display Device Including the Same
CN101727844A (zh) * 2008-10-10 2010-06-09 华映视讯（吴江）有限公司 液晶显示器及其驱动方法
CN102866551A (zh) * 2012-10-11 2013-01-09 深圳市华星光电技术有限公司 液晶显示装置及其驱动电路
CN103941502A (zh) * 2013-12-31 2014-07-23 上海中航光电子有限公司 一种像素单元阵列、液晶显示面板及驱动方法
CN104317122A (zh) * 2014-10-10 2015-01-28 上海中航光电子有限公司 像素结构、阵列基板、显示面板和显示装置及其驱动方法
CN104992681A (zh) * 2015-07-03 2015-10-21 武汉华星光电技术有限公司 显示面板和用于显示面板的像素电路
CN105047161A (zh) * 2015-08-26 2015-11-11 京东方科技集团股份有限公司 像素单元驱动装置、方法和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101963728A (zh) * 2009-07-24 2011-02-02 瀚宇彩晶股份有限公司 液晶显示器
CN102096254B (zh) * 2010-11-04 2012-08-29 华映视讯（吴江）有限公司 液晶显示器
CN104267552A (zh) * 2014-09-24 2015-01-07 深圳市华星光电技术有限公司 阵列基板及液晶显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090009673A1 (en) * 2005-03-15 2009-01-08 Sharp Kabushiki Kaisha Active Matrix Substance and Display Device Including the Same
CN1983369A (zh) * 2005-12-13 2007-06-20 群康科技(深圳)有限公司 液晶显示面板驱动电路和采用该驱动电路的液晶显示面板
CN101727844A (zh) * 2008-10-10 2010-06-09 华映视讯（吴江）有限公司 液晶显示器及其驱动方法
CN102866551A (zh) * 2012-10-11 2013-01-09 深圳市华星光电技术有限公司 液晶显示装置及其驱动电路
CN103941502A (zh) * 2013-12-31 2014-07-23 上海中航光电子有限公司 一种像素单元阵列、液晶显示面板及驱动方法
CN104317122A (zh) * 2014-10-10 2015-01-28 上海中航光电子有限公司 像素结构、阵列基板、显示面板和显示装置及其驱动方法
CN104992681A (zh) * 2015-07-03 2015-10-21 武汉华星光电技术有限公司 显示面板和用于显示面板的像素电路
CN105047161A (zh) * 2015-08-26 2015-11-11 京东方科技集团股份有限公司 像素单元驱动装置、方法和显示装置

Also Published As

Publication number Publication date
CN106940505B (zh) 2019-11-15
CN106940505A (zh) 2017-07-11

Similar Documents

Publication Publication Date Title
WO2014023050A1 (zh) 液晶显示面板及显示装置
US7319448B2 (en) Liquid crystal display device and method for driving the same
WO2017092082A1 (zh) 阵列基板以及液晶显示装置
WO2018072287A1 (zh) 一种像素结构及液晶显示面板
WO2019119566A1 (zh) 显示面板的驱动方法及显示装置
WO2016095279A1 (zh) 一种液晶显示面板
WO2016061837A1 (zh) 用于曲面屏幕的液晶显示面板
WO2016074180A1 (zh) 阵列基板、液晶面板以及液晶显示器
WO2017015972A1 (zh) 一种液晶显示器
WO2013174109A1 (zh) 阵列基板、液晶显示面板和液晶显示装置
WO2017031790A1 (zh) 阵列基板及其驱动方法
WO2019127767A1 (zh) 显示面板的驱动方法及显示装置
WO2016176914A1 (zh) 基板及其液晶显示装置
WO2013078670A1 (zh) 液晶显示器
WO2022116310A1 (zh) 显示面板及其驱动方法
WO2016074181A1 (zh) 阵列基板、液晶面板以及液晶显示器
WO2017092137A1 (zh) 液晶显示面板的驱动方法及液晶显示面板
WO2017088268A1 (zh) 具有数据线共享架构的阵列基板
WO2017075886A1 (zh) 液晶显示设备及液晶面板与液晶面板的驱动方法
WO2017088264A1 (zh) 具有低切换频率的数据线驱动极性的阵列基板
WO2019015078A1 (zh) 一种阵列基板以及显示面板
WO2017031793A1 (zh) 一种液晶显示面板及其阵列基板
WO2019104839A1 (zh) 像素驱动架构、显示面板及显示装置
WO2017101161A1 (zh) 基于hsd结构的显示面板和显示装置
WO2018126510A1 (zh) 一种阵列基板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17909615

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17909615

Country of ref document: EP

Kind code of ref document: A1