WO2016095279A1 - 一种液晶显示面板 - Google Patents

一种液晶显示面板 Download PDF

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Publication number
WO2016095279A1
WO2016095279A1 PCT/CN2014/095587 CN2014095587W WO2016095279A1 WO 2016095279 A1 WO2016095279 A1 WO 2016095279A1 CN 2014095587 W CN2014095587 W CN 2014095587W WO 2016095279 A1 WO2016095279 A1 WO 2016095279A1
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Prior art keywords
pixel
sub
line
liquid crystal
display panel
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PCT/CN2014/095587
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English (en)
French (fr)
Inventor
陈彩琴
许哲豪
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深圳市华星光电技术有限公司
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Priority to US14/416,646 priority Critical patent/US10229643B2/en
Publication of WO2016095279A1 publication Critical patent/WO2016095279A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular to a liquid crystal display panel.
  • liquid crystal display technology With the development of liquid crystal display technology, various liquid crystal displays currently have the advantages of low cost, low power consumption and high performance.
  • the various components of the LCD panel are often integrated through precision design to ensure optimal display while reducing cost and power consumption.
  • TFT-LCD thin film transistor-liquid crystal display
  • a large number of source driving circuits and gate driving circuits are required in the liquid crystal display panel for vertical and horizontal pixel driving.
  • the cost and power consumption of the gate driver chip are relatively low, so that the number of data lines can be reduced by rationally designing the structure of the pixel array, thereby using fewer source driver chips. Further, the object of reducing the manufacturing cost and power consumption of the liquid crystal display is achieved.
  • the left and right adjacent sub-pixels of the half-source driven HSD (Half Source Driving) pixel array share one data line, so that the number of data lines is halved with respect to the number of data lines of the conventional liquid crystal driving pixel array.
  • Adjacent sub-pixels of the same row connect different scan lines, and sub-pixels of the same row separated by one sub-pixel are connected to the same scan line, such that the number of scan lines is doubled with respect to the number of scan lines of the conventional drive pixel array.
  • a 2H line inversion driving that is, a two-line inversion driving method can be employed in the HSD pixel array.
  • the polarity of the data drive signal level is inverted once during two scan cycles. Since the number of scan lines is doubled, the scan time allocated to the scan lines is reduced, so that the charging time of the sub-pixels is reduced. Further, since the data line has a certain impedance, the voltage signal causes delay distortion of the waveform during transmission, and the distortion becomes more serious at the end of the data line. This results in a difference in the charging rate between the odd column sub-pixel and the even column sub-pixel at the end of the data line. For example, the odd-numbered column image that is driven first Insufficient charging and low brightness; relatively speaking, the post-driven even-numbered sub-pixels charge better and the brightness is higher.
  • the technical problem to be solved by the present invention is to overcome the defect that the degree of brightness and darkness of the liquid crystal display panel in the prior art is not uniform.
  • an embodiment of the present application provides a liquid crystal display panel, including:
  • the pixel array being formed by orthogonally configuring a plurality of data lines and a plurality of scan lines, the plurality of scan lines including:
  • a first scan line connected to the first sub-pixel, the first scan line being turned on in a first time period after the polarity of the data line drive signal is inverted, and charging the first sub-pixel through the data line;
  • At least one second scan line respectively connected to the at least one second sub-pixel, the second scan line being turned on in a second time period after the first time period, and charging the second sub-pixel through the data line;
  • the RC delay of the second scan line is greater than the RC delay of the first scan line to compensate for the difference in charging rate between the first sub-pixel and the second sub-pixel of the data line.
  • the wiring resistance of the second scan line is greater than the wiring resistance of the first scan line.
  • the thickness of the second scan line is the same as the thickness of the first scan line, and the width of the second scan line is smaller than the width of the first scan line.
  • the data line is used to drive the first sub-pixel and the at least one second sub-pixel, and a driving signal level of the data line is periodically inverted.
  • the inversion period of the data line driving signal level is two scanning periods.
  • the inversion period of the data line driving signal level is three scanning periods.
  • the first time period after the data line signal level is inverted is equal to the time length of the second time period, and the first scan line is equal to the opening time of the at least one second scan line.
  • the polarity of the drive signal level of the data line is the same during the first time period and the second time period.
  • the driving signal level of the second scan line is equal to the driving signal level of the first scan line, such that the feedthrough on the pixel electrode of the first sub-pixel and the at least one second sub-pixel The voltage is the same.
  • the pixel array is a half source driven pixel array or a triple gate type pixel array.
  • the liquid crystal display panel provided by the embodiment of the present invention compensates for the difference of the charging rate of the data line to the sub-pixel by configuring different RC delays of the scan lines, so that the stable holding voltage values obtained by the sub-pixels after being charged by the data line are consistent, and the sub-pixel is achieved.
  • the pixels are spatially uniform in brightness and darkness, thereby eliminating bright and dark lines in the liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of an HSD liquid crystal display panel according to Embodiment 1 of the present invention.
  • FIG. 2 is a waveform diagram of driving signal voltages on a data line and a scanning line of an HSD panel in the prior art
  • FIG. 3 is a waveform diagram of a pixel electrode voltage change of a sub-pixel of an HSD panel in the prior art
  • FIG. 4 is a waveform diagram of a pixel electrode voltage change of a sub-pixel after delay compensation by a scan line RC in the first embodiment
  • FIG. 5 is a schematic structural view of a three-gate liquid crystal display panel according to Embodiment 2 of the present invention.
  • FIG. 6 is a waveform diagram of driving signal voltages on a data line and a scan line of a tri-gate type panel in the prior art
  • FIG. 7 is a waveform diagram of a voltage change of a pixel electrode of a sub-pixel of a tri-gate panel in the prior art
  • FIG. 8 is a waveform diagram showing changes in pixel electrode voltage of sub-pixels after delay compensation by scan line RC in the second embodiment.
  • FIG. 1 is a schematic structural diagram of a half source driving HSD (Half Source Driving) liquid crystal display panel of the present embodiment.
  • the display panel includes a plurality of data lines (data lines D1, D2, D3, D4 as shown in the figure) and a plurality of scan lines (scan lines G1, G2 as shown in the figure).
  • G3, G4) A pixel array formed by orthogonal arrangement, and a plurality of sub-pixels P11 to P36 arranged in the array.
  • the sub-pixel Pxy is defined here to be set in the xth row and the yth column.
  • the sub-pixel P12 is set in the 1st row, the 2nd column, and so on.
  • the sub-pixel P12 is connected to the scanning line G1 and the data line D2, and the sub-pixel P13 is connected to the scanning line G2 and the data line D2. P12 and P13 are respectively disposed on both sides of the data line D2.
  • the sub-pixel P22 is connected to the scan line G3 and the data line D2, and the sub-pixel P23 is connected to the scan line G4 and the data line D2. P22 and P23 are respectively disposed on both sides of the data line D2.
  • the way other sub-pixels are arranged is like this.
  • the sub-pixels of the HSD liquid crystal display panel are spatially uneven in brightness, and the HSD pixel array as a whole appears to produce bright and dark lines along the vertical direction. There are two main reasons for this defect.
  • the first reason is that there is an RC delay on the data line that causes a difference in the charging rate of the sub-pixels.
  • the waveform of the driving signal voltage on the data line and the scanning line in a certain frame is as shown in FIG. 2.
  • the level of the drive signal provided on data line D2 is periodically inverted.
  • the first time period after the polarity inversion occurs is the scanning period T3, and the second time period is the scanning period T4.
  • the data line D2 is for driving the first sub-pixel P22 and the second sub-pixel P23.
  • the first scan line G3 is turned on in the scan period T3, and the data line D2 is charged to the first sub-pixel P22 with a positive data signal voltage.
  • the second scan line G4 is turned on, and the data line D2 is charged with the positive data signal voltage for the second sub-pixel P23.
  • the driving signal of the data line D2 cannot reach the predetermined charging level during the initial part of the scanning period T3, resulting in insufficient charging of the first sub-pixel P22.
  • the brightness is low. While the driving signal of the data line D2 has stably reached the predetermined charging level during the scanning period T4, the second sub-pixel P23 can be fully charged, and the brightness presented is high.
  • the second reason is the difference in the charging rate of the sub-pixels caused by the inversion driving method.
  • the HSD pixel array adopts a 2H inversion driving, that is, a two-line inversion driving method.
  • the polarity of the data driving signal level is inverted once in two scanning periods, that is, the inversion period of the data line driving signal level is two scanning periods.
  • the driving signal level of the data line D2 is reversed in polarity, and is shifted from the low level of the scanning period T2 to the high level of the scanning period T3.
  • the driving signal of the data line D2 since the driving signal of the data line D2 needs to generate a large voltage change, the driving signal of the data line D2 cannot reach the predetermined charging current during the initial part of the scanning period T3. Flat, causing sub-pixel P22 to be undercharged. Conversely, at the initial timing of the scanning period T4, the driving signal level of the data line D2 does not undergo polarity inversion. The drive signal of the data line D2 can maintain a stable predetermined charge level during the scan period T4, and the sub-pixel P23 can be fully charged.
  • the feedthrough voltage ⁇ Vp can be expressed as:
  • Vgh is the scan line driving voltage high level, that is, the turn-on level
  • Vgl is the scan line driving voltage low level, that is, the turn-off level
  • Cgs is a parasitic capacitance
  • Cst is a storage capacitor
  • Clc is a liquid crystal capacitor.
  • the waveform changes of the pixel voltages of the sub-pixels P22 and P23 are as shown in FIG.
  • the scanning line G3 is turned on, the driving signal of the data line D2 cannot reach a predetermined charging level, and the charging rate of the data line D2 to the sub-pixel P22 is low.
  • the pixel voltage Vp22 of the sub-pixel P22 reaches a maximum value.
  • the feedthrough voltage ⁇ Vp22 gradually reduces the pixel voltage Vp22 to a stable holding voltage.
  • the scanning line G4 is turned on, the driving signal of the data line D2 maintains a stable predetermined charging level, and the charging rate of the data line D2 to the sub-pixel P23 is high.
  • the pixel voltage Vp22 of the sub-pixel P23 reaches a maximum value and is higher than the maximum value of the pixel voltage Vp22 of the sub-pixel P22.
  • the feedthrough voltage ⁇ Vp23 gradually reduces the pixel voltage Vp23 to a stable holding voltage.
  • the holding voltage obtained by the sub-pixel P22 is lower than the holding voltage obtained by the pixel P23, resulting in the final brightness of the sub-pixel P22. Lower.
  • the embodiment compensates the difference in the charging rate of the data lines to the sub-pixels by configuring different RC delays of the scan lines, so that the stable holding voltage values obtained by the sub-pixels after being charged by the data lines are consistent, and the sub-pixels are realized. A uniform brightness and darkness is exhibited in the space, thereby eliminating bright and dark lines in the HSD liquid crystal display panel.
  • the RC delay of the configurable second scan line G4 is greater than the RC delay of the first scan line G3.
  • the width of the scanning line G4 is made smaller than the width of the scanning line G3, so that the wiring resistance of the scanning line G4 is larger than the wiring resistance of the scanning line G3.
  • the scanning line G3 is turned on, the driving signal voltage of the data line D2 cannot reach a predetermined charging level, and the charging rate of the data line D2 to the sub-pixel P22 is low.
  • the pixel voltage Vp22 of the sub-pixel P22 reaches a maximum value.
  • the feedthrough voltage ⁇ Vp22 gradually reduces the pixel voltage Vp22 to a stable holding voltage.
  • the polarity of the drive signal of the data line D2 is the same in the scan periods T3 and T4. And at the initial timing of the scanning period T4, the scanning line G4 is turned on, and the driving signal of the data line D2 maintains a stable predetermined charging level. Meanwhile, since the RC delay of the scanning line G4 is greater than the RC delay of the scanning line G3, the scanning line G4 is not fully turned on, and the maximum value Vgh of the scanning driving level actually applied to the sub-pixel P23 is less than a preset level value, so that the data line D2 has a lower charging rate for sub-pixel P23. At the end of the scanning period T4, the pixel voltage Vp23 of the sub-pixel P23 reaches a maximum value.
  • the time length of the first time period T3 and the second time period T4 are equal, that is, the time when the scanning line G3 is turned on is equal to the time when the scanning line G4 is turned on.
  • the scanning line G3 and the scanning line G4 provide the same value of the driving signal level. Therefore, the embodiment does not need to change the driving manner of the gate driving chip and the source driving chip in the prior art, and can achieve good compatibility with the existing driving chip.
  • the difference in charging rate of the sub-pixels P22 and P23 of the data line D2 in the prior art is compensated only by increasing the RC delay of the scanning line G4, so that the charging rates of the sub-pixels P22 and P23 are the same, that is, the scanning line G4 is guaranteed.
  • the maximum value reached by the pixel voltage Vp23 of the sub-pixel P23 is the same as the maximum value of the pixel voltage Vp22 of the sub-pixel P22.
  • the feedthrough voltage ⁇ Vp23 gradually reduces the pixel voltage Vp23 to a stable holding voltage.
  • the scan signal G3 and the scan line G4 provide the same value of the drive signal level, that is, the turn-on level Vgh value provided by G3 and G4 is the same, and the turn-off level Vgl value provided by G3 and G4 is the same.
  • the holding voltage obtained by the sub-pixel P22 is the same as the holding voltage value obtained by the sub-pixel P23, so that the luminances finally presented by the sub-pixel P22 and the sub-pixel P23 are the same.
  • the difference between the RC delay of the second scan line G4 and the RC delay of the first scan line G3 can be configured for the two reasons described above that result in a bright dark line defect. That is, the larger RC delay of the scan line G4 is used to compensate for the difference in the charging rate of the sub-pixels caused by the RC delay on the data line D2, and the difference in the charging rate of the sub-pixels caused by the 2H inversion driving method.
  • both the HSD liquid crystal display panel and the conventional liquid crystal display panel are suitable for the 2H inversion driving method.
  • the odd-numbered scan lines and the even-numbered scan lines can be configured to compensate for the difference in the charging rate of the data lines to the sub-pixels, so that the final charging voltages of the odd-numbered column sub-pixels and the even-numbered column sub-pixels tend to be consistent to eliminate the edge. Bright and dark lines in the vertical direction.
  • FIG. 5 is a schematic structural view of a Tri-Gate liquid crystal display panel of the present embodiment.
  • the display panel includes a plurality of data lines (data lines D1 to D6 as shown in the drawing) and orthogonally arranged with a plurality of scanning lines (scanning lines G1 to G6 as shown in the drawing).
  • the red sub-pixel (R) P11, the green sub-pixel (G) P21, and the blue sub-pixel (B) P31 constitute one pixel unit.
  • the number of scanning lines of the three-gate liquid crystal display panel is 3m
  • the data line data is n
  • the number of scanning lines of the ordinary display panel is m
  • the data line data is 3n.
  • the number of scanning lines of the three-gate type liquid crystal display panel is increased by three times and the number of data lines is reduced by one third at the same resolution as compared with the conventional display panel. That is to say, the tri-gate liquid crystal display panel uses more gate driving chips and fewer source driving chips, which can reduce manufacturing cost and power consumption.
  • the sub-pixels of the liquid crystal display panel of the present embodiment are spatially uneven in brightness, and the three-gate pixel array as a whole appears to produce bright and dark lines along the horizontal direction.
  • the reason for this defect is as follows.
  • the voltage waveforms of the driving signals on the data lines and the scanning lines are as shown in FIG. 6.
  • the level of the drive signal provided on the data line D1 is periodically inverted.
  • the first time period after the polarity inversion occurs is the scanning period T4
  • one second time period is the scanning period T5
  • the other second time period is the scanning period T6.
  • the data line D1 is used to drive the first sub-pixel P41, the second sub-pixel P51, and another second sub-pixel P61.
  • the first scan line G4 is turned on in the scan period T4, and the data line D1 is charged to the sub-pixel P41 with a positive data signal voltage.
  • the second scanning line G5 is turned on, and the data line D1 is charged with the positive data signal voltage for the sub-pixel P51.
  • another second scanning line G6 is turned on, and the data line D1 is charged with P61.
  • the sub-pixel charging time is reduced by two-thirds compared to a normal display panel, which causes the problem of insufficient charging of the sub-pixel by the data line.
  • the driving signal of the data line D1 cannot reach the predetermined charging level during the initial part of the scanning period T4, resulting in insufficient charging of the sub-pixel P41.
  • the brightness is low. While the data line D1 has stably reached the predetermined charge level during the scan periods T4 and T5, the sub-pixels P51 and P61 can be fully charged, and the brightness presented is high.
  • the three-gate pixel array adopts a 3H inversion driving method, that is, a three-line inversion driving method.
  • the polarity of the data driving signal level is inverted once in three scanning periods, that is, the inversion period of the data line driving signal level is three scanning periods.
  • the driving signal level of the data line D1 is reversed in polarity, and the low level of the scanning period T3 jumps to the high level of the scanning period T4. Since the driving signal of the data line D1 needs to generate a large voltage change, the driving signal of the data line D1 cannot reach the predetermined charging level during the initial portion of the scanning period T4, resulting in insufficient charging of the sub-pixel P41.
  • the driving signal level of the data line D1 does not undergo polarity inversion.
  • the drive signal of the data line D1 can maintain a stable predetermined charge level during the scan periods T5 and T6, and the sub-pixels P51 and P61 can be fully charged.
  • the waveform changes of the pixel voltages of the sub-pixels P41, P51, and P61 are as shown in FIG. 7 due to the influence of the feedthrough voltage caused by the parasitic capacitance.
  • the scanning line G4 is turned on, the driving signal level of the data line D1 cannot reach a predetermined charging level, and the charging rate of the data line D1 to the sub-pixel P41 is low.
  • the pixel voltage Vp41 of the sub-pixel P41 reaches a maximum value.
  • the feedthrough voltage ⁇ Vp41 gradually reduces the pixel voltage Vp41 to a stable holding voltage.
  • the scanning line G5 is turned on, the driving signal of the data line D1 maintains a stable predetermined charging level, and the charging rate of the data line D1 to the sub-pixel P41 is high.
  • the pixel voltage Vp51 of the sub-pixel P51 reaches a maximum value and is higher than the maximum value of the pixel voltage Vp41 of the sub-pixel P41.
  • the feedthrough voltage ⁇ Vp51 gradually reduces the pixel voltage Vp51 to a stable holding voltage.
  • the scanning line G6 is turned on, and the charging rate of the data line D1 to the sub-pixel P61 is high. After the scanning line G6 is turned off, the feedthrough voltage ⁇ Vp61 gradually lowers the pixel voltage Vp61 to a stable holding voltage.
  • the stable pixel voltage Vp41 obtained by the sub-pixel P41 in the same frame period is obtained by the pixels P51 and P61.
  • the stable pixel voltage average value is lower, resulting in the final brightness of the sub-pixel P41 being lower, while the sub-pixels P51 and P61 exhibit higher brightness.
  • the present embodiment compensates for the difference in the charging rate of the data line to the sub-pixel by configuring different RC delays of the scan lines.
  • the RC delay of the second scan lines G5 and G6 can be configured to be greater than the RC delay of the first scan line G4.
  • the widths of the scanning lines G5 and G6 are made smaller than the width of the scanning line G4, so that the wiring resistance of the scanning lines G5 and G6 is larger than the scanning line. G4 wiring resistance.
  • the driving signal of the data line D1 cannot reach a predetermined charging level, and the charging rate of the data line D1 to the sub-pixel P41 is low.
  • the pixel voltage Vp41 of the sub-pixel P41 reaches a maximum value. After the scanning line G4 is turned off, the feedthrough voltage ⁇ Vp41 gradually reduces the pixel voltage Vp41 to a stable holding voltage.
  • the polarity of the drive signal of the data line D1 is the same in the scan periods T4 and T5. And at the initial timing of the scanning period T5, the driving signal of the data line D1 maintains a stable predetermined charging level. Since the RC delay of the scan line G5 is greater than the RC delay of the scan line G4, the scan line G5 is not fully turned on, and the maximum value Vgh of the scan drive signal level actually applied to the sub-pixel P51 is less than the preset charge level, so that the data line D1 has a lower charging rate for sub-pixel P51. At the end of the scanning period T5, the pixel voltage Vp51 of the sub-pixel P51 reaches a maximum value.
  • the scanning periods T4, T5, and T6 have the same length of time, that is, the scanning line G4 is turned on at the same time as the scanning lines G5 and G6 are turned on. Further, the scanning line G4 has the same value as the driving signal level supplied from the scanning lines G5 and G6. Therefore, the embodiment does not need to change the driving manner of the gate driving chip and the source driving chip of the tri-gate liquid crystal display in the prior art, and can achieve good compatibility with the existing driving chip.
  • This embodiment compensates for the difference in charging rate of the sub-pixels P41, P51, and P61 of the data line D1 in the related art only by increasing the RC delay of the scanning lines G5 and G6, so that the charging rates of the sub-pixels P41, P51, and P61 are the same. That is, it is ensured that the maximum value reached by the pixel voltage Vp51 of the sub-pixel P51 is the same as the maximum value of the pixel voltage Vp41 of the sub-pixel P41 at the timing when the scanning line G5 is turned off. And at the timing when the scanning line G6 is turned off, the maximum value reached by the pixel voltage Vp61 of the sub-pixel P61 is the same as the maximum value of the pixel voltage Vp41 of the sub-pixel P41.
  • the feedthrough voltage ⁇ Vp51 gradually reduces the pixel voltage Vp51 to a stable voltage value.
  • the feedthrough voltage ⁇ Vp61 gradually reduces the pixel voltage Vp61 to a stable voltage value.
  • the holding voltage obtained by the sub-pixel P51 is the same as the holding voltage value obtained by the sub-pixel P41, so that the luminances finally presented by the sub-pixel P51 and the sub-pixel P41 are the same.
  • the difference between the RC delay of the second scan lines G5 and G6 and the RC delay of the first scan line G4 can be configured for the two reasons for the bright dark line defect described above.
  • the larger RC delay of the scan lines G5 and G6 is used to compensate for the difference in the charging rate of the sub-pixels caused by the RC delay on the data line D1, and the difference in the charging rate of the sub-pixels caused by the 3H inversion driving method.
  • the scan drive signal actually supplied to the sub-pixel is at a high level Vgh on the scan line G5,
  • the 3k+1th and 3k+th scan lines can be arranged to compensate the data line pair by using a different wiring width than the 3kth scan line.
  • the difference in charging rate of the pixels (k is an integer, k ⁇ 0), so that the final charging voltage of each row of sub-pixels tends to be uniform to eliminate bright and dark lines distributed in the horizontal direction.
  • the HSD liquid crystal display panel in the first embodiment and the ordinary liquid crystal display panel are also applicable to the 3H inversion driving method.
  • the difference between the charging rate of the data line and the sub-pixel can be compensated by configuring the 3k+1th and 3k+2th scanning lines to have different wiring widths from the 3kth scanning line. Eliminate defects that show uneven brightness.

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Abstract

提供了一种液晶显示面板。包括配置在像素阵列中的多个亚像素（Pxy），像素阵列由多条数据线（D1`D4）和多条扫描线（G1`G6）正交配置形成，多条扫描线（G1`G6）包括：第一扫描线（G3），在数据线（D1`D4）驱动信号电平反转后的第一时间段（T3）内开启；至少一条第二扫描线（G4），在第一时间段（T3）之后的第二时间段（T4）内开启；其中，第二扫描线（G4）的RC延迟大于第一扫描线（G3）的RC延迟。

Description

一种液晶显示面板
相关申请的交叉引用
本申请要求享有2014年12月16日提交的名称为“一种液晶显示面板”的中国专利申请CN201410784300.3的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种液晶显示面板。
背景技术
随着液晶显示工艺的发展，目前各种液晶显示器大多具备低成本、低功耗和高性能的优点。液晶显示面板的各种元件往往通过精密设计进行整合，以在降低成本和功耗的同时保证最佳的显示效果。
在薄膜晶体管-液晶显示器(TFT-LCD)领域，液晶显示面板中需要设置大量的源极驱动电路与栅极驱动电路来进行垂直与水平方面的像素驱动。与源极驱动芯片相比而言，栅极驱动芯片的成本与耗电量均较低，因此可通过合理设计像素阵列的结构来减少数据线的数量，从而使用较少的源极驱动芯片，进而达到降低液晶显示器的制造成本及耗电量的目的。
例如，现有技术中半源极驱动HSD(Half Source Driving)像素阵列的左右相邻的亚像素共用一条数据线，使得数据线的数目相对于传统液晶驱动像素阵列的数据线数目减半。同一行的相邻亚像素连接不同的扫描线，同一行相隔一个亚像素的亚像素连接相同的扫描线，这样使得扫描线的数目相对于传统驱动像素阵列的扫描线数目加倍。
通常，在HSD像素阵列中可采用2H线反转驱动，即两行反转驱动方式。在两个扫描周期之内数据驱动信号电平的极性发生一次反转。由于扫描线数目的加倍使得分配到扫描线上的扫描时间减少，从而亚像素的充电时间减少。进一步，由于数据线具有一定的阻抗，电压信号在传输过程中会造成波形的延迟失真，越到数据线的末端失真越严重。这样导致在数据线尾端奇数列亚像素与偶数列亚像素充电率差异。例如，先驱动的奇数列亚像 素充电不足，亮度较低；相对而言，后驱动的偶数列亚像素充电较好，亮度较高。
这使得在同一帧周期内，液晶显示面板的亚像素在空间上呈现的亮暗程度并不均匀，HSD像素阵列整体看来会产生亮暗线。
发明内容
本发明所要解决的技术问题是克服现有技术中液晶显示面板在空间上呈现的亮暗程度并不均匀的缺陷。
为了解决上述技术问题，本申请的实施例提供一种液晶显示面板，包括：
配置在像素阵列中的多个亚像素，所述像素阵列由多条数据线和多条扫描线正交配置形成，所述多条扫描线包括：
第一扫描线，其与第一亚像素连接，所述第一扫描线在数据线驱动信号电平极性反转后的第一时间段内开启，通过该数据线向第一亚像素充电；
至少一条第二扫描线，其分别与至少一个第二亚像素连接，所述第二扫描线在该第一时间段之后的第二时间段内开启，通过该数据线向第二亚像素充电；
其中，第二扫描线的RC延迟大于第一扫描线的RC延迟，以补偿该数据线对第一亚像素与对第二亚像素的充电率差异。
优选地，所述第二扫描线的布线电阻大于第一扫描线的布线电阻。
优选地，所述第二扫描线的厚度与第一扫描线的厚度相同，第二扫描线的宽度小于第一扫描线的宽度。
优选地，所述数据线用于驱动所述第一亚像素和所述至少一个第二亚像素，且所述数据线的驱动信号电平呈周期性反转。
优选地，在所述第二扫描线为一条的情况下，所述数据线驱动信号电平的反转周期为两个扫描周期。
优选地，在所述第二扫描线为两条的情况下，数据线驱动信号电平的反转周期为三个扫描周期。
优选地，所述数据线信号电平反转后的第一时间段与第二时间段的时间长度相等，所述第一扫描线与所述至少一条第二扫描线的开启时间相等。
优选地，所述数据线的驱动信号电平的极性在第一时间段与第二时间段内相同。
优选地，所述第二扫描线的驱动信号电平与第一扫描线的驱动信号电平大小相等，使得所述第一亚像素和所述至少一个第二亚像素的像素电极上的馈通电压相同。
优选地，所述像素阵列为半源极驱动像素阵列或者三栅型像素阵列。
本发明实施例提供的液晶显示面板通过配置扫描线不同的RC延迟来补偿数据线对亚像素的充电率差异，以使得亚像素在经过数据线充电后获得的稳定的保持电压数值一致，实现亚像素在空间上呈现均匀的亮暗程度，从而消除液晶显示面板中的亮暗线。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案或现有技术的进一步理解，并且构成说明书的一部分，但并不构成对本申请技术方案的限制。
图1是根据本发明实施例一的HSD液晶显示面板的结构示意图；
图2是现有技术中HSD面板数据线和扫描线上的驱动信号电压波形图；
图3是现有技术中HSD面板亚像素的像素电极电压变化波形图；
图4是实施例一中经过扫描线RC延迟补偿之后，亚像素的像素电极电压变化波形图；
图5是本发明实施例二的三栅型液晶显示面板的结构示意图；
图6是现有技术中三栅型面板数据线和扫描线上的驱动信号电压波形图；
图7是现有技术中三栅型面板亚像素的像素电极电压变化波形图；
图8是实施例二中经过扫描线RC延迟补偿之后，亚像素的像素电极电压变化波形图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。本申请实施例以及实施例中的各个特征，在不相冲突的前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一
图1为本实施例的半源极驱动HSD(Half Source Driving)液晶显示面板的结构示意图。如图1所示，该显示面板包括由多条数据线(如图中所示的数据线D1、D2、D3、D4)与多条扫描线(如图中所示的扫描线G1、G2、G3、G4)正交配置形成的像素阵列，以及配置在阵列中的多个亚像素P11～P36。为了表述简洁，在此定义亚像素Pxy是设置于第x行、第y列。例如，亚像素P12设置于第1行、第2列，并以此类推。
亚像素P12与扫描线G1和数据线D2连接，亚像素P13与扫描线G2和数据线D2连接。P12和P13分别设置在数据线D2的两侧。类似的，亚像素P22与扫描线G3和数据线D2连接，亚像素P23与扫描线G4和数据线D2连接。P22和P23分别设置在数据线D2的两侧。其他亚像素的排布方式以此类推。
现有技术中，在同一帧周期内，HSD液晶显示面板的亚像素在空间上呈现的亮暗程度并不均匀，HSD像素阵列整体看来会产生沿垂直方向的的亮暗线。产生这种缺陷的原因主要有两个。
第一个原因在于，数据线上存在RC延迟导致亚像素的充电率差异。在某一帧内数据线和扫描线上的驱动信号电压波形如图2所示。数据线D2上提供的驱动信号电平呈周期性反转。本实施例中，发生极性反转后的第一时间段为扫描周期T3，第二时间段为扫描周期T4。数据线D2用于驱动第一亚像素P22和第二亚像素P23。在扫描周期T3中第一扫描线G3开启，数据线D2以正极性的数据信号电压为第一亚像素P22充电。同样的，在扫描周期T4中第二扫描线G4开启，数据线D2以正极性的数据信号电压为第二亚像素P23充电。如图2中虚线所示，由于数据线D2上存在RC延迟，在扫描周期T3初始的部分时间内数据线D2的驱动信号不能达到预定的充电电平，导致第一亚像素P22充电不足，呈现的亮度较低。而在扫描周期T4内数据线D2的驱动信号已稳定到达预定的充电电平，第二亚像素P23能被完全充电，呈现的亮度较高。
第二个原因在于，反转驱动方式导致的亚像素的充电率差异。通常HSD像素阵列采用2H反转驱动，即两行反转驱动方式。在两个扫描周期之内数据驱动信号电平的极性发生一次反转，即数据线驱动信号电平的反转周期为两个扫描周期。如图2所示，在扫描周期T3的初始时刻，数据线D2的驱动信号电平发生极性反转，由扫描周期T2的低电平跳变至扫描周期T3的高电平。此时由于数据线D2的驱动信号需要产生较大的电压变化，同样使得在扫描周期T3初始的部分时间内数据线D2的驱动信号不能达到预定的充电电 平，导致亚像素P22充电不足。相反的，在扫描周期T4的初始时刻，数据线D2的驱动信号电平并不会发生极性反转。在扫描周期T4内数据线D2的驱动信号可保持稳定的预定充电电平，亚像素P23能被完全充电。
从另一方面来说，由于亚像素间存在寄生电容，在扫描线关闭的瞬间亚像素的像素电极上产生馈通电压(feed through voltage)，导致像素电极电压降低。馈通电压ΔVp可表示为：
ΔVp＝(Vgh-Vgl)*Cgs/(Cst+Clc+Cgs)
其中，Vgh为扫描线驱动电压高电平，即开启电平；Vgl为扫描线驱动电压低电平，即关断电平；Cgs为寄生电容，Cst为存储电容，Clc为液晶电容。
具体来说，亚像素P22和P23像素电极电压的波形变化如图3所示。
在扫描周期T3的初始时刻，扫描线G3开启，数据线D2的驱动信号不能达到预定的充电电平，数据线D2对亚像素P22的充电率较低。在扫描周期T3结束时，亚像素P22的像素电压Vp22达到最大值。在扫描线G3关闭之后，馈通电压ΔVp22使像素电压Vp22逐渐降低至稳定的保持电压。
在扫描周期T4的初始时刻，扫描线G4开启，数据线D2的驱动信号保持稳定的预定充电电平，数据线D2对亚像素P23的充电率较高。在扫描周期T4结束时，亚像素P23的像素电压Vp22达到最大值，并且高于亚像素P22的像素电压Vp22的最大值。在扫描线G4关闭之后，馈通电压ΔVp23使像素电压Vp23逐渐降低至稳定的保持电压。由于扫描线G3和G4的驱动信号电平完全相同，即馈通电压ΔVp23＝ΔVp22，使得亚像素P22获得的保持电压比亚像素P23获得的保持电压数值较低，导致亚像素P22最终呈现的亮度较低。
基于上述分析，本实施例通过配置扫描线不同的RC延迟来补偿数据线对亚像素的充电率差异，以使得亚像素在经过数据线充电后获得的稳定的保持电压数值一致，实现亚像素在空间上呈现均匀的亮暗程度，从而消除HSD液晶显示面板中的亮暗线。
再次如图1所示，可配置第二扫描线G4的RC延迟大于第一扫描线G3的RC延迟。具体的，在扫描线G4的厚度与扫描线G3的厚度相同的情况下，使扫描线G4的宽度小于扫描线G3的宽度，从而使得扫描线G4的布线电阻大于扫描线G3的布线电阻。
如此以来，亚像素P22和P23像素电极电压的波形变化如图4所示。
在扫描周期T3的初始时刻，扫描线G3开启，数据线D2的驱动信号电压不能达到预定的充电电平，数据线D2对亚像素P22的充电率较低。在扫描周期T3结束时，亚像素P22的像素电压Vp22达到最大值。在扫描线G3关闭之后，馈通电压ΔVp22使像素电压Vp22逐渐降低至稳定的保持电压。
如图4所示，数据线D2的驱动信号的极性在扫描周期T3和T4内相同。并且在扫描周期T4的初始时刻，扫描线G4开启，数据线D2的驱动信号保持稳定的预定充电电平。同时，由于扫描线G4的RC延迟大于扫描线G3的RC延迟，扫描线G4并不能完全开启，实际施加到亚像素P23的扫描驱动电平的最大值Vgh小于预设电平值，使得数据线D2对亚像素P23的充电率较低。在扫描周期T4结束时，亚像素P23的像素电压Vp23达到最大值。
需要说明的是，第一时间段T3与第二时间段T4的时间长度相等，即扫描线G3开启的时间与扫描线G4开启的时间相等。并且，扫描线G3与扫描线G4提供的驱动信号电平数值相同。因此，本实施例并不需要改变现有技术中栅极驱动芯片和源极驱动芯片的驱动方式，能够与现有的驱动芯片实现良好兼容。
本实施例仅仅通过增大扫描线G4的RC延迟来补偿现有技术中数据线D2对亚像素P22和P23的充电率差异，使得亚像素P22和P23的充电率相同，即保证在扫描线G4关闭的时刻，亚像素P23的像素电压Vp23达到的最大值与亚像素P22的像素电压Vp22的最大值相同。在扫描线G4关闭之后，馈通电压ΔVp23使像素电压Vp23逐渐降低至稳定的保持电压。
再者，由于扫描线G3与扫描线G4提供的驱动信号电平数值相同，即G3与G4提供的开启电平Vgh数值相同，且G3与G4提供的关断电平Vgl数值相同。引起馈通电压的电平差值(Vgh-Vgl)在扫描线G4与G3关闭的时刻完全相同，可保证馈通电压ΔVp23＝ΔVp22。这样，亚像素P22获得的保持电压与亚像素P23获得的保持电压数值相同，从而使亚像素P22和亚像素P23最终呈现的亮度相同。
需要说明的是，可针对上文描述的导致亮暗线缺陷的两个原因，配置第二扫描线G4的RC延迟与第一扫描线G3的RC延迟之间的差值。即扫描线G4较大的RC延迟用于补偿数据线D2上存在RC延迟导致亚像素的充电率差异，以及用于补偿2H反转驱动方式导致的亚像素的充电率差异。
并且，本实施例中通过合理配置扫描线G4的RC延迟与扫描线G3的RC延迟之间 的差值，来使得实际提供给亚像素的扫描驱动信号高电平Vgh在扫描线G4关闭时刻与扫描线G3关闭时刻完全相同，从而保证馈通电压ΔVp23＝ΔVp22。
本领域技术人员容易理解，对于HSD液晶显示面板和普通的液晶显示面板，均适用于2H反转驱动方式。可配置奇数扫描线和偶数扫描线的采用不同的布线宽度来补偿该数据线对亚像素的充电率差异，从而使奇数列亚像素和偶数列亚像素最终的充电电压趋于一致，来消除沿垂直方向的亮暗线。
实施例二
图5为本实施例的三栅型(Tri-Gate)液晶显示面板的结构示意图。如图5所示，显示面板包括由多条数据线(如图中所示的数据线D1～D6)与多条扫描线(如图中所示的扫描线G1～G6)正交配置形成的像素阵列，以及配置在阵列中的多个亚像素P11～P66。其中，红色亚像素(R)P11、绿色亚像素(G)P21以及蓝色亚像素(B)P31组成一个像素单元。
在分辨率为n*m的情况下，三栅型液晶显示面板的扫描线数目为3m条，数据线数据为n条，而普通显示面板的扫描线数目为m条，数据线数据为3n条。换言之，与普通显示面板相比较，在相同的分辨率下，三栅型液晶显示面板的扫描线的数量增加为三倍，而数据线的数量则减少为三分之一。也就是说，三栅型液晶显示面板采用较多的栅极驱动芯片和较少的源极驱动芯片，可降低制造成本及耗电量。
在同一帧周期内，本实施例的液晶显示面板的亚像素在空间上呈现的亮暗程度并不均匀，三栅型像素阵列整体看来会产生沿水平方向的亮暗线。这一缺陷产生的原因如下文所述。
在某一帧内，数据线和扫描线上的驱动信号电压波形如图6所示。数据线D1上提供的驱动信号电平呈周期性反转。本实施例中，发生极性反转后的第一时间段为扫描周期T4，一个第二时间段为扫描周期T5，另一第二时间段为扫描周期T6。在本实施例中，数据线D1用于驱动第一亚像素P41、第二亚像素P51和另一第二亚像素P61。在扫描周期T4中第一扫描线G4开启，数据线D1以正极性的数据信号电压为亚像素P41充电。在扫描周期T5中，第二扫描线G5开启，数据线D1以正极性的数据信号电压为亚像素P51充电。同样的，在扫描周期T6中，另一第二扫描线G6开启，数据线D1为P61充电。与普通显示面板相比，亚像素的充电时间减少了三分之二，这导致了数据线对亚像素充电不足的问题。
如图6中虚线所示，由于数据线D1上存在RC延迟，在扫描周期T4初始的部分时间内，数据线D1的驱动信号不能达到预定的充电电平，导致亚像素P41充电不足，呈现的亮度较低。而在扫描周期T4和T5内数据线D1已稳定到达预定的充电电平，亚像素P51和P61能被完全充电，呈现的亮度较高。
再者，三栅型像素阵列采用3H反转驱动方式，即三行反转驱动方式。在三个扫描周期之内数据驱动信号电平的极性发生一次反转，即数据线驱动信号电平的反转周期为三个扫描周期。如图6所示，在扫描周期T4的初始时刻，数据线D1的驱动信号电平发生极性反转，由扫描周期T3的低电平跳变至扫描周期T4的高电平。由于数据线D1的驱动信号需要产生较大的电压变化，同样使得在扫描周期T4初始的部分时间内数据线D1的驱动信号不能达到预定的充电电平，导致亚像素P41充电不足。相反的，在扫描周期T5和T6的初始时刻，数据线D1的驱动信号电平并不会发生极性反转。在扫描周期T5和T6内数据线D1的驱动信号可保持稳定的预定充电电平，亚像素P51和P61能被完全充电。
此外，与实施例一类似，受到寄生电容引起的馈通电压的影响，亚像素P41、P51和P61像素电极电压的波形变化如图7所示。
在扫描周期T4的初始时刻，扫描线G4开启，数据线D1的驱动信号电平不能达到预定的充电电平，数据线D1对亚像素P41的充电率较低。在扫描周期T4结束时，亚像素P41的像素电压Vp41达到最大值。在扫描线G4关闭之后，馈通电压ΔVp41使像素电压Vp41逐渐降低至稳定的保持电压。
在扫描周期T5的初始时刻，扫描线G5开启，数据线D1的驱动信号保持稳定的预定充电电平，数据线D1对亚像素P41的充电率较高。在扫描周期T5结束时，亚像素P51的像素电压Vp51达到最大值，并且高于亚像素P41的像素电压Vp41的最大值。在扫描线G5关闭之后，馈通电压ΔVp51使像素电压Vp51逐渐降低至稳定的保持电压。
类似的，在扫描周期T6的初始时刻，扫描线G6开启，数据线D1对亚像素P61的充电率较高。在扫描线G6关闭之后，馈通电压ΔVp61使像素电压Vp61逐渐降低至稳定的保持电压。
由于扫描线G4、G5和G6的驱动信号电平完全相同，即馈通电压ΔVp41＝ΔVp51＝ΔVp61，使得在同一帧周期内亚像素P41获得的稳定的像素电压Vp41比亚像素P51和P61获得的稳定的像素电压均数值较低，导致亚像素P41最终呈现的亮度较低，而亚像素P51和P61呈现的亮度较高。
基于上述分析，本实施例通过配置扫描线不同的RC延迟来补偿数据线对亚像素的充电率差异。
再次如图5所示，可配置第二扫描线G5和G6的RC延迟大于第一扫描线G4的RC延迟。具体的，在扫描线G5和G6的厚度与扫描线G4的厚度相同的情况下，使扫描线G5和G6的宽度小于扫描线G4的宽度，从而使得扫描线G5和G6的布线电阻大于扫描线G4的布线电阻。
如此以来，亚像素P41、P51和P61像素电极电压的波形变化如图8所示。
在扫描周期T4的初始时刻，数据线D1的驱动信号不能达到预定的充电电平，数据线D1对亚像素P41的充电率较低。在扫描周期T4结束时，亚像素P41的像素电压Vp41达到最大值。在扫描线G4关闭之后，馈通电压ΔVp41使像素电压Vp41逐渐降低至稳定的保持电压。
如图8所示，数据线D1的驱动信号的极性在扫描周期T4和T5内相同。并且在扫描周期T5的初始时刻，数据线D1的驱动信号保持稳定的预定充电电平。由于扫描线G5的RC延迟大于扫描线G4的RC延迟，扫描线G5并不能完全开启，实际施加到亚像素P51的扫描驱动信号电平的最大值Vgh小于预设的充电电平，使得数据线D1对亚像素P51的充电率较低。在扫描周期T5结束时，亚像素P51的像素电压Vp51达到最大值。
需要说明的是，扫描周期T4、T5、T6的时间长度相等，即扫描线G4开启的时间与扫描线G5、G6开启的时间相等。并且，扫描线G4与扫描线G5、G6提供的驱动信号电平数值相同。因此，本实施例并不需要改变现有技术中三栅型液晶显示器栅极驱动芯片和源极驱动芯片的驱动方式，能够与现有的驱动芯片实现良好兼容。
本实施例仅仅通过增大扫描线G5和G6的RC延迟来补偿现有技术中数据线D1对亚像素P41、P51和P61的充电率差异，使得亚像素P41、P51和P61的充电率相同。即保证在扫描线G5关闭的时刻，亚像素P51的像素电压Vp51达到的最大值与亚像素P41的像素电压Vp41的最大值相同。且在扫描线G6关闭的时刻，亚像素P61的像素电压Vp61达到的最大值与亚像素P41的像素电压Vp41的最大值相同。
在扫描线G5关闭之后，馈通电压ΔVp51使像素电压Vp51逐渐降低至稳定的电压值。类似的，在扫描线G6关闭之后，馈通电压ΔVp61使像素电压Vp61逐渐降低至稳定的电压值。
再者，由于扫描线G4、G5、G6提供的驱动信号电平数值相同，即G4、G5与G6提供的开启电平Vgh数值相同，且G4、G5与G6提供的关断电平Vgl数值相同。因此，引起馈通电压的电平差值(Vgh-Vgl)在扫描线G5与G4关闭时刻完全相同，可保证馈通电压ΔVp51＝ΔVp41。这样，亚像素P51获得的保持电压与亚像素P41获得的保持电压数值相同，从而使亚像素P51和亚像素P41最终呈现的亮度相同。类似的，也可保证馈通电压ΔVp61＝ΔVp41，从而使亚像素P61和亚像素P41最终呈现的亮度相同。
需要说明的是，可针对上文所述的导致亮暗线缺陷的两个原因，配置第二扫描线G5和G6的RC延迟与第一扫描线G4的RC延迟之间的差值。
即扫描线G5和G6较大的RC延迟用于补偿数据线D1上存在RC延迟导致亚像素的充电率差异，以及用于补偿3H反转驱动方式导致的亚像素的充电率差异。
并且，本实施例中通过合理配置扫描线G5、G6的RC延迟与扫描线G4的RC延迟之间的差值，来使得实际提供给亚像素的扫描驱动信号高电平Vgh在扫描线G5、G6关闭时刻与扫描线G4关闭时刻相同，从而保证馈通电压ΔVp41＝ΔVp51＝ΔVp61。
因此，本领域技术人员容易理解，对于三栅型液晶显示面板，可配置第3k+1条、第3k+2条扫描线采用与第3k条扫描线不同的布线宽度来补偿该数据线对亚像素的充电率差异(k为整数，k≥0)，从而使每一行亚像素最终的充电电压趋于一致，来消除沿水平方向分布的亮暗线。
此外，对于实施例一中的HSD液晶显示面板，以及普通的液晶显示面板，也同样适用于3H反转驱动方式。这种反转驱动方式下，也可通过配置第3k+1条、第3k+2条扫描线采用与第3k条扫描线不同的布线宽度来补偿该数据线对亚像素的充电率差异，来消除显示亮度不均匀的缺陷。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，实施例中采用的2H反转驱动方式和3H反转驱动方式并非用以限定本发明。本发明也可适用于其他的反转驱动方式。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种液晶显示面板，包括：
    配置在像素阵列中的多个亚像素，所述像素阵列由多条数据线和多条扫描线正交配置形成，所述多条扫描线包括：
    第一扫描线，其与第一亚像素连接，所述第一扫描线在数据线驱动信号电平极性反转后的第一时间段内开启，通过该数据线向第一亚像素充电；
    至少一条第二扫描线，其分别与至少一个第二亚像素连接，所述第二扫描线在该第一时间段之后的第二时间段内开启，通过该数据线向第二亚像素充电；
    其中，第二扫描线的RC延迟大于第一扫描线的RC延迟，以补偿该数据线对第一亚像素与对第二亚像素的充电率差异。
  2. 根据权利要求1所述的液晶显示面板，其中，所述第二扫描线的布线电阻大于第一扫描线的布线电阻。
  3. 根据权利要求1所述的液晶显示面板，其中，所述第二扫描线的厚度与第一扫描线的厚度相同，第二扫描线的宽度小于第一扫描线的宽度。
  4. 根据权利要求2所述的液晶显示面板，其中，所述数据线用于驱动所述第一亚像素和所述至少一个第二亚像素，且所述数据线的驱动信号电平呈周期性反转。
  5. 根据权利要求3所述的液晶显示面板，其中，所述数据线用于驱动所述第一亚像素和所述至少一个第二亚像素，且所述数据线的驱动信号电平呈周期性反转。
  6. 根据权利要求4所述的液晶显示面板，其中，在所述第二扫描线为一条的情况下，所述数据线驱动信号电平的反转周期为两个扫描周期。
  7. 根据权利要求5所述的液晶显示面板，其中，在所述第二扫描线为一条的情况下，所述数据线驱动信号电平的反转周期为两个扫描周期。
  8. 根据权利要求4所述的液晶显示面板，其中，在所述第二扫描线为两条的情况下，数据线驱动信号电平的反转周期为三个扫描周期。
  9. 根据权利要求5所述的液晶显示面板，其中，在所述第二扫描线为两条的情况下，数据线驱动信号电平的反转周期为三个扫描周期。
  10. 根据权利要求4所述的液晶显示面板，其中，所述数据线信号电平反转后的第一 时间段与第二时间段的时间长度相等，所述第一扫描线与所述至少一条第二扫描线的开启时间相等。
  11. 根据权利要求5所述的液晶显示面板，其中，所述数据线信号电平反转后的第一时间段与第二时间段的时间长度相等，所述第一扫描线与所述至少一条第二扫描线的开启时间相等。
  12. 根据权利要求10所述的液晶显示面板，其中，所述数据线的驱动信号电平的极性在第一时间段与第二时间段内相同。
  13. 根据权利要求11所述的液晶显示面板，其中，所述数据线的驱动信号电平的极性在第一时间段与第二时间段内相同。
  14. 根据权利要求12所述的液晶显示面板，其中，所述第二扫描线的驱动信号电平与第一扫描线的驱动信号电平数值相等，使得所述第一亚像素和所述至少一个第二亚像素的像素电极上的馈通电压相同。
  15. 根据权利要求13所述的液晶显示面板，其中，所述第二扫描线的驱动信号电平与第一扫描线的驱动信号电平数值相等，使得所述第一亚像素和所述至少一个第二亚像素的像素电极上的馈通电压相同。
  16. 根据权利要求14所述的液晶显示面板，其中，所述像素阵列为半源极驱动像素阵列或者三栅型像素阵列。
  17. 根据权利要求15所述的液晶显示面板，其中，所述像素阵列为半源极驱动像素阵列或者三栅型像素阵列。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104849888B (zh) 2015-05-05 2018-07-03 深圳市华星光电技术有限公司 液晶显示面板的驱动方法
CN104778937B (zh) * 2015-05-08 2017-09-22 京东方科技集团股份有限公司 栅极驱动电路、阵列基板及显示装置
KR102371896B1 (ko) * 2015-06-29 2022-03-11 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하는 표시 장치
US10410599B2 (en) * 2015-08-13 2019-09-10 Samsung Electronics Co., Ltd. Source driver integrated circuit for ompensating for display fan-out and display system including the same
KR102486413B1 (ko) * 2016-06-15 2023-01-10 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치
CN107731153A (zh) * 2017-11-30 2018-02-23 武汉天马微电子有限公司 异形显示面板和异形显示装置
CN109346017A (zh) * 2018-10-22 2019-02-15 惠科股份有限公司 显示面板
CN109410867B (zh) * 2018-12-05 2020-10-16 惠科股份有限公司 一种显示面板及驱动方法和显示装置
CN109410866B (zh) * 2018-12-05 2021-04-02 惠科股份有限公司 一种显示面板及驱动方法和显示装置
CN109307965B (zh) * 2018-12-05 2021-08-06 惠科股份有限公司 一种显示面板和显示装置
CN109658892A (zh) * 2019-01-30 2019-04-19 惠科股份有限公司 一种显示面板、显示面板的驱动方法和显示装置
CN109658869A (zh) * 2019-01-30 2019-04-19 惠科股份有限公司 一种显示面板、驱动方法和显示装置
JP7529758B2 (ja) 2020-03-19 2024-08-06 京東方科技集團股▲ふん▼有限公司 表示基板及び表示装置
CN113421513B (zh) 2021-06-23 2022-07-12 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN114242007B (zh) * 2021-12-10 2023-06-30 重庆惠科金渝光电科技有限公司 像素驱动方法以及显示设备
CN118298776B (zh) * 2024-06-06 2024-08-16 Tcl华星光电技术有限公司 一种显示装置的驱动方法和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030058758A (ko) * 2001-12-31 2003-07-07 엘지.필립스 엘시디 주식회사 액정표시소자
JP2007017928A (ja) * 2005-06-09 2007-01-25 Sanyo Epson Imaging Devices Corp 電気光学装置および電子機器
CN1949067A (zh) * 2005-10-13 2007-04-18 三星电子株式会社 液晶显示器
KR20070074789A (ko) * 2006-01-10 2007-07-18 삼성전자주식회사 액정 표시 장치
US20090195489A1 (en) * 2008-02-01 2009-08-06 Innolux Display Corp. Thin film transistor substrate having high aperture ratio and method of manufacturing same
CN101644867A (zh) * 2009-09-03 2010-02-10 上海广电光电子有限公司 液晶显示器的栅极线驱动装置
CN102566166A (zh) * 2010-12-22 2012-07-11 北京京东方光电科技有限公司 一种双栅的tft基板及其制造方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW526462B (en) * 2000-04-06 2003-04-01 Chi Mei Optoelectronics Corp Method for reducing flicker and uneven brightness of LCD screen
KR100741857B1 (ko) * 2006-05-03 2007-07-24 삼성전자주식회사 계면 저항을 줄일 수 있는 게이트 콘택 구조체를 구비하는반도체 장치 및 그 제조 방법
JP5727120B2 (ja) * 2006-08-25 2015-06-03 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 液晶表示装置
KR101337256B1 (ko) * 2007-02-14 2013-12-05 삼성디스플레이 주식회사 표시 장치의 구동 장치 및 이를 포함하는 표시 장치
CN100533239C (zh) * 2007-10-23 2009-08-26 昆山龙腾光电有限公司 液晶显示面板
CN101256327A (zh) * 2008-03-14 2008-09-03 上海广电光电子有限公司 液晶显示器
TWI410941B (zh) * 2009-03-24 2013-10-01 Au Optronics Corp 可改善畫面閃爍之液晶顯示器和相關驅動方法
CN101520998B (zh) * 2009-04-02 2011-01-05 友达光电股份有限公司 可改善画面闪烁的液晶显示器和相关驱动方法
TWI497477B (zh) * 2010-05-13 2015-08-21 Novatek Microelectronics Corp 驅動模組與驅動方法
KR101777265B1 (ko) * 2010-12-23 2017-09-12 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하기 위한 표시 장치
KR20120111684A (ko) * 2011-04-01 2012-10-10 엘지디스플레이 주식회사 액정표시장치
CN102568398B (zh) * 2012-03-02 2014-06-04 福州华映视讯有限公司 亮度均匀的双闸极液晶显示器
CN102855861A (zh) * 2012-09-27 2013-01-02 深圳市华星光电技术有限公司 液晶面板的驱动电路构造
CN103177691A (zh) * 2013-03-26 2013-06-26 深圳市华星光电技术有限公司 平板显示器
US20140354616A1 (en) * 2013-05-31 2014-12-04 Shenzhen China Star Optoelectronics Technology Co., Ltd. Active matrix display, scanning driven circuits and the method thereof
KR102102882B1 (ko) * 2013-06-25 2020-04-22 엘지디스플레이 주식회사 입체 영상 표시장치와 그 구동 방법
US20150185574A1 (en) * 2013-12-30 2015-07-02 Shenzhen China Star Optoelectronics Technology Co., Ltd. Thin-film transistor liquid crystal display device and signal line therefor
KR102211764B1 (ko) * 2014-04-21 2021-02-05 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하는 표시 장치
KR102164701B1 (ko) * 2014-07-04 2020-10-13 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN104252071B (zh) * 2014-09-24 2017-10-17 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板
CN104317127B (zh) * 2014-11-14 2017-05-17 深圳市华星光电技术有限公司 一种液晶显示面板
KR102284296B1 (ko) * 2015-01-13 2021-08-03 삼성디스플레이 주식회사 표시 장치 및 이를 이용한 표시 패널의 구동 방법
KR102336702B1 (ko) * 2015-06-12 2021-12-08 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR102371896B1 (ko) * 2015-06-29 2022-03-11 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하는 표시 장치
CN106019743B (zh) * 2016-06-15 2023-08-22 京东方科技集团股份有限公司 一种阵列基板、其驱动方法及相关装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030058758A (ko) * 2001-12-31 2003-07-07 엘지.필립스 엘시디 주식회사 액정표시소자
JP2007017928A (ja) * 2005-06-09 2007-01-25 Sanyo Epson Imaging Devices Corp 電気光学装置および電子機器
CN1949067A (zh) * 2005-10-13 2007-04-18 三星电子株式会社 液晶显示器
KR20070074789A (ko) * 2006-01-10 2007-07-18 삼성전자주식회사 액정 표시 장치
US20090195489A1 (en) * 2008-02-01 2009-08-06 Innolux Display Corp. Thin film transistor substrate having high aperture ratio and method of manufacturing same
CN101644867A (zh) * 2009-09-03 2010-02-10 上海广电光电子有限公司 液晶显示器的栅极线驱动装置
CN102566166A (zh) * 2010-12-22 2012-07-11 北京京东方光电科技有限公司 一种双栅的tft基板及其制造方法

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