WO2016074308A1 - 一种液晶显示面板 - Google Patents

一种液晶显示面板 Download PDF

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Publication number
WO2016074308A1
WO2016074308A1 PCT/CN2014/093900 CN2014093900W WO2016074308A1 WO 2016074308 A1 WO2016074308 A1 WO 2016074308A1 CN 2014093900 W CN2014093900 W CN 2014093900W WO 2016074308 A1 WO2016074308 A1 WO 2016074308A1
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Prior art keywords
pixel
sub
data line
liquid crystal
display panel
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PCT/CN2014/093900
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English (en)
French (fr)
Inventor
陈彩琴
许哲豪
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深圳市华星光电技术有限公司
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Priority to US14/416,643 priority Critical patent/US9952477B2/en
Publication of WO2016074308A1 publication Critical patent/WO2016074308A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to the field of display technologies, and in particular to a liquid crystal display panel.
  • liquid crystal display technology With the development of liquid crystal display technology, various liquid crystal displays currently have the advantages of low cost, low power consumption and high performance.
  • the various components of the LCD panel are often integrated through precision design to ensure optimal display while reducing cost and power consumption.
  • TFT-LCD thin film transistor-liquid crystal display
  • a large number of source driving circuits and gate driving circuits are required in the liquid crystal display panel for vertical and horizontal pixel driving.
  • the cost and power consumption of the gate driver chip are relatively low, so that the number of data lines can be reduced by rationally designing the structure of the pixel array, thereby using fewer source driver chips. Further, the object of reducing the manufacturing cost and power consumption of the liquid crystal display is achieved.
  • the left and right adjacent sub-pixels of the half-source driven HSD (Half Source Driving) pixel array share one data line, so that the number of data lines is halved with respect to the number of data lines of the conventional liquid crystal driving pixel array.
  • Adjacent sub-pixels of the same row connect different scan lines, and sub-pixels of the same row separated by one sub-pixel are connected to the same scan line, such that the number of scan lines is doubled with respect to the number of scan lines of the conventional drive pixel array.
  • a 2H line inversion driving that is, a two-line inversion driving method can be employed in the HSD pixel array.
  • the polarity of the data drive signal level is inverted once during two scan cycles. Since the number of scan lines is doubled, the scan time allocated to the scan lines is reduced, so that the charging time of the sub-pixels is reduced. Further, since the data line has a certain impedance, the voltage signal causes delay distortion of the waveform during transmission, and the distortion becomes more serious at the end of the data line. This results in a difference in the charging rate between the odd column sub-pixel and the even column sub-pixel at the end of the data line. For example, the odd-numbered column image that is driven first Insufficient charging and low brightness; relatively speaking, the post-driven even-numbered sub-pixels charge better and the brightness is higher.
  • the technical problem to be solved by the present invention is to overcome the defect that the degree of brightness and darkness of the liquid crystal display panel in the prior art is not uniform.
  • an embodiment of the present application provides a liquid crystal display panel, including:
  • the pixel array being formed by orthogonally configuring a plurality of data lines and a plurality of scan lines, the plurality of scan lines including:
  • a first scan line connected to the first sub-pixel, the first scan line being turned on in a first time period after the polarity of the data line drive signal is inverted, and charging the first sub-pixel through the data line;
  • At least one second scan line respectively connected to the at least one second sub-pixel, the second scan line being turned on in a second time period after the first time period, and charging the second sub-pixel through the data line;
  • the equivalent capacitance of the first sub-pixel is greater than the equivalent capacitance of the second sub-pixel such that the holding voltages of the first sub-pixel and the second sub-pixel are the same.
  • the storage capacitance of the first sub-pixel is greater than the storage capacitance of the second sub-pixel, and/or the liquid crystal capacitance of the first sub-pixel is greater than the liquid crystal capacitance of the second sub-pixel.
  • the driving signal level of the second scan line is equal to the driving signal level value of the first scan line, such that the feedthrough voltage of the first sub-pixel is smaller than the feedthrough voltage of the second sub-pixel.
  • the data line is used to drive the first sub-pixel and the at least one second sub-pixel, and a driving signal level of the data line is periodically inverted.
  • the inversion period of the data line driving signal level is two scanning periods.
  • the inversion period of the data line driving signal level is three scanning periods.
  • the first time period after the data line signal level is inverted is equal to the time length of the second time period
  • the first scan line is equal to the on time of the at least one second scan line.
  • the polarity of the drive signal level of the data line is the same during the first time period and the second time period.
  • the driving signal inversion manner of the data line is a polarity row inversion.
  • the pixel array is a half source driven pixel array or a triple gate type pixel array.
  • Embodiments of the present invention compensate for differences in the charging rate of data lines to sub-pixels by arranging different equivalent capacitances for sub-pixels so that the sub-pixels are charged through the data line and are stabilized by the feed-through voltage.
  • the values are consistent, and the sub-pixels are uniformly spatially darkened, thereby eliminating bright and dark lines in the liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of an HSD liquid crystal display panel according to Embodiment 1 of the present invention.
  • FIG. 2 is a waveform diagram of driving signal voltages on a data line and a scanning line of an HSD panel in the prior art
  • FIG. 3 is an equivalent circuit diagram of a sub-pixel of the first embodiment
  • FIG. 4 is a waveform diagram of a pixel electrode voltage change of a sub-pixel of an HSD panel in the prior art
  • FIG. 5 is a waveform diagram of a pixel electrode voltage change of a sub-pixel after the equivalent capacitance compensation of the first embodiment
  • FIG. 6 is a schematic structural view of a three-gate liquid crystal display panel according to Embodiment 2 of the present invention.
  • FIG. 7 is a waveform diagram of driving signal voltages on a data line and a scanning line of a three-gate type display panel in the prior art
  • FIG. 9 is a waveform diagram of a voltage change of a pixel electrode of a sub-pixel of a three-gate type display panel in the prior art.
  • FIG. 10 is a waveform diagram showing changes in pixel electrode voltage of a sub-pixel after equivalent capacitance compensation in the second embodiment.
  • FIG. 1 is a schematic structural diagram of a half source driving HSD (Half Source Driving) liquid crystal display panel of the present embodiment.
  • the display panel includes a plurality of data lines (data lines D1, D2, D3, D4 as shown in the figure) and a plurality of scan lines (scan lines G1, G2 as shown in the figure).
  • G3, G4) A pixel array formed by orthogonal arrangement, and a plurality of sub-pixels P11 to P36 arranged in the array.
  • the sub-pixel Pxy is defined here to be set in the xth row and the yth column.
  • the sub-pixel P12 is set in the 1st row, the 2nd column, and so on.
  • the sub-pixel P12 is connected to the scanning line G1 and the data line D2, and the sub-pixel P13 is connected to the scanning line G2 and the data line D2. P12 and P13 are respectively disposed on both sides of the data line D2.
  • the sub-pixel P22 is connected to the scan line G3 and the data line D2, and the sub-pixel P23 is connected to the scan line G4 and the data line D2. P22 and P23 are respectively disposed on both sides of the data line D2.
  • the way other sub-pixels are arranged is like this.
  • the sub-pixels of the HSD liquid crystal display panel are not uniform in brightness and spatially, and the HSD pixel array as a whole appears to produce bright and dark lines along the vertical direction. There are two main reasons for this defect.
  • the first reason is that there is an RC delay on the data line that causes a difference in the charging rate of the sub-pixels.
  • the waveform of the driving signal voltage on the data line and the scanning line in a certain frame is as shown in FIG. 2.
  • the level of the driving signal provided on the data line D2 is periodically inverted.
  • the first period after the polarity inversion occurs is the scanning period T3, and the second period is the scanning period T4.
  • the data line D2 is for driving the first sub-pixel P22 and the second sub-pixel P23.
  • the first scan line G3 is turned on in the scan period T3, and the data line D2 is charged to the first sub-pixel P22 with a positive data signal voltage.
  • the second scan line G4 is turned on, and the data line D2 is charged with the positive data signal voltage for the second sub-pixel P23.
  • the driving signal of the data line D2 cannot reach the predetermined charging level during the initial part of the scanning period T3, resulting in insufficient charging of the first sub-pixel P22.
  • the brightness is low. While the driving signal of the data line D2 has stably reached the predetermined charging level during the scanning period T4, the second sub-pixel P23 can be fully charged, and the brightness presented is high.
  • the driving signal of the data line D2 since the driving signal of the data line D2 needs to generate a large voltage change, the driving signal of the data line D2 cannot reach the predetermined charging level during the initial portion of the scanning period T3, resulting in insufficient charging of the sub-pixel P22. Conversely, at the initial timing of the scanning period T4, the driving signal level of the data line D2 does not undergo polarity inversion. The drive signal of the data line D2 can maintain a stable predetermined charge level during the scan period T4, and the sub-pixel P23 can be fully charged.
  • the feedthrough voltage ⁇ Vp can be expressed as:
  • Vgh is the scan line driving voltage high level, that is, the turn-on level
  • Vgl is the scan line driving voltage low level, that is, the turn-off level
  • Cgs is a parasitic capacitance
  • Cst is a storage capacitor
  • Clc is a liquid crystal capacitor.
  • the storage capacitor Cst and the liquid crystal capacitor Clc are connected in parallel to form an equivalent capacitance.
  • the waveform changes of the pixel voltages of the sub-pixels P22 and P23 are as shown in FIG.
  • the scanning line G3 is turned on, the driving signal of the data line D2 cannot reach a predetermined charging level, and the charging rate of the data line D2 to the sub-pixel P22 is low.
  • the pixel voltage Vp22 of the sub-pixel P22 reaches a maximum value.
  • the feedthrough voltage ⁇ Vp22 gradually reduces the pixel voltage Vp22 to a stable holding voltage.
  • the scanning line G4 is turned on, the driving signal of the data line D2 maintains a stable predetermined charging level, and the charging rate of the data line D2 to the sub-pixel P23 is high.
  • the pixel voltage Vp22 of the sub-pixel P23 reaches a maximum value and is higher than the maximum value of the pixel voltage Vp22 of the sub-pixel P22.
  • the feedthrough voltage ⁇ Vp23 gradually reduces the pixel voltage Vp23 to a stable voltage value.
  • the value of the stable holding voltage Vp23 obtained by the holding voltage Vp22 is lower than that of the pixel P23, resulting in a lower luminance of the sub-pixel P22.
  • the present embodiment generates different feedthrough voltages by configuring different equivalent capacitances of sub-pixels, so that the values of the holding voltages obtained by the sub-pixels after being charged by the data lines are consistent, and the sub-pixels are uniformly represented in space. Brightness and darkness, thereby eliminating the bright and dark lines in the vertical direction in the HSD liquid crystal display panel.
  • the equivalent capacitance C22 of the configurable sub-pixel P22 is greater than the equivalent capacitance C23 of the sub-pixel P23 such that the feed-through voltage ⁇ Vp22 ⁇ ⁇ Vp23.
  • the storage capacitor Cst22>Cst23 may be configured, or the liquid crystal capacitor Clc22>Clc23 may be configured. It is easy to understand that since the storage capacitor Cst and the liquid crystal capacitor Clc are connected in parallel to form an equivalent capacitance, Cst22>Cst23 and Clc22>Clc23 are also arranged.
  • the first scanning line G3 is turned on, the driving signal voltage of the data line D2 cannot reach a predetermined charging level, and the charging rate of the data line D2 to the sub-pixel P22 is low.
  • the pixel voltage Vp22 of the sub-pixel P22 reaches a maximum value.
  • the feedthrough voltage ⁇ Vp22 gradually reduces the pixel voltage Vp22 to a stable holding voltage value.
  • the polarity of the drive signal of the data line D2 is the same in the scan periods T3 and T4.
  • the second scanning line G4 is turned on, and the driving signal of the data line D2 maintains a stable predetermined charging level.
  • the pixel voltage Vp23 of the sub-pixel P23 reaches a maximum value and is higher than the maximum value of the pixel voltage Vp22 of the sub-pixel P22.
  • the feedthrough voltage ⁇ Vp23 gradually reduces the pixel voltage Vp23 to a stable holding voltage value.
  • the equivalent capacitance C22>C23 can be configured such that the feedthrough voltage ⁇ Vp22 ⁇ Vp23, so that the holding voltages of the sub-pixels P22 and P23 are the same, that is, the final brightness of the sub-pixel P22 and the sub-pixel P23. the same.
  • the time length of the first time period T3 and the second time period T4 are equal, that is, the time when the scanning line G3 is turned on is equal to the time when the scanning line G4 is turned on.
  • the scanning line G3 and the scanning line G4 provide the same value of the driving signal level. Therefore, the embodiment does not need to change the driving manner of the gate driving chip and the source driving chip in the prior art, and can achieve good compatibility with the existing driving chip.
  • the driving signal voltage of the data line D2 cannot reach a predetermined charging level, and the charging rate of the sub-pixel P22 by the data line D2 is low.
  • the equivalent capacitance of the sub-pixel P22 is large, that is, the data line D2 is sub-pixel P22 in the scanning period T3.
  • the charging load is large and the charging rate is further reduced.
  • the equivalent capacitance C22>C23 is configured, and the difference between C22 and C23 is reasonably set to compensate for the difference between the peaks reached by Vp22 and Vp23, and the holding voltage of the sub-pixels P22 and P23 is made by the action of the feed-through voltage.
  • the values are consistent.
  • both the HSD liquid crystal display panel and the conventional liquid crystal display panel are suitable for the 2H inversion driving method.
  • the equivalent capacitance of the configurable odd-column sub-pixels is different from the equivalent capacitance of the even-numbered sub-pixels, and different feed-through voltages are generated to compensate for the difference in brightness caused by the difference in sub-pixel charging rates between the data lines.
  • the final charging voltages of the odd column sub-pixels and the even column sub-pixels tend to be uniform to improve the bright and dark lines in the vertical direction.
  • FIG. 6 is a schematic structural view of a Tri-Gate liquid crystal display panel of the embodiment.
  • the display panel includes a plurality of data lines (data lines D1 to D6 as shown in the drawing) and orthogonally arranged with a plurality of scanning lines (scanning lines G1 to G6 as shown in the drawing).
  • the red sub-pixel (R) P11, the green sub-pixel (G) P21, and the blue sub-pixel (B) P31 constitute one pixel unit.
  • the number of scanning lines of the three-gate liquid crystal display panel is 3m
  • the data line data is n
  • the number of scanning lines of the ordinary display panel is m
  • the data line data is 3n.
  • the number of scanning lines of the three-gate type liquid crystal display panel is increased by three times and the number of data lines is reduced by one third at the same resolution as compared with the conventional display panel. That is to say, the tri-gate liquid crystal display panel uses more gate driving chips and fewer source driving chips, which can reduce manufacturing cost and power consumption.
  • the sub-pixels of the prior art tri-gate type liquid crystal display panel exhibit spatially uneven brightness, and the three-gate type pixel array as a whole appears to produce bright and dark lines along the horizontal direction.
  • the reason for this defect is as follows.
  • the voltage waveforms of the driving signals on the data lines and the scanning lines are as shown in FIG.
  • the level of the drive signal provided on the data line D1 is periodically inverted.
  • the first time period after the polarity inversion occurs is the scanning period T4
  • one second time period is the scanning period T5
  • the other second time period is the scanning period T6.
  • the data line D1 is used to drive the first sub-pixel P41, the second sub-pixel P51, and another second sub-pixel P61.
  • the first scanning line G4 is turned on in T4, and the data line D1 is charged to the sub-pixel P41 with a positive data signal voltage.
  • the second scan line G5 is turned on in the scan period T5, and the data line D1 is charged to the sub-pixel P51 with a positive data signal voltage.
  • another second scan line G6 is turned on, and the data line D1 charges P61 during the scan period T6.
  • the sub-pixel charging time is reduced by two-thirds compared to a normal display panel, which causes the problem of insufficient charging of the sub-pixel by the data line.
  • the driving signal of the data line D1 cannot reach the predetermined charging level during the initial part of the scanning period T4, resulting in insufficient charging of the sub-pixel P41.
  • the brightness is low. While the data line D1 has stably reached the predetermined charge level during the scan periods T4 and T5, the sub-pixels P51 and P61 can be fully charged, and the brightness presented is high.
  • the three-gate pixel array adopts a 3H inversion driving method, that is, a three-line inversion driving method.
  • the polarity of the data driving signal level is inverted once in three scanning periods, that is, the inversion period of the data line driving signal level is three scanning periods.
  • the driving signal level of the data line D1 is reversed in polarity, and the low level of the scanning period T3 jumps to the high level of the scanning period T4. Since the driving signal of the data line D1 needs to generate a large voltage change, the driving signal of the data line D1 cannot reach the predetermined charging level during the initial portion of the scanning period T4, resulting in insufficient charging of the sub-pixel P41.
  • the driving signal level of the data line D1 does not undergo polarity inversion.
  • the drive signal of the data line D1 can maintain a stable predetermined charge level during the scan periods T5 and T6, and the sub-pixels P51 and P61 can be fully charged.
  • the storage capacitor Cst and the liquid crystal capacitor Clc are connected in parallel to form an equivalent capacitance.
  • the waveform changes of the pixel voltages of the sub-pixels P41, P51, and P61 are as shown in FIG. 9 due to the influence of the feedthrough voltage caused by the parasitic capacitance.
  • the scanning line G4 is turned on, the driving signal level of the data line D1 cannot reach a predetermined charging level, and the charging rate of the data line D1 to the sub-pixel P41 is low.
  • the pixel voltage Vp41 of the sub-pixel P41 reaches a maximum value.
  • the feedthrough voltage ⁇ Vp41 gradually reduces the pixel voltage Vp41 to a stable holding voltage.
  • the scanning line G6 is turned on, and the charging rate of the data line D1 to the sub-pixel P61 is high. After the scanning line G6 is turned off, the feedthrough voltage ⁇ Vp61 gradually lowers the pixel voltage Vp61 to a stable holding voltage.
  • the stable pixel voltages obtained by Vp41 and P61 are lower, resulting in lower brightness of sub-pixel P41 and higher brightness of sub-pixels P51 and P61.
  • the present embodiment generates different feedthrough voltages by configuring different equivalent capacitances of sub-pixels, so that the values of the hold voltages obtained by the sub-pixels after being charged by the data lines are consistent.
  • the driving signal of the data line D1 cannot reach a predetermined charging level, and the charging rate of the data line D1 to the sub-pixel P41 is low.
  • the pixel voltage Vp41 of the sub-pixel P41 reaches a maximum value. After the scanning line G4 is turned off, the feedthrough voltage ⁇ Vp41 gradually reduces the pixel voltage Vp41 to a stable holding voltage value.
  • the polarity of the drive signal of the data line D1 is the same in the scan periods T4 and T5. And at the initial timing of the scanning period T5, the driving signal of the data line D1 maintains a stable predetermined charging level. At the end of the scanning period T5, the pixel voltage Vp51 of the sub-pixel P51 reaches a maximum value and is higher than the maximum value of the pixel voltage Vp41 of the sub-pixel P41. After the scanning line G5 is turned off, the feedthrough voltage ⁇ Vp51 gradually reduces the pixel voltage Vp51 to a stable holding voltage value.
  • the driving signal level values provided by the scanning lines G4, G5, and G6 are the same, and the predetermined driving signal level has been reached at the timing when the scanning lines G5 and G6 are turned off, the driving signal level is exactly the same as the scanning signal G4 is turned off.
  • the difference between the turn-on voltage and the turn-off voltage (Vgh-Vgl) is the same. As shown in FIG.
  • the scanning periods T4, T5, and T6 have the same length of time, that is, the scanning line G4 is turned on at the same time as the scanning lines G5 and G6 are turned on. Further, the scanning line G4 has the same value as the driving signal level supplied from the scanning lines G5 and G6. Therefore, the embodiment does not need to change the driving manner of the gate driving chip and the source driving chip of the tri-gate liquid crystal display in the prior art, and can achieve good compatibility with the existing driving chip.
  • the equivalent capacitance C41 is increased, the load of charging the sub-pixel P41 by the data line D1 is large, and the charging rate is further lowered, so that the pixel voltages Vp41, Vp51, and Vp61 are reached at the time when the scanning line is turned off. The difference in peaks is greater.
  • the holding voltages of the sub-pixels P41, P51 and P61 can be made the same by the feedthrough voltage.
  • the data line RC has a large delay.
  • the driving signals of the data line D1 are not averaged at a predetermined charging level in the scanning periods T4 and T5, and the sub-pixels P41 and P51 are both insufficiently charged. phenomenon.
  • Sub-pixels P41 and P51 exhibit lower brightness, while sub-pixel P61 exhibits higher brightness.
  • different values of the equivalent capacitances C41, C51 and C61 can be configured to make the holding voltages of the sub-pixels P41, P51 and P61 the same by the effect of the feed-through voltage.
  • the equivalent capacitance of the 3k+1th row and the 3k+2th row of subpixels can be different from the equivalent capacitance of the 3kth row of subpixels (k is An integer, k ⁇ 0), to generate different feedthrough voltages such that the value of the hold voltage obtained by each row of subpixels after charging through the data line is uniform, thereby improving the bright and dark lines along the horizontal direction.
  • the HSD liquid crystal display panel in the first embodiment and the ordinary liquid crystal display panel are also applicable to the 3H inversion driving method.
  • the data line pair sub-pixel can also be compensated by configuring the equivalent capacitance of the 3k+1th row and the 3k+2th row sub-pixel to be different from the equivalent capacitance of the 3kth row sub-pixel.
  • the difference in charging rate is to improve the defect of uneven display brightness.

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Abstract

一种液晶显示面板，包括配置在像素数组中的多个亚像素（P11-P36），像素数组由多条数据线（D1-D4）和多条扫描线（G1-G4）正交配置形成，多条扫描线（G1-G4）包括：第一扫描线（G3），在数据线（D2）驱动信号电平反转后的第一时间段（T3）内开启，通过数据线（D2）向第一亚像素（P22）充电；至少一条第二扫描线（G4），在第二时间段（T4）内开启，通过数据线（D2）向第二亚像素（P23）充电；其中，第一亚像素（P22）的等效电容（C22）大于第二亚像素（P23）的等效电容（C23），以使得第一亚像素（P22）和第二亚像素（P23）的保持电压（Vp22，Vp23）相同。

Description

一种液晶显示面板
相关申请的交叉引用
本申请要求享有2014年11月14日提交的名称为“一种液晶显示面板”的中国专利申请CN201410650152.6的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种液晶显示面板。
背景技术
随着液晶显示工艺的发展，目前各种液晶显示器大多具备低成本、低功耗和高性能的优点。液晶显示面板的各种元件往往通过精密设计进行整合，以在降低成本和功耗的同时保证最佳的显示效果。
在薄膜晶体管-液晶显示器(TFT-LCD)领域，液晶显示面板中需要设置大量的源极驱动电路与栅极驱动电路来进行垂直与水平方面的像素驱动。与源极驱动芯片相比而言，栅极驱动芯片的成本与耗电量均较低，因此可通过合理设计像素阵列的结构来减少数据线的数量，从而使用较少的源极驱动芯片，进而达到降低液晶显示器的制造成本及耗电量的目的。
例如，现有技术中半源极驱动HSD(Half Source Driving)像素阵列的左右相邻的亚像素共用一条数据线，使得数据线的数目相对于传统液晶驱动像素阵列的数据线数目减半。同一行的相邻亚像素连接不同的扫描线，同一行相隔一个亚像素的亚像素连接相同的扫描线，这样使得扫描线的数目相对于传统驱动像素阵列的扫描线数目加倍。
通常，在HSD像素阵列中可采用2H线反转驱动，即两行反转驱动方式。在两个扫描周期之内数据驱动信号电平的极性发生一次反转。由于扫描线数目的加倍使得分配到扫描线上的扫描时间减少，从而亚像素的充电时间减少。进一步，由于数据线具有一定的阻抗，电压信号在传输过程中会造成波形的延迟失真，越到数据线的末端失真越严重。这样导致在数据线尾端奇数列亚像素与偶数列亚像素充电率差异。例如，先驱动的奇数列亚像 素充电不足，亮度较低；相对而言，后驱动的偶数列亚像素充电较好，亮度较高。
这使得在同一帧周期内，液晶显示面板的亚像素在空间上呈现的亮暗程度并不均匀，HSD像素阵列整体看来会产生亮暗线。
发明内容
本发明所要解决的技术问题是克服现有技术中液晶显示面板在空间上呈现的亮暗程度并不均匀的缺陷。
为了解决上述技术问题，本申请的实施例提供一种液晶显示面板，包括：
配置在像素阵列中的多个亚像素，所述像素阵列由多条数据线和多条扫描线正交配置形成，所述多条扫描线包括：
第一扫描线，其与第一亚像素连接，所述第一扫描线在数据线驱动信号电平极性反转后的第一时间段内开启，通过该数据线向第一亚像素充电；
至少一条第二扫描线，其分别与至少一个第二亚像素连接，所述第二扫描线在该第一时间段之后的第二时间段内开启，通过该数据线向第二亚像素充电；
其中，第一亚像素的等效电容大于第二亚像素的等效电容，以使得第一亚像素和第二亚像素的保持电压相同。
优选地，所述第一亚像素的存储电容大于第二亚像素的存储电容，以及/或者所述第一亚像素的液晶电容大于第二亚像素的液晶电容。
优选地，所述第二扫描线的驱动信号电平与第一扫描线的驱动信号电平数值相等，使得所述第一亚像素的馈通电压小于第二亚像素的馈通电压。
优选地，所述数据线用于驱动所述第一亚像素和所述至少一个第二亚像素，且所述数据线的驱动信号电平呈周期性反转。
优选地，在所述第二扫描线为一条的情况下，所述数据线驱动信号电平的反转周期为两个扫描周期。
优选地，在所述第二扫描线为两条的情况下，数据线驱动信号电平的反转周期为三个扫描周期。
优选地，所述数据线信号电平反转后的第一时间段与第二时间段的时间长度相等，所 述第一扫描线与所述至少一条第二扫描线的开启时间相等。
优选地，所述数据线的驱动信号电平的极性在第一时间段与第二时间段内相同。
优选地，所述数据线的驱动信号反转方式为极性行反转。
优选地，所述像素阵列为半源极驱动像素阵列或者三栅型像素阵列。
本发明的实施例通过为亚像素配置不同的等效电容来补偿数据线对亚像素的充电率差异，以使得亚像素在经过数据线充电，并经过馈通电压作用后获得的稳定的像素电压数值一致，实现亚像素在空间上呈现均匀的亮暗程度，从而消除液晶显示面板中的亮暗线。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案或现有技术的进一步理解，并且构成说明书的一部分，但并不构成对本申请技术方案的限制。
图1是根据本发明实施例一的HSD液晶显示面板的结构示意图；
图2是现有技术中HSD面板数据线和扫描线上的驱动信号电压波形图；
图3是实施例一的亚像素的等效电路图；
图4是现有技术中HSD面板亚像素的像素电极电压变化波形图；
图5是实施例一的经过等效电容补偿之后，亚像素的像素电极电压变化波形图；
图6是本发明实施例二的三栅型液晶显示面板的结构示意图；
图7是现有技术中三栅型显示面板数据线和扫描线上的驱动信号电压波形图；
图8是实施例二的亚像素的等效电路图；
图9是现有技术中三栅型显示面板亚像素的像素电极电压变化波形图；
图10是实施例二的经过等效电容补偿之后，亚像素的像素电极电压变化波形图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。本申请实施例以及实施例中的各个特征，在不相冲突的前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一
图1为本实施例的半源极驱动HSD(Half Source Driving)液晶显示面板的结构示意图。如图1所示，该显示面板包括由多条数据线(如图中所示的数据线D1、D2、D3、D4)与多条扫描线(如图中所示的扫描线G1、G2、G3、G4)正交配置形成的像素阵列，以及配置在阵列中的多个亚像素P11～P36。为了表述简洁，在此定义亚像素Pxy是设置于第x行、第y列。例如，亚像素P12设置于第1行、第2列，并以此类推。
亚像素P12与扫描线G1和数据线D2连接，亚像素P13与扫描线G2和数据线D2连接。P12和P13分别设置在数据线D2的两侧。类似的，亚像素P22与扫描线G3和数据线D2连接，亚像素P23与扫描线G4和数据线D2连接。P22和P23分别设置在数据线D2的两侧。其他亚像素的排布方式以此类推。
现有技术中，在同一帧周期内，HSD液晶显示面板的亚像素在空间上呈现的亮暗程度并不均匀，HSD像素阵列整体看来会产生沿垂直方向的亮暗线。产生这种缺陷的原因主要有两个。
第一个原因在于，数据线上存在RC延迟导致亚像素的充电率差异。在某一帧内数据线和扫描线上的驱动信号电压波形如图2所示。本实施例中，数据线D2上提供的驱动信号电平呈周期性反转。发生极性反转后的第一时间段为扫描周期T3，第二时间段为扫描周期T4。数据线D2用于驱动第一亚像素P22和第二亚像素P23。在扫描周期T3中第一扫描线G3开启，数据线D2以正极性的数据信号电压为第一亚像素P22充电。同样的，在扫描周期T4中第二扫描线G4开启，数据线D2以正极性的数据信号电压为第二亚像素P23充电。如图2中虚线所示，由于数据线D2上存在RC延迟，在扫描周期T3初始的部分时间内数据线D2的驱动信号不能达到预定的充电电平，导致第一亚像素P22充电不足，呈现的亮度较低。而在扫描周期T4内数据线D2的驱动信号已稳定到达预定的充电电平，第二亚像素P23能被完全充电，呈现的亮度较高。
第二个原因在于，反转驱动方式导致的亚像素的充电率差异。通常HSD像素阵列采用2H反转驱动，即两行反转驱动方式。在两个扫描周期之内数据驱动信号电平的极性发 生一次反转，即数据线驱动信号电平的反转周期为两个扫描周期。如图2所示，在扫描周期T3的初始时刻，数据线D2的驱动信号电平发生极性反转，由扫描周期T2的低电平跳变至扫描周期T3的高电平。此时由于数据线D2的驱动信号需要产生较大的电压变化，同样使得在扫描周期T3初始的部分时间内数据线D2的驱动信号不能达到预定的充电电平，导致亚像素P22充电不足。相反的，在扫描周期T4的初始时刻，数据线D2的驱动信号电平并不会发生极性反转。在扫描周期T4内数据线D2的驱动信号可保持稳定的预定充电电平，亚像素P23能被完全充电。
从另一方面来说，由于亚像素间存在寄生电容，在扫描线关闭的瞬间亚像素的像素电极上产生馈通电压(feed through voltage)，导致像素电极电压降低。馈通电压ΔVp可表示为：
ΔVp＝(Vgh-Vgl)*Cgs/(Cst+Clc+Cgs)
其中，Vgh为扫描线驱动电压高电平，即开启电平，Vgl为扫描线驱动电压低电平，即关断电平，Cgs为寄生电容，Cst为存储电容，Clc为液晶电容。
如图3的等效电路图所示，存储电容Cst和液晶电容Clc并联形成等效电容。现有技术中亚像素P22的等效电容C22与亚像素P23的等效电容C23相同，使得馈通电压ΔVp22＝ΔVp23。
具体来说，亚像素P22和P23像素电极电压的波形变化如图4所示。
在扫描周期T3的初始时刻，扫描线G3开启，数据线D2的驱动信号不能达到预定的充电电平，数据线D2对亚像素P22的充电率较低。在扫描周期T3结束时，亚像素P22的像素电压Vp22达到最大值。在扫描线G3关闭之后，馈通电压ΔVp22使像素电压Vp22逐渐降低至稳定的保持电压。
在扫描周期T4的初始时刻，扫描线G4开启，数据线D2的驱动信号保持稳定的预定充电电平，数据线D2对亚像素P23的充电率较高。在扫描周期T4结束时，亚像素P23的像素电压Vp22达到最大值，并且高于亚像素P22的像素电压Vp22的最大值。在扫描线G4关闭之后，馈通电压ΔVp23使像素电压Vp23逐渐降低至稳定的电压值。由于扫描线G3和G4的驱动信号电平完全相同，且亚像素P22的等效电容C22与亚像素P23的等效电容C23相同，即馈通电压ΔVp23＝ΔVp22，使得亚像素P22获得的稳定的保持电压Vp22比亚像素P23获得的稳定的保持电压Vp23数值较低，导致亚像素P22最终呈现的亮度较低。
基于上述分析，本实施例通过配置亚像素不同的等效电容来产生不同的馈通电压，以使得亚像素在经过数据线充电后获得的保持电压数值一致，实现亚像素在空间上呈现均匀的亮暗程度，从而消除HSD液晶显示面板中沿垂直方向的亮暗线。
再次如图3所示，可配置亚像素P22的等效电容C22大于亚像素P23的等效电容C23，使得馈通电压ΔVp22＜ΔVp23。具体来说，可以配置存储电容Cst22＞Cst23，或者配置液晶电容Clc22＞Clc23。容易理解，由于存储电容Cst和液晶电容Clc并联形成等效电容，也配置Cst22＞Cst23且Clc22＞Clc23。
如此以来，亚像素P22和P23像素电极电压的波形变化如图5所示。
在扫描周期T3的初始时刻，第一扫描线G3开启，数据线D2的驱动信号电压不能达到预定的充电电平，数据线D2对亚像素P22的充电率较低。在扫描周期T3结束时，亚像素P22的像素电压Vp22达到最大值。在扫描线G3关闭之后，馈通电压ΔVp22使像素电压Vp22逐渐降低至稳定的保持电压数值。
如图5所示，数据线D2的驱动信号的极性在扫描周期T3和T4内相同。并且在扫描周期T4的初始时刻，第二扫描线G4开启，数据线D2的驱动信号保持稳定的预定充电电平。在扫描周期T4结束时，亚像素P23的像素电压Vp23达到最大值，并且高于亚像素P22的像素电压Vp22的最大值。在扫描线G4关闭之后，馈通电压ΔVp23使像素电压Vp23逐渐降低至稳定的保持电压数值。
由于扫描线G3与扫描线G4提供的驱动信号电平数值相同，且在扫描线G4关闭的时刻已达到预定的驱动信号电平，与扫描线G3关闭的时刻的驱动信号电平完全相同，则对于亚像素P22和P23来说，开启电压与关断电压的差值(Vgh-Vgl)是相同的。如图5所示，本实施例中可以配置等效电容C22＞C23，使得馈通电压ΔVp22＜ΔVp23，从而亚像素P22和P23的保持电压相同，即亚像素P22和亚像素P23最终呈现的亮度相同。
需要说明的是，第一时间段T3与第二时间段T4的时间长度相等，即扫描线G3开启的时间与扫描线G4开启的时间相等。并且，扫描线G3与扫描线G4提供的驱动信号电平数值相同。因此，本实施例并不需要改变现有技术中栅极驱动芯片和源极驱动芯片的驱动方式，能够与现有的驱动芯片实现良好兼容。
此外，如上文所提到的，在扫描周期T3的初始时刻，数据线D2的驱动信号电压不能达到预定的充电电平，数据线D2对亚像素P22的充电速率较低。事实上，与亚像素P23相比而言，亚像素P22的等效电容较大，即在扫描周期T3中数据线D2对亚像素P22 充电的负载较大，充电速率进一步降低。这两个原因导致在扫描线G3、G4关闭的时刻，像素电压Vp22和Vp23达到的峰值的差异更大。
在本实施例中配置等效电容C22＞C23，并合理设定C22与C23的差值来补偿Vp22和Vp23达到的峰值的差异，通过馈通电压的作用来使得亚像素P22和P23的保持电压数值一致。
本领域技术人员容易理解，对于HSD液晶显示面板和普通的液晶显示面板，均适用于2H反转驱动方式。可配置奇数列亚像素的等效电容与偶数列亚像素的等效电容不同，产生不同的馈通电压，来补偿数据线对亚像素充电率差异导致的亮度差异。从而使奇数列亚像素和偶数列亚像素最终的充电电压趋于一致，来改善沿垂直方向的亮暗线。
实施例二
图6为本实施例的三栅型(Tri-Gate)液晶显示面板的结构示意图。如图6所示，显示面板包括由多条数据线(如图中所示的数据线D1～D6)与多条扫描线(如图中所示的扫描线G1～G6)正交配置形成的像素阵列，以及配置在阵列中的多个亚像素P11～P66。其中，红色亚像素(R)P11、绿色亚像素(G)P21以及蓝色亚像素(B)P31组成一个像素单元。
在分辨率为n*m的情况下，三栅型液晶显示面板的扫描线数目为3m条，数据线数据为n条，而普通显示面板的扫描线数目为m条，数据线数据为3n条。换言之，与普通显示面板相比较，在相同的分辨率下，三栅型液晶显示面板的扫描线的数量增加为三倍，而数据线的数量则减少为三分之一。也就是说，三栅型液晶显示面板采用较多的栅极驱动芯片和较少的源极驱动芯片，可降低制造成本及耗电量。
在同一帧周期内，现有技术中的三栅型液晶显示面板的亚像素在空间上呈现的亮暗程度并不均匀，三栅型像素阵列整体看来会产生沿水平方向的亮暗线。这一缺陷产生的原因如下文所述。
在某一帧内，数据线和扫描线上的驱动信号电压波形如图7所示。数据线D1上提供的驱动信号电平呈周期性反转。本实施例中，发生极性反转后的第一时间段为扫描周期T4，一个第二时间段为扫描周期T5，另一第二时间段为扫描周期T6。在本实施例中，数据线D1用于驱动第一亚像素P41、第二亚像素P51和另一第二亚像素P61。在扫描周期 T4中第一扫描线G4开启，数据线D1以正极性的数据信号电压为亚像素P41充电。在扫描周期T5中第二扫描线G5开启，数据线D1以正极性的数据信号电压为亚像素P51充电。同样的，另一第二扫描线G6开启，在扫描周期T6中数据线D1为P61充电。与普通显示面板相比，亚像素的充电时间减少了三分之二，这导致了数据线对亚像素充电不足的问题。
如图7中虚线所示，由于数据线D1上存在RC延迟，在扫描周期T4初始的部分时间内，数据线D1的驱动信号不能达到预定的充电电平，导致亚像素P41充电不足，呈现的亮度较低。而在扫描周期T4和T5内数据线D1已稳定到达预定的充电电平，亚像素P51和P61能被完全充电，呈现的亮度较高。
再者，三栅型像素阵列采用3H反转驱动方式，即三行反转驱动方式。在三个扫描周期之内数据驱动信号电平的极性发生一次反转，即数据线驱动信号电平的反转周期为三个扫描周期。如图7所示，在扫描周期T4的初始时刻，数据线D1的驱动信号电平发生极性反转，由扫描周期T3的低电平跳变至扫描周期T4的高电平。由于数据线D1的驱动信号需要产生较大的电压变化，同样使得在扫描周期T4初始的部分时间内数据线D1的驱动信号不能达到预定的充电电平，导致亚像素P41充电不足。相反的，在扫描周期T5和T6的初始时刻，数据线D1的驱动信号电平并不会发生极性反转。在扫描周期T5和T6内数据线D1的驱动信号可保持稳定的预定充电电平，亚像素P51和P61能被完全充电。
如图8的等效电路图所示，存储电容Cst和液晶电容Clc并联形成等效电容。现有技术中亚像素P41、P51、P61的等效电容均相同，使得馈通电压ΔVp41＝ΔVp51＝ΔVp61。
与实施例一类似，受到寄生电容引起的馈通电压的影响，亚像素P41、P51和P61像素电极电压的波形变化如图9所示。
在扫描周期T4的初始时刻，扫描线G4开启，数据线D1的驱动信号电平不能达到预定的充电电平，数据线D1对亚像素P41的充电率较低。在扫描周期T4结束时，亚像素P41的像素电压Vp41达到最大值。在扫描线G4关闭之后，馈通电压ΔVp41使像素电压Vp41逐渐降低至稳定的保持电压。
在扫描周期T5的初始时刻，扫描线G5开启，数据线D1的驱动信号保持稳定的预定充电电平，数据线D1对亚像素P41的充电率较高。在扫描周期T5结束时，亚像素P51的像素电压Vp51达到最大值，并且高于亚像素P41的像素电压Vp41的最大值。在扫描线G5关闭之后，馈通电压ΔVp51使像素电压Vp51逐渐降低至稳定的保持电压。
类似的，在扫描周期T6的初始时刻，扫描线G6开启，数据线D1对亚像素P61的充电率较高。在扫描线G6关闭之后，馈通电压ΔVp61使像素电压Vp61逐渐降低至稳定的保持电压。
由于扫描线G4、G5和G6的驱动信号电平完全相同，等效电容C41＝C51＝C61，即馈通电压ΔVp41＝ΔVp51＝ΔVp61，使得在同一帧周期内亚像素P41获得的稳定的像素电压Vp41比亚像素P51和P61获得的稳定的像素电压均数值较低，导致亚像素P41最终呈现的亮度较低，而亚像素P51和P61呈现的亮度较高。
基于上述分析，本实施例通过配置亚像素不同的等效电容来产生不同的馈通电压，以使得亚像素在经过数据线充电后获得的保持电压数值一致。
再次如图8所示，可配置第一亚像素P41的等效电容C41大于第二亚像素P51和第二亚像素P61的等效电容，即C41＞C51＝C61，使得馈通电压ΔVp41＜ΔVp51＝ΔVp61。具体来说，可以配置存储电容Cst41＞Cst51＝Cst61，或者配置液晶电容Clc41＞Clc51＝Clc61。容易理解，由于存储电容Cst和液晶电容Clc并联形成等效电容，也配置Cst41＞Cst51＝Cst61且Clc41＞Clc51＝Clc61。
如此以来，亚像素P41、P51和P61像素电极电压的波形变化如图10所示。
在扫描周期T4的初始时刻，数据线D1的驱动信号不能达到预定的充电电平，数据线D1对亚像素P41的充电率较低。在扫描周期T4结束时，亚像素P41的像素电压Vp41达到最大值。在扫描线G4关闭之后，馈通电压ΔVp41使像素电压Vp41逐渐降低至稳定的保持电压数值。
如图10所示，数据线D1的驱动信号的极性在扫描周期T4和T5内相同。并且在扫描周期T5的初始时刻，数据线D1的驱动信号保持稳定的预定充电电平。在扫描周期T5结束时，亚像素P51的像素电压Vp51达到最大值，且高于亚像素P41的像素电压Vp41的最大值。在扫描线G5关闭之后，馈通电压ΔVp51使像素电压Vp51逐渐降低至稳定的保持电压数值。
由于扫描线G4、G5、G6提供的驱动信号电平数值相同，且在扫描线G5、G6关闭的时刻已达到预定的驱动信号电平，与扫描线G4关闭的时刻的驱动信号电平完全相同，则对于亚像素P41、P51和P61来说，开启电压与关断电压的差值(Vgh-Vgl)是相同的。如图8所示，本实施例中可以配置等效电容C41＞C51＝C61，使得馈通电压ΔVp41＜ΔVp51＝ΔVp61，从而亚像素P41、P51和P61的保持电压相同，即亚像素P41、P51和P61 最终呈现的亮度相同。
需要说明的是，扫描周期T4、T5、T6的时间长度相等，即扫描线G4开启的时间与扫描线G5、G6开启的时间相等。并且，扫描线G4与扫描线G5、G6提供的驱动信号电平数值相同。因此，本实施例并不需要改变现有技术中三栅型液晶显示器栅极驱动芯片和源极驱动芯片的驱动方式，能够与现有的驱动芯片实现良好兼容。
与实施例一类似，由于增大了等效电容C41，使得数据线D1对亚像素P41充电的负载较大，充电速率进一步降低，导致在扫描线关闭的时刻，像素电压Vp41、Vp51和Vp61达到的峰值的差异更大。配置等效电容C41、C51与C61的数值差异，能够通过馈通电压的作用来使得亚像素P41、P51和P61的保持电压相同。
更进一步的，在三栅型液晶显示面板的驱动过程中，可能存在数据线RC延迟较大的情况。这与图9所示的数据线D1的驱动信号不同的是，在扫描周期T4和T5中数据线D1的驱动信号电平均不能达到预定的充电电平，亚像素P41和P51均存在充电不足的现象。这使得像素电压Vp41、Vp51的峰值比Vp61的峰值要小。亚像素P41和P51呈现的亮度较低，而亚像素P61呈现的亮度较高。类似的，配置等效电容C41、C51与C61的不同数值，能够通过馈通电压的作用来使得亚像素P41、P51和P61的保持电压相同。
因此，本领域技术人员容易理解，对于三栅型液晶显示面板，可配置第3k+1行、第3k+2行亚像素的等效电容与第3k行亚像素的等效电容不同(k为整数，k≥0)，来产生不同的馈通电压，以使得每一行亚像素在经过数据线充电后获得的保持电压数值一致，从而改善沿水平方向的亮暗线。
此外，对于实施例一中的HSD液晶显示面板，以及普通的液晶显示面板，也同样适用于3H反转驱动方式。这种反转驱动方式下，也可通过配置第3k+1行、第3k+2行亚像素的等效电容与第3k行亚像素的等效电容不同，来补偿该数据线对亚像素的充电率差异，来改善显示亮度不均匀的缺陷。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种液晶显示面板，包括：
    配置在像素阵列中的多个亚像素，所述像素阵列由多条数据线和多条扫描线正交配置形成，所述多条扫描线包括：
    第一扫描线，其与第一亚像素连接，所述第一扫描线在数据线驱动信号电平极性反转后的第一时间段内开启，通过该数据线向第一亚像素充电；
    至少一条第二扫描线，其分别与至少一个第二亚像素连接，所述第二扫描线在该第一时间段之后的第二时间段内开启，通过该数据线向第二亚像素充电；
    其中，第一亚像素的等效电容大于第二亚像素的等效电容，以使得第一亚像素和第二亚像素的保持电压相同。
  2. 根据权利要求1所述的液晶显示面板，其中，所述第一亚像素的存储电容大于第二亚像素的存储电容，以及/或者
    所述第一亚像素的液晶电容大于第二亚像素的液晶电容。
  3. 根据权利要求2所述的液晶显示面板，其中，所述第二扫描线的驱动信号电平与第一扫描线的驱动信号电平数值相等，使得所述第一亚像素的馈通电压小于第二亚像素的馈通电压。
  4. 根据权利要求3所述的液晶显示面板，其中，所述数据线用于驱动所述第一亚像素和所述至少一个第二亚像素，且所述数据线的驱动信号电平呈周期性反转。
  5. 根据权利要求4所述的液晶显示面板，其中，在所述第二扫描线为一条的情况下，所述数据线驱动信号电平的反转周期为两个扫描周期。
  6. 根据权利要求4所述的液晶显示面板，其中，在所述第二扫描线为两条的情况下，数据线驱动信号电平的反转周期为三个扫描周期。
  7. 根据权利要求4所述的液晶显示面板，其中，所述数据线信号电平反转后的第一时间段与第二时间段的时间长度相等，所述第一扫描线与所述至少一条第二扫描线的开启时间相等。
  8. 根据权利要求7所述的液晶显示面板，其中，所述数据线的驱动信号电平的极性在第一时间段与第二时间段内相同。
  9. 根据权利要求7所述的液晶显示面板，其中，所述数据线的驱动信号反转方式为极性行反转。
  10. 根据权利要求7所述的液晶显示面板，其中，所述像素阵列为半源极驱动像素阵列或者三栅型像素阵列。
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