WO2018040163A1 - 液晶面板及液晶显示器 - Google Patents

液晶面板及液晶显示器 Download PDF

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WO2018040163A1
WO2018040163A1 PCT/CN2016/100322 CN2016100322W WO2018040163A1 WO 2018040163 A1 WO2018040163 A1 WO 2018040163A1 CN 2016100322 W CN2016100322 W CN 2016100322W WO 2018040163 A1 WO2018040163 A1 WO 2018040163A1
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Prior art keywords
film transistor
thin film
liquid crystal
sub
gate
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PCT/CN2016/100322
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English (en)
French (fr)
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吴晶晶
曾德康
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深圳市华星光电技术有限公司
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Priority to US15/315,718 priority Critical patent/US20180210301A1/en
Publication of WO2018040163A1 publication Critical patent/WO2018040163A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

Definitions

  • the invention belongs to the technical field of liquid crystal displays, and in particular to a liquid crystal panel and a liquid crystal display.
  • a liquid crystal panel such as a thin film transistor liquid crystal display (TFT LCD)
  • TFT LCD thin film transistor liquid crystal display
  • the TFT is turned on within a limited time.
  • the resolution and refresh rate of the liquid crystal panel become higher and higher, the turn-on time of each scan line is greatly shortened, and the problem of insufficient charging time of the liquid crystal panel (storage capacitor Cst and liquid crystal capacitor Clc) becomes more prominent, so there is a problem of insufficient charging time. .
  • pre-charge and charge sharing There are two methods for solving the problem of insufficient charging time in the prior art: pre-charge and charge sharing.
  • the pre-charging method the gate of the next row is turned on in advance, so that the data of the previous row is precharged to the next row, and the polarity of the charge of the next row is reversed in advance, thereby reducing the charging time of the liquid crystal panel.
  • the charge sharing method according to the polarity inversion signal, in the blanking region before the polarity inversion, the data driver internally connects the adjacent odd data lines with the even data lines, and the parasitic capacitances of the two data lines The charge is neutralized, which shortens the charging time of the liquid crystal panel.
  • pre-charging is only applicable to column inversion or frame inversion.
  • Charge sharing is only applicable to inversion methods with higher polarity inversion frequencies such as dot inversion.
  • an exemplary embodiment of the present invention provides a liquid crystal surface that can be shortened A thin film transistor liquid crystal panel that charges the board and reduces the power consumption and temperature of the data driver.
  • a liquid crystal panel including: a plurality of gate lines extending in a row direction and parallel to each other; a plurality of data lines extending in a column direction and parallel to each other, the data a line is disposed to intersect the gate line; a sub-pixel disposed at an intersection of each of the data lines and each of the gate lines; a switch disposed between adjacent sub-pixels and even sub-pixels adjacent to each other on each line a thin film transistor; the odd sub-pixel is a sub-pixel located in an odd column, and the even sub-pixel is a sub-pixel located in an even column; wherein a gate of the switching thin film transistor is connected to a gate line of a corresponding upper row, The drain of the switching thin film transistor is connected to a corresponding odd sub-pixel, and the source of the switching thin film transistor is connected to a corresponding even sub-pixel.
  • the sub-pixel includes: a thin film transistor, a liquid crystal capacitor, and a storage capacitor, a gate of the thin film transistor is connected to a corresponding gate line, and a source of the thin film transistor is connected to a corresponding data line, the liquid crystal A capacitor and the storage capacitor are connected in parallel and connected to a drain of the thin film transistor.
  • a drain of the switching thin film transistor is connected to a parallel storage capacitor and a liquid crystal capacitor of a corresponding odd sub-pixel, and a source of the switching thin film transistor is connected to a parallel storage capacitor and a liquid crystal capacitor of the corresponding even sub-pixel .
  • the voltage of the nth gate line is converted from a low level to a high level and remains converted to a low level after a certain period of time, and the voltage of the n+1th gate line is converted to a low level. Converting from a low level to a high level for a certain period of time, so that when the voltage of the nth gate line is high, the switching thin film transistor connected to the n+1th gate line is turned on, The n+1th gate line neutralizes the charges of the storage capacitors and the liquid crystal capacitors of the odd-numbered sub-pixels and the even-numbered sub-pixels on the n+1th row in the case where the voltage is at the low level.
  • the thin film transistor and/or the switching thin film transistor is an amorphous silicon thin film transistor or a low temperature polysilicon thin film transistor.
  • a liquid crystal display including a liquid crystal panel, a gate driver, and a data driver, the liquid crystal panel including: a plurality of gate lines extending in a row direction and parallel to each other; The plurality of gate lines are connected to the gate driver; a plurality of data lines extending in a column direction and parallel to each other, the data lines are disposed to intersect with the gate lines; and the plurality of data lines are connected And receiving the data driver; a sub-pixel disposed at an intersection of each of the data lines and each of the gate lines; and a switching thin film transistor disposed between the odd-numbered sub-pixels and the even-numbered sub-pixels adjacent to each other on each of the rows; The odd sub-pixels are sub-pixels located in an odd-numbered column, and the even-numbered sub-pixels are sub-pixels located in an even-numbered column; wherein a gate of the switching thin film transistor is connected to a gate line of a corresponding upper row, the
  • the voltage supplied from the gate driver to the nth gate line is converted from a low level to a high level and remains converted to a low level after a certain period of time, and the gate is converted to a low level.
  • the voltage supplied from the pole driver to the n+1th gate line is converted from a low level to a high level for a certain period of time, so that when the voltage supplied from the gate driver to the nth gate line is high
  • the switching thin film transistor connected to the n+1th gate line is turned on, so that the n+1th gate line is adjacent to each other on the n+1th row when the voltage is low level
  • the storage capacitors of the sub-pixels and the even sub-pixels and the charges of the liquid crystal capacitors are mutually neutralized.
  • the liquid crystal panel provided according to an exemplary embodiment of the present invention can shorten the charging time of the liquid crystal panel and reduce the power consumption and temperature of the data driver.
  • FIG. 1 is a schematic view showing a liquid crystal panel according to an exemplary embodiment of the present invention
  • FIG. 2 is a timing chart showing charging of a liquid crystal panel according to an exemplary embodiment of the present invention.
  • the liquid crystal panel referred to herein includes a plurality of pixels, each of which includes sub-pixels of a plurality of colors, such as, by way of example only, sub-pixels of a plurality of colors may be red sub-pixels, green sub-pixels, and blue Subpixel.
  • FIG. 1 is a schematic view showing a liquid crystal display (LCD) according to an exemplary embodiment of the present invention.
  • LCD liquid crystal display
  • the LCD includes: a liquid crystal panel assembly 100; a gate driver 200 and a data driver 300, both of which are connected to the liquid crystal panel assembly 100.
  • the liquid crystal panel assembly 100 comprising: a plurality of transfer gate signal gate lines G 1 to G n, a plurality of data lines transmitting data signals D 1 through D 2m, a plurality of sub-pixels and a plurality of switching thin film transistors (TFT) T1.
  • TFT switching thin film transistors
  • Gate lines G 1 through G n extend in a row direction and are parallel to each other, the data lines D 1 through D 2m extend in the column direction and parallel to each other. Each of the gate lines and each of the data lines are disposed across and separated from each other.
  • a sub-pixel is disposed at the intersection of each gate line and each data line.
  • Each of the sub-pixels includes a thin film transistor T2, a liquid crystal capacitor Clc, and a storage capacitor Cst.
  • Each of the thin film transistors T2 is connected to a corresponding gate line and a corresponding data line.
  • the liquid crystal capacitor Clc and the storage capacitor Cst are connected in parallel to the thin film transistor T2.
  • a switching thin film transistor T1 is disposed between odd-numbered sub-pixels and even-numbered sub-pixels adjacent to each other on each pixel row (or row).
  • the gate G of the switching TFT T1 is connected to the gate line of the previous pixel row, the drain thereof is connected to the storage capacitor Cst of the odd sub-pixel and the liquid crystal capacitor Clc, and the source is connected to the storage capacitor Cst of the even sub-pixel and the liquid crystal capacitor Clc.
  • An odd sub-pixel refers to a sub-pixel located in an odd column.
  • Even sub-pixels refer to sub-pixels located in even columns.
  • the gate driver 200 is connected to the gate lines G 1 to G n of the liquid crystal panel assembly 100 to apply gate signals (which are composed of a high-level voltage signal and a low-level voltage signal) to the gate lines G 1 to G n Voltage signal).
  • the data driver 300 is connected to the data lines D 1 to D 2m of the liquid crystal panel assembly 100 and applies a data voltage to each sub-pixel.
  • the difference between the data voltage applied to each sub-pixel and the common voltage Vcom can be interpreted as a voltage with which the liquid crystal capacitor Clc of each sub-pixel is charged, that is, a pixel voltage.
  • the arrangement of the liquid crystal molecules in the liquid crystal layer varies depending on the amplitude of the pixel voltage, and thus the polarity of the light transmitted through the liquid crystal layer can also be changed, resulting in a change in the transmittance of the liquid crystal layer.
  • FIG. 2 is a timing chart showing charging of a liquid crystal panel according to an exemplary embodiment of the present invention.
  • the gate driver 200 applies a high level signal to the gate line G n-1 , and the gate of the switching thin film transistor T1 between the factor pixel A and the sub-pixel B is connected to the gate line G n- 1 , so that the switching thin film transistor T1 between the sub-pixel A and the sub-pixel B is turned on, the charges of the sub-pixel A and the storage capacitor Cst of the sub-pixel B and the liquid crystal capacitor Clc are mutually neutralized, and the sub-pixel B is made of a positive high potential a The point is lowered to point c, and the sub-pixel A is raised from the low-level b-point of the negative polarity to the point c, and the charges are neutralized with each other.
  • the gate driver 200 applies a high level signal to the gate line G n a second time period, the gate line G n connected to the pixel thin film transistor T2 is turned on, the data driver to the gate line 300 G All the sub-pixels connected to n data voltage is applied to all the sub-pixels connected to the gate line G n is charged. Due to the charge neutralization in the first time period t 1 , in the second time period t 2 , the thin film transistor T2 of the sub-pixel A and the sub-pixel B can be charged from a voltage level closer to the target sub-pixel (ie, the sub-pixel B is charged from point c to point e, and sub-pixel A is charged from point c to point d), thereby reducing charging time. In addition, neutralizing the sub-pixel charges with each other can also reduce the power consumption and temperature of the data driver 300.
  • each gate line is sequentially turned on in a row order, that is, the voltage of the gate line G n-1 of the liquid crystal panel can be converted from a low level to a high level for a certain period of time. After that, it is converted to a low level, and the gate line G n voltage is converted from a low level to a high level while being converted to a low level for a certain period of time, so that the voltage of the gate line of the current pixel row is high.
  • the switching TFT of the next pixel row is turned on, so that the gate line of the next pixel row is in the case where the voltage is at a low level (that is, before the actual sub-pixel voltage is written), the gate lines of the next pixel row are mutually
  • the charge of the storage capacitor Cst and the liquid crystal capacitor Clc of the adjacent odd-numbered sub-pixels and the even-numbered sub-pixels are mutually neutralized, so that the charging time of the liquid crystal panel can be shortened, and the power consumption and temperature of the data driver can be reduced.
  • the above method according to the present invention can be implemented as computer code in a computer readable recording medium.
  • the computer code can be implemented by those skilled in the art in accordance with the description of the above method.
  • the above method of the present invention is implemented when the computer code is executed in a computer.
  • each unit in the driving device of the liquid crystal panel may be implemented as a hardware component.
  • Those skilled in the art can implement the various units using, for example, a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), depending on the processing performed by the various defined units.
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶面板（100），包括：按行方向延伸且彼此平行的多条栅极线；按列方向延伸且彼此平行的多条数据线，数据线与栅极线交叉设置；在每条数据线与每条栅极线的交叉处设置的子像素；在每一行上的彼此相邻的奇数子像素和偶数子像素之间设置的开关薄膜晶体管（T1）；奇数子像素为位于奇数列的子像素，偶数子像素为位于偶数列的子像素；其中，开关薄膜晶体管（T1）的栅极（G）连接到对应的上一行的栅极线，开关薄膜晶体管（T1）的漏极连接到对应的奇数子像素，开关薄膜晶体管（T1）的源极连接到对应的偶数子像素。能够缩短液晶面板（100）的充电时间，并降低数据驱动器（200）的功耗及温度。

Description

液晶面板及液晶显示器 技术领域
本发明属于液晶显示器技术领域，具体地说，涉及一种液晶面板及液晶显示器。
背景技术
液晶面板逐行开启扫描线时通过数据线写入所需电压来实现画面的正常显示。为防止液晶面板的直流阻隔效应和直流残留，必须在液晶两端施加交流电压(此交流电压是以VCOM为零参考电位)，即数据驱动电压既有正极性又有负极性。
因此，液晶面板(诸如，薄膜晶体管液晶显示器(TFT LCD))的工作过程是不断地将像素电极由正极性充电至负极性，再由负极性充电至正极性，而此充电过程必需在每行TFT打开的有限时间内完成。随着液晶面板解析度及刷新频率越来越高，每条扫描线开启时间大为缩短，液晶面板充电时间(存储电容器Cst和液晶电容Clc)不足的问题愈加突出，因此存在充电时间不足的问题。
现有技术中解决充电时间不足的方法有两种：预充电(pre-charge)和电荷分享(charge sharing)。在预充电方法中，下一行的栅极提前打开，使上一行的数据预充到下一行，下一行的电荷极性得以提前反转，从而缩减液晶面板充电时间。在电荷分享方法中，根据极性反转信号，在极性反转前的消隐(blanking)区，数据驱动器内部将相邻奇数数据线与偶数数据线相连，两条数据线上寄生电容的电荷中和，使液晶面板充电时间缩短。然而，预充电只适用于列反转或帧反转，电荷分享只适用于点反转等极性反转频率较高的反转方式。
发明内容
为克服现有技术的不足，本发明的示例性实施例提供一种能够缩短液晶面 板的充电时间并降低数据驱动器的功耗及温度的薄膜晶体管液晶面板。
根据本发明的示例性实施例一方面提供了一种液晶面板，其包括：按行方向延伸且彼此平行的多条栅极线；按列方向延伸且彼此平行的多条数据线，所述数据线与所述栅极线交叉设置；在每条数据线与每条栅极线的交叉处设置的子像素；在每一行上的彼此相邻的奇数子像素和偶数子像素之间设置的开关薄膜晶体管；所述奇数子像素为位于奇数列的子像素，所述偶数子像素为位于偶数列的子像素；其中，所述开关薄膜晶体管的栅极连接到对应的上一行的栅极线，所述开关薄膜晶体管的漏极连接到对应的奇数子像素，所述开关薄膜晶体管的源极连接到对应的偶数子像素。
进一步地，所述子像素包括：薄膜晶体管、液晶电容器和存储电容器，所述薄膜晶体管的栅极连接到相应的栅极线，所述薄膜晶体管的源极连接到相应的数据线，所述液晶电容器和所述存储电容器并联且连接到所述薄膜晶体管的漏极。
进一步地，所述开关薄膜晶体管的漏极连接到对应的奇数子像素的并联的存储电容器和液晶电容器，所述开关薄膜晶体管的源极连接到对应的偶数子像素的并联的存储电容器和液晶电容器。
进一步地，第n条栅极线的电压由低电平转换为高电平并保持特定时间段之后转换为低电平，在转换为低电平的同时第n+1条栅极线的电压由低电平转换为高电平并保持特定时间段，从而当第n条栅极线的电压为高电平时，与第n+1条栅极线连接的所述开关薄膜晶体管导通，使第n+1条栅极线在电压为低电平的情况下第n+1行上的彼此相邻的奇数子像素与偶数子像素的存储电容器和液晶电容器的电荷相互中和。
进一步地，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
根据本发明的示例性实施例的另一方面提供了一种液晶显示器，包括液晶面板、栅极驱动器和数据驱动器，所述液晶面板包括：按行方向延伸且彼此平行的多条栅极线；所述多条栅极线连接到所述栅极驱动器；按列方向延伸且彼此平行的多条数据线，所述数据线与所述栅极线交叉设置；所述多条数据线连 接到所述数据驱动器；在每条数据线与每条栅极线的交叉处设置的子像素；在每一行上的彼此相邻的奇数子像素和偶数子像素之间设置的开关薄膜晶体管；所述奇数子像素为位于奇数列的子像素，所述偶数子像素为位于偶数列的子像素；其中，所述开关薄膜晶体管的栅极连接到对应的上一行的栅极线，所述开关薄膜晶体管的漏极连接到对应的奇数子像素，所述开关薄膜晶体管的源极连接到对应的偶数子像素。
进一步地，所述栅极驱动器提供给第n条栅极线的电压由低电平转换为高电平并保持特定时间段之后转换为低电平，在转换为低电平的同时所述栅极驱动器提供给第n+1条栅极线的电压由低电平转换为高电平并保持特定时间段，从而当所述栅极驱动器提供给第n条栅极线的电压为高电平时，与第n+1条栅极线连接的所述开关薄膜晶体管导通，使第n+1条栅极线在电压为低电平的情况下第n+1行上的彼此相邻的奇数子像素与偶数子像素的存储电容器和液晶电容器的电荷相互中和。
根据本发明的示例性实施例提供的液晶面板能够缩短液晶面板的充电时间并降低数据驱动器的功耗及温度。
将在接下来的描述中部分阐述本发明另外的方面和/或优点，还有一部分通过描述将是清楚的，或者可以经过本发明的实施而得知。
附图说明
通过下面结合附图进行的对实施例的描述，本发明的上述和/或其它目的和优点将会变得更加清楚，其中：
图1是示出根据本发明示例性实施例的液晶面板的示意图；
图2是示出根据本发明示例性实施例的液晶面板的充电时序图。
具体实施方式
现将详细描述本发明的示例性实施例，所述实施例的示例在附图中示出，其中，相同的标号指示相同的部分。以下将通过参照附图来说明所述实施例，以便解释本发明。
应予说明，这里所说的液晶面板包括多个像素，每一像素包括多个颜色的子像素，诸如，仅作为示例，多个颜色的子像素可以是红色子像素、绿色子像素和蓝色子像素。
图1是示出根据本发明示例性实施例的液晶显示器(LCD)的示意图。
参照图1，LCD包括：液晶面板组件100；栅极驱动器200和数据驱动器300，二者都连接到液晶面板组件100。
液晶面板组件100包括：传送栅极信号的多条栅极线G1至Gn、传送数据信号的多条数据线D1至D2m、多个子像素以及多个开关薄膜晶体管(TFT)T1。
栅极线G1至Gn按行方向延伸并且彼此平行，数据线D1至D2m按列方向延伸并且彼此平行。每条栅极线和每条数据线交叉设置且彼此隔离。在每条栅极线和每条数据线的交叉处设置一个子像素。每个子像素包括：薄膜晶体管T2、液晶电容器Clc和存储电容器Cst。每个薄膜晶体管T2连接到相应的栅极线和相应的数据线。液晶电容器Clc和存储电容器Cst并联连接到薄膜晶体管T2。
每个像素行(或称行)上的彼此相邻的奇数子像素与偶数子像素中间设置一开关薄膜晶体管T1。开关TFT T1的栅极G连接到上一个像素行的栅极线，其漏极连接到奇数子像素的存储电容器Cst和液晶电容器Clc，其源极连接到偶数子像素的存储电容器Cst和液晶电容器Clc。奇数子像素指的是位于奇数列的子像素。偶数子像素指的是位于偶数列的子像素。
栅极驱动器200连接到液晶面板组件100的栅极线G1至Gn，以向栅极线G1至Gn施加栅极信号(其是由高电平电压信号和低电平电压信号组成的电压信号)。
数据驱动器300连接到液晶面板组件100的数据线D1至D2m，并向各子像素施加数据电压。
施加到每个子像素的数据电压和公共电压Vcom之间的差可以被解释为是利用其对每个子像素的液晶电容器Clc充电的电压，即像素电压。液晶层内的液晶分子的排列根据像素电压的幅度而变化，因而通过液晶层传送的光的极性也可以变化，从而导致液晶层的透射率的变化。
以下对根据本发明的实施例的彼此相邻的奇数子像素与偶数子像素的充电过程进行说明。
图2是示出根据本发明示例性实施例的液晶面板的充电时序图。
结合图1和图2所示，以图1所示的栅极线Gn连接的的子像素A和子像素B的充电过程为例：
在第一时间段t1，栅极驱动器200向栅极线Gn-1施加高电平信号，因子像素A和子像素B之间的开关薄膜晶体管T1的栅极连接到栅极线Gn-1上，故子像素A和子像素B之间的开关薄膜晶体管T1打开，子像素A与子像素B的存储电容器Cst和液晶电容器Clc的电荷相互中和，子像素B由正极性的高电位a点降到c点，子像素A由负极性的低电位b点升到c点，电荷相互中和。
在第二时间段t2，栅极驱动器200向栅极线Gn施加高电平信号，栅极线Gn连接的所有的子像素的薄膜晶体管T2导通，数据驱动器300向栅极线Gn连接的所有的子像素施加数据电压，以对栅极线Gn连接的所有的子像素进行充电。由于在第一时间段t1的电荷中和作用，在第二时间段t2，子像素A和子像素B的薄膜晶体管T2可以从较接近目标子像素的电压准位进行充电(即，子像素B由c点充到e点，子像素A由c点充到d点)，从而可减少充电时间。此外，子像素电荷相互中和亦可降低数据驱动器300的功耗及温度。
根据本发明的示例性实施例，按行顺序依次打开每条栅极线，也就是说，液晶面板的栅极线Gn-1的电压可由低电平转换为高电平并保持特定时间段之后转换为低电平，在转换为低电平的同时栅极线Gn电压由低电平转换为高电平并保持特定时间段，从而当当前像素行的栅极线的电压为高电平时下一像素行的开关TFT打开，使下一像素行的栅极线在电压为低电平的情况下(即，在实际子像素电压写入前)下一像素行的栅极线的彼此相邻的奇数子像素与偶数子像素的存储电容器Cst和液晶电容器Clc的电荷相互中和，从而能够缩短液晶面板的充电时间，并降低数据驱动器的功耗及温度。
此外，根据本发明的上述方法可以被实现为计算机可读记录介质中的计算机代码。本领域技术人员可以根据对上述方法的描述来实现所述计算机代码。当所述计算机代码在计算机中被执行时实现本发明的上述方法。
此外，根据本发明的示例性实施例的液晶面板的驱动装置中的各个单元可被实现为硬件组件。本领域技术人员根据限定的各个单元所执行的处理，可以使用例如现场可编程门阵列(FPGA)或专用集成电路(ASIC)来实现各个单元。
本发明的以上实施例仅仅是示例性的，而本发明并不受限于此。本领域技术人员应该理解：在不脱离本发明的原理和精神的情况下，可对这些实施例进行改变，其中，本发明的范围在权利要求及其等同物中限定。

Claims (16)

  1. 一种液晶面板，其中，所述液晶面板包括：
    按行方向延伸且彼此平行的多条栅极线；
    按列方向延伸且彼此平行的多条数据线；所述数据线与所述栅极线交叉设置；
    在每条数据线与每条栅极线的交叉处设置的子像素；
    在每一行上的彼此相邻的奇数子像素和偶数子像素之间设置的开关薄膜晶体管；所述奇数子像素为位于奇数列的子像素，所述偶数子像素为位于偶数列的子像素；
    其中，所述开关薄膜晶体管的栅极连接到对应的上一行的栅极线，所述开关薄膜晶体管的漏极连接到对应的奇数子像素，所述开关薄膜晶体管的源极连接到对应的偶数子像素。
  2. 根据权利要求1所述的液晶面板，其中，所述子像素包括：薄膜晶体管、液晶电容器和存储电容器，所述薄膜晶体管的栅极连接到相应的栅极线，所述薄膜晶体管的源极连接到相应的数据线，所述液晶电容器和所述存储电容器并联且连接到所述薄膜晶体管的漏极。
  3. 根据权利要求2所述的液晶面板，其中，所述开关薄膜晶体管的漏极连接到对应的奇数子像素的并联的存储电容器和液晶电容器，所述开关薄膜晶体管的源极连接到对应的偶数子像素的并联的存储电容器和液晶电容器。
  4. 根据权利要求3所述的液晶面板，其中，第n条栅极线的电压由低电平转换为高电平并保持特定时间段之后转换为低电平，在转换为低电平的同时第n+1条栅极线的电压由低电平转换为高电平并保持特定时间段，从而当第n条栅极线的电压为高电平时，与第n+1条栅极线连接的所述开关薄膜晶体管导通，使第n+1条栅极线在电压为低电平的情况下第n+1行上的彼此相邻的奇数子像素与偶数子像素的存储电容器和液晶电容器的电荷相互中和。
  5. 根据权利要求1所述的液晶面板，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  6. 根据权利要求2所述的液晶面板，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  7. 根据权利要求3所述的液晶面板，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  8. 根据权利要求4所述的液晶面板，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  9. 一种液晶显示器，包括液晶面板、栅极驱动器和数据驱动器，其中，所述液晶面板包括：
    按行方向延伸且彼此平行的多条栅极线；所述多条栅极线连接到所述栅极驱动器；
    按列方向延伸且彼此平行的多条数据线；所述数据线与所述栅极线交叉设置；所述多条数据线连接到所述数据驱动器；
    在每条数据线与每条栅极线的交叉处设置的子像素；
    在每一行上的彼此相邻的奇数子像素和偶数子像素之间设置的开关薄膜晶体管；所述奇数子像素为位于奇数列的子像素，所述偶数子像素为位于偶数列的子像素；
    其中，所述开关薄膜晶体管的栅极连接到对应的上一行的栅极线，所述开关薄膜晶体管的漏极连接到对应的奇数子像素，所述开关薄膜晶体管的源极连接到对应的偶数子像素。
  10. 根据权利要求9所述的液晶显示器，其中，所述子像素包括：薄膜晶体管、液晶电容器和存储电容器，所述薄膜晶体管的栅极连接到相应的栅极线，所述薄膜晶体管的源极连接到相应的数据线，所述液晶电容器和所述存储电容器并联且连接到所述薄膜晶体管的漏极。
  11. 根据权利要求10所述的液晶显示器，其中，所述开关薄膜晶体管的漏极连接到对应的奇数子像素的并联的存储电容器和液晶电容器，所述开关薄膜晶体管的源极连接到对应的偶数子像素的并联的存储电容器和液晶电容器。
  12. 根据权利要求11所述的液晶显示器，其中，所述栅极驱动器提供给第n条栅极线的电压由低电平转换为高电平并保持特定时间段之后转换为低电平，在转换为低电平的同时所述栅极驱动器提供给第n+1条栅极线的电压由低电平转换为高电平并保持特定时间段，从而当所述栅极驱动器提供给第n条栅极线的电压为高电平时，与第n+1条栅极线连接的所述开关薄膜晶体管导通，使第n+1条栅极线在电压为低电平的情况下第n+1行上的彼此相邻的奇数子像素与偶数子像素的存储电容器和液晶电容器的电荷相互中和。
  13. 根据权利要求9所述的液晶显示器，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  14. 根据权利要求10所述的液晶显示器，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  15. 根据权利要求11所述的液晶显示器，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
  16. 根据权利要求12所述的液晶显示器，其中，所述薄膜晶体管和/或所述开关薄膜晶体管为非晶硅薄膜晶体管或者低温多晶硅薄膜晶体管。
PCT/CN2016/100322 2016-08-31 2016-09-27 液晶面板及液晶显示器 WO2018040163A1 (zh)

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