WO2018201831A1 - 通信方法和装置 - Google Patents

通信方法和装置 Download PDF

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Publication number
WO2018201831A1
WO2018201831A1 PCT/CN2018/081506 CN2018081506W WO2018201831A1 WO 2018201831 A1 WO2018201831 A1 WO 2018201831A1 CN 2018081506 W CN2018081506 W CN 2018081506W WO 2018201831 A1 WO2018201831 A1 WO 2018201831A1
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WIPO (PCT)
Prior art keywords
code block
code
block
sequence
value
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PCT/CN2018/081506
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English (en)
French (fr)
Inventor
郑晨
马亮
魏岳军
曾歆
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18793985.5A priority Critical patent/EP3570476A4/en
Priority to BR112019022803-9A priority patent/BR112019022803A2/pt
Priority to JP2019560397A priority patent/JP2020519174A/ja
Publication of WO2018201831A1 publication Critical patent/WO2018201831A1/zh
Priority to US16/196,824 priority patent/US10419158B2/en
Priority to US16/562,389 priority patent/US10985868B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H04L1/1845—Combining techniques, e.g. code combining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0025—Transmission of mode-switching indication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present application relates to communication technologies, and more particularly to a communication method and apparatus.
  • LDPC low density parity check bits
  • a new radio (NR) system it is necessary to implement code block group based transmission.
  • the existing rate matching algorithm is based on a system using Turbo code coding.
  • Turbo code coding both the initial transmission and the retransmission are for all the code blocks in one transport block. Therefore, Some rate matching algorithms are not applicable to systems based on code block group transmission.
  • the communication method and apparatus provided by the embodiments of the present application are for providing a scheme suitable for a system based on code block group transmission.
  • the present application provides a rate matching method, where the rate matching method includes: acquiring an input sequence, where the input sequence is an initial transmission sequence or a retransmission sequence corresponding to a transport block, where the input sequence includes M code blocks. Group, the value of M is less than or equal to the number of code block groups obtained after the transmission block is divided;
  • the number of blocks C t , and the soft buffer size N IR of the transport block are determined; a set of bits for transmission is determined according to the B j ; an output sequence is obtained from the set of bits.
  • an embodiment of the present application further provides a communication device.
  • the communication device can be used to implement the communication method of the first aspect described above.
  • the communication device can be a terminal, a base station, or a baseband chip, or a data signal processing chip, or a general purpose chip.
  • the soft buffer size when each code block rate is matched is determined according to the actually transmitted code block group, so that resources can be fully utilized and performance can be improved.
  • N max represents the maximum coded block length available. In this way, the encoder only needs to complete a relatively simple coding operation, and the remaining restrictions are completed at the time of rate matching, and the function implementation of each stage is more clearly defined.
  • the present application further provides a communication method, where the method is applicable to retransmitting a scenario, including: acquiring an input sequence of rate matching, where the input sequence is a retransmission sequence corresponding to a transport block, and the retransmitted
  • the sequence includes M code block groups, the value of M is smaller than the number of code block groups obtained after the transmission block is divided, the M code block groups include C t code blocks, and the C t code blocks are rate matched, where C
  • the length of the rate matched output sequence of each code block in the t code blocks satisfies the following condition: when j ⁇ C t - ⁇ -1, When j>C t - ⁇ -1,
  • the output of the rate matching is based on the retransmitted code block group, and the air interface resource can be more fully utilized.
  • the embodiment of the present application further provides a communication device.
  • the communication device can be used to implement the communication method of the above third aspect.
  • the communication device can be a terminal, a base station, or a baseband chip, or a data signal processing chip, or a general purpose chip.
  • the method and apparatus provided by the present application can be used in a communication system employing LDPC.
  • the communication device of the above second or fourth aspect includes a processor and a memory.
  • the memory is for storing instructions to implement the communication method described above; the processor is operative to execute the above instructions to implement the aforementioned communication method.
  • the communication device of the above second or fourth aspect includes a processor and a memory.
  • the memory is coupled to the processor; the processor is configured to implement a corresponding process, including but not limited to:
  • the input sequence is an initial transmission sequence or a retransmission sequence corresponding to a transport block
  • the input sequence includes M code block groups, and a value of M is less than or equal to that obtained by the transport block after segmentation Number of code block groups;
  • the foregoing communication device may further include a transceiver.
  • the embodiment of the present application further provides a computer program product, which, when run on a computer, causes the computer to implement the foregoing communication method.
  • the embodiment of the present application further provides a computer readable storage medium having stored thereon instructions for causing a computer to implement the foregoing communication method when running on a computer.
  • FIG. 1 is a simplified schematic diagram of a wireless communication system
  • FIG. 2 is a schematic diagram showing a simplified structure of a terminal
  • FIG. 3 is a simplified schematic diagram of a structure of a base station
  • FIG. 5 is a schematic flowchart of a communication method according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a set of transmitted bits according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a communication apparatus according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a communication apparatus according to still another embodiment of the present application.
  • a bit sequence is a sequence consisting of bits "0" and/or "1".
  • the length of the bit sequence refers to the number of bits included in the bit sequence.
  • the bit sequence 00 includes 2 bits and has a length of 2;
  • the bit sequence 111 includes 3 bits and has a length of 3;
  • the bit sequence "0100" includes 4 bits and has a length of 4.
  • a transport block (transport blocB, TB) and a code block (code blocB, CB) can all be regarded as a bit sequence.
  • the code block is obtained by dividing the transport block or the processed transport block, and is an encoded object. Therefore, in the present application, the code block length refers to the number of bits included in the bit sequence corresponding to the code block, and the code block length may also be referred to as a code block size; the transport block length refers to the bit sequence corresponding to the transport block. The number of bits included, the transport block length may also be referred to as the transport block size. It will be appreciated that as technology advances, transport blocks or code blocks may have different terminology names.
  • the processed transport block may also be understood as a transport block, and the process may be to add a check bit on the basis of the initial transport block, for example, adding a cyclic redundancy check (CRC) bit.
  • CRC cyclic redundancy check
  • the communication device is a device having a communication function.
  • the communication device may be a base station, or a terminal, or a chip or the like, and the chip may be, for example, a baseband chip or a communication chip.
  • the wireless communication system includes at least one base station B200 and a terminal T100 (only one shown in the figure).
  • the base station B200 can communicate with the terminal T100 using different communication resources.
  • the base station B200 can communicate with the terminal T100 using a wide beam and/or a narrow beam.
  • the wireless communication system may be a 4G communication system, such as an LTE (long term evolution) system, a 5G communication system, such as an NR system, and a communication system in which a plurality of communication technologies are integrated (for example, a communication system in which LTE technology and NR technology are integrated) ), as well as subsequent evolution systems.
  • Both the base station B200 and the terminal T100 can function as a transmitting device or a receiving device.
  • the terminal acts as a transmitting device
  • the base station acts as a receiving device
  • the base station acts as a transmitting device
  • the terminal acts as a receiving device.
  • the wireless communication system may include a radio access network and a core network, where the radio access network includes a base station B200, and may also include other access devices, such as a relay station, or other devices.
  • the core network may include a core network device, such as a mobility management entity, or other control or storage device.
  • the terminal T100 is a device having a wireless communication function, and may be a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • FIG. 2 shows a schematic structural diagram of the terminal T100. As shown in FIG.
  • the terminal T100 includes a processor, a memory, a radio frequency circuit, an antenna, and an input and output device.
  • the processor is mainly used for processing communication protocols and communication data, and controlling terminals, executing software programs, processing data of software programs, and the like.
  • Memory is primarily used to store software programs and data.
  • the RF circuit is mainly used for the conversion of the baseband signal and the RF signal and the processing of the RF signal.
  • the antenna is mainly used to transmit and receive RF signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, keyboards, etc., are primarily used to receive user input data and output data to the user. It should be noted that some types of terminals may not have input and output devices.
  • the processor When the data needs to be sent, the processor performs baseband processing on the data to be sent, and outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit performs radio frequency processing on the baseband signal, and then sends the radio frequency signal to the outside through the antenna in the form of electromagnetic waves.
  • the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor, which converts the baseband signal into data and processes the data.
  • Figure 2 shows only one memory and processor.
  • the memory may also be referred to as a storage medium or a storage device or the like.
  • the memory may be independent of the processor, or may be integrated with the processor, which is not limited in this embodiment of the present application.
  • the processor may include a baseband processor and/or a central processing unit.
  • the baseband processor is mainly used to process a communication protocol and communication data
  • the central processing unit is mainly used to control the entire terminal. Execute a software program that processes the data of the software program.
  • the processor in FIG. 2 may be a function of integrating a baseband processor and a central processing unit, and those skilled in the art may understand that the baseband processor and the central processing unit may also be independent processors.
  • the terminal may include multiple baseband processors to adapt to different network standards.
  • the terminal may include multiple central processors to enhance its processing capabilities.
  • the functions of the baseband processor and the central processing unit can be integrated on one processor.
  • the various components of the terminal can be connected via various buses.
  • the baseband processor can also be expressed as a baseband processing circuit or a baseband processing chip.
  • the central processing unit can also be expressed as a central processing circuit or a central processing chip.
  • the function of processing the communication protocol and the communication data may be built in the processor, or may be stored in the storage unit in the form of a software program, and the processor executes the software program to implement the baseband processing function.
  • the antenna and the radio frequency circuit having the transceiving function can be regarded as the transceiving unit of the terminal, and the processor having the processing function can be regarded as the processing unit of the terminal.
  • the terminal T100 includes a transceiver unit 101 and a processing unit 102.
  • the transceiver unit can also be referred to as a transceiver, a transceiver, a transceiver, and the like.
  • the processing unit may also be referred to as a processor, a processing board, a processing module, a processing device, and the like.
  • the device for implementing the receiving function in the transceiver unit 101 can be regarded as a receiving unit, and the device for implementing the sending function in the transceiver unit 101 is regarded as a sending unit, that is, the transceiver unit 101 includes a receiving unit and a sending unit.
  • the transceiver unit may also be referred to as a transceiver, a transceiver, or a transceiver circuit.
  • the receiving unit may also be referred to as a receiver, a receiver, or a receiving circuit or the like.
  • the transmitting unit may also be referred to as a transmitter, a transmitter, or a transmitting circuit, and the like.
  • the base station B200 which may also be referred to as a base station device, is a device deployed in a wireless access network to provide wireless communication functions.
  • a base station in an LTE network is called an evolved Node B (eNB or eNodeB)
  • a base station in an NR network is called a TRP (transmission reception point) or a gNB (generation node B, next generation Node B).
  • FIG. 3 shows a schematic structural diagram of the base station B200.
  • the base station B200 shown in FIG. 3 may be a split base station.
  • FIG. 3 shows, on the left, a distributed base station including antennas, a remote radio unit (RRU), and a baseband unit (BBU).
  • RRU remote radio unit
  • BBU baseband unit
  • a base station includes a 201 portion and a 202 portion.
  • Part 201 is mainly used for the transmission and reception of radio frequency signals and the conversion of radio frequency signals and baseband signals; the 202 part is mainly used for baseband processing and control of base stations.
  • Section 201 can be generally referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver.
  • the 202 portion is typically the control center of the base station and can generally be referred to as a processing unit.
  • part 201 is a transceiver unit, which may also be called a transceiver, or a transceiver, etc., which includes an antenna and a radio frequency unit, wherein the radio frequency unit is mainly used for radio frequency processing.
  • the device for implementing the receiving function in part 201 may be regarded as a receiving unit, and the device for implementing the transmitting function may be regarded as a transmitting unit, that is, the part 201 includes a receiving unit and a transmitting unit.
  • the receiving unit may also be referred to as a receiver, a receiver, or a receiving circuit, etc.
  • the transmitting unit may be referred to as a transmitter, a transmitter, or a transmitting circuit or the like.
  • the 202 part may include one or more boards, each board may include one or more processors and one or more memories, and the processor is used to read and execute programs in the memory. To achieve baseband processing functions and control of the base station. If multiple boards exist, the boards can be interconnected to increase processing power. As an optional implementation manner, multiple boards share one or more processors, or multiple boards share one or more memories, or multiple boards share one or more processes at the same time. Device.
  • the transmitting device sends the bit sequence to the receiving device, the bit sequence is divided, encoded, rate matched, code block cascaded, etc., as shown in FIG. 4 .
  • rate matching is to adjust the code rate to the desired output code rate.
  • L coded bits may be selected as an output of a cyclic buffer rate match, and different code rates may be obtained by adjusting the number of read coded bits;
  • the loop buffer rate match reads L coded bits from a specified start position in the buffer, which is called bit selection.
  • bit selection In general, the bits selected for transmission can be read from any location in the buffer. If the end of the buffer is reached, you can return to the beginning of the buffer to continue reading data. Therefore, loop-based rate matching can be achieved in a simple way.
  • the circular cache has the advantage of flexibility and granularity.
  • HARQ is an extremely important link adaptation technique in digital communication systems.
  • the receiving end decodes the data packet received by the receiving end, and if the decoding is correct, the ACK signal is fed back to the transmitting end to notify it to send a new data packet; if the decoding fails, the NACK signal is fed back to the transmitting end, and the transmitting end requests the transmitting end to resend the data. package.
  • the receiving end can improve the probability of successful decoding and achieve high reliability requirements for link transmission.
  • different locations can be specified in the circular buffer as the starting point for each data read.
  • the definition of the redundancy version (RV) determines the multiple starting positions of the transmission data read in the circular buffer.
  • the value of the redundancy version determines that the data transmitted this time is read in the circular buffer. Specific starting point location.
  • the coded block length is 96
  • the number of RVs is 4, which are RV0, RV1, RV2, and RV3 respectively. If 64 bits are read from RV0 to generate a code block, then Rate ratio after rate matching If 128 bits are read, the rate ratio after rate matching
  • the soft information buffer also referred to as soft buffer
  • the rate is matched at the transmitting end, the size of the soft buffer of the receiving end is taken into consideration, and the data is sent through the pair.
  • the restriction can ensure that the soft information received by the receiving end can be stored in the soft buffer without overflow.
  • the size of the soft buffer is the number of stored soft information.
  • the size of the soft buffer refers to how many 8-bit data can be stored, and an 8-bit of the receiving end.
  • the soft information corresponds to one bit of the originating end, so only the size of the soft buffer is used at the transmitting end, and the bit level data is actually stored.
  • the present application provides a communication method that can be applied to a communication system based on code block group transmission, such as a communication system employing LDPC coding, which may include initial transmission and/or retransmission.
  • the communication method is implemented by the communication device. It can be understood that the communication device is implemented in the embodiment of the present application.
  • the device located at the transmitting end may also be referred to as a first device. As shown in FIG. 5, the method may include:
  • the input sequence is an initial transmission sequence or a retransmission sequence corresponding to the transport block.
  • the input sequence is a rate matched input sequence and the output of the encoder can be viewed as an input sequence of a rate matching module.
  • the input sequence may be retransmission data or initial data.
  • the transport block or the processed transport block input performs a code block splitting operation, where the code block splitting operation may include dividing the transport block or the processed transport block into at least one code block, and the at least A code block can be divided into at least one code block group.
  • the number of code block groups may be determined before the code block is divided, or may be determined after the code block is divided.
  • the code block group check bit may be added according to the system design requirement for each code block group, which is not limited in this embodiment of the present application.
  • the code block group included in at least one code block obtained after the code block is divided by the transport block or the processed transport block is simply referred to as the code block group included in the transport block.
  • the input sequence includes M code block groups, and the M code block groups are included in the transport block for the scene in which the input sequence is the initial data. For example, if the number of code block groups included in the transport block is 4, according to the ACK fed back by the receiving end, it is known that the first code block group is correctly received, and then the retransmission may be the transmission of the next three code block groups, that is, The number of retransmitted code block groups is less than the number of initial code block groups. After determining the retransmitted code block group, the retransmitted code block group may be re-encoded and then rate-matched, or may not be re-encoded, which is not limited in this embodiment of the present application.
  • the value of B j may be determined based on at least one of the following parameters: a length K w encoded by the jth code block, a number C t of code blocks included in the M code block groups, and a soft buffer size N IR of the transport block And the maximum coded block length N max available is determined.
  • B j K w .
  • B j K w .
  • K w represents the encoded length K w of the jth code block
  • C t represents the number of code blocks included in the M code block groups
  • N IR represents the soft buffer size of the transport block
  • N max represents The maximum coded block length available.
  • each code block may determine the corresponding method by using the same method.
  • Soft cache size may be used.
  • K w may be an encoder notifying the rate matching module after encoding
  • a rate matching module may be learned by K w another embodiment, the present embodiment is not limited to this application embodiment.
  • N IR transport block (also referred to as a second device may be) related to, for example, (1) N IR is known by the following formula:
  • N soft soft information representing the number of bits corresponding to the level of capability of the receiving device (soft channel bits)
  • M DL_HARQ represents the maximum number of downlink HARQ processes
  • the constant for example, may be 8
  • K MIMO is a parameter corresponding to the transmission mode.
  • K MIMO may be 2 in some transmission modes
  • K MIMO may be 1 in some transmission modes.
  • the receiving apparatus according capability level by look-up table size N IR can be obtained, for example, may be learned by table lookup N soft decision based on the value K C N soft, and then in accordance with Equation (1) finally yields N IR .
  • the B j determined in S502 limits the set of bits that can be transmitted.
  • the white area (the non-slashed portion) in FIG. 6 represents a set of bits in the circular buffer that cannot be transmitted because of the soft buffer size limitation
  • the slashed grid portion represents a set of bits that can be transmitted, and the number of bits included in the set of transmittable bits is determined according to the size of the soft buffer.
  • the above-mentioned set of bits that can be transmitted is also the data that can be read in the circular buffer. For example, if the soft buffer size determined in S502 is 300 and the Kw is 400, then the loop buffer size is 400, then the first 300 bits in the encoded bit sequence are used as the bit set for transmission. Optionally, it is also possible to include padding bits in the transmitted bit set.
  • the rate matched output sequence is a bit sequence obtained by reading the RV value based on the above bit set. For example, reading is started from the corresponding starting position of RV0, and the length of reading is determined according to the bit length for each code block transmission. The length read is also the length of the rate matched output sequence.
  • the padding bit is included in the bit set, it can be skipped when reading.
  • the soft buffer size when each code block rate is matched is determined according to the actually transmitted code block group factor, and the soft cache resource can be fully utilized to improve performance.
  • the buffer of each code block is limited in the initial transmission.
  • the code rate (excluding the repeated part) of each code block is higher, and the coding gain is relatively limited.
  • the soft buffer of the code block is limited, the size is only 12000, then he can only follow 1 /2 code rate is encoded to 12000, and then 6,000 bits are repeated, so that a part of the coding gain is lost.
  • only part of the code block group is retransmitted, and then the soft buffer is re-allocated during retransmission.
  • Each code block can be allocated to a larger soft buffer for greater coding gain. For example, in the above example, it is assumed that each code block group contains only one code block. If the initial transmission contains two code block groups and only one code block group needs to be retransmitted, the available buffer size of the retransmitted code block group can be increased. Up to 24000, this can be encoded at 1/3 bit rate.
  • N max the coded block length does not exceed N max and At this time, B j can be determined as K w , where It can be understood that N IR is allocated to the size of each code block.
  • the limitation of the N max and the soft buffer size of the transport block on the coded block length is unified in the coding phase, which reduces redundant bits in rate matching and has low complexity.
  • B j is directly determined as K w , which is not limited in this application.
  • N max the output of the encoder considers N max and does not consider other factors
  • other factors such as N IR , may be taken into account when determining the size of the soft buffer corresponding to the code block, which may be:
  • the algorithm in the encoding stage is relatively simple and relatively easy to implement.
  • the method can also be applied to scenarios in which the N max and N IR are considered in the coding stage, and can also be applied to other scenarios.
  • B j is directly determined as This application does not limit this.
  • the soft buffer size B j corresponding to the jth code block may be determined as That is, the value of B j satisfies the formula: among them, Rounded down.
  • This implementation can be applied to the output of the encoder without any limitation, such as the scenario where the encoder directly encodes at the lowest bit rate, or the output of the encoder is subjected to one of, for example, N max and N IR or A scenario in which a plurality of factors are limited is not limited in this embodiment of the present application. In this way, the encoder only needs to complete a relatively simple coding operation, and the remaining restrictions are completed at the time of rate matching, and the function implementation of each stage is more clearly defined.
  • the various determinations B j manner, be understood that the number of C t, the value of transport blocks B and K w j is the j-th length of the encoded code block, the M code blocks included in the code block group
  • the soft buffer size N IR , the maximum coded block length available N max is related.
  • the length of the rate matched output sequence may satisfy the following conditions:
  • N L mainly appears in a multi-antenna scene.
  • N L is equal to the number of data streams actually transmitted.
  • the length of the rate matched output sequence can be determined by the number of bits used for each code block transmission. This length is determined by the air interface resources (ie, the number of RBs) and the number of code blocks of the entire transport block. For example, the entire air interface resource can be evenly distributed to Each code block. It should be noted that the foregoing method for determining the length of the rate matched output sequence may be applied to S504; or may be independent of the embodiment shown in FIG. 5, that is, any scenario based on code block retransmission may be used, It is limited to the manner of determining the size of the soft buffer corresponding to the jth code block in the embodiment of FIG. 5.
  • the embodiment of the present application further provides a communication method, which may be applicable to a retransmission scenario, including but not limited to the following steps:
  • the input sequence is a retransmission sequence corresponding to a transport block
  • the input sequence includes M code block groups, and a value of M is smaller than a number of code block groups obtained by the transport block after the segmentation
  • the M code block groups include C t code blocks; rate matching is performed on C t code blocks, wherein the length of the rate matched output sequence of each code block in the C t code blocks satisfies the following condition: when j ⁇ C t - ⁇ -1, When j>C t - ⁇ -1,
  • the output of the rate matching is based on the retransmitted code block group, and the air interface resource can be more fully utilized.
  • each code block calculates the size of the soft buffer according to the same method as the transmitting end, and receives the size according to the size of the soft buffer.
  • the soft information is subjected to a de-rate matching operation, and the soft information sequence whose output length is less than or equal to the soft buffer size is decoded by the decoder.
  • the device at the receiving end may be located in the second device, and may include a corresponding functional unit to implement the above functions.
  • the apparatus at the receiving end may include: a memory for storing instructions, and a processor for executing the instructions for implementing the above-described process of performing rate de-matching and decoding at the receiving end.
  • the embodiment of the present application further provides a communication device 700, which is used to implement the method performed by the foregoing embodiment in a transmitting end, such as a first device, where the communication device may be a terminal, a base station, a baseband chip, or Data signal processing chip, general purpose chip, or general purpose chip.
  • the apparatus can include:
  • the input unit 701 is configured to obtain an input sequence, where the input sequence includes M code block groups, and the value of M is less than or equal to the number of code block groups obtained after the transmission block is divided.
  • the obtaining unit 702 is configured to obtain a soft buffer size corresponding to the jth code block in the M code block groups, where the soft buffer size corresponding to the jth code block is based on the coding of the jth code block length K w, M code blocks included in the group number of code blocks C t, the soft buffer size N IR transmission block, after at least one of the maximum available coding code determined in the block length N max.
  • the determining unit 703 is configured to determine a transmitted bit set according to a soft buffer size corresponding to the jth code block.
  • the output unit 704 is configured to obtain an output sequence of the rate matching according to the bit set determined by the determining unit 703.
  • the embodiment of the present application further provides a communication device, which may be a terminal, a base station, a baseband chip, or a data signal processing chip, a general-purpose chip, or a general-purpose chip.
  • a communication device which may be a terminal, a base station, a baseband chip, or a data signal processing chip, a general-purpose chip, or a general-purpose chip.
  • the communication device includes: an input unit, configured to acquire an input sequence, where the input sequence is a retransmission sequence corresponding to the transport block, the input sequence includes M code block groups, and the value of M is smaller than the code obtained after the segmentation of the transport block a number of block groups, the M code block groups including C t code blocks;
  • the input unit and the rate matching unit in this embodiment may be implemented by the processor shown in FIG. 2, FIG. 3, or the rate matching module shown in FIG.
  • a communication device 800 is further provided in the embodiment of the present application. As shown in FIG. 8, the device may include: a memory 801 and a processor 802. Memory 801 and processor 802 may have different functions in different applications.
  • the memory 801 is coupled to a processor 802, configured to: acquire a rate matched input sequence, wherein the input sequence is an initial transmission sequence or a retransmission sequence corresponding to a transport block, the input sequence including M code block groups
  • the value of M is less than or equal to the number of code block groups obtained after the transmission block is divided; the soft buffer size B j corresponding to the jth code block in the M code block groups is obtained, wherein the value of B j is based on Decoding the length K w of the jth code block, the number C t of code blocks included in the M code block groups, and the soft buffer size N IR of the transport block; determining for transmission according to the B j a set of bits; and an output sequence that obtains a rate match based on the set of bits.
  • the processor 802 is configured to obtain a rate matched input sequence, where the input sequence is a retransmission sequence corresponding to a transport block, the input sequence includes M code block groups, and a value of M is smaller than the transport block. a number of code block groups obtained after the division, the M code block groups comprising C t code blocks;
  • the memory 801, all or part of the output sequence of the encoder, may be stored in the memory 801.
  • the output sequence stored in the memory may be the input sequence described in the above embodiment, wherein the C t code blocks included in the input sequence may respectively correspond to one virtual cache.
  • the virtual buffer also referred to as a circular buffer
  • size may be equal to K w.
  • the memory 801 can be a register, a random read/write memory (RAM), a cache (Cache), a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a hard disk, a mobile hard disk, a CD-ROM, or are well known in the art. Any other form of storage medium is not limited in this embodiment of the present application.
  • the processor 802 can be used to implement the functions of the obtaining unit 702, the determining unit 703, and the output unit 704 in the embodiment shown in FIG. Alternatively, the processor 802 may also be used for C t rate matched code blocks, wherein the length of code blocks C t rate matching each code block output sequence satisfy the following condition: when j ⁇ C t - ⁇ -1, When j>C t - ⁇ -1,
  • the memory 801 can be used to store instructions that implement the communication methods described in the various embodiments above; the processor 802 can be used to execute the instructions described above to implement the communication methods described in the various embodiments above. It can be understood that, in the above various cases, the memory 801 and the processor 802 may exist independently or may be integrated on one chip. The present embodiment does not limit the existence form of the memory 801 and the processor 802.
  • the communication device in the embodiment of the present application determines the soft buffer size when each code block rate matches according to factors such as the actually transmitted code block group, so that the small block length can support a lower code rate than the large block length, and It does not increase the size of the soft cache and can improve rate matching performance.
  • the communication device provided in the foregoing embodiments of FIG. 7 and FIG. 8 may include other units in addition to the functional units shown in the drawings, which is not limited in this embodiment, and may also include, for example, implementing a transceiving function. Unit.
  • the processor mentioned in the present application may be a central processing unit (CPU), a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), and a field programmable gate array (FPGA). Or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one unit, or each unit may exist separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above software function parts can be stored in the storage unit.
  • the storage unit includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform some of the steps of the methods described in various embodiments of the present application.
  • the storage unit includes: one or more memories, such as a read-only memory (ROM), a random access memory (RAM), and an electrically erasable programmable read only memory (EEPROM). and many more.
  • the storage unit may exist independently or may be integrated with the processor.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a Solid State DisB (SSD)) or the like.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape
  • an optical medium eg, a DVD
  • a semiconductor medium eg, a Solid State DisB (SSD)

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Abstract

本申请的一个实施例提供一种通信方法和装置。该方法包括：获取速率匹配的输入序列，其中所述输入序列是与传输块对应的初始传输序列或者重传序列，所述输入序列包括M个码块组，M的值小于或者等于所述传输块在分割后得到的码块组的数量；获取与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的；根据所述B j确定用于传输的比特集合；根据所述比特集合获取速率匹配的输出序列。该方法可以适用于基于码块组传输的系统，尽量充分利用资源，提升性能。

Description

通信方法和装置
本申请要求于2017年5月5日提交中国专利局、申请号为201710313891.X、申请名称为“通信方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术，尤其是一种通信方法和装置。
背景技术
随着技术的发展，在通信系统中引入了低密度奇偶校验比特(low density parity checB code,LDPC)对信息进行编码，其校验矩阵是一种稀疏矩阵。
在可以应用LDPC进行编码的系统中，例如，新无线(new radio，NR)系统，需要实现基于码块组的传输。而现有的速率匹配算法是基于采用Turbo码编码的系统的，在采用Turbo码编码的系统中，无论是初传还是重传，都是针对一个传输块中的所有码块的，因此，现有的速率匹配算法是不能适用于基于码块组传输的系统的。
发明内容
本申请的实施例提供的通信方法和装置，用于提供一种适用于基于码块组传输的系统的方案。
第一方面，本申请提供一种速率匹配方法，该速率匹配方法包括：获取输入序列，其中，该输入序列是与传输块对应的初始传输序列或者重传序列，该输入序列包括M个码块组，M的值小于或者等于所述传输块在分割后得到的码块组数量；
获取与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的；根据所述B j确定用于传输的比特集合；根据所述比特集合获取输出序列。
第二方面，本申请实施例还提供一种通信装置。该通信装置可用于实现上述第一方面的通信方法。该通信装置可以是终端，基站，或者基带芯片，或者数据信号处理芯片，或者通用芯片。
上述方法和装置中，根据实际发送的码块组确定每个码块速率匹配时的软缓存大小，从而可以尽量充分利用资源，提升性能。
一种可能的实现方式中，当K w是受到N max和N IR的限制时，B j的值满足B j＝K w，该方式中将N max和传输块的软缓存大小对编码后码块长度的限制统一在编码阶段完成，减少了速率匹配时的多余比特，复杂度较低。
一种可能的实现方式中，当K w是受到N max限制时，B j的值满足
Figure PCTCN2018081506-appb-000001
Figure PCTCN2018081506-appb-000002
该方式中，在编码阶段的算法相对简单，比较容易实现。
另一种可能的实现方式中，B j的值满足
Figure PCTCN2018081506-appb-000003
N max表示可用的最大编码后码块长度。该种方式中，编码器只需完成相对简单的编码操作，其余的限制都在速率匹配时完成，各个阶段的功能实现划分更明确。
第三方面，本申请还提供了一种通信方法，该方法适用于重传场景，包括：获取速率匹配的输入序列，其中，该输入序列是与传输块对应的重传序列，该重传的序列包括M个码块组，M的值小于传输块在分割后得到的码块组数量，所述M个码块组包括C t个码块；对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
Figure PCTCN2018081506-appb-000004
当j＞C t-γ-1时，
Figure PCTCN2018081506-appb-000005
该方法中，速率匹配的输出以重传的码块组为基础，可以更加充分的利用空口资源。
第四方面，本申请实施例还提供一种通信装置。该通信装置可用于实现上述第三方面的通信方法。该通信装置可以是终端，基站，或者基带芯片，或者数据信号处理芯片，或者通用芯片。
可选的，本申请提供的方法和装置可以用于采用LDPC的通信系统。
作为另一种可选的设计，上述第二方面或第四方面的通信装置包括处理器和存储器。存储器用于存储实现前述所描述的通信方法的指令；处理器用于运行上述指令以实现前述通信方法。
作为另一种可选的设计，上述第二方面或第四方面的通信装置包括处理器和存储器。存储器与处理器耦合；处理器用于实现相应的处理过程，包括但不限于：
获取速率匹配的输入序列，其中所述输入序列是与传输块对应的初始传输序列或者重传序列，所述输入序列包括M个码块组，M的值小于或者等于传输块在分割后得到的码块组数量；
获取与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传 输块的软缓存大小N IR确定的；根据所述B j确定用于传输的比特集合；以及根据所述比特集合获取速率匹配的输出序列。
可选的，上述通信装置还可以进一步包括收发机。
本申请实施例还提供一种计算机程序产品，当其在计算机上运行时，使得计算机实现前述通信方法。
本申请实施例还提供一种计算机可读存储介质，其上存储有指令，当在计算机上运行时，使得计算机实现前述通信方法。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍。
图1为无线通信系统的简化示意图；
图2为一种终端的结构简化示意图示意图；
图3为一种基站的结构简化示意图；
图4为示例的一种比特序列处理过程；
图5为本申请实施例一种通信方法流程示意图；
图6为本申请实施例一种传输的比特集合示意图；
图7为本申请实施例一种通信装置结构示意图；
图8为本申请又一实施例一种通信装置结构示意图。
具体实施方式
下面将结合本申请中的附图，对本申请的实施例进行描述。
以下对本申请中的一些术语和约定做出说明。
比特序列是一种由比特“0”和/或“1”组成的序列。比特序列的长度是指比特序列包括的比特的数目。例如：比特序列00包括2个比特，其长度为2；比特序列111包括3个比特，其长度为3；比特序列“0100”包括4个比特，其长度为4。
传输块(transport blocB,TB)以及码块(code blocB,CB)都可以视为一种比特序列。码块是通过对传输块或者经过处理的传输块分割后得到的，是编码的对象。因此，本申请中，码块长度指的是该码块对应的比特序列所包括的比特的数目，码块长度也可以称为码块大小；传输块长度指的是该传输块对应的比特序列所包括的比特 的数目，传输块长度也可以称为传输块大小。可以理解，随着技术的发展，传输块或者码块可能有不同的术语名称。本申请实施例中，经过处理的传输块也可以理解为传输块，该处理可以是在初始的传输块基础上添加校验比特，例如添加循环冗余校验(cyclic redundancy check，CRC)比特，本申请实施例对此不做限定。
在本申请实施例中，通信装置是一种具有通信功能的装置。例如：通信装置可以是基站、或者终端，或者芯片等，其中的芯片例如可以是基带芯片，或者通信芯片。
本申请实施例的技术方案可以用于如图1所示的无线通信系统中。如图1所示，在无线通信系统包括至少一个基站B200和终端T100(图中仅示出一个)。基站B200可以利用不同的通信资源与终端T100进行通信。例如：基站B200可以利用宽波束和/或窄波束与终端T100进行通信。该无线通信系统可以是4G通信系统，例如：LTE(长期演进，long term evolution)系统，5G通信系统，例如NR系统，多种通信技术融合的通信系统(例如LTE技术和NR技术融合的通信系统)，以及后续演进系统等。基站B200和终端T100均可以作为发送设备或接收设备。在上行链路，终端作为发送设备，基站作为接收设备，在下行链路，基站作为发送设备，终端作为接收设备。可以理解的是，所述无线通信系统可以包括无线接入网和核心网，所述无线接入网中包括基站B200，也可以包括其他接入设备，例如中继站，或者其他设备等。所述核心网可以包括核心网设备，如，移动管理实体，或其他控制或存储设备等。
本申请中，终端T100是一种具有无线通信功能的设备，可以是具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。需要说明的是，为便于理解和图示方便，图1，图2中，终端T100以手机作为例子。图2给出了终端T100的结构示意图。如图2所示，终端T100包括处理器、存储器、射频电路、天线以及输入输出装置。处理器主要用于对通信协议以及通信数据进行处理，以及对终端进行控制，执行软件程序，处理软件程序的数据等。存储器主要用于存储软件程序和数据。射频电路主要用于基带信号与射频信号的转换以及对射频信号的处理。天线主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。需要说明的是，有些种类的终端可以不具有输入输出装置。
当需要发送数据时，处理器对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到终端时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器，处理器将基带信号转换为数据并对该数据进行处理。
为了便于说明，图2仅示出了一个存储器和处理器。在实际的终端产品中，可以存在一个或多个处理器和一个或多个存储器。存储器也可以称为存储介质或者存储设备等。存储器可以是独立于处理器设置，也可以是与处理器集成在一起，本申请实施例对此不做限制。
作为一种可选的实现方式，处理器可以包括基带处理器和/或中央处理器，基带处理器主要用于对通信协议以及通信数据进行处理，中央处理器主要用于对整个终端进行控制，执行软件程序，处理软件程序的数据。图2中的处理器可以是集成了基带处理器和中央处理器的功能，本领域技术人员可以理解，基带处理器和中央处理器也可以是各自独立的处理器。可选的，终端可以包括多个基带处理器以适应不同的网络制式。可选的，终端可以包括多个中央处理器以增强其处理能力。可选的，可以将基带处理器和中央处理器的功能集成在一个处理器上实现。可选的，终端的各个部件可以通过各种总线连接。基带处理器也可以表述为基带处理电路或者基带处理芯片。中央处理器也可以表述为中央处理电路或者中央处理芯片。可选的，对通信协议以及通信数据进行处理的功能可以内置在处理器中，也可以以软件程序的形式存储在存储单元中，由处理器执行软件程序以实现基带处理功能。
在本申请实施例中，可以将具有收发功能的天线和射频电路视为终端的收发单元，将具有处理功能的处理器视为终端的处理单元。如图2所示，终端T100包括收发单元101和处理单元102。收发单元也可以称为收发器、收发机、收发装置等。处理单元也可以称为处理器，处理单板，处理模块、处理装置等。可选的，可以将收发单元101中用于实现接收功能的器件视为接收单元，将收发单元101中用于实现发送功能的器件视为发送单元，即收发单元101包括接收单元和发送单元。收发单元有时也可以称为收发机、收发器、或收发电路等。接收单元有时也可以称为接收机、接收器、或接收电路等。发送单元有时也可以称为发射机、发射器或者发射电路等。
基站B200，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。例如：在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB 或者eNodeB)，在NR网络中的基站称为TRP(收发点，transmission reception point)或者gNB(generation nodeB，下一代节点B)。图3给出了基站B200的一种结构示意图。图3所示的基站B200可以是分体式基站,例如图3靠左示出了包括天线(antennas)、无线射频单元(remote radio unit,RRU)和基带单元(baseband unit，BBU)的分布式基站，图3所示的基站也可以是一体式基站，例如图3靠右示出的小站(small cell)。可以理解，图3仅仅是给出了基站的一个实施例，基站的物理结构也可以是其他形式，本申请并不限定。一般而言，基站包括201部分以及202部分。201部分主要用于射频信号的收发以及射频信号与基带信号的转换；202部分主要用于基带处理，对基站进行控制等。201部分通常可以称为收发单元、收发机、收发电路、或者收发器等。202部分通常是基站的控制中心，通常可以称为处理单元。
作为一种可选的实施方式，201部分为收发单元，也可以称为收发机，或收发器等，其包括天线和射频单元，其中射频单元主要用于进行射频处理。可选的，可以将201部分中用于实现接收功能的器件视为接收单元，将用于实现发送功能的器件视为发送单元，即201部分包括接收单元和发送单元。接收单元也可以称为接收机、接收器、或接收电路等，发送单元可以称为发射机、发射器或者发射电路等。
作为一种可选的实施方式，202部分可以包括一个或多个单板，每个单板可以包括一个或多个处理器和一个或多个存储器，处理器用于读取和执行存储器中的程序以实现基带处理功能以及对基站的控制。若存在多个单板，各个单板之间可以互联以增加处理能力。作为一中可选的实施方式，也可以是多个单板共用一个或多个处理器，或者是多个单板共用一个或多个存储器，或者是多个单板同时共用一个或多个处理器。
可以理解是的，以上图1-图3仅为实施例，并不限于此。
需要说明的是，发送设备在将比特序列发送给接收设备之前，会对比特序列进行分割、编码、速率匹配、码块级联等处理，如图4所示。
可以理解的是，上述分割、编码、速率匹配、码块级联等处理可以通过图3或者图2中的处理器实现。
速率匹配的目的在于将码率调整到期望的输出码率。在循环缓存速率匹配(circular buffer rate matching)算法中，根据期望的输出码率，可以选择L个编码比特，作为循环缓存速率匹配的输出，调整读取编码比特的多少可得到不同的码率；循环缓存速率匹配从缓存器中某个指定的开始位置读出L个编码比特，被称为比特选择。总 的来说，被选择用于传输的比特可以从缓存器中的任何位置开始读出来。如果达到缓存器的末尾，可以返回到缓存器的开始位置继续读取数据。所以，通过简单的方法便可实现基于循环缓存的速率匹配。对于混合自动重传请求(hybrid automatic repeat request，HARQ)，循环缓存又具有灵活性和颗粒度的优势。
HARQ是一种数字通信系统中极其重要的链路自适应技术。接收端对其接收的数据包进行译码，若译码正确则反馈ACK信号给发送端，通知其发送新的数据包；若译码失败则反馈NACK信号给发送端，请求发送端重新发送数据包。接收端通过对多次重传的数据包译码，可以提高其译码成功概率，实现链路传输的高可靠性要求。在HARQ方式下，在循环缓存中可以指定不同的位置作为每次传输数据读取的起点位置。通过对冗余版本(redundancy version，RV)的定义即确定了传输数据在循环缓存中读取的多个起点位置，冗余版本取值便确定了本次传输的数据在循环缓存中读取的具体起点位置。
假设编码码率为1/3，编码后的码块长度为96，RV的数目为4，分别为RV0，RV1,RV2,RV3，如果从RV0开始读取64个比特生成一个码块的话，则速率匹配后的码率
Figure PCTCN2018081506-appb-000006
如果读取128个比特的话，则速率匹配后的码率
Figure PCTCN2018081506-appb-000007
由于接收端能力等因素，可能会存在接收端的软信息缓存(也可以称为软缓存)受限的情况，在发送端进行速率匹配时，将接收端的软缓存的大小考虑进去，通过对发送数据进行限制，可以保证接收端接收到的软信息能够存储在软缓存中，不会溢出。
可以理解的是，软缓存的大小是存储的软信息的数目，比如当每个软信息是8比特数据时，软缓存的大小就是指能够存储多少个8比特数据，而接收端的一个8比特的软信息对应发端的一个比特，所以在发送端只是用到软缓存的大小，实际存储的是比特级的数据。
本申请提供了一种通信方法，可以适用于基于码块组传输的通信系统，例如采用LDPC编码的通信系统，上述传输可以包括初传和/或重传。该通信方法由通信装置实现，可以理解的是，该通信装置在本申请实施例中实现的是位于发送端的方法。本申请中，可以将位于发送端的设备也可以称为第一设备。如图5所示，该方法可以包括：
S501，获取输入序列，其中所述输入序列包括M个码块组，M的值小于或者 等于传输块在分割后得到的码块组数量。
输入序列是与传输块对应的初始传输序列或者重传序列。所述输入序列是速率匹配的输入序列，可以将编码器的输出看作是速率匹配模块的输入序列。
此处，输入序列，可是重传数据，也可以是初传数据。如图4所示，传输块或者经过处理后的传输块输入进行码块分割操作，此处的码块分割操作可以包括将传输块或者处理后的传输块分割为至少一个码块，而该至少一个码块可以分为至少一个码块组。码块组的数目可以在码块分割之前确定，也可以在码块分割之后确定。可选的，对每一个码块组可以根据系统设计需求添加码块组校验比特，本申请实施例对此不做限定。为描述方便，本申请实施例后续将传输块或者处理后的传输块在码块分割后得到的至少一个码块所包括的码块组简称为传输块包括的码块组。
本实施例中，输入序列包括M个码块组，对于输入序列是初传数据的场景，该M个码块组即为传输块包括的。例如，假设传输块包括的码块组数量为4，根据接收端反馈的ACK，得知第1个码块组被正确接收，那么重传时可以是传输后面3个码块组，也就是说重传的码块组数量少于初传的码块组的数量。在确定重传的码块组后，可以对重传的码块组进行重新编码后进行速率匹配，也可以不重新编码，本申请实施例对此不做限定。
S502，获取与M个码块组中的第j个码块对应的软缓存大小B j。
B j的值可以是基于以下至少一个参数确定的：第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、所述传输块的软缓存大小N IR以及可用的最大编码后码块长度N max确定的。
例如，在某些实现方式中，B j＝K w。又例如，在某些实现方式中，
Figure PCTCN2018081506-appb-000008
再例如，在某些实现方式中，
Figure PCTCN2018081506-appb-000010
其中
Figure PCTCN2018081506-appb-000011
表示向下取整，K w表示该第j个码块的编码后长度K w、C t表示M个码块组包括的码块的数目、N IR表示传输块的软缓存大小、N max表示可用的最大编码后码块长度。
可以理解的是，上述B j满足的公式形式仅为举例说明，还可以基于上述任意一种公式进行变型，例如向下取整改成向上取整，或者对其中的
Figure PCTCN2018081506-appb-000012
或者N max可以进行加权等等，本申请实施例对此不做限定。
获知了所述输入序列中包括的码块组，可以针对该M个码块组中的各个码块 确定对应的软缓存大小，可选的，每个码块可以采用相同的方法确定其对应的软缓存大小。
其中，在一种实现方式中，K w可以是编码器在编码后通知给速率匹配模块，
也可以是速率匹配模块通过其他方式获知K w，本申请实施例对此不做限定。
传输块的软缓存大小N IR的值与接收端设备(也可以称为第二设备)的等级相关，例如可以通过如下公式(1)获知N IR：
Figure PCTCN2018081506-appb-000013
其中，N soft表示与接收设备的能力等级对应的软信息比特的数目(soft channel bits)，K C的取值由N soft确定，M DL_HARQ表示下行HARQ进程的最大数目，M limit为一个预定义的常数，例如可以为8，K MIMO是与传输模式对应的参数，例如在某些传输模式下K MIMO可以为2，在某些传输模式下K MIMO可以为1，本申请实施例对此不做限定。上述公式(1)可以理解为将软缓存按照进程数划分，为每个进程预留资源。
一种可能的实现方式中，可以根据接收设备的能力等级，通过查表便可得到N IR的大小，例如可以通过查表的方式获知N soft，根据N soft的取值决定K C，再根据公式(1)最终得到N IR。
Figure PCTCN2018081506-appb-000014
其中，
Figure PCTCN2018081506-appb-000015
是指在编码器中可用的最大编码块长度K max对应的最小码率，其中，
Figure PCTCN2018081506-appb-000016
的具体取值可以是协议预先规定好的,参数P可以为0，也可以是打孔信息比特的数目，本申请实施例对此不做限定。
S503，根据B j确定用于传输的比特集合。
S502中确定的B j限制了可以传输的比特集合，如图6所示，图6中白色区域(无斜线部分)表示循环缓存中因为软缓存大小限制而不能被传输的比特集合，而有斜线格子部分表示可以传输的比特的集合，该可以传输的比特集合中包括的比特数目是根据软缓存大小确定的。上述可以传输的比特集合也就是在循环缓存中可以读取的数据。例如S502中确定的软缓存大小为300，K w为400，那么循环缓存大小为400，那么将编码后的比特序列中的前300个比特作为用于传输的比特集合。可选的，在传输的比特集合中也有可能包括填充比特。
S504，根据上述比特集合获取速率匹配的输出序列。
速率匹配的输出序列是在上述比特集合的基础上结合RV取值进行读取后得 到的比特序列。例如，从RV0对应起始位置开始读取，读取的长度根据用于每个码块传输的比特长度确定。所读取的长度也就是速率匹配的输出序列的长度。
可选的，如果上述比特集合中包括填充比特时，在读取时可以跳过。
本申请实施例中，根据实际发送的码块组因素确定每个码块速率匹配时的软缓存大小，可以尽量充分利用软缓存资源，提升性能。
进一步的，特别是在缓存受限场景下,初传时每个码块的缓存均受限,此时每个码块的编码码率(不包含重复部分)较高，编码增益相对受限。例如，一个码块编码前信息比特长度K＝6000，按1/3码率编码可以得到编码后长度18000，若此时码块的软缓存受限，大小仅为12000，那么他只能按照1/2码率编码至12000，然后重复6000比特，这样便会损失一部分编码增益，而采用本申请实施例的方法，仅部分码块组进行重传,那么重传时对软缓存进行重新分配,每个码块便可分配到更大的软缓存,从而获取更大的编码增益。例如上述例子中，假设每个码块组仅包含一个码块，若初传包含两个码块组，仅有一个码块组需要重传，那么重传的码块组可用的缓存大小可以增加到24000，这样便可以按照1/3码率进行编码了。
下面具体举例说明几种可能的确定与第j个码块对应的软缓存大小的方式。
一种可能的实现方式中，当K w的值是受到N max和传输块的软缓存大小N IR的限制时，那么第j个码块对应的软缓存大小B j与K w相等，即，B j的值满足公式：B j＝K w。
也就是说当编码器的输出考虑了N max和N IR，使得编码后的码块长度不超过N max以及
Figure PCTCN2018081506-appb-000017
时，此时可以将B j确定为K w，其中
Figure PCTCN2018081506-appb-000018
可以理解为N IR分配到每个码块的大小。
该种实现方式中，将N max和传输块的软缓存大小对编码后码块长度的限制统一在编码阶段完成，减少了速率匹配时的多余比特，复杂度较低。
可以理解的是，上述确定B j的方式也可以适用于其他场景，例如不考虑编码器的实现，直接将B j确定为K w，本申请对此不做限定。
另一种可能的实现方式中，当K w是受到N max限制时，那么确定第j个码块对应的软缓存大小B j的值满足公式：
Figure PCTCN2018081506-appb-000019
其中
Figure PCTCN2018081506-appb-000020
为向下取整。
也就是说，如果编码器的输出考虑了N max，没有考虑其他因素，那么在确定码块对应的软缓存大小时，可以将其他因素，例如，N IR考虑进去，具体可以是：
Figure PCTCN2018081506-appb-000021
Figure PCTCN2018081506-appb-000022
该种实现方式中，在编码阶段的算法相对简单，比较容易实现。
可以理解的是，该种方式也可以适用于编码阶段考虑了N max和N IR的场景，也可以适用于其他场景，例如不考虑编码器的实现，直接将B j确定为
Figure PCTCN2018081506-appb-000023
本申请对此不做限定。
又一种可能的实现方式中，可以将第j个码块对应的软缓存大小B j确定为
Figure PCTCN2018081506-appb-000024
即B j的取值满足公式：
Figure PCTCN2018081506-appb-000025
其中，
Figure PCTCN2018081506-appb-000026
为向下取整。
该种实现方式，可以适用于编码器的输出不受任何因素限制，例如编码器直接采用最低码率进行编码的场景，也可以适用于编码器的输出受到例如N max和N IR中的一个或者多个因素限制的场景，本申请实施例对此不做限定。该种方式中，编码器只需完成相对简单的编码操作，其余的限制都在速率匹配时完成，各个阶段的功能实现划分更明确。
可选的，上述各种确定B j的方式，可以理解为B j的值与该第j个码块的编码后长度K w、M个码块组包括的码块的数目C t、传输块的软缓存大小N IR、可用的最大编码后码块长度N max相关。
可选的，上述实施例中，速率匹配的输出序列的长度可以满足以下条件：
当j≤C t-γ-1时，
Figure PCTCN2018081506-appb-000027
当j＞C t-γ-1时，
Figure PCTCN2018081506-appb-000028
其中，G′＝G/(N L·Q m)，γ＝G′mod C t，Q m为调制阶数，N L为数据流的数目，G为用于所述传输块传输的可用比特数目。
可以理解的是，N L主要出现于多天线场景中，例如发送分集模式下，每个调制符号会通过一系列运算生成两路正交信号，在两根天线同时发送，那么此时N L＝2；而在复用模式下，N L等于实际发送的数据流的数目。
速率匹配的输出序列的长度可以由用于每个码块传输的比特数目决定，这个长度由整个传输块的空口资源(即RB数)和码块数目决定，例如，整个空口资源可以均匀分配到各个码块。需要说明的是，上述确定速率匹配的输出序列的长度的方法，可以应用于S504；也可以独立于图5所示的实施例，即对于任何基于码块组重传的场景都可以使用，不限于以采用图5实施例中确定第j个码块对应的软缓存大小的方式 为基础。
例如，本申请实施例还提供了一种通信方法，该方法可以适用于重传的场景中，包括但不限于以下步骤：
获取速率匹配的输入序列，所述输入序列是与传输块对应的重传序列，所述输入序列包括M个码块组，M的值小于传输块在分割后得到的码块组数量，所述M个码块组包括C t个码块；对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
Figure PCTCN2018081506-appb-000029
当j＞C t-γ-1时，
Figure PCTCN2018081506-appb-000030
该方法中，速率匹配的输出以重传的码块组为基础，可以更加充分的利用空口资源。
可以理解的是，在接收端，可以采用对应的方式进行解速率匹配以及译码，例如，每个码块按照与发送端相同的方法计算出软缓存的大小，根据软缓存的大小对接收到的软信息进行解速率匹配操作，解速率匹配模块输出长度小于等于软缓存大小的软信息序列给译码器进行译码即可。该接收端的装置可以位于第二设备中，可以包括相应的功能单元实现上述功能。例如，该接收端的装置可以包括：用于存储指令的存储器,以及用于执行该指令的处理器,用于实现上述在接收端完成的进行解速率匹配以及译码的过程。
本申请实施例还提供了一种通信装置700，该通信装置用于实现上述实施例在发送端，例如第一设备中，所执行的方法，该通信装置可以是终端，基站、基带芯片、或者数据信号处理芯片，通用芯片，或者通用芯片等。如图7所示，该装置可以包括：
输入单元701，用于获取输入序列，其中该输入序列包括M个码块组，M的值小于或者等于传输块在分割后得到的码块组数量。
获取单元702，用于获取与M个码块组中的第j个码块对应的软缓存大小，其中与第j个码块对应的软缓存大小是基于所述第j个码块的编码后长度K w、M个码块组包括的码块的数目C t、传输块的软缓存大小N IR、可用的最大编码后码块长度N max中的至少一个确定的。
确定单元703，用于根据第j个码块对应的软缓存大小确定传输的比特集合。
输出单元704，用于根据确定单元703确定的比特集合获取速率匹配的输出序列。
可以理解的是，上述各个单元可以是独立的逻辑功能模块，也可以通过集成的 功能单元实现，本申请实施例对此不做限定。进一步的，上述各个单元的具体功能和实现方式可以参考方法实施例以及附图1至6的相关描述。
本申请实施例还提供了一种通信装置，该通信装置可以是终端，基站、基带芯片、或者数据信号处理芯片，通用芯片，或者通用芯片等。
所述通信装置包括：输入单元，用于获取输入序列，该输入序列是与传输块对应的重传序列，该输入序列包括M个码块组，M的值小于传输块在分割后得到的码块组数量，所述M个码块组包括C t个码块；
速率匹配单元，用于对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
Figure PCTCN2018081506-appb-000031
当j＞C t-γ-1时，
Figure PCTCN2018081506-appb-000032
其中，G′＝G/(N L·Q m)，γ＝G′mod C t，Q m为调制阶数，N L为数据流的数目，G为用于所述传输块传输的可用比特数目。该实施例中的输入单元、速率匹配单元可以通过图2、图3所示的处理器、或者图4所示的速率匹配模块来实现。一些相关的描述可以参照上述实施例中的描述，在此不再赘述。
可选的，本申请实施例中还提供了一种通信装置800，如图8所示，该装置可以包括：存储器801和处理器802。在不同的应用中，存储器801和处理器802可能有不同的功能。
在一种可能的实现方式中：
存储器801与处理器802耦合，处理器802用于：获取速率匹配的输入序列，其中所述输入序列是与传输块对应的初始传输序列或者重传序列，所述输入序列包括M个码块组，M的值小于或者等于传输块在分割后得到的码块组数量；获取与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的；根据所述B j确定用于传输的比特集合；以及根据所述比特集合获取速率匹配的输出序列。或者，处理器802用于，获取速率匹配的输入序列，其中所述输入序列是与传输块对应的重传序列，所述输入序列包括M个码块组，M的值小于所述传输块在分割后得到的码块组数量，所述M个码块组包括C t个码块；
对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
Figure PCTCN2018081506-appb-000033
当j＞C t-γ-1时，
Figure PCTCN2018081506-appb-000034
在另一种可能的实现方式中：
存储器801，编码器的输出序列的全部或者部分可以存储在该存储器801中。
此处，存储器中存储的输出序列可以是上述实施例中所描述的输入序列，其中，所述输入序列所包括的C t个码块可以分别对应一个虚拟缓存。该虚拟缓存(也可以称为循环缓存)的大小可以与K w相等。
可以理解的是，该存储器801可以是寄存器、随机读写存储器(RAM)、高速缓冲寄存器(Cache)、闪存、ROM存储器、EPROM存储器、EEPROM存储器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质，本申请实施例对此不做限定。
处理器802，可以用于实现上述图7所示实施例中获取单元702，确定单元703和输出单元704的功能，具体不再赘述。或者，该处理器802也可以用于对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
Figure PCTCN2018081506-appb-000035
当j＞C t-γ-1时，
Figure PCTCN2018081506-appb-000036
或者，在又一种可能的实现方式中，
存储器801可以用于存储实现前述各个实施例中所描述的通信方法的指令；处理器802可以用于运行上述指令以实现前述各个实施例中所描述的通信方法。可以理解的是，上述各种情况下，存储器801和处理器802可以独立存在，也可以集成在一个芯片上实现，本申请实施例对存储器801和处理器802的存在形式不做限定。
本申请实施例中的通信装置，根据实际发送的码块组等因素确定每个码块速率匹配时的软缓存大小，从而可以满足小块长可以支持比大块长更低的码率，而不会增加软缓存的大小，可以改善速率匹配性能。
需要说明的是，上述图7和8实施例所提供的通信装置，除了附图所示的功能单元，还可能包括其他单元，本申请实施例对此不做限定，例如还可以包括实现收发功能的单元。
需要说明的是，本申请中提到的的处理器可以是中央处理器(CPU)，通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)，现场可编程门阵列(FPGA)或者其他可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多于一个微处理器组合，DSP和微处理器的组合等等。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个单元中，也可以是各个单元单独存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述软件功能部分可以存储在存储单元中。所述存储单元包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施例所述方法的部分步骤。所述存储单元包括：一个或多个存储器，如只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)，电可擦写可编程只读存储器(EEPROM)，等等。所述存储单元可以独立存在，也可以和处理器集成在一起。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本领域普通技术人员可以理解：本文中涉及的第一、第二等各种数字编号仅为描述方便进行的区分，并不用来限制本申请实施例的范围。
本领域普通技术人员可以理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来 实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State DisB(SSD))等。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种通信方法，其特征在于，包括：
    获取速率匹配的输入序列，其中所述输入序列是与传输块对应的重传序列，所述输入序列包括M个码块组，M的值小于所述传输块在分割后得到的码块组数量，所述M个码块组包括C t个码块；
    对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
    Figure PCTCN2018081506-appb-100001
    当j＞C t-γ-1时，
    Figure PCTCN2018081506-appb-100002
    其中，G′＝G/(N L·Q m)，γ＝G′mod C t，Q m为调制阶数，N L为数据流的数目，G为用于所述传输块传输的可用比特数目,j表示M个码块组中的第j个码块。
  2. 根据权利要求1所述的方法，其特征在于，所述对C t个码块进行速率匹配之前还包括：
    获取与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的；
    根据所述B j确定用于传输的比特集合；
    所述对C t个码块进行速率匹配包括：
    根据所述比特集合获取速率匹配的输出序列。
  3. 根据权利要求2所述的方法，其特征在于，所述B j的值是根据所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的，包括：
    B j的值满足
    Figure PCTCN2018081506-appb-100003
  4. 根据权利要求2所述的方法，其特征在于，所述B j的值是根据所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的，包括：
    B j的值满足
    Figure PCTCN2018081506-appb-100004
    N max表示可用的最大编码后码块长度。
  5. 一种通信装置，其特征在于，包括：
    输入单元，用于获取输入序列，该输入序列是与传输块对应的重传序列，该输入序列包括M个码块组，M的值小于传输块在分割后得到的码块组数量，所述M个码块组 包括C t个码块；
    速率匹配单元，用于对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
    Figure PCTCN2018081506-appb-100005
    当j＞C t-γ-1时，
    Figure PCTCN2018081506-appb-100006
    其中，G′＝G/(N L·Q m)，γ＝G′mod C t，Q m为调制阶数，N L为数据流的数目，G为用于所述传输块传输的可用比特数目，j表示M个码块组中的第j个码块。
  6. 根据权利要求5所述的装置，其特征在于，还包括：
    获取单元，用于获取与所述与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的；
    确定单元，用于根据所述B j确定用于传输的比特集合；以及
    输出单元，用于根据所述比特集合获取速率匹配的输出序列。
  7. 根据权利要求6所述的装置，其特征在于，
    B j的值满足
    Figure PCTCN2018081506-appb-100007
  8. 根据权利要求6所述的装置，其特征在于，
    B j的值满足
    Figure PCTCN2018081506-appb-100008
    N max表示可用的最大编码后码块长度。
  9. 一种通信装置，其特征在于，所述装置包括：
    存储器、处理器以及存储在存储器上并可在处理器上运行的指令，当所述处理器运行所述指令时，使得所述通信装置实现如权利要求1-4任一项所述的方法。
  10. 一种通信装置，其特征在于，包括：
    存储器，用于存储速率匹配的输入序列，其中所述输入序列是与传输块对应的初始传输序列或者重传序列，所述输入序列包括M个码块组，M的值小于或者等于所述传输块在分割后得到的码块组的数量；
    以及，
    处理器，用于对C t个码块进行速率匹配，其中C t个码块中每个码块的速率匹配的输出序列的长度满足以下条件：当j≤C t-γ-1时，
    Figure PCTCN2018081506-appb-100009
    当j＞C t-γ-1时，
    Figure PCTCN2018081506-appb-100010
    其中，G′＝G/(N L·Q m)，γ＝G′mod C t，Q m为调制阶数，N L为数据流的数目，G为 用于所述传输块传输的可用比特数目,j表示M个码块组中的第j个码块。
  11. 根据权利要求10所述的装置，其特征在于，所述处理器还用于：
    获取与所述与M个码块组中的第j个码块对应的软缓存大小B j，其中，B j的值是基于所述第j个码块编码后的长度K w、M个码块组包括的码块的数目C t、以及所述传输块的软缓存大小N IR确定的；
    根据所述B j确定用于传输的比特集合；
    根据所述比特集合获取速率匹配的输出序列。
  12. 根据权利要求11所述的装置，其特征在于，B j的值满足
    Figure PCTCN2018081506-appb-100011
  13. 根据权利要求12所述的装置，其特征在于，
    B j的值满足
    Figure PCTCN2018081506-appb-100012
    N max表示可用的最大编码后码块长度。
  14. 一种计算机可读存储介质，其特征在于，所述介质上存储有指令，当其在计算机上运行时，使得通信装置实现如权利要求1-4任一项所述的通信方法。
  15. 一种计算机程序，其特征在于，其特征在于，当所述程序被执行时，使得通信装置实现如权利要求1至4任一项所述的方法。
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