WO2018171778A1 - 通信方法和装置 - Google Patents

通信方法和装置 Download PDF

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Publication number
WO2018171778A1
WO2018171778A1 PCT/CN2018/080380 CN2018080380W WO2018171778A1 WO 2018171778 A1 WO2018171778 A1 WO 2018171778A1 CN 2018080380 W CN2018080380 W CN 2018080380W WO 2018171778 A1 WO2018171778 A1 WO 2018171778A1
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WIPO (PCT)
Prior art keywords
bit sequence
value
equal
bits
bit
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PCT/CN2018/080380
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English (en)
French (fr)
Inventor
马亮
曾歆
卡佐卡梅拉
魏岳军
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from CN201710305802.7A external-priority patent/CN108631941B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18770422.6A priority Critical patent/EP3591865B1/en
Publication of WO2018171778A1 publication Critical patent/WO2018171778A1/zh
Priority to US16/580,961 priority patent/US11139917B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to communication technologies, and more particularly to a communication method and apparatus.
  • the maximum block length supported by the Turbo code encoder is 6144 bits.
  • a code block segmentation operation is performed before encoding, that is, dividing more than 6144 bit sequences into multiple Each code block is encoded separately.
  • LDPC low density parity check bits
  • the decoding error block rate decreases faster as the number of bits after encoding increases.
  • the decoding error block rate decreases.
  • the complexity of the LDPC decoder is positively correlated with the number of bits after encoding. From the perspective of the compromised block error rate and the complexity of the decoder, the number of bits of the encoded bit sequence can be limited, so that While ensuring a certain decoding error block rate, it has reasonable decoding complexity. That is, in a communication system employing LDPC encoding, the number of bits of the encoded bit sequence is limited.
  • the communication method and apparatus provided by the embodiments of the present application are for providing a communication method for a communication system with a limited number of bits of a coded bit sequence, and performing segmentation of a bit sequence reasonably.
  • the embodiment of the present application provides a communication method, where the method includes: acquiring a first bit sequence to be divided, where the number of bits of the first bit sequence is B, and the physical resource corresponding to the first bit sequence can be carried.
  • the number of bits is N 1 ; then, the number C of the bit sequence after the first bit sequence is divided according to N 1 and the parameter L, where the value of L is equal,
  • B 1 is an integer greater than or equal to 0; the first bit sequence is divided into C divided bit sequences.
  • the embodiment of the present application further provides a communication device.
  • the communication device can be used to implement the communication method described above.
  • the communication device can be a terminal, a base station, or a baseband chip, or a data signal processing chip, or a general purpose chip.
  • the communication device includes a memory and a processor, wherein the memory is configured to store a first bit sequence to be divided; the processor is configured to: determine, after determining the first bit sequence, according to N 1 and parameter L The number of bit sequences C, where the value of L and equal, A minimum code rate corresponding to the available maximum coding block length K max , B 1 is an integer greater than or equal to 0; and, the first bit sequence is divided into C divided bit sequences.
  • the above determines the number of divided coding blocks according to N 1 and L, and may determine C by comparing N 1 and L (or comparing L and N 1 ), or by comparing N 1 with (or compare (B+B 1 ) Determine the C with N 1 ).
  • B 1 is an adjustment value (or correction value). It can be understood that when the above determination C is made, the adjustment value B 1 may not be required, that is, B 1 is 0. When B 1 is 0, the value of L and Equally, the number of coded blocks that are divided by N 1 and L may be determined by comparing N 1 and L (or comparing L and N 1 ) to determine C, or by comparing N 1 with (or compare Determine the C with N 1 ).
  • a possible way to determine C can be: when L ⁇ N 1 , among them, Indicates rounding up, the value of N max and The values are equal.
  • the C determined by the method makes the code block length of the coded block after encoding and rate matching as close as possible to N max , and can obtain the code length as much as possible without losing the code rate gain. Gain, which improves decoding performance.
  • N threshold is a preset threshold
  • ⁇ is an offset value
  • ⁇ is a positive integer
  • ⁇ is such that
  • the coded block length of the bit sequence after the division is smaller than the N threshold , it indicates that the coded block length gain loss due to the code block division operation is large at this time, and the C tmp is corrected by the offset value ⁇ .
  • the block length gain loss after encoding is reduced, and the decoding performance of the transport block is improved.
  • N 1 is the lowest code rate supported by the encoding, so that the decoding performance can be improved.
  • C C tmp ⁇
  • N threshold is a preset threshold
  • ⁇ is an offset value
  • ⁇ is a positive integer
  • ⁇ is such that Thereby, the decoding performance can be improved.
  • Another possible way to determine C can be: when L ⁇ N 1 , among them, Indicates rounding up, and L CB is the number of bits of the check bits of the divided bit sequence.
  • L ⁇ N 1 among them, Indicates rounding up
  • L CB is the number of bits of the check bits of the divided bit sequence.
  • the above B can be determined in the following manner.
  • K TB is the transport block length
  • L TB is the integer number
  • the above B1 is an adjustment value (or a correction value), and its value can be defined according to the system design. For example, when B1 is greater than 0, the value of B 1 is equal to the sum of the number of code block group check bits of the A code block groups, the code block group is a group of C divided bit sequences, and A is a code block group. Number of. In this design, since the number of code block group check bits is considered in advance when determining the number C of the divided bit sequences, the difference in the length of the bit sequence after the division can be avoided, and the code rate after encoding of different code blocks is not Uniform problems improve decoding performance.
  • the code block group check bit may also be added after the last code block in each of the A code block groups.
  • the value of B 1 above may also be designed to be related to one or more other system parameters, which is not limited thereto.
  • the solution provided by the present application may also not need to adjust the value B 1 , that is, B 1 is 0.
  • the method and apparatus provided by the present application can be used in a communication system employing LDPC.
  • the above communication device includes a processor and a memory.
  • the memory is for storing instructions to implement the communication method described above; the processor is operative to execute the above instructions to implement the aforementioned communication method.
  • the foregoing communication device may further include a transceiver.
  • the embodiment of the present application also provides a computer program product, the program product comprising instructions for implementing the foregoing method.
  • the embodiment of the present application further provides a computer readable storage medium storing instructions for implementing the foregoing communication method.
  • FIG. 1 is a simplified schematic diagram of a wireless communication system
  • FIG. 2 is a schematic diagram showing a simplified structure of a terminal
  • FIG. 3 is a simplified schematic diagram of a structure of a base station
  • FIG. 4 is a schematic flowchart of a communication method according to an embodiment of the present application.
  • FIG. 5 is an example of a bit sequence processing procedure
  • FIG. 6 is a schematic flowchart of a communication method according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a communication apparatus according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a communication apparatus according to still another embodiment of the present application.
  • a bit sequence is a sequence consisting of bits "0" and/or "1".
  • the length of the bit sequence refers to the number of bits included in the bit sequence.
  • the bit sequence 00 includes 2 bits and has a length of 2;
  • the bit sequence 111 includes 3 bits and has a length of 3;
  • the bit sequence "0100" includes 4 bits and has a length of 4.
  • a transport block (transport blocB, TB) and a code block (code blocB, CB) can all be regarded as a bit sequence.
  • the code block is obtained by dividing the transport block or the processed transport block, and is an encoded object. Therefore, in the present application, the length of the code block refers to the number of bits included in the bit sequence corresponding to the code block, and the length of the transport block refers to the number of bits included in the bit sequence corresponding to the transport block, and the transport block The length can also be referred to as the size of the transport block. It will be appreciated that as technology advances, transport blocks or code blocks may have different terminology names.
  • the natural number mentioned in the embodiment of the present application includes 0.
  • the communication device is a device having a communication function.
  • the communication device may be a base station, or a terminal, or a chip or the like, and the chip may be, for example, a baseband chip or a communication chip.
  • the wireless communication system includes at least one base station B200 and a terminal T100 (only one shown in the figure).
  • the base station B200 can communicate with the terminal T100 using different communication resources.
  • the base station B200 can communicate with the terminal T100 using a wide beam and/or a narrow beam.
  • the wireless communication system may be a 4G communication system, such as an LTE (long term evolution) system, a 5G communication system, such as an NR (new radio) system, and a communication system in which various communication technologies are integrated (for example, LTE technology). Communication system integrated with NR technology).
  • Both the base station B200 and the terminal T100 can function as a transmitting device or a receiving device.
  • the terminal acts as a transmitting device
  • the base station acts as a receiving device
  • the base station acts as a transmitting device
  • the terminal acts as a receiving device.
  • the wireless communication system may include a radio access network and a core network, where the radio access network includes a base station B200, and may also include other access devices, such as a relay station, or other devices.
  • the core network may include a core network device, such as a mobility management entity, or other control or storage device.
  • the terminal T100 is a device having a wireless communication function, and may be a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
  • Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
  • FIG. 1 and FIG. 2 shows a schematic structural diagram of the terminal T100. As shown in FIG.
  • the terminal T100 includes a processor, a memory, a radio frequency circuit, an antenna, and an input and output device.
  • the processor is mainly used for processing communication protocols and communication data, and controlling terminals, executing software programs, processing data of software programs, and the like.
  • Memory is primarily used to store software programs and data.
  • the RF circuit is mainly used for the conversion of the baseband signal and the RF signal and the processing of the RF signal.
  • the antenna is mainly used to transmit and receive RF signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, keyboards, etc., are primarily used to receive user input data and output data to the user. It should be noted that some types of terminals may not have input and output devices.
  • the processor When the data needs to be sent, the processor performs baseband processing on the data to be sent, and outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit performs radio frequency processing on the baseband signal, and then sends the radio frequency signal to the outside through the antenna in the form of electromagnetic waves.
  • the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor, which converts the baseband signal into data and processes the data.
  • Figure 2 shows only one memory and processor.
  • the memory may also be referred to as a storage medium or a storage device or the like.
  • the memory may be independent of the processor, or may be integrated with the processor, which is not limited in this embodiment of the present application.
  • the processor may include a baseband processor and/or a central processing unit.
  • the baseband processor is mainly used to process a communication protocol and communication data
  • the central processing unit is mainly used to control the entire terminal. Execute a software program that processes the data of the software program.
  • the processor in FIG. 2 integrates the functions of the baseband processor and the central processing unit.
  • the baseband processor and the central processing unit may also be separate processors.
  • the terminal may include multiple baseband processors to adapt to different network standards.
  • the terminal may include multiple central processors to enhance its processing capabilities.
  • the functions of the baseband processor and the central processing unit can be integrated on one processor.
  • the various components of the terminal can be connected via various buses.
  • the baseband processor can also be expressed as a baseband processing circuit or a baseband processing chip.
  • the central processing unit can also be expressed as a central processing circuit or a central processing chip.
  • the function of processing the communication protocol and the communication data may be built in the processor, or may be stored in the storage unit in the form of a software program, and the processor executes the software program to implement the baseband processing function.
  • the antenna and the radio frequency circuit having the transceiving function can be regarded as the transceiving unit of the terminal, and the processor having the processing function can be regarded as the processing unit of the terminal.
  • the terminal T100 includes a transceiver unit 101 and a processing unit 102.
  • the transceiver unit can also be referred to as a transceiver, a transceiver, a transceiver, and the like.
  • the processing unit may also be referred to as a processor, a processing board, a processing module, a processing device, and the like.
  • the device for implementing the receiving function in the transceiver unit 101 can be regarded as a receiving unit, and the device for implementing the sending function in the transceiver unit 101 is regarded as a sending unit, that is, the transceiver unit 101 includes a receiving unit and a sending unit.
  • the transceiver unit may also be referred to as a transceiver, a transceiver, or a transceiver circuit.
  • the receiving unit may also be referred to as a receiver, a receiver, or a receiving circuit or the like.
  • the transmitting unit may also be referred to as a transmitter, a transmitter, or a transmitting circuit, and the like.
  • the base station B200 which may also be referred to as a base station device, is a device deployed in a wireless access network to provide wireless communication functions.
  • a base station in an LTE network is called an evolved Node B (eNB or eNodeB)
  • a base station in an NR network is called a TRP (transmission reception point) or a gNB (generation node B, next generation Node B).
  • the structure of the base station B200 can be as shown in FIG.
  • the base station B200 shown in FIG. 3 may be a split base station.
  • FIG. 3 shows, on the left, a distributed base station including antennas, a remote radio unit (RRU), and a baseband unit (BBU).
  • RRU remote radio unit
  • BBU baseband unit
  • a base station includes a portion 201 and a portion 202.
  • Part 201 is mainly used for the transmission and reception of radio frequency signals and the conversion of radio frequency signals and baseband signals; the 202 part is mainly used for baseband processing and base station control.
  • Section 201 can be generally referred to as a transceiver unit, a transceiver, a transceiver circuit, a transceiver, and the like.
  • Section 202 can generally be referred to as a processing unit.
  • part 202 is the control center of the base station.
  • part 201 is a transceiver unit, which may also be called a transceiver, a transceiver, etc., and includes an antenna and a radio frequency unit, wherein the radio frequency unit is mainly used for radio frequency processing.
  • the device for implementing the receiving function in part 201 may be regarded as a receiving unit, and the device for implementing the transmitting function may be regarded as a transmitting unit, that is, the part 201 includes a receiving unit and a transmitting unit.
  • the receiving unit may also be referred to as a receiver, a receiver, a receiving circuit, etc.
  • the transmitting unit may be referred to as a transmitter, a transmitter, or a transmitting circuit or the like.
  • the 202 part may include one or more boards, each of the boards may include a processor and a memory, and the processor is configured to read and execute a program in the memory to implement a baseband processing function and a base station. control. If multiple boards exist, the boards can be interconnected to increase processing power.
  • An embodiment of the present application provides a communication method, which is implemented by a communication device, which may be a base station, or a terminal, or a chip, etc., which is not limited in this embodiment of the present application. As shown in FIG. 4, it may include:
  • the first bit sequence to be divided is obtained, where the number of bits of the first bit sequence is B, and the number of bits carried by the physical resource corresponding to the first bit sequence is N 1 .
  • the first bit sequence that is, the bit sequence to be divided, is an input of a code block division operation, that is, the object of the code block division is a first bit sequence.
  • the first bit sequence can be, for example, a sequence to be transmitted, or a processed bit sequence to be transmitted.
  • the processing of the sequence of transmitted bits may include, but is not limited to, adding check bits, such as adding cyclic redundancy check (CRC) bits.
  • CRC cyclic redundancy check
  • the check bit is exemplified by the CRC bit. With the development of the technology, the above CRC bits may be replaced by other check bits.
  • the foregoing to-be-sent sequence may also be referred to as a transport block (TB).
  • TB transport block
  • the sequence to be transmitted may be transferred from a higher layer to a physical layer.
  • the upper layer here may be, for example, a medium access control (MAC) layer.
  • MAC medium access control
  • the input of the read block splitting operation when performing code block partitioning can be understood as acquiring the first bit sequence.
  • the number of bits of the first bit sequence can be known.
  • the number of bits of the first bit sequence is represented by B.
  • the channel state information, the user priority, the service priority, or the amount of data in the cache may be determined according to information about the radio link between the base station and the terminal, and The terminal allocates physical resources for data transmission. While determining the physical resources used for data transmission, the modulation coding scheme MCS and the transport block size (TBS) of the data transmission are determined.
  • the size of the transport block is associated with the number of bits B of the first bit sequence.
  • the physical resource can be regarded as a physical resource corresponding to the transport block, and the number of bits that can be carried on the physical resource is N 1 . It can be understood that the transport block is associated with the first bit sequence in the embodiment of the present application.
  • the first bit sequence described above may be the transport block itself, or may refer to the processed transport block.
  • the physical resource corresponding to the transport block can also be understood as a physical resource corresponding to the first bit sequence.
  • the foregoing is an example manner for understanding the physical resources corresponding to the first bit sequence, and there may be other ways of understanding, which is not limited by the embodiment of the present application.
  • resource allocation described above includes uplink scheduling or downlink scheduling.
  • L is determined first bit sequence to be divided into a number of bit sequences, i.e., determines the number of bits of the C sequence into a first bit sequence in accordance with the number of bits of the first bit sequence corresponding to the physical resource carrying the parameter N 1 - , where the value of L and equal, The minimum code rate corresponding to the maximum allowed coding block length K max .
  • the above B 1 can be understood as an adjustment amount to B, which may have different values according to different scenarios.
  • the first bit sequence is divided into C divided bit sequences.
  • the first bit sequence is divided to obtain C bit sequences.
  • the method for dividing the first bit sequence may be multiple.
  • the first bit sequence may be divided into approximately uniform C bit sequences.
  • the manner of the segmentation is not limited in this embodiment of the present application.
  • the partitioning may be performed in a manner similar to that described in section 5.1.2 of 3GPP TS 36.212 V13.4.0, or may be as described in section 5.1.2 of 3GPP TS 36.212 V13.4.0.
  • the splitting operation may further include operations such as padding and/or adding check bits.
  • the total length of the divided C bit sequences is greater than the length of the first bit sequence.
  • the term length of a bit sequence refers to the number of bits included in the bit sequence.
  • the number of bits allocated by the physical resource to the single divided bit sequence may be greater than the maximum block length N max after the encoding.
  • N max the maximum block length after the encoding.
  • the sending device before sending the first bit sequence to the receiving device, performs processing such as segmentation, encoding, rate matching, interleaving, resource mapping, and the like on the first bit sequence, for example, as shown in FIG. 5 .
  • processing such as segmentation, encoding, rate matching, interleaving, resource mapping, and the like on the first bit sequence, for example, as shown in FIG. 5 .
  • FIG. 5 exemplifies a possible processing procedure for the first bit sequence, which is not limited in this embodiment of the present application.
  • the first bit sequence is processed and mapped onto a resource element (RE).
  • resource allocation may be performed in units of resource blocks (RBs) or in units of REs.
  • RB resource blocks
  • One RB may include one or more REs.
  • one or more REs in the RB may be used to carry the pilot symbols.
  • the REs for carrying the pilot symbols may be removed from the corresponding RBs. That is to say, those REs after removing the REs for carrying pilot symbols in the RB are used to carry information bits corresponding to the first bit sequence.
  • the processing of the first bit sequence before mapping to the physical resource may have many different situations, the above is only an example.
  • it may also include processing such as cascading, punching, and the like.
  • the process and sequence of processing can also be adapted to the requirements of the system.
  • the RB is an example of a physical resource, and the physical resource may have other different forms.
  • the RB corresponding to the first bit sequence may be one or more.
  • the physical resource corresponding to the transport block has been determined, and then the physical resource corresponding to the first bit sequence is also determined.
  • the number of bits that can be carried on the physical resource can be known.
  • the number of bits that can be carried on the physical resource may be the modulation order, the number of RBs, and one
  • the number of REs included in the RB is related. For example, suppose the number of RBs corresponding to the first bit sequence is N PRB , the modulation order is Q m , and the number of REs included in one RB is I RB , and the number of layers mapped to each transport block is N L . Then, one possible way to determine N 1 is: N 1 ⁇ N PRB ⁇ I RB ⁇ Q m ⁇ N L .
  • This rate limit is for the encoder, and a wider range of code rates can be achieved by the rate matching operation after encoding throughout the transmission.
  • the specific value may be implemented by a multiplier and an adder, or may be implemented by an adder only, or implemented in other manners, which is not limited by the embodiment of the present application.
  • B 1 is an adjustment value or a correction value, and the definition of the B1 value can be set according to system design requirements. It can be understood that this adjustment value may also be unnecessary, that is, B 1 is equal to 0.
  • the divided bit sequences can be grouped into A code block groups for each code block.
  • the group may perform an operation of adding a code block group check bit, for example, a code block group check bit may be added after the last code block of each code block group.
  • the check bits added for the code block group may be referred to as code block group check bits, and the check bits added for the code block may be referred to as code block check bits.
  • code block partitioning and the bits in each bit sequence after the code block grouping are represented as c r0 , c r1 , L, r is the number of each bit sequence, and K r is the length of the rth bit sequence. If the rth bit sequence is the last bit sequence in a code block group, then the bit The following bits are parity bits, including code block check bits and code block group check bits, and the code block group check bits may be located before or after the code block check bits.
  • L CBG is the length of one code block group check bit.
  • L CB is the length of the code block check bit. If the rth bit sequence is not the last bit sequence in a code block group, the bit The following bits are code block check bits.
  • the manner of adding the code block group check bits is not limited to the system that uses the code block segmentation method in the embodiment of the present application, that is, the method for adding the code block group check bits is not the same as the embodiment of the present application.
  • the code block segmentation method is coupled and can be applied in a system using other code block segmentation methods.
  • the check bits can be added to the code block group in the manner of the embodiment of the present application.
  • the code block group check bits can be taken into account.
  • the value of B 1 is equal to the sum of the number of code block group check bits of the A code block groups, and B1 can be determined according to A, and the number of code block group check bits of each code block group.
  • B1 may be related to one or more parameters according to system design requirements, which is not limited in this application.
  • one possible way to determine C can be:
  • the coded block length of the encoder is limited by N max , the code after the coding and rate matching The block length is greater than N max, and - can only be achieved by a simple repetition method, which leads to loss of coding gain, resulting in degradation of the decoding performance of the entire transport block.
  • the C determined by the above method makes the code block length of the coded block after encoding and rate matching as close as possible to N max , and can obtain the code length as much as possible without losing the code rate gain. Gain, which improves decoding performance.
  • N 1 ' can be understood as a correction to N 1
  • N 1 ' min(N 1 ,(B+B 1 )/R min )
  • the comparison between (B+B 1 )/R min and N 1 The small value is determined as N 1 '
  • R min represents the minimum code rate supported by the encoding, which may also be referred to as the lowest available code rate.
  • R min may be 1/5, which is not limited in the embodiment of the present application.
  • the bit sequence resources of the N max length are allocated according to each of the divided code blocks, since each bit sequence includes a repeated bit, the actual coding is performed.
  • the bit sequence length is less than N max , which results in a relatively large number of divided code blocks, and each code block includes a relatively small number of bits.
  • N threshold represents the minimum length after the coded and rate matching of the divided bit sequence.
  • the manner of determining C can be understood as further optimization based on the method (1) of determining C.
  • the code block is determined at this time.
  • the coded block gain loss caused by the operation is large, and the correction of C tmp by the offset value ⁇ can reduce the block length gain loss after encoding and improve the decoding performance.
  • optimization scheme mentioned in the similar manner (1) can also be used to optimize the manner of acquiring C tmp , for example:
  • N 1 ' min(N 1 ,(B+B 1 )/R min );
  • N threshold is a preset threshold
  • ⁇ is an offset value
  • ⁇ is a positive integer
  • ⁇ is such that
  • L CB is the number of bits of the check bits included in the divided bit sequence.
  • the check bits herein may be CRC bits, and may also be other check bits, which is not limited in this embodiment of the present application.
  • B 1 is an adjustment value (or a correction value), and its value can be defined according to the system design. For example, when B 1 is greater than 0, the value of B 1 is equal to the data of the code block group corresponding to the C divided bit sequences. In this design, since the number of code block group check bits is considered in advance when determining the number C of the divided bit sequences, the length of the bit sequence before encoding can be made close to improve performance.
  • the value of B 1 above may also be designed to be related to one or more other system parameters, which is not limited thereto.
  • B 1 is introduced in the above description and formula. It can be understood that, when the adjustment value B 1 is not required, that is, when B 1 is 0, the above formula can be correspondingly deformed, excluding the parameter B 1 .
  • Another embodiment of the present application further provides a communication method, which is implemented by a communication device and is implemented on the transmitting side. As shown in FIG. 6, the method includes:
  • the first bit sequence to be divided is obtained, the number of bits of the first bit sequence is B, and the number of bits that the physical resource corresponding to the first bit sequence can carry is N 1 ;
  • B 1 can be referred to the related description of the foregoing embodiment.
  • R min, K indicates that the minimum code rate supported by the encoder when the block length is not limited after encoding may be a predefined value, for example, 1/5.
  • K threshold1 3600
  • K threshold2 6000
  • the first bit sequence is divided into C divided bit sequences.
  • the code block length of each code block is smaller than the K threshold after the code block is divided, it indicates that the coded block length gain loss due to code block segmentation is large at this time, and the block total value C is corrected by the offset value ⁇ .
  • the block length gain loss after encoding can be reduced, and the decoding performance can be improved.
  • the offset value ⁇ needs to be satisfied In order to avoid that the block length of the block before the correction is larger than the maximum code length K max supported by the encoder, or the loss of the block code rate after the code is too long, the decoding performance of the block is degraded.
  • the foregoing process exemplarily illustrates the implementation of the code block segmentation on the transmitting side.
  • the corresponding method is used for decoding and cascading on the receiving side.
  • the same method as the transmitting side may be used.
  • the number C of bit sequences after segmentation on the transmitting side is determined, thereby knowing that C code blocks need to be decoded and concatenated. That is to say, in the communication method on the receiving side, after determining C, the size of the bit sequence before and after encoding can be determined according to C and decoded, and after the decoding is completed, the concatenation is performed to obtain the decoded transport block.
  • the above decoding and cascading can be implemented by a communication device and implemented on the receiving side.
  • An embodiment of the present application further provides a communication device 700, which is used to implement the communication method implemented on the transmitting side.
  • the communication device may include:
  • the obtaining unit 701 is configured to acquire a first bit sequence to be divided.
  • the number of bits of the first bit sequence is B, and the number of bits that the physical resource corresponding to the first bit sequence can carry is N 1 .
  • a determining unit 702 configured to determine, according to N 1 and the parameter L, the number C of bit sequences after dividing the first bit sequence, where the value of L is equal,
  • the minimum code rate corresponding to the maximum coding block length K max available, B 1 is an integer greater than or equal to 0.
  • the dividing unit 703 is configured to divide the first bit sequence into C divided bit sequences.
  • the foregoing obtaining unit 701, the determining unit 702, and the dividing unit 703 may be independent logical function modules, and may be implemented by an integrated functional unit, which is not limited in this embodiment of the present application. Further, the specific functions and implementation manners of the foregoing various units may refer to related descriptions of the method embodiments.
  • a further embodiment of the present application further provides a communication device 800 for implementing the communication method implemented on the transmitting side.
  • the communication device may include: a memory 801 and a processor 802 in different applications.
  • the memory 801 and the processor 802 may have different functions.
  • the memory 801 may be configured to store a first bit sequence to be divided, where the number of bits of the first bit sequence is B, and the number of bits that the physical resource corresponding to the first bit sequence can carry is N 1 ; It may be used to determine the number C of bit sequences after dividing the first bit sequence according to N 1 and the parameter L, where the value of L and equal, A minimum code rate corresponding to the maximum coding block length K max available, B 1 is an integer greater than or equal to 0; and, the first bit sequence is divided into C divided bit sequences.
  • the memory 801 which is a unit that implements a storage function, and can be, for example, a register or a random read/write memory (RAM). It can also be a cache register (Cache), which is not limited in this embodiment of the present application.
  • the memory 801 can be used to store instructions that implement the communication methods described in the various embodiments above; the processor 802 can be used to execute the instructions described above to implement the communication methods described in the various embodiments above, for example, to be segmented a first bit sequence, the number of bits of the first bit sequence is B, and the number of bits that the physical resource corresponding to the first bit sequence can carry is N 1 ; determining the first bit according to N 1 and the parameter L The number of bit sequences after sequence segmentation, where the value of L and equal, A minimum code rate corresponding to the available maximum coding block length K max , B 1 is an integer greater than or equal to 0; the first bit sequence is divided into C divided bit sequences.
  • the memory 801 and the processor 802 may exist independently or may be integrated on one chip.
  • the present embodiment does not limit the existence form of the memory 801 and the processor 802.
  • processor 802 in the embodiment of the present application may refer to related descriptions in the method embodiments, and details are not described herein again. It can be understood that the processor 802 herein can also implement the corresponding functions of the determining unit 702 and the dividing unit 703 in the foregoing embodiments.
  • the communication device provided by the embodiments of FIG. 7 and FIG. 8 determines the number of divided coding blocks by combining N1 and L, and avoids loss of coding gain as much as possible, thereby providing a Reasonable code block segmentation scheme.
  • the communication device provided in the foregoing embodiments of FIG. 7 and FIG. 8 may include other units in addition to the functional units shown in the drawings, which is not limited in this embodiment, and may also include, for example, implementing a transceiving function. Unit.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above software function parts can be stored in the storage unit.
  • the storage unit includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform some of the steps of the methods described in various embodiments of the present application.
  • the storage unit includes: one or more memories, such as a read-only memory (ROM), a random access memory (RAM), and an electrically erasable programmable read only memory (EEPROM). and many more.
  • the storage unit may exist independently or may be integrated with the processor.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a Solid State DisB (SSD)) or the like.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape
  • an optical medium eg, a DVD
  • a semiconductor medium eg, a Solid State DisB (SSD)

Abstract

本申请的一个实施例提供一种通信方法。该方法包括：获取待分割的第一比特序列，所述第一比特序列的比特数目为B,所述第一比特序列对应的物理资源能够携带的比特的数目为N 1；根据N 1和参数L确定将所述第一比特序列分割后的比特序列的数量C，其中，L的值和相等，为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数；将所述第一比特序列分割成C个分割后的比特序列。通过该方法，可以提供了一种合理的码块分割方案，尽可能的避免编码增益的损失，提高译码性能，从而改善系统性能。

Description

通信方法和装置
本申请要求于2017年3月24日提交中国专利局、申请号为201710184937.2、申请名称为“通信方法和装置”的中国专利申请的优先权，2017年5月3日提交中国专利局、申请号为201710305802.7的申请名称为“通信方法和装置”的中国专利申请优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术，尤其是一种通信方法和装置。
背景技术
在长期演进(LTE)协议中，Turbo码编码器支持的最大块长为6144比特，为了支持更大的信息长度，在编码前会进行码块分割操作，也就是将超过6144比特序列分割成多个码块分别进行编码。
随着技术的发展，在通信系统中引入了低密度奇偶校验比特(low density parity checB code,LDPC)对信息进行编码，其校验矩阵是一种稀疏矩阵。
采用LDPC编码系统中，编码后总比特数较少时，译码误块率随编码后比特数增加而下降的速度较快，编码后总比特数目较多时，译码误块率下降的速度相对较慢；LDPC译码器的复杂度和编码后比特数目正相关，从折衷译码误块率和译码器复杂度的角度看,可以对编码后的比特序列的比特数目进行限制，使得其在保证一定译码误块率的同时，具有合理的译码复杂度。也就是说，在采用LDPC编码的通信系统中，编码后的比特序列的比特数目是受限的。
然而，目前尚没有一种针对编码后比特序列的比特数目受限的通信系统的合理的比特序列的分割方案。
发明内容
本申请的实施例提供的通信方法和装置，用于提供一种针对编码后比特序列的比特数目受限的通信系统的通信方法，合理的进行比特序列的分割。
一方面，本申请实施例提供一种通信方法，该方法包括：获取待分割的第一比特序列，该第一比特序列的比特数目为B,所述第一比特序列对应的物理资源能够携带的比特的数目为N 1；然后，根据N 1和参数L确定该第一比特序列分割后的比特序列的数量C，其中，L的值和
Figure PCTCN2018080380-appb-000001
相等，
Figure PCTCN2018080380-appb-000002
为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数；该第一比特序列分割成C个分割后的比特序列。上述方法中，通过结合N 1和L确定出分割的编码块的数量，提供 了一种合理的码块分割方案，可以尽可能的避免编码增益的损失。
另一方面，本申请实施例还提供一种通信装置。该通信装置可用于实现上述的通信方法。该通信装置可以是终端，基站，或者基带芯片，或者数据信号处理芯片，或者通用芯片。
作为一种可选的设计，该通信装置包括存储器和处理器，其中存储器用于存储待分割的第一比特序列；处理器用于：根据N 1和参数L确定将所述第一比特序列分割后的比特序列的数量C，其中，L的值和
Figure PCTCN2018080380-appb-000003
相等，
Figure PCTCN2018080380-appb-000004
为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数；以及，将所述第一比特序列分割成C个分割后的比特序列。
上述根据N 1和L确定出分割的编码块的数量，可以是通过比较N 1与L(或者比较L与N 1)来确定C，也可以是通过比较N 1与
Figure PCTCN2018080380-appb-000005
(或者比较(B+B 1)
Figure PCTCN2018080380-appb-000006
与N 1)来确定C。
B 1为调整值(或修正值)。可以理解的是上述确定C时，也可以不需要调整值B 1，也就是说B 1为0。当B 1为0时，L的值和
Figure PCTCN2018080380-appb-000007
相等，所述通过N 1和L确定出分割的编码块的数量，可以是通过比较N 1与L(或者比较L与N 1)来确定C，也可以是通过比较N 1与
Figure PCTCN2018080380-appb-000008
(或者比较
Figure PCTCN2018080380-appb-000009
与N 1)来确定C。
一种可能的确定C的方式可以为：当L<N 1时，
Figure PCTCN2018080380-appb-000010
其中，
Figure PCTCN2018080380-appb-000011
表示向上取整，N max的值和
Figure PCTCN2018080380-appb-000012
的值相等。而通过该方式确定出来的C，使得分割后的编码块在经过编码和速率匹配后的码块长度尽可能的接近N max，能在不损失码率增益的同时，尽可能多的获得码长的增益，从而提升译码性能。
又一种可能的确定C的方式可以为：当L<N 1时，
Figure PCTCN2018080380-appb-000013
其中，
Figure PCTCN2018080380-appb-000014
表示向上取整，N max的值和
Figure PCTCN2018080380-appb-000015
的值相等；当
Figure PCTCN2018080380-appb-000016
时,C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
Figure PCTCN2018080380-appb-000017
此处，当分割后比特序列的编码后块长小于N threshold时，说明此时因码块分割操作导致的编码后块长增益损失较大，通过偏移值Δ对C tmp进行修正后，可减少编码后块长增益损失，改善传输块的译码性能。
又一种可能的确定C的方式可以为：当L<N 1时，
Figure PCTCN2018080380-appb-000018
其中，
Figure PCTCN2018080380-appb-000019
表 示向上取整，N max的值和
Figure PCTCN2018080380-appb-000020
的值相等，N 1'＝min(N 1,(B+B 1)/R min)，R min为编码支持的最低码率，从而可以改善译码性能。
又一种可能的确定C的方式可以为：当L<N 1时，
Figure PCTCN2018080380-appb-000021
其中，
Figure PCTCN2018080380-appb-000022
表示向上取整，N max的值和
Figure PCTCN2018080380-appb-000023
的值相等，N 1'＝min(N 1,(B+B 1)/R min)，R min为编码支持的最低码率；当
Figure PCTCN2018080380-appb-000024
时,C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
Figure PCTCN2018080380-appb-000025
从而可以改善译码性能。
又一种可能的确定C的方式可以为：当L≥N 1时，
Figure PCTCN2018080380-appb-000026
其中，
Figure PCTCN2018080380-appb-000027
表示向上取整，L CB是分割后的比特序列的校验比特的比特数目。此处，可以在分割后的比特序列的长度小于K max的前提下，使得每个分割后的比特序列的长度尽可能的大，从而可以获得较为理想的码长增益，提高译码性能。
可选的，上述B可以通过以下方式确定。B＝K TB+L TB；其中,K TB为传输块长度,L TB为传输块的校验比特的比特数目L TB为大于或者等于0的整数，当L TB＝0时，B＝K TB。
上述B1为调整值(或修正值)，其取值可以根据系统设计来定义。例如，B1大于0时，B 1的值与A个码块组的码块组校验比特数目之和相等，所述码块组为C个分割后的比特序列的分组，A为码块组的数目。在这种设计中，由于在确定分割后的比特序列的数量C时，提前考虑了码块组校验比特数目，可以避免分割后的比特序列长度差别较大，不同码块编码后码率不均匀的问题，改善了译码性能。
可选的，还可以在所述A个码块组中的每个码块组中最后一个码块后添加码块组校验比特。
上述B 1的值也可以设计为与其他一个或多个系统参数有关，对此不作限定。
本申请提供的涉及方案，也可以不需要调整值B 1，也就是说B 1为0。
可选的，本申请提供的方法和装置可以用于采用LDPC的通信系统。
作为另一种可选的设计，上述通信装置包括处理器和存储器。存储器用于存储实现前述所描述的通信方法的指令；处理器用于运行上述指令以实现前述通信方法。
可选的，上述通信装置还可以进一步包括收发机。
本申请实施例还提供一种计算机程序产品，该程序产品包括用于实现前述的方法的指令。
本申请实施例还提供一种计算机可读存储介质，该介质存储有用于实现前述通信方法的指令。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍。
图1为无线通信系统的简化示意图；
图2为一种终端的结构简化示意图示意图；
图3为一种基站的结构简化示意图；
图4为本申请实施例一种通信方法流程示意图；
图5为示例的一种比特序列处理过程；
图6为本申请实施例一种通信方法流程示意图；
图7为本申请实施例一种通信装置结构示意图；
图8为本申请又一实施例一种通信装置结构示意图。
具体实施方式
下面将结合本申请中的附图，对本申请的实施例进行描述。
以下对本申请中的一些术语和约定做出说明。
比特序列是一种由比特“0”和/或“1”组成的序列。比特序列的长度是指比特序列包括的比特的数目。例如：比特序列00包括2个比特，其长度为2；比特序列111包括3个比特，其长度为3；比特序列“0100”包括4个比特，其长度为4。
传输块(transport blocB,TB)以及码块(code blocB,CB)都可以视为一种比特序列。码块是通过对传输块或者经过处理的传输块分割后得到的，是编码的对象。因此，本申请中，码块的长度指的是该码块对应的比特序列所包括的比特的数目，传输块的长度指的是该传输块对应的比特序列所包括的比特的数目，传输块的长度也可以称为传输块的大小。可以理解，随着技术的发展，传输块或者码块可能有不同的术语名称。
本申请实施例中所提到的自然数包括0。
在本申请实施例中，通信装置是一种具有通信功能的装置。例如：通信装置可以是基站、或者终端，或者芯片等，其中的芯片例如可以是基带芯片，或者通信芯片。
本申请实施例的技术方案可以用于如图1所示的无线通信系统中。如图1所示，在无线通信系统包括至少一个基站B200和终端T100(图中仅示出一个)。基站B200可以利用不同的通信资源与终端T100进行通信。例如：基站B200可以利用宽波束和/或窄波束与终端T100进行通信。该无线通信系统可以是4G通信系统，例如：LTE(长期演进，long term evolution)系统，5G通信系统，例如NR(new radio，新空口)系统，多种通信技术融合的通信系统(例如LTE技术和NR技术融合的通信系统)。基站B200和终端T100均可以作为发送设备或接收设备。在上行链路，终端作为发送设备，基站作为接收设备，在下行链路，基站作为发送设备，终端作为接收设备。可以理解的是，所述无线通信系统可以包括无线接入网和核心网，所述无线接入网中包括基站B200，也可以包括其他接入设备，例如中继站，或者其他设备等。所述核心网可以包括核心网设备，如，移动管理实体，或其他控制或存储设备等。
本申请中，终端T100是一种具有无线通信功能的设备，可以是具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等。在不同的网络中终端可以叫做不同的名称，例如：用户设备，移动台，用户单元，站台，蜂窝电话，个人数字助理，无线调制解调器，无线通信设备，手持设备，膝上型电脑，无绳电话，无线本地环路台等。需要说明的是，为便于理解和图示方便，图1，图2中，终端T100以手机作为图示示例，为了便于说明，图2给出了终端T100的结构示意图。如图2所示，终端T100包括处理器、存储器、射频电路、天线以及输入输出装置。处理器主要用于对通信协议以及通信数据进行处理，以及对终端进行控制，执行软件程序，处理软件程序的数据等。存储器主要用于存储软件程序和数据。射频电路主要用于基带信号与射频信号的转换以及对射频信号的处理。天线主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。需要说明的是，有些种类的终端可以不具有输入输出装置。
当需要发送数据时，处理器对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到终端时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器，处理器将基带信号转换为数据并对该数据进行处理。
为了便于说明，图2仅示出了一个存储器和处理器。在实际的终端产品中，可以存 在一个或多个处理器和一个或多个存储器。存储器也可以称为存储介质或者存储设备等。存储器可以是独立于处理器设置，也可以是与处理器集成在一起，本申请实施例对此不做限制。
作为一种可选的实现方式，处理器可以包括基带处理器和/或中央处理器，基带处理器主要用于对通信协议以及通信数据进行处理，中央处理器主要用于对整个终端进行控制，执行软件程序，处理软件程序的数据。图2中的处理器集成了基带处理器和中央处理器的功能，本领域技术人员可以理解，基带处理器和中央处理器也可以是各自独立的处理器。可选的，终端可以包括多个基带处理器以适应不同的网络制式。可选的，终端可以包括多个中央处理器以增强其处理能力。可选的，可以将基带处理器和中央处理器的功能集成在一个处理器上实现。可选的，终端的各个部件可以通过各种总线连接。基带处理器也可以表述为基带处理电路或者基带处理芯片。中央处理器也可以表述为中央处理电路或者中央处理芯片。可选的，对通信协议以及通信数据进行处理的功能可以内置在处理器中，也可以以软件程序的形式存储在存储单元中，由处理器执行软件程序以实现基带处理功能。
在本申请实施例中，可以将具有收发功能的天线和射频电路视为终端的收发单元，将具有处理功能的处理器视为终端的处理单元。如图2所示，终端T100包括收发单元101和处理单元102。收发单元也可以称为收发器、收发机、收发装置等。处理单元也可以称为处理器，处理单板，处理模块、处理装置等。可选的，可以将收发单元101中用于实现接收功能的器件视为接收单元，将收发单元101中用于实现发送功能的器件视为发送单元，即收发单元101包括接收单元和发送单元。收发单元有时也可以称为收发机、收发器、或收发电路等。接收单元有时也可以称为接收机、接收器、或接收电路等。发送单元有时也可以称为发射机、发射器或者发射电路等。
基站B200，也可称为基站设备，是一种部署在无线接入网用以提供无线通信功能的设备。例如：在LTE网络中的基站称为演进的节点B(evolved NodeB，eNB或者eNodeB)，在NR网络中的基站称为TRP(收发点，transmission reception point)或者gNB(generation nodeB，下一代节点B)。基站B200的结构可以如图3所示。图3所示的基站B200可以是分体式基站,例如图3靠左示出了包括天线(antennas)、无线射频单元(remote radio unit,RRU)和基带单元(baseband unit，BBU)的分布式基站，图3所示的基站也可以是一体式基站，例如图3靠右示出的小站(small cell)。一般而言，基站包 括201部分以及202部分。201部分主要用于射频信号的收发以及射频信号与基带信号的转换；202部分主要用于进行基带处理，对基站进行控制等。201部分通常可以称为收发单元、收发机、收发电路、收发器等。202部分通常可以称为处理单元。通常202部分是基站的控制中心。
作为一种可选的实施方式，201部分为收发单元，也可以称为收发机，收发器等，其包括天线和射频单元，其中射频单元主要用于进行射频处理。可选的，可以将201部分中用于实现接收功能的器件视为接收单元，将用于实现发送功能的器件视为发送单元，即201部分包括接收单元和发送单元。示例性的，接收单元也可以称为接收机、接收器、接收电路等，发送单元可以称为发射机、发射器或者发射电路等。
作为一种可选的实施方式，202部分可以包括一个或多个单板，每个单板可以包括处理器和存储器，处理器用于读取和执行存储器中的程序以实现基带处理功能以及对基站的控制。若存在多个单板，各个单板之间可以互联以增加处理能力。
可以理解是的，以上图1-图3仅为示例，并不限于此。
本申请一实施例提供了一种通信方法，该通信方法由通信装置实现，该通信装置可以是基站、或者终端，或者芯片等，本申请实施例对此不做限定。如图4所示，可以包括：
S401，获取待分割的第一比特序列，所述第一比特序列的比特数目为B,所述第一比特序列对应的物理资源所携带的比特的数目为N 1。
第一比特序列即待分割的比特序列，为码块分割操作的输入，也就是说码块分割的对象是第一比特序列。
第一比特序列例如可以是待发送序列，也可以是经过处理的待发送比特序列。
对待发送比特序列的处理可以包括但不限于添加校验比特，例如添加循环冗余校验(cyclic redundancy check，CRC)比特。需要说明的是，这里校验比特以CRC比特为例，随着技术的发展，也可以由其他的校验比特来替代上述的CRC比特。
可选的，上述待发送序列有时也可以称为为传输块(transport block,TB)。
所述待发送序列可以从高层被传递到物理层。此处的高层，例如可以是媒体接入控制(MAC)层。
可以将进行码块分割时读取码块分割操作的输入理解为获取第一比特序列。当获取到第一比特序列后，便可以得知第一比特序列的比特数目，本申请实施例中，第一比特序列的比特数目用B表示。
可选的，在进行资源分配时，可以根据基站与终端之间的无线链路的信道状态信息、用户优先级、业务优先级或缓存中的数据量等信息，确定在调度时间单元上为哪些终端分配物理资源用于数据传输。确定用于数据传输的物理资源的同时，也就确定了数据传输的调制编码方案MCS和传输块大小(transport block size,TBS)。传输块的大小与第一比特序列的比特数目B是关联的。该物理资源可以视作是和传输块对应的物理资源，该物理资源上所能够携带的比特的数目即N 1。可以理解的是，传输块和本申请实施例中的第一比特序列是关联的，例如，前文所述的第一比特序列可能是传输块本身，也可以是指经过处理的传输块，因此，与传输块所对应的物理资源也可以理解为与第一比特序列对应的物理资源。上述是理解与第一比特序列对应的物理资源的一种示例方式，也有可能有其他的理解方式，本申请实施例对此不做限定。
需要说明的是，上文所述的资源分配包括上行调度或者下行调度。
S402，根据与第一比特序列对应的物理资源所携带的比特的数目N 1和参数L确定第一比特序列将要被分成多少个比特序列，即确定第一比特序列分割后的比特序列的数量C，其中，L的值和
Figure PCTCN2018080380-appb-000028
相等，
Figure PCTCN2018080380-appb-000029
为允许的最大编码块长度K max对应的最小码率。
Figure PCTCN2018080380-appb-000030
是指在编码器中可用的最大编码块长度K max对应的最小码率，其中，
Figure PCTCN2018080380-appb-000031
的具体取值可以是协议预先规定好的。上述B 1可以理解为是对B的一个调整量，根据不同的场景，可能会有不同的取值。
S403，将该第一比特序列分割成C个分割后的比特序列。
在确定了分割后的比特序列的数量后，将第一比特序列进行分割，得到C个比特序列。其中，对第一比特序列进行分割的方式可能有多种，比如可以将第一比特序列分割成近似均匀的C个比特序列，本申请实施例对分割的方式不做限定。
可选的，可以采用类似于3GPP TS36.212 V13.4.0的5.1.2章节中所描述的方式进行分割，或者，可以是采用在3GPP TS36.212 V13.4.0的5.1.2章节中所描述的方式的基础上进行改进的方式进行分割。
此外，分割操作中也可能进一步包括填充和/或添加校验比特等操作，此时，分割后的C个比特序列的总长度是大于第一比特序列的长度的。
需要说明的是，本申请实施例中，为了描述方便，会出现比特序列的长度这一术语，而比特序列的长度是指该比特序列所包括的比特的数目。
在编码器编码后块长受限的场景下，采用传统分割方法时，可能出现所述物理资源分配给单个分割后比特序列的比特数目大于编码后最大块长N max的情况，此时只能通过重复发送一个较高码率的编码后比特段，来填充所有编码后比特，从而损失了编码增益，导致整个传输块的误块率上升。本申请实施例中，通过结合N 1和L确定出分割的编码块的数量，提供了一种合理的码块分割方案，可以尽可能的避免编码增益的损失。
下面具体描述上述方法中所涉及到的各个参数的可能的确定方式。
1.对于参数N 1
可选的，发送设备在将第一比特序列发送给接收设备之前，会对第一比特序列进行分割、编码、速率匹配、交织、资源映射等处理，例如图5所示。可以理解的是，图5只是示例了一种可能的对第一比特序列的处理过程，本申请实施例对此不做限定。
所述第一比特序列被处理后被映射到资源单元(resource element，RE)上。，在通信系统中，可以以资源块(resource block，RB)为单位，或者以RE为单位进行资源分配。一个RB可以包括一个或多个RE。将所述第一比特序列经过处理后映射到物理资源上，可以理解为将第一比特序列对应的信息符号映射到RE上，或者理解为将第一比特序列对应的信息符号映射到RB上。
可选的，RB中的一个或多个RE可能用于承载导频符号，在确定第一比特序列对应的物理资源时，可以将用于承载导频符号的RE从相应的RB中剔除。也就是说RB中去除了用于承载导频符号的RE之后的那些RE用来承载对应于第一比特序列的信息比特。
可以理解的是，第一比特序列在映射到物理资源之前的处理可能有多种不同的情况，上述仅为举例。例如，还可能包括级联，打孔等处理。处理的过程以及顺序也可以适应于系统的要求有所不同。
可以理解的是，RB是物理资源的一种举例说明，物理资源可能有其他不同的形式，可选的，与第一比特序列对应的RB可能是一个或者多个。
如前所述，在进行资源分配时，与传输块对应的物理资源已经确定，那么与第一比特序列对应的物理资源也是确定的。
根据第一比特序列对应的物理资源信息，便可以获知在该物理资源上能够携带的比特的数目，例如，在物理资源上能够携带的比特的数目可能与调制阶数，RB的个数，一个RB所包括的RE的数目相关。举例来说，假设第一比特序列对应的RB个数为N PRB，调制阶数为Q m，一个RB所包括的RE个数为I RB，，每个传输块映射到的层数为N L，那么一种可能的确定N 1的方式为：N 1≈N PRB×I RB×Q m×N L。
可选的，如果系统包含了有限缓存(Limited Buffer)的设计，则N 1的确定还需要考虑被限制后的循环缓存的大小，例如，假设直接由相关物理资源信息计算得的比特数为N k，有限缓存的大小为N IR，则N 1应选择两者间的较小值，即N 1＝min(N k，N IR)。
2.对于参数L
L的值和
Figure PCTCN2018080380-appb-000032
相等。可以理解的是，
Figure PCTCN2018080380-appb-000033
这一码率限制是针对编码器而言的，而在整个传输过程中，通过编码之后的速率匹配操作，可以实现更大范围的码率。
例如，假设
Figure PCTCN2018080380-appb-000034
B 1＝0，那么
Figure PCTCN2018080380-appb-000035
即3*B。
Figure PCTCN2018080380-appb-000036
的具体数值也就是L的数值，从而被用来确定C。
具体的，在获取
Figure PCTCN2018080380-appb-000037
这一具体数值时可以通过乘法器和加法器实现，也可以仅通过加法器实现，或者其他的方式实现，本申请实施例对此不做限定。
3.对于参数B
根据不同的对待发送序列的处理，B可能有不同的确定方式，例如，假设第一比特序列是对传输块进行添加校验比特之后的序列，传输块长度是K TB，添加的校验比特的长度是L TB，那么B＝K TB+L TB。
需要说明的是,L TB的取值可能为0,也就是说,对传输块添加校验比特的操作不是必须的,当L TB为0时，B＝K TB。
4.对于参数B 1
B 1为调整值或修正值，B1值的定义可以根据系统设计需要来设定。可以理解，也可以不需要这个调整值，也就是B 1等于0。
对于B 1大于0时，也就是说需要设计调整值时，一个可能的设计如下：对第一比特序列分割后，可以将分割后的比特序列分组为A个码块组，对每一个码块组可以进行添加码块组校验比特的操作，例如可以将码块组校验比特添加在每个码块组的最后一个码块后面。
本申请实施例中，可以将针对码块组添加的校验比特称为码块组校验比特，将针对码块添加的校验比特称为码块校验比特。
例如，假设C＝12，A＝4，每个码块组添加的码块组校验比特的比特数目为24，也就说将12个分割后的比特序列分成4个码块组，每个码块组包括3个分割后的比 特序列，4个码块组的码块组校验比特数目之和为24×4＝96。
假设进行码块分割且码块分组后的每个比特序列中的比特表示为c r0,c r1,L,
Figure PCTCN2018080380-appb-000038
r为每个比特序列的编号，K r为第r个比特序列的长度。如果该第r个比特序列是一个码块组中最后一个比特序列，那么比特
Figure PCTCN2018080380-appb-000039
之后的比特为校验比特，包括码块校验比特和码块组校验比特，码块组校验比特可以位于码块校验比特之前或者之后L CBG为一个码块组校验比特的长度，L CB为码块校验比特的长度。如果该第r个比特序列不是一个码块组中最后一个比特序列，比特
Figure PCTCN2018080380-appb-000040
之后的比特为码块校验比特。
可以理解的是，上述添加码块组校验比特的方式不仅限于应用于采用本申请实施例的码块分割方法的系统中，即上述码块组校验比特的添加方式不与本申请实施例的码块分割方法耦合，在采用其他码块分割方法的系统中也可以应用。只要针对的对象是码块组，便可以采用本申请实施例中的方式对码块组添加校验比特。
如果在对编码前，有码块分组的操作，且会针对码块组添加码块组校验比特，那么在确定C时，可以将码块组校验比特数目之和考虑进去。那么B 1的值与A个码块组的码块组校验比特数目之和相等，根据A，以及每个码块组的码块组校验比特数目便可以确定B1。在确定分割后的比特序列的数量C时，提前考虑码块组校验比特数目，可以避免分割后的比特序列长度差别较大，不同码块编码后码率不均匀的问题，改善了译码性能。
需要说明的是，如果不对码块组进行添加码块组校验比特的操作，或者，在对第一比特序列分割后没有分组的操作，或者，即使对码块组进行添加码块组校验比特的操作，但是为了简化运算，不考虑B 1，这三种场景都可以理解为不考虑码块组校验比特，那么在确定C时，可以不考虑B 1，或者可以理解为B 1＝0，那么此时，L的值和
Figure PCTCN2018080380-appb-000041
相等。
可以理解的是，B1的取值，也可以是根据系统设计需求，涉及成与其他一个或者多个参数有关，本申请对此不作限定。
5.对于参数C
可选的，一种可能的确定C的方式可以是：
(1)当L<N 1时，
Figure PCTCN2018080380-appb-000042
其中，
Figure PCTCN2018080380-appb-000043
为向上取整，N max的值和
Figure PCTCN2018080380-appb-000044
的值相等。例如，假设B＝9000，
Figure PCTCN2018080380-appb-000045
K max＝8000，N 1＝60000，那么L＝27000，N max＝24000，那么
Figure PCTCN2018080380-appb-000046
通常情况下，当码率一定时，编码后比特序列的长度越长，码长增益越大；此外，如果编码器的编码后码块长度受限于N max,当编码和速率匹配后的码块长度大于N max，-则只能通过简单重复的方式实现，会导致编码增益的损失，导致整个传输块的译码性 能下降。而通过上述方式确定出来的C，使得分割后的编码块在经过编码和速率匹配后的码块长度尽可能的接近N max，能在不损失码率增益的同时，尽可能多的获得码长的增益，从而提升译码性能。
进一步的，当支持的编码码率存在最小值时候,通过
Figure PCTCN2018080380-appb-000047
的方式得到的C可能偏大,从而使得分割总数偏多,每个码块的编码输入长度偏小,可能影响译码性能,为了尽量避免该问题,还可以在上面公式的基础上进行进一步的优化,例如
Figure PCTCN2018080380-appb-000048
其中N 1'可以理解为是对N 1的修正,N 1'＝min(N 1,(B+B 1)/R min),即将(B+B 1)/R min和N 1中的较小值确定为N 1',而R min表示编码支持的最小码率，也可以称为可用的最低码率，例如R min可以为1/5,本申请实施例对此不做限定。举例来说，例如，N max＝2000，假设N 1＝16000，(B+B 1)＝1000,
Figure PCTCN2018080380-appb-000049
R min＝1/4，那么L＝1000*3＝3000，如果按照
Figure PCTCN2018080380-appb-000050
得到C＝8，那么每个码块输入长度125，按最低码率1/4得到的编码后长度为500，需要通过重复的方式重复到16000/8＝2000比特；但是，如果按照
Figure PCTCN2018080380-appb-000051
的方式，得到C＝4，每个码块输入长度500，按最低码率1/4得到的编码后长度为2000比特，重复到4000比特。
当支持的编码码率存在最小值时候，此时，如果还是按照每个分割后码块分配N max长度的比特序列资源进行分割的话，由于每个比特序列中包含了重复比特，其实际编码后比特序列长度是小于N max的，这就导致分割的码块数目相对较多，每个码块所包括的比特数目相对较少。而通过上述改进的方法，使得每个分割后的码块的编码后长度尽可能接近N max，其分割后码块的数目相对较少，每个码块所包括的比特数相对较多，因此可以改善译码性能。
可选的，另一种可能的确定C的方式可以是：
(2)当L<N 1时，
Figure PCTCN2018080380-appb-000052
其中，
Figure PCTCN2018080380-appb-000053
为向上取整，N max的值和K max/
Figure PCTCN2018080380-appb-000054
的值相等；
这里，定义阈值N threshold，N threshold表示分割后的比特序列经编码和速率匹配后的最小长度，当
Figure PCTCN2018080380-appb-000055
时，表示若采用C tmp对第一比特序列进行分割，得到的编码和速率匹配后的比特序列的长度过小，可以将C tmp的值向下调整。此时，可以利用偏移值Δ对C tmp进行调整,且找到满足
Figure PCTCN2018080380-appb-000056
的Δ，Δ为正整数， 例如Δ可以为1，Δ的具体取值可以根据实际情况确定，本申请实施例对此不做限定。可选的，如果找不到满足条件的Δ，则Δ可以取0。
当
Figure PCTCN2018080380-appb-000057
时，C＝C tmp。
此处的确定C的方式，可以理解为是在确定C的方式(1)的基础上进行的进一步优化，当分割后比特序列的编码后块长小于N threshold时，说明此时因码块分割操作导致的编码后块长增益损失较大，通过偏移值Δ对C tmp进行修正后，可减少编码后块长增益损失，改善译码性能。
例如，假设不考虑码块分组的校验比特，B＝5000，
Figure PCTCN2018080380-appb-000058
K max＝8000，N 1＝30000，那么L＝15000，L<N 1，N max＝24000，那么
Figure PCTCN2018080380-appb-000059
又N thershold＝18000，
Figure PCTCN2018080380-appb-000060
可以对C tmp进行修正，令偏移值Δ＝1，且
Figure PCTCN2018080380-appb-000061
则最终C＝2-1＝1。
进一步的，也可以采用类似方式(1)所提到的优化方案对获取C tmp的方式进行优化，例如:
当L<N 1时，
Figure PCTCN2018080380-appb-000062
N 1'＝min(N 1,(B+B 1)/R min)；
当
Figure PCTCN2018080380-appb-000063
时,C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
Figure PCTCN2018080380-appb-000064
可选的，另一种可能的确定C的方式可以是：
(3)当L≥N 1时， 其中，
Figure PCTCN2018080380-appb-000066
为向上取整，L CB是分割后的比特序列中包括的校验比特的比特数目。
此处的校验比特可以是CRC比特，也可以是其他校验比特，本申请实施例对此不做限定。
当分割后的比特序列中不包括校验比特时，L CB＝0，那么
Figure PCTCN2018080380-appb-000067
或者，
当分割后的比特序列包括校验比特，但是不考虑码块组的校验比特时，B 1＝0，那么
Figure PCTCN2018080380-appb-000068
或者，
当分割后的比特序列不包括校验比特，且不考虑码块组的校验比特时，L CB和B 1均为0，那么
Figure PCTCN2018080380-appb-000069
例如，当L CB和B 1均为0时，假设B＝15000，
Figure PCTCN2018080380-appb-000070
K max＝8000，N 1＝30000，那么L＝45000，L>N 1，那么
Figure PCTCN2018080380-appb-000071
分割后的比特序列长度为7500。
当L≥N 1时，说明编码后比特数目不会出现受限的情况，那么可以在分割后的比特序列的长度小于K max的前提下，使得每个分割后的比特序列的长度尽可能的大，从而可以获得较为理想的码长增益，提高译码性能。
可以理解的是，对于C的确定，也可以直接是将N 1与
Figure PCTCN2018080380-appb-000072
比较，或者是将N 1与
Figure PCTCN2018080380-appb-000073
比较，本申请实施例对此不做限定。上述B 1为调整值(或修正值)，其取值可以根据系统设计来定义。例如，B 1大于0时，B 1的值与C个分割后的比特序列对应的码块组的数据相等。在这种设计中，由于在确定分割后的比特序列的数量C时，提前考虑了码块组校验比特数目，可以使得编码前的比特序列的长度接近，提升性能。
上述B 1的值也可以设计为与其他一个或多个系统参数有关，对此不作限定。
上述确定C的方案中，也可以不需要调整值B 1，也就是说B 1为0。为表述方便，上面的描述及公式中，都引入了B 1。可以理解的是，在不需要调整值B 1，也就是B 1为0时，上述公式可以相应的变形，不包括参数B 1。
本申请另一实施例还提供了一种通信方法，该通信方法由通信装置实现，在发送侧实施，如图6所示，包括：
S601，获取待分割的第一比特序列，所述第一比特序列的比特数目为B,所述第一比特序列对应的物理资源能够携带的比特的数目为N 1；
该步骤的具体实现和含义可以参考前述实施例的相关描述，此处不再赘述。
S602，根据第一编码率R，
Figure PCTCN2018080380-appb-000074
和R min,K确定将所述第一比特序列分割后的比特序列的数量C，其中，R的值等于(B+B 1)/N 1。
具体的，
Figure PCTCN2018080380-appb-000075
B 1的含义和取值可以参考前述实施例的相关描述。
具体的，R min,K表示编码后块长不受限时，编码器支持的最低编码码率，可以为预先 定义的数值，例如为1/5。
根据R，
Figure PCTCN2018080380-appb-000076
和R min,K确定C具体包括：
当
Figure PCTCN2018080380-appb-000077
时，
Figure PCTCN2018080380-appb-000078
,其中，关于L CB以及K max的含义以及取值也可以参考前述实施例的相关描述，此处不再赘述。
或者，
当
Figure PCTCN2018080380-appb-000079
时，令
Figure PCTCN2018080380-appb-000080
则
Figure PCTCN2018080380-appb-000081
当
Figure PCTCN2018080380-appb-000082
时，说明若采用C'作为分割后的比特序列的数量，可能会导致的较大的编码后块长增益损失，那么可以对C'进行向下调整，即C＝C'-Δ，Δ为偏置值，Δ为正整数，且通过Δ的设置，使得
Figure PCTCN2018080380-appb-000083
其中，K threshold1和K threshold2为预设的阈值，且
Figure PCTCN2018080380-appb-000084
例如Δ可以为1。如果找不到满足条件的Δ使得
Figure PCTCN2018080380-appb-000085
时，C＝C'。
例如，B＝5000，B 1＝0,R min,Kmax＝1/3，R min,K＝1/5，K max＝8000，N 1＝30000，L CB＝0，那么
Figure PCTCN2018080380-appb-000086
那么
Figure PCTCN2018080380-appb-000087
Figure PCTCN2018080380-appb-000088
定义K threshold1＝3600，K threshold2＝6000，令偏移值Δ＝1，
Figure PCTCN2018080380-appb-000089
满足3600＜5000＜6000，则最终C＝2-1＝1。
S603，将所述第一比特序列分割成C个分割后的比特序列。
其中，根据C对第一比特序列进行分割的方式也可以参考前述实施例的相关描述。
当码块分割后每个码块的编码前块长小于K threshold时，说明此时因码块分割导致的编码后块长增益损失很大，通过偏移值Δ对分块总数C进行修正后，减少分块总数后，可减少编码后块长增益损失，改善译码性能。偏移值Δ需要满足
Figure PCTCN2018080380-appb-000090
Figure PCTCN2018080380-appb-000091
以避免修正后分块的编码前块长大于编码器支持的最大编码快长度K max，或者编码后块长码率损失过多导致传输块译码性能下降。
需要说明的是，上述过程示例性的说明了在发送侧的实现的码块分割，对应的，在接收侧会采用相应的方法进行译码和级联，例如可以采用与发送侧相同的方法来确定在发送 侧分割后的比特序列的数量C，从而知道需要对C个码块进行译码和级联。也就是说，在接收侧的通信方法，在确定C后，根据C可以确定出编码前后的比特序列的大小并进行译码，译码完成后进行级联，得到译码后的传输块。上述的译码和级联可以通过一个通信装置实现，在接收侧实施。
本申请一实施例还提供一种通信装置700，用于实现上述在发送侧实施的通信方法，如图7所示，该通信装置可以包括：
获取单元701，用于获取待分割的第一比特序列。
其中，第一比特序列的比特数目为B,该第一比特序列对应的物理资源能够携带的比特的数目为N 1。
确定单元702，用于根据N 1和参数L确定将第一比特序列分割后的比特序列的数量C，其中，L的值和
Figure PCTCN2018080380-appb-000092
相等，
Figure PCTCN2018080380-appb-000093
为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数。
分割单元703，用于将第一比特序列分割成C个分割后的比特序列。
需要说明的是，上述获取单元701，确定单元702，分割单元703可以是独立的逻辑功能模块，也可以通过集成的功能单元实现，本申请实施例对此不做限定。进一步的，上述各个单元的具体功能和实现方式可以参考方法实施例的相关描述。
本申请又一实施例还提供一种通信装置800，用于实现上述在发送侧实施的通信方法，如图8所示，该通信装置中可以包括：存储器801和处理器802，在不同的应用中，存储器801和处理器802可能有不同的功能。
例如，存储器801，可以用于存储待分割的第一比特序列，该第一比特序列的比特数目为B,该第一比特序列对应的物理资源能够携带的比特的数目为N 1；处理器802可以用于根据N 1和参数L确定将该第一比特序列分割后的比特序列的数量C，其中，L的值和
Figure PCTCN2018080380-appb-000094
相等，
Figure PCTCN2018080380-appb-000095
为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数；以及，将第一比特序列分割成C个分割后的比特序列。
可以理解的是，当需要进行分割的第一比特序列输入时，可以存储到存储器801中，该存储器801，是实现存储功能的单元，例如可以是寄存器，也可以是随机读写存储器(RAM)，也可以是高速缓冲寄存器(Cache)，本申请实施例对此不做限定。
又例如，存储器801可以用于存储实现前述各个实施例中所描述的通信方法的指令；处理器802可以用于运行上述指令以实现前述各个实施例中所描述的通信方法，例如，获取待分割的第一比特序列，该第一比特序列的比特数目为B，以及，该第一比特序列对应的物理资源能够携带的比特的数目为N 1；根据N 1和参数L确定将该第一比特序列分割后的比特序列的数量C，其中，L的值和
Figure PCTCN2018080380-appb-000096
相等，
Figure PCTCN2018080380-appb-000097
为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数；将该第一比特序列分割成C个分割后的比特序列。
可以理解的是，上述各种情况下，存储器801和处理器802可以独立存在，也可以集成在一个芯片上实现，本申请实施例对存储器801和处理器802的存在形式不做限定。
进一步的，本申请实施例中处理器802的具体功能和实现可以参考方法实施例处的相关描述，此处不再赘述。可以理解的是，此处的处理器802也可以相应的实现上述实施例中确定单元702以及分割单元703的相应功能。
本申请实施例图7和8实施例所提供的通信装置，本申请实施例中，通过结合N1和L确定出分割的编码块的数量，尽可能的避免编码增益的损失，从而提供了一种合理的码块分割方案。
需要说明的是，上述图7和8实施例所提供的通信装置，除了附图所示的功能单元，还可能包括其他单元，本申请实施例对此不做限定，例如还可以包括实现收发功能的单元。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述软件功能部分可以存储在存储单元中。所述存储单元包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执 行本申请各个实施例所述方法的部分步骤。所述存储单元包括：一个或多个存储器，如只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)，电可擦写可编程只读存储器(EEPROM)，等等。所述存储单元可以独立存在，也可以和处理器集成在一起。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本领域普通技术人员可以理解：本文中涉及的第一、第二等各种数字编号仅为描述方便进行的区分，并不用来限制本申请实施例的范围。
本领域普通技术人员可以理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State DisB(SSD))等。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (21)

  1. 一种通信方法，包括：
    获取待分割的第一比特序列，所述第一比特序列的比特数目为B,所述第一比特序列对应的物理资源能够携带的比特的数目为N 1；
    根据N 1和参数L确定所述第一比特序列分割后的比特序列的数量C，其中，L的值和
    Figure PCTCN2018080380-appb-100001
    相等，
    Figure PCTCN2018080380-appb-100002
    为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数；
    将所述第一比特序列分割成C个分割后的比特序列。
  2. 根据权利要求1所述的方法，所述根据N 1和L确定C，包括：
    当L<N 1时，
    Figure PCTCN2018080380-appb-100003
    其中，
    Figure PCTCN2018080380-appb-100004
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100005
    的值相等。
  3. 根据权利要求1所述的方法，其特征在于，所述根据N 1和L确定C，包括：
    当L<N 1时，
    Figure PCTCN2018080380-appb-100006
    其中，
    Figure PCTCN2018080380-appb-100007
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100008
    的值相等；
    当
    Figure PCTCN2018080380-appb-100009
    时,C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
    Figure PCTCN2018080380-appb-100010
  4. 根据权利要求1所述的方法，其特征在于，所述根据N 1和L确定C，包括：
    当L<N 1时，
    Figure PCTCN2018080380-appb-100011
    其中，
    Figure PCTCN2018080380-appb-100012
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100013
    的值相等，N 1'＝min(N 1,(B+B 1)/R min)，R min为编码支持的最低码率。
  5. 根据权利要求1所述的方法，其特征在于，所述根据N 1和L确定C，包括：
    当L<N 1时，
    Figure PCTCN2018080380-appb-100014
    其中，
    Figure PCTCN2018080380-appb-100015
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100016
    的值相等，N 1'＝min(N 1,(B+B 1)/R min)，R min为编码支持的最低码率；
    当
    Figure PCTCN2018080380-appb-100017
    时,C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
    Figure PCTCN2018080380-appb-100018
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述根据N 1和L确定C，包括：
    当L≥N 1时，
    Figure PCTCN2018080380-appb-100019
    其中，
    Figure PCTCN2018080380-appb-100020
    表示向上取整，L CB是分割后 的比特序列的校验比特的比特数目。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，B＝K TB+L TB；其中,K TB为传输块长度,L TB为传输块的校验比特的比特数目L TB为大于或者等于0的整数。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，B 1＝0，L的值和
    Figure PCTCN2018080380-appb-100021
    相等。
  9. 根据权利要求1-7任一项的所述的方法，其特征在于，B 1的值与A个码块组的码块组校验比特数目之和相等，所述A为所述C个分割后的比特序列分组的数目。
  10. 根据权利要求9所述的方法，其特征在于，所述方法还包括：在所述A个码块组中的每个码块组中最后一个码块后添加码块组校验比特。
  11. 一种通信装置，其特征在于，包括：
    存储器，用于存储待分割的第一比特序列，所述第一比特序列的比特数目为B,所述第一比特序列对应的物理资源能够携带的比特的数目为N 1；
    处理器，根据N 1和参数L确定将所述第一比特序列分割后的比特序列的数量C，其中，L的值和
    Figure PCTCN2018080380-appb-100022
    相等，
    Figure PCTCN2018080380-appb-100023
    为可用的最大编码块长度K max对应的最小码率，B 1为大于或者等于0的整数，；以及，将所述第一比特序列分割成C个分割后的比特序列。
  12. 根据权利要求11所述的装置，其特征在于，所述处理器具体用于，
    当L<N 1时，确定
    Figure PCTCN2018080380-appb-100024
    其中，
    Figure PCTCN2018080380-appb-100025
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100026
    的值相等。
  13. 根据权利要求11所述的装置，其特征在于，所述处理器具体用于：
    当L<N 1时，确定
    Figure PCTCN2018080380-appb-100027
    其中，
    Figure PCTCN2018080380-appb-100028
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100029
    的值相等；
    当
    Figure PCTCN2018080380-appb-100030
    时,确定C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
    Figure PCTCN2018080380-appb-100031
  14. 根据权利要求11所述的装置，其特征在于，所述处理器具体用于：
    当L<N 1时，确定
    Figure PCTCN2018080380-appb-100032
    其中，
    Figure PCTCN2018080380-appb-100033
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100034
    的值相等，N 1'＝min(N 1,(B+B 1)/R min)，R min为编码支持的最低码率。
  15. 根据权利要求11所述的装置，其特征在于，所述处理器具体用于：
    当L<N 1时，确定
    Figure PCTCN2018080380-appb-100035
    其中，
    Figure PCTCN2018080380-appb-100036
    表示向上取整，N max的值和
    Figure PCTCN2018080380-appb-100037
    的值相等，N 1'＝min(N 1,(B+B 1)/R min)，R min为编码支持的最低码率；
    当
    Figure PCTCN2018080380-appb-100038
    时,确定C＝C tmp-Δ，,其中，N threshold为预设的阈值，Δ为偏置值，Δ为正整数，且Δ的取值使得
    Figure PCTCN2018080380-appb-100039
  16. 根据权利要求11-15任一项所述的装置，其特征在于，所述处理器具体用于：
    当L≥N 1时，确定
    Figure PCTCN2018080380-appb-100040
    其中，
    Figure PCTCN2018080380-appb-100041
    表示向上取整，L CB是分割后的比特序列的校验比特的比特数目。
  17. 根据权利要求11-16任一项所述的装置，其特征在于，B＝K TB+L TB；其中,K TB为传输块长度,L TB为传输块的校验比特的比特数目L TB为大于或者等于0的整数。
  18. 根据权利要求11-17任一项所述的装置，其特征在于，B 1＝0，L的值和
    Figure PCTCN2018080380-appb-100042
    相等。
  19. 根据权利要求11-17任一项的所述的装置，其特征在于，B 1的值与A个码块组的码块组校验比特数目之和相等，所述A为所述C个分割后的比特序列分组的数目。
  20. 根据权利要求19所述的装置，其特征在于，在所述A个码块组中的每个码块组中最后一个码块后添加码块组校验比特。
  21. 一种通信装置，其特征在于，包括：
    存储器，用于存储指令；
    处理器，用于执行所述存储器中的指令，实现如权利要求1-10任一项所述的通信方法。
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