WO2018201763A1 - 连接器的测试方法、装置及存储介质 - Google Patents

连接器的测试方法、装置及存储介质 Download PDF

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Publication number
WO2018201763A1
WO2018201763A1 PCT/CN2018/074275 CN2018074275W WO2018201763A1 WO 2018201763 A1 WO2018201763 A1 WO 2018201763A1 CN 2018074275 W CN2018074275 W CN 2018074275W WO 2018201763 A1 WO2018201763 A1 WO 2018201763A1
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Prior art keywords
connector
board
pin
test
test signal
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PCT/CN2018/074275
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English (en)
French (fr)
Inventor
耿晨曦
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中兴通讯股份有限公司
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Publication of WO2018201763A1 publication Critical patent/WO2018201763A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F11/00—Apparatus requiring external operation adapted at each repeated and identical operation to measure and separate a predetermined volume of fluid or fluent solid material from a supply or container, without regard to weight, and to deliver it
    • G01F11/10—Apparatus requiring external operation adapted at each repeated and identical operation to measure and separate a predetermined volume of fluid or fluent solid material from a supply or container, without regard to weight, and to deliver it with measuring chambers moved during operation
    • G01F11/12—Apparatus requiring external operation adapted at each repeated and identical operation to measure and separate a predetermined volume of fluid or fluent solid material from a supply or container, without regard to weight, and to deliver it with measuring chambers moved during operation of the valve type, i.e. the separating being effected by fluid-tight or powder-tight movements
    • G01F11/20—Apparatus requiring external operation adapted at each repeated and identical operation to measure and separate a predetermined volume of fluid or fluent solid material from a supply or container, without regard to weight, and to deliver it with measuring chambers moved during operation of the valve type, i.e. the separating being effected by fluid-tight or powder-tight movements wherein the measuring chamber rotates or oscillates
    • G01F11/22—Apparatus requiring external operation adapted at each repeated and identical operation to measure and separate a predetermined volume of fluid or fluent solid material from a supply or container, without regard to weight, and to deliver it with measuring chambers moved during operation of the valve type, i.e. the separating being effected by fluid-tight or powder-tight movements wherein the measuring chamber rotates or oscillates for liquid or semiliquid
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]

Definitions

  • Embodiments of the present invention relate to the field of testing technologies, and in particular, to a connector testing method, apparatus, and storage medium.
  • the backplane test methods in the related art need to develop a special test system, and the cost is very high; and the test scheme in the related art directly tests the backplane connector, and tests During the process, the connector cannot be used at the same time as the product. For the case where the backplane connector is damaged during use, or when the backplane is mounted on the product frame, it can only be checked by manual visual inspection. Whether the pins on the back panel are damaged.
  • embodiments of the present invention are directed to providing a test method, apparatus, and storage medium for a connector, so as to at least solve the related problem in the related art that a test solution for a backplane connector is costly and cannot be applied to a connector in a product being used.
  • Technical issues of testing are provided.
  • a method for testing a connector includes: obtaining a first test signal sent by a first board corresponding to a test command; and acquiring a second board received by the second board a test signal, wherein the connector is connected between the first board and the second board; comparing the first test signal with the second test signal; and determining whether the pin on the connector is faulty according to the comparison result.
  • the method before acquiring the test signal corresponding to the test command sent by the first board, the method further includes: generating a test command; and sending the test command to the first board, where the first board is pre-stored with At least one test signal corresponding to the test instruction.
  • the test instruction includes at least one of the following: a first fault test command for detecting a low level fault caused by the connection between the pin of the connector and the ground pin; and a second fault test command for detecting the connector The high level fault caused by the connection of the pin to the power pin; the third fault test command is used to detect a short circuit fault caused by the connection of the pin of the connector to the adjacent pin.
  • the first test signal and the second test signal are a sequence consisting of 1 and 0, wherein the level of the pin corresponding to the 1 code is a high level, and the level of the pin corresponding to the 0 code is low. Level.
  • the first test signal is an all-one sequence, wherein, according to the comparison result, determining whether the pin on the connector has a fault includes: if the second test signal All high level, it is determined that there is no low level fault on the pin on the connector; if at least one bit in the second test signal is low, it is determined that the pin on the connector has a low level fault, and The pin position corresponding to the low level on the connector is the pin position where there is a low level fault.
  • the first test signal is an all-zero sequence, wherein, according to the comparison result, determining whether the pin on the connector has a fault includes: if the second test signal To be all low, it is determined that there is no high level fault on the pin on the connector; if at least one of the second test signals is high, it is determined that there is a high level fault on the pin on the connector. Moreover, the pin position corresponding to the high level on the connector is the pin position where the high level fault exists.
  • the first test signal is a sequence occurring between 0 and 1 phase, wherein, according to the comparison result, the position of the faulty pin on the connector is determined, including : if three consecutive equal levels do not appear in the second test signal, it is determined that there is no short circuit fault on the pins on the connector; if three consecutive equal levels appear in the second test signal, then It is determined that at least two of the three pins corresponding to consecutive equal levels on the connector have a short circuit fault.
  • the method further includes: intermediate the first test signal with the three pins
  • the serial code corresponding to the pin is set to a high level or a low level, and the other bits are set to opposite levels; the second test signal received by the second main chip pin on the second board is detected; according to the detection result, Determine the pin on the connector that has a short-circuit fault.
  • determining a pin having a short circuit fault on the connector includes: if the levels of the first two pins of the three pins are the same, determining that the connector corresponds to the first two pins There is a short circuit fault between the two pins; if the levels of the last two pins of the three pins are the same, it is determined that there are short-circuit faults on the two pins corresponding to the first two pins on the connector; if three pins The average of the three pins in the middle is the same, then it is determined that there are short-circuit faults on all three pins on the connector.
  • the pin on one side of the connector is connected to the pin of at least one first main chip in the first single board, the pin on the other side of the connector and the tube of at least one second main chip in the second single board. Connected to the foot; wherein, the first test signal is sent to the pin of the first main chip through the Jtag interface of the first main chip; the second received by the pin of the second main chip is read by the Jtag interface of the second main chip Test signal.
  • a test apparatus for a connector includes: a first acquisition module configured to acquire a first test signal corresponding to a test command sent by a first board; and a second acquisition module, The second test board is configured to obtain a second test signal received by the second board.
  • the connector is connected between the first board and the second board.
  • the comparison module is configured to compare the first test signal with the second test.
  • a determining module configured to compare the test signal sent by the first board with the test signal received by the second board.
  • the device further includes: a generating module configured to generate a test command, and a sending module configured to send the test command to the first board, wherein at least one type corresponding to the test command is pre-stored in the first board Test signal.
  • an electronic device includes: a control board configured to generate a test command; a first board connected to the control board, configured to send a first test signal corresponding to the test command; a second board, connected to the first board through a connector, configured to receive a second test signal received through the connector; wherein the control board is configured to compare the first test signal with the second test signal, and according to the comparison result , determine if there is a fault in the pins on the connector.
  • a storage medium includes a stored program, and the program code that executes the following steps when the program is running: acquiring a first test signal corresponding to the test command sent by the first board; and acquiring a second test signal received by the second board through the connector
  • the connector is connected between the first board and the second board; compares the first test signal with the second test signal; and according to the comparison result, determines whether there is a fault in the pin on the connector.
  • a processor is also provided.
  • the processor is configured to run a program, and when the program is running, execute the following program code: obtain a first test signal corresponding to the test command sent by the first board, and obtain a second test signal received by the second board through the connector,
  • the connector is connected between the first board and the second board; compares the first test signal with the second test signal; and according to the comparison result, determines whether there is a fault in the pin on the connector.
  • the test signal (ie, the first test signal) is sent to the pin on the side of the connector connected to the first board through the first board.
  • the first test signal is transmitted to the second board connected to the other side of the connector through the pin of the connector, and the second board receives the test signal (ie, the second test signal) through the connector, and finally passes the comparison.
  • the test signal sent by the first board and the second test signal received by the second board through the connector achieve the need to develop a test interface card, but the service connected to the connector on the basis of the existing product.
  • the board indirectly realizes the purpose of the connector test, thereby achieving the technical effect of reducing the cost of developing the test interface card, and performing the technical effect of the online test in the process of using the product, thereby solving the test of the backplane connector in the related art.
  • the solution is costly and cannot be applied to the technical issues of connector testing in the product being used.
  • FIG. 1 is a block diagram showing the hardware structure of a computer device for testing a connector according to an embodiment of the present invention
  • FIG. 2 is a flow chart of a method of testing a connector in accordance with an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a single board connection in the case of an optional backplane according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of a single board connection in the case of an optional backplane according to an embodiment of the invention.
  • FIG. 5 is a flow chart of a method of testing an optional connector in accordance with an embodiment of the present invention.
  • FIG. 6 is a flow chart of a method of testing an optional connector in accordance with an embodiment of the present invention.
  • FIG. 7 is a flow chart of a method of testing an optional connector in accordance with an embodiment of the present invention.
  • FIG. 8 is a flow chart of a method of testing an optional connector in accordance with an embodiment of the present invention.
  • FIG. 9 is a flow chart of a method of testing an optional connector in accordance with an embodiment of the present invention.
  • FIG. 10 is a flow chart of an alternative method of testing a connector in accordance with an embodiment of the present invention.
  • FIG. 11 is a flow chart of an optional fixed 0 level fault detection method according to an embodiment of the present invention.
  • FIG. 12 is a flow chart of an optional fixed 1-level fault detection method in accordance with an embodiment of the present invention.
  • FIG. 13 is a flow chart of an optional short circuit fault detection method according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of an electronic device according to an embodiment of the invention.
  • FIG. 15 is a schematic structural diagram of an optional single board according to an embodiment of the invention.
  • 16 is a schematic structural diagram of an optional Jtag test logic function according to an embodiment of the present invention.
  • 17 is a block diagram showing the structure of a test apparatus for a connector according to an embodiment of the present invention.
  • the connector for connecting the single board mainly has the following two problems: First, since the pin of the backplane connector is composed of a single fisheye-shaped fine needle, the connector During the processing, it is necessary to align one of the pins on the connector with one of the small holes on the back plate. If the pins (or pins) on the connector are not vertical, the pins of the connector cannot be placed in the vias. In the process of mechanical pressing, the pin is pressed, and the pin is connected to the surrounding ground pin, power pin or other signal pin.
  • the pin on the connector is shorted to the ground pin, it will appear as a continuous low level on the signal, which is commonly referred to as a fixed 0 fault; if the pin on the connector is shorted to the power pin Together, it appears as a continuous high level on the signal, commonly known as a fixed 1 fault.
  • the board of the backplane connector is pinched when the board is frequently inserted and removed (for example, the first board and the second board are often inserted and removed during the use of the switch). This situation is carefully observed with the naked eye, and the connector pins on the back panel can be found. Due to the large number of pins on the connector, the manual detection scheme is not suitable for automated mass inspection in the production process. As a result, the detection of the backplane connector is often difficult and the maintenance is very troublesome.
  • test methods of the backplane connectors are generally as follows: appearance inspection, flying probe detection, in-line inspection (IntuuitTest, ICT), functional testing, and gating testing.
  • This test scheme mainly opens the analog switch or relay through the gating module on the interface board.
  • the control unit is responsible for connecting the test instrument multimeter to the interface board, and by testing the signal on the backplane, the resistance of the backplane signal is tested.
  • the value is used to judge the quality of the backplane signal; the other is to test the backplane through the console, control unit and interface adapter.
  • This test scheme scans the backplane network through the interface adapter to obtain the network relationship data, and obtains the comparison test. Network relationship data and standard network relationship data get a problematic network.
  • the test method embodiment of the connector provided by the embodiment of the present application can be executed in a large communication device, an ultra high performance server, and an electronic device including a supercomputer, an industrial computer, a high-end storage device, or the like, which includes multiple components for data communication or the like.
  • the connector is used for vertical connection between the board and the backplane.
  • the connector is used for docking between the boards.
  • FIG. 1 is a block diagram showing the hardware structure of a computer device for testing a connector according to an embodiment of the present invention.
  • computer device 10 may include one or more (only one shown) processor 102 (processor 102 may include, but is not limited to, a Microcontroller Unit (MCU) or a programmable logic device ( A processing device such as a Field-Programmable Gate Array (FPGA), a memory 104 configured to store data, and a transfer device 106 configured as a communication function.
  • MCU Microcontroller Unit
  • FPGA Field-Programmable Gate Array
  • FIG. 1 is merely illustrative and does not limit the structure of the above electronic device.
  • computer device 10 may also include more or fewer components than those shown in FIG. 1, or have a different configuration than that shown in FIG.
  • the memory 104 can be configured as a software program and a module for storing application software, such as program instructions/modules corresponding to the test method of the connector in the embodiment of the present invention, and the processor 102 runs the software program and the module stored in the memory 104, thereby The above methods are implemented by performing various functional applications and data processing.
  • Memory 104 may include high speed random access memory, and may also include non-volatile memory such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory.
  • memory 104 may further include memory remotely located relative to processor 102, which may be connected to computer device 10 over a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • Transmission device 106 is configured to receive or transmit data via a network.
  • the network examples described above may include a wireless network provided by a communication provider of computer device 10.
  • the transmission device 106 includes a Network Interface Controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet.
  • the transmission device 106 can be a Radio Frequency (RF) module configured to communicate with the Internet wirelessly.
  • NIC Network Interface Controller
  • RF Radio Frequency
  • a test method for a connector running on the above computer device is provided, which can be applied to the test of the backplane connector of the electronic device having the backplane assembly, and the direct docking device connector without the backplane assembly
  • Related tests. 2 is a flow chart of a method for testing a connector according to an embodiment of the present invention. As shown in FIG. 2, the process includes the following steps:
  • Step S202 acquiring a first test signal corresponding to the test instruction sent by the first board
  • Step S204 obtaining a second test signal received by the second board through the connector, wherein the connector is connected between the first board and the second board;
  • Step S206 comparing the first test signal with the second test signal
  • Step S208 according to the comparison result, determining whether there is a fault in the pin on the connector.
  • the first board and the second board may be service boards connected by connectors in the electronic device, and the first board and the second board may be directly connected through the connector, or may be connected through the connector.
  • FIG. 3 is a schematic diagram of a single board connection in the case of an optional backplane according to an embodiment of the present invention.
  • FIG. 4 is an optional diagram according to an embodiment of the present invention.
  • the test signal ie, the first test signal
  • the connector including the backboard and the The second board receiving the test signal (ie, the second test signal) can be determined by comparing the second board to the second test signal and the first test signal sent by the first board. Whether the connector connected between the first board and the second board is faulty.
  • the first board and the second board connected by the same connector may be configured to detect whether a pin (ie, a pin) connected to the connector between the two is faulty, For example, if the pin on the connector is shorted to the ground pin due to the pin, a fixed low level fault (or a fixed “0” level fault, that is, the pin shorted to the ground pin is continuously low.
  • a pin ie, a pin
  • FIG. 3 is a schematic diagram of a single board connection in the case of an optional backplane according to an embodiment of the present invention
  • FIG. 4 is an optional backless board according to an embodiment of the present invention.
  • the first board and the second board have at least one main chip, wherein each main chip has a Jtag interface, and the Jtag interface has 4 lines.
  • TCK, TMS, TDI, and TDO where TCK is the clock signal;
  • TMS is the state control signal of the Jtag module, which controls the state of the chip Jtag module;
  • TDI is the data input signal;
  • TDO is the data output signal.
  • the pin on one side of the connector may be connected to the pin of the at least one first main chip in the first board, and the pin on the other side of the connector and the second board The pins of the at least one second main chip are connected; wherein the first test signal is sent to the pin of the first main chip through the Jtag interface of the first main chip; the Jtag interface of the second main chip can be read The second test signal received by the pins of the two main chips.
  • test signal is a sequence consisting of 0 and 1, wherein the pin level corresponding to 0 is a low level, and the corresponding pin level is a high level
  • the first test signal sent by a single board can be used to characterize the level state of the pin on one side of the connector, and the second test signal received by the second board through the connector can be used to characterize the other side of the connector.
  • Level status if the test signal is a sequence consisting of 0 and 1, wherein the pin level corresponding to 0 is a low level, and the corresponding pin level is a high level
  • the test signal (ie, the first test signal) is sent to the pin on the side of the connector that is connected to the first board through the first board, and is connected through
  • the pin of the device transmits the first test signal to the second board connected to the other side of the connector, and the second board receives the test signal (ie, the second test signal) through the connector, and finally passes the comparison first.
  • the first test signal sent by the board and the second test signal received by the second board through the connector can determine whether the connector connected between the first board and the second board is faulty.
  • Embodiment 1 of the present application it is achieved that the test interface card is not required to be developed, but the purpose of the connector test is indirectly realized by the service board connected to the connector on the basis of the existing product, thereby achieving the reduction.
  • the method may further include the following steps:
  • Step S502 generating a test instruction
  • Step S504 the test command is sent to the first board, where at least one test signal corresponding to the test command is pre-stored in the first board.
  • the test command includes at least one of the following: a first fault test command for detecting a low level fault caused by a connection between a pin of the connector and the ground pin; and a second fault test command for A high-level fault caused by the connection between the pin of the connector and the power pin is detected; a third fault test command is used to detect a short-circuit fault caused by the connection of the pin of the connector to the adjacent pin.
  • Each test command can be used to test different fault types.
  • the test signal corresponding to each test command can be one or more types, which are pre-stored in the first board, and the first board receives the test. After the instruction, the corresponding test signal can be obtained for testing.
  • the test signal corresponding to the first fault test command may be an all-one sequence; the test signal corresponding to the second fault test command It may be an all-zero sequence; the test signal corresponding to the third fault test command may be a sequence occurring between 0 and 1 phases, wherein the level of the pin corresponding to the 1 code is a high level, and the pin corresponding to the 0 code The level is low.
  • the test signal corresponding to the first fault test command may be “11111111”
  • the test signal corresponding to the second fault test command may be “00000000”, corresponding to the third fault test command.
  • the test signal can be "10101010" or "01010101".
  • the first test signal is an all-one sequence, as shown in FIG. 6, step S208, according to comparison.
  • determining whether the pin on the connector is faulty may include the following steps:
  • Step S602 if the second test signal is all high level, it is determined that the pin on the connector does not have a low level fault
  • Step S604 if at least one of the second test signals is at a low level, it is determined that the pin on the connector has a low level fault, and the pin position corresponding to the low level on the connector is a low level. Faulty pin location.
  • steps S602 and S604 are interchangeable, that is, step S604 can be performed first and then step S602 can be performed.
  • the second test signal is a test signal received by the second board through the connector after the first test signal of the first board is sent by the first board (ie, the second board and the connector)
  • the pin level of at least one main chip connected may be a fault caused by the connection of the connector pin to the ground pin, that is, a fixed "0" level fault. Since the first test signal sent by the first board can be used to characterize the level state of the pin on one side of the connector, the second test signal received by the second board through the connector can be used to characterize the other side of the connector.
  • the level state of the pin therefore, if the second test signal is all high level (ie, all 1 sequence), it indicates that the level of the pins on both sides of the connector is the same, and it can be determined that the pins on the connector are not There is a fixed low level fault; if the second test signal is not all high level (ie, at least one bit in the sequence is 0 code), it indicates that the level of the pins on both sides of the connector is inconsistent, due to the first transmission
  • the test signal is in one sequence, the pin on the side of the connector that is connected to the first board is high, and the second test signal indicates that the pin on the side of the connector that is connected to the second board If there is a low level pin, it means that the pin is shorted to the ground pin and a fixed low level fault occurs.
  • the board 1 and the board 2 connected through the backplane connector shown in FIG. 3 or 4 are taken as an example, and the method for detecting a fixed “0” level fault is if the connector tube When the foot has a needle, when it is crimped, the pin is overlapped with the surrounding ground pin, which is low level, that is, the fixed 0 level fault. If a pin is shorted to ground, the signal received by the opposite end of the connector must have a signal low level, and the phase and the position where the low level is detected can be detected. As shown in FIG. 3 or 4, the board 1 test logic module sends 8 consecutive high levels, that is, 8 1 signals, to the backplane connector through the Jtag command of the Jtag interface.
  • the transmitted signal (ie, the first test signal) is represented as 8'b11111111
  • the Jtag test logic on the board 2 indirectly receives 8 signals through the Jtag interface of the chip, assuming that the fourth bit is received in the middle.
  • the corresponding pin has a short circuit to ground, the corresponding bit must be low, which means 0.
  • the first test signal is an all-zero sequence, as shown in FIG. 7, step S208, according to comparison.
  • determining whether the pin on the connector is faulty may include the following steps:
  • Step S702 if the second test signal is all low level, it is determined that the pin on the connector does not have a high level fault
  • Step S704 if at least one of the second test signals is at a high level, it is determined that the pin on the connector has a high level fault, and the pin position corresponding to the high level on the connector is a high level. Faulty pin location.
  • steps S702 and S704 are interchangeable, that is, the above step S704 may be performed before step S702.
  • the second test signal is a test signal received by the second board through the connector after the first test signal of the all-zero sequence is sent by the first board (ie, the second board and the connector)
  • the level state of the pin therefore, if the second test signal is all low level (ie, all 0 sequence), it indicates that the level of the pins on both sides of the connector is consistent, and it can be determined that the pins on the connector are not There is a fixed high level fault; if the second test signal is not all low level (that is, at least one bit in the sequence is 1 code), it indicates that the level of the pins on both sides of the connector is inconsistent, due to the first transmission
  • the test signal is in the 0 sequence, the pin on the side of the connector that is connected to the first board is low, and the second test signal indicates the pin on the side of the connector that is connected to the second board.
  • the presence of a high-level pin indicates that the pin is shorted to the power pin and a fixed high-level fault has occurred.
  • the board 1 and the board 2 connected through the backplane connector shown in FIG. 3 or 4 are still taken as an example, and the connector tube is fixed for the detection method of the “1” level fault.
  • the connector tube is fixed for the detection method of the “1” level fault.
  • this pin In the case of a pin on the foot, when crimped, this pin is lapped with the surrounding power pin and appears to be high, that is, the fixed 1-level fault. If one of the pins is shorted to the power supply, the signal received by the opposite end must have a high level. By inputting or outputting the signal or operating, the data position of the high level is detected, and the tube in question can be determined. The position of the foot. As shown in FIG.
  • the board 1 test logic module sends 8 consecutive low levels, that is, 8 0 signals, to the backplane connector through the Jtag command of the Jtag interface. That is, the transmitted signal (ie, the first test signal) is represented as 8'b00000000.
  • the Jtag test logic on the board 2 indirectly receives 8 signals through the Jtag interface of the chip, assuming that the fourth bit is received in the middle.
  • the received signal ie, the second test signal
  • the corresponding bit must be low, which means 1 is.
  • the first test signal is a sequence of 0 and 1 phase occurrences, as shown in FIG. S208. Determine, according to the comparison result, whether a pin on the connector is faulty, and the method includes the following steps:
  • Step S802 if three consecutive equal levels do not appear in the second test signal, it is determined that there is no short circuit fault on the pin on the connector;
  • Step S804 if three consecutive equal levels appear in the second test signal, it is determined that at least two of the three pins corresponding to the consecutive equal levels on the connector have a short circuit fault.
  • steps S802 and S804 are interchangeable, that is, the above step S804 may be performed before step S802.
  • the second test signal is a test signal received by the second board through the connector after the first board sends the first test signal of the sequence between 0 and 1 (ie, the second board)
  • the pin level of at least one main chip connected to the connector); the short circuit fault described above may be a fault caused by the connection of the connector pin to another adjacent signal pin. Since the first test signal sent by the first board can be used to characterize the level state of the pin on one side of the connector, the second test signal received by the second board through the connector can be used to characterize the other side of the connector. The level state of the pin.
  • the second test signal does not have three consecutive equal levels, it indicates that the level of the pins on both sides of the connector is the same, and it can be determined that the pin on the connector does not have a fixed height.
  • Level failure if three consecutive equal levels appear in the second test signal (ie, there are three consecutive 1 or three 0 codes in the sequence), it indicates that the levels of the pins on both sides of the connector are inconsistent. Due to the sequence of the first test signal transmitted between 0 and 1, the pin on the side of the connector connected to the first board should be in a high and low level, and the second test signal indicates the connection.
  • the single board 1 and the single board 2 connected through the backplane connector shown in FIG. 3 and FIG. 4 are taken as an example, and the short circuit of the adjacent pins is short-circuited for detecting the short circuit of the adjacent pins. It means that the signals received by two adjacent pins are 00 or 11 at the same time. Since the pins of the connector are compressed, two signal pins are connected together.
  • the transmission interval of the transmission signal is 1010, that is, two adjacent bits are signals of different levels, and if the receiving end detects the same signal of the adjacent bits, a short circuit of the adjacent pins occurs.
  • Short circuit fault detection is performed after eliminating a fixed level fault. The detection process is as follows. Take the 8-bit test signal as an example.
  • the signal sent by the board 1 (that is, the first test signal) is 8'b01010101. 2
  • the middle 4, 5, 6 bits are 000 to indicate the 4th, 5th or 5th, 6th and 2nd short circuit.
  • the connector is determined and continuous. After at least two of the three pins corresponding to the equal level have a short circuit fault, the above method may further include the following steps:
  • Step S902 setting a sequence code corresponding to the middle pin of the three pins in the first test signal to a high level or a low level, and setting other bits to opposite levels;
  • Step S904 detecting a second test signal received by the second main chip pin on the second board;
  • Step S906 determining, according to the detection result, a pin having a short circuit fault on the connector.
  • the first test signal and the middle tube of the three pins may be The sequence code corresponding to the foot is set to a high level (ie, 1 code) or a low level (ie, 0 code), and is resent to the second board connected to the other side of the connector, and received according to the second board.
  • the result of comparing the second test signal with the first test signal determines a pin having a short circuit fault on the connector.
  • determining a pin having a short circuit fault on the connector may include the following steps:
  • Step S9061 if the levels of the first two pins of the three pins are the same, it is determined that there is a short circuit fault between the two pins corresponding to the first two pins on the connector;
  • Step S9063 if the levels of the last two pins of the three pins are the same, it is determined that there is a short circuit fault between the two pins corresponding to the first two pins on the connector;
  • step S9065 if the electric average of the three pins of the three pins is the same, it is determined that there is a short circuit fault in the three pins on the connector.
  • steps S9061, S9063, and S9065 is interchangeable, that is, any one of the above steps may be performed first.
  • the signal sent by the board 1 is 8'b01010101
  • the board 2 receives After the signal (that is, the second test signal) is 8'01000101, since the middle 4, 5, and 6 bits are 000, the 4th, 5th, or 5th, 6th, and 2nd bits are short-circuited, and then, the board 1 is sent 8 'b11101111, that is, the bit that may be short-circuited in the middle, that is, the fifth bit is sent low level, and the others are high level, then the signal received by the board 2 side must be 8'b11100111, and 4, 5 can be detected by this method.
  • the two pins are shorted. Short circuits in other locations can be detected in the same way.
  • execution body of each step described above may be a control board or the like in an electronic device, but is not limited thereto.
  • FIG. 11 is an embodiment according to the present invention.
  • FIG. 12 is a flowchart of a fixed 1-level fault detection method according to an embodiment of the present invention
  • FIG. 13 is a flow chart of a short-circuit fault detection method according to an embodiment of the present invention.
  • Table 1 the detection patterns used for different types of failures are shown in Table 1.
  • the fixed 0 level is a frequent failure phenomenon in the process of crimping the backplane connector, mainly due to the fact that when the crimping is performed, individual pins are not aligned with the crimping vias on the backing plate pcb, causing the needle to be crushed. Therefore, it is short-circuited with the surrounding ground, causing the pin to be pulled low after power-on, forming a fixed 0-level fault.
  • the fixed 0 level detection step is as shown in FIG. 11.
  • the control board 1 first sends a Jtag 0 level detection command to the single board 1, and the control unit of the single board 1 controls the Jtag module in the EPLD through the local bus, Jtag.
  • the module outputs a high level 1 state to all pins of the main chip through the Jtag interface connected to the main chip.
  • the main chip status is transmitted to the corresponding backplane connector of the board 2 through the backplane high speed connector.
  • the control board sends an instruction to the board 2 through the communication link, and the control unit of the board 2 samples the state of the related pin of the main chip backplane connector through the Jtag.
  • the control board reads the detection status of the board 2 through the communication link. If the connector is normal, the corresponding state should be a high level "1". If it is 0, the pin has a fixed 0 level fault. .
  • Fixed 1 level means the pin is pulled high 1
  • the fixed 1-level detection step is as shown in FIG. 12.
  • the control board first sends a Jtag 1 level detection command to the single board 1.
  • the single board 1 control unit controls the Jtag module in the EPLD through the local bus, and the Jtag module. All the pins of the main chip are outputted to a high level 0 state through the Jtag interface connected to the main chip.
  • the main chip status is transmitted to the corresponding backplane connector of the board 2 through the backplane high speed connector.
  • the control board sends an instruction to the board 2 through the communication link, and the control unit of the board 2 samples the state of the related pin of the main chip backplane connector through the Jtag.
  • the control board reads the detection status of the board 2 through the communication link. If the connector is normal, the corresponding state should be a high level “0”. If it is 1, the pin has a fixed 1 level fault. .
  • the two pins are short-circuited.
  • the backplane connector often has an inverted pin, which leads to two adjacent pins. The state will change at the same time, either high 11 or low 00 at the same time
  • the pin short detection step is as shown in FIG. 13.
  • the control board first sends a pin short detection command to the single board 1.
  • the single board 1 control unit controls the Jtag module in the EPLD through the local bus, and the Jtag module passes
  • the Jtag interface connected to the main chip causes all the pins of the main chip to output a high level of 10101010.
  • the main chip status is transmitted to the corresponding backplane connector of the board 2 through the backplane high speed connector.
  • the control board sends an instruction to the board 2 through the communication link, and the control unit of the board 2 samples the state of the related pin of the main chip backplane connector through Jtag.
  • the control board reads the detection state of the board 2 through the communication link.
  • the corresponding state should be a high level "10101010", if there are three consecutive 11 or three consecutive 00 In the state, there is a short circuit fault in two of the corresponding three corresponding pins.
  • the control board sends a detection command to the board 1 and the board 2, and the three consecutive equal levels in the detection pattern sent by the board 1 are 1 in the middle or 0 or in the middle. 0 is all 1.
  • the main control board reads the detected state through the single board 2, thereby confirming that the two pins are short-circuited.
  • test method of the connector disclosed in this embodiment has fundamental differences from the existing connector test method in the concept of logic implementation and test structure.
  • first of all there are differences in the concept of the test structure.
  • the previous test system needs to develop a specific test board and test mold, etc.
  • the present invention only needs to embed the Jtag-related test signal and the Jtag test logic module into the current product.
  • Backplane testing does not require the development of a specific test system.
  • the test module of the present invention sends the test signal to the pin of the main chip of the product through the 4 lines of the Jtag interface, and the test signal is connected to the tube connected to the backplane connector by the main chip.
  • the foot is passed over the backplane connector, and the test logic on the board 2 on the other side of the backplane receives the test signal through the Jtag interface.
  • the previous method was to send test data directly through the control unit and interface adapter.
  • the test system is directly connected to the backplane pins, and the present invention is an indirect implementation test.
  • the previous invention either uses the interface card to test the resistance on the backplane or test the backplane connection relationship network through the interface adapter card, and tests the backplane through the comparison network.
  • the present invention uses the Jtag interface to directly transmit different The pattern directly tests for faults in the backplane.
  • the test logic is disconnected from the Jtag interface of the board, and does not affect the normal function of the product.
  • the test logic is tested through the Jtag interface to implement online testing of the backplane connector.
  • the present invention differs from the prior art concept in the concept of backplane testing. One is direct testing and one is embedded into the product for indirect testing. There are also differences in the test logic. One requires the interface adapter to directly send the test signal test, and the other is to indirectly realize the test signal transmission and reception through the Jtag interface of the chip in the product.
  • test method of the connector does not need to develop a special test interface card, but uses the Jtag interface of the service board chip and the logic chip on the board to implement the backplane connector.
  • the test can be compatible with the existing single-board structure. It is only necessary to add the Jtag test module to the logic of the single board to implement online testing of the backplane.
  • the invention embeds the test module into the current product, all the products can be used, and it is not necessary to develop a special test system, thereby achieving a substantial reduction of the test cost.
  • the Jtag test method in the present invention can be applied to the backplane related tests in all products, as long as other technicians use this method to test the backplane, which may trigger the present invention.
  • the invention is applicable to the test that all the boards in the product are connected to each other.
  • the boards of different slots in the product may be connected through the backplane, or may be connected by a direct connection without the backplane, and the present invention is applicable.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
  • FIG. 14 is a schematic diagram of an electronic device according to an embodiment of the invention. As shown in FIG. 14, the electronic device includes a control board 141, a first board 143, and a second board 145.
  • the control board 141 is configured to generate a test command.
  • the first board 143 is connected to the control board and configured to send a first test signal corresponding to the test command.
  • the second board 145 is connected to the first board through a connector, and configured to receive the second test signal received through the connector;
  • the control board is configured to compare the first test signal with the second test signal, and according to the comparison result, determine whether there is a fault in the pin on the connector.
  • connection structure of the first board and the second board in the above electronic device may include the case of the back board in FIG. 3 and the case of the back board in FIG. 4, and the control board is a control unit of the entire electronic device product.
  • the first board, the second board, and the control board communicate through a communication link.
  • a test command for testing a connector failure is generated by the control board 141, and sent to the first board 143 and the second board 145, where the first single
  • the board 143 obtains a test signal corresponding to the test command, and sends the test signal (ie, the first test signal) to the connector, and transmits the first test signal to the connector through the connector.
  • the second board 145 receives the test signal (ie, the second test signal) through the connector, and finally the control board 141 compares the test signal sent by the first board 143 with the second board 145 through the connector.
  • the received second test signal can determine whether there is a fault in the connector connected between the first board 143 and the second board 145.
  • test interface card is not required to be developed, but the purpose of the connector test is indirectly realized through the service board connected to the connector on the basis of the existing product, thereby reducing the development.
  • the first board may include: a first main chip and a first logic chip configured to test a pin of the first main chip, where the first main chip has a first Jtag interface, and The first logic chip communicates through the first Jtag interface;
  • the second board may include: a second main chip and a second logic chip configured to test a pin level of the second main chip, where the second main chip There is a second Jtag interface, and the second logic chip communicates through the second Jtag interface.
  • the first main chip may be a main chip in a first single board connected to one side of the backplane connector
  • the second main chip may be a second single connected to a side of the backplane connector.
  • the main chip in the board, the first main chip and the second main chip both have a Jtag interface, wherein the first Jtag interface is an interface between the first main chip and the first logic chip, and the second Jtag interface is a second main chip and The interface of the second logic chip communication.
  • the signal lines of the four Jtag interfaces of the main chip connected to the backplane connector in the single board on both sides of the backplane are connected to the logic chip of the single board.
  • connection structure of the first main chip and the first logic chip, and the connection structure of the two main chips and the second logic chip may be the connection structure shown in FIG. 3 or 4.
  • the pin on one side of the connector is connected to the pin of at least one first main chip in the first single board, the pin on the other side of the connector and at least one second main chip in the second single board.
  • the pins are connected.
  • the first board may further include: a first control unit configured to control the first logic chip by using a local bus; the second board further includes: a second control unit configured to pass the local bus Control the second logic chip.
  • the first control unit in the first board on the side of the backplane connector sends the required test data (ie, the first test signal) to the backplane connector through the Jtag interface.
  • the second board on the other side of the backplane connector receives the test data (ie, the level state corresponding to the first test signal transmitted through the backplane connector).
  • the second control unit of the second board controls the second logic chip to read the level state of the second main chip pin through the local bus to obtain a second test signal, thereby implementing the test of the backplane connector.
  • connection structure of the first control unit and the first control unit in the first board and the second board may be a connection structure as shown in FIG. 3 or 4.
  • FIG. 15 is a schematic structural view of a single board according to an embodiment of the present invention, which may be used as the structure of the first single board or the second single board, as shown in FIG.
  • a single board and a second board may include a control unit and a single board EPLD logic chip, and at least one master chip, wherein the master chip is primarily responsible for data communication.
  • the single-board EPLD logic chip includes a logic program for performing Jtag test, as shown in the “Jtag test” bold box in FIG. 15, and the Jtag interface of the main chip is connected to the EPLD logic chip through serial or parallel manner. The Jtag logic is thus tested by Jtag logic.
  • the Jtag test logic function structure is as shown in Figure 16:
  • the local bus interface part is responsible for communicating with the control unit above the board.
  • the Jtag interface part is responsible for communicating with the Jtag interface of the main chip on the board.
  • the data store is primarily responsible for storing test signals received from the control unit.
  • the instruction store primarily stores test instructions received from the control unit.
  • the control unit part is mainly responsible for transmitting relevant test commands to the Jtag interface according to the test instruction, and transmitting the test signal to the chip through the Jtag interface, thereby being transmitted to the connector pins of the backplane.
  • the connector between the first board and the second board can be detected as follows:
  • the control board control unit sends the test command and test data of "fixed 0 level fault" to the logic chip through the communication interface and the control unit of the board 1 and the local bus interface.
  • the logic logic sends the test signal to be sent to the main chip of the board according to the test instruction, and then sends it to the backplane connector.
  • the control panel control unit reads the test signal through the Jtag test logic on the second board. The pin position of the fixed 0 level fault on the backplane connector is determined by comparison.
  • the control board control unit sends the test command and test data of "fixed 1 level fault" to the logic through the communication interface, the control unit of the line forwarding function board and the local bus interface.
  • the logic signal is sent to the main chip of the board according to the test instruction according to the test instruction, and then sent to the backplane connector.
  • the control panel control unit reads the test signal through the Jtag test logic on the second board. The position of the pin with a fixed 1-level fault on the backplane connector is determined by comparison.
  • the short-circuit fault detection the control panel control unit through the communication interface, the line forwarding function board control unit and the local bus interface, the "short-circuit fault" test command and test data is sent to the logic chip in the test instructions and data storage
  • the logic logic sends the test signal to be sent to the main chip of the board according to the test instruction, and then sends the test signal to the backplane connector.
  • the control panel control unit reads the test signal through the Jtag test logic on the second board. The position of the pin with a short circuit fault on the backplane connector is determined by comparison.
  • the Jtag interfaces of the main chip on the first board and the second board are connected to the logic chip of the board, and the control unit of the first board controls the logic chip through the local bus.
  • the Jtag test module inputs the test code stream to the main chip of the single board
  • the control unit of the second board controls the Jtag module of the logic of the local bus to detect the input code stream of the Jtag interface of the main chip.
  • the control board controls the control units of the first board and the second board respectively through the communication link 1 and the communication link 2, and detects the backplane by comparing the test code streams of the input and output. Whether the above fault condition occurs in the pin of the upper high speed connector. It realizes the problem of detecting the "fixed 0 level”, "fixed 1 level” and "adjacent pin short circuit" on the backplane connector pins, and satisfies the detection of the connector during the use of the backplane.
  • the foregoing embodiments of the present application have at least the following advantages: 1.
  • the cost of the first board and the second board are not increased, as long as the Jtag interface of the main chip is introduced into the logic of the board, as long as the corresponding Jtag logic module and add corresponding software algorithms.
  • Second, the board can be detected online, providing powerful measures for quickly locating the corresponding problem of the backboard crc.
  • the embodiment further provides a test device for a connector, which is configured to implement the test method of the connector described above, and has not been described again.
  • the term “module” may implement a combination of software and/or hardware of a predetermined function.
  • FIG. 17 is a structural block diagram of a test apparatus for a connector according to an embodiment of the present invention. As shown in FIG. 17, the apparatus includes: a first acquisition module 171, a second acquisition module 173, a comparison module 175, and a determination module 177.
  • the first obtaining module 171 is configured to acquire a first test signal corresponding to the test command sent by the first board;
  • the second obtaining module 173 is configured to obtain a second test signal received by the second board through the connector, wherein the connector is connected between the first board and the second board;
  • the comparing module 175 is configured to compare the first test signal with the second test signal
  • the determining module 177 is configured to compare the test signal sent by the first board with the test signal received by the second board.
  • first obtaining module 171, the second obtaining module 173, the comparing module 175, and the determining module 177 correspond to steps S202 to S208 in the embodiment 1, and the modules and examples implemented by the corresponding steps are
  • the application scenario is the same, but is not limited to the content disclosed in the above embodiment 1.
  • the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • the first acquisition module 171 acquires a test signal (ie, a first test signal) corresponding to the test instruction sent by the first board, where the first test signal is Sending to the pin on the side of the connector that is connected to the first board, the pin of the connector transmits the first test signal to the second board connected to the other side of the connector, and passes through the second acquisition module.
  • the 173 obtains the test signal (ie, the second test signal) received by the second board through the connector, and finally compares the first test signal sent by the first board with the second board through the connector through the comparison module 175.
  • the second test signal determines whether the connector connected between the first board and the second board is faulty.
  • test interface card is not required to be developed, but the purpose of the connector test is indirectly realized by the service board connected to the connector on the basis of the existing product, thereby achieving the reduction.
  • the device may further include: a generating module configured to generate a test command, and a sending module configured to send the test command to the first board, where the first board is pre-stored with a test command At least one test signal.
  • the foregoing generating module and the sending module correspond to the steps S502 to S504 in the foregoing embodiment, and the foregoing modules are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to the contents disclosed in the foregoing embodiments. . It should be noted that the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • the determining module 177 may include: a first determining unit configured to: if the second test signal is all high Level, it is determined that there is no low level fault on the pin on the connector; the second determining unit is configured to determine that the pin on the connector has low power if at least one of the second test signals is low level The fault is flat, and the pin position corresponding to the low level on the connector is the pin position where there is a low level fault.
  • first determining unit and second determining unit correspond to steps S602 to S604 in Embodiment 1, and the foregoing modules are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to the above embodiments. 1 published content. It should be noted that the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • the first test signal adopts an all-zero sequence
  • the determining module 177 may include: a third determining unit configured to: if the second test signal is all Low level, it is determined that there is no high level fault on the pin on the connector; the fourth determining unit is configured to determine that the pin on the connector is high if at least one of the second test signals is at a high level The level is faulty, and the pin position corresponding to the high level on the connector is the pin position where there is a high level of failure.
  • the foregoing third determining unit and fourth determining unit correspond to steps S702 to S704 in Embodiment 1, and the foregoing modules are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to the above embodiments.
  • the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • the first test signal adopts a sequence of 0 and 1 phase occurrences
  • the determining module 177 may include: a fifth determining unit configured to read if The second test signal does not have three consecutive equal levels, then it is determined that there is no short circuit fault on the pin on the connector; the sixth determining unit is configured to have three consecutive equal levels if the second test signal is read. Then, it is determined that at least two of the three pins corresponding to the consecutive equal levels on the connector have a short circuit fault.
  • the foregoing fifth determining unit and the sixth determining unit correspond to steps S802 to S804 in the embodiment, and the foregoing modules are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to the foregoing embodiments. Public content. It should be noted that the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • the sixth determining unit may include: a setting unit configured to sequence the first test signal corresponding to the middle pin of the three pins The code is set to a high level or a low level, and the other bits are set to opposite levels; the detecting unit is configured to detect a second test signal received by the second main chip pin on the second board; Configured to determine the presence of a short-circuit fault on the connector based on the test results.
  • the foregoing setting unit, the detecting unit, and the determining subunit correspond to steps S902 to S906 in the embodiment, and the foregoing modules are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to the above embodiments. Public content. It should be noted that the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • the determining subunit may include: a first sub-determining module configured to be the same if the first two pins of the three pins are at the same level, Then, it is determined that there are short-circuit faults on the two pins corresponding to the first two pins on the connector; the second sub-determination module is configured to determine the connector if the levels of the last two pins of the three pins are the same There is a short circuit fault between the two pins corresponding to the first two pins; the third sub-determination module is configured to determine that the three pins on the connector are the same if the average of the three pins of the three pins is the same There is a short circuit fault.
  • the foregoing first sub-determination module, the second sub-determination module, and the third sub-determination module correspond to steps S9061 to S9065 in the embodiment, and the foregoing modules are the same as the examples and application scenarios implemented by the corresponding steps. However, it is not limited to the contents disclosed in the above embodiments. It should be noted that the above modules may be implemented as part of a device in a computer system such as a set of computer executable instructions.
  • Embodiments of the present invention also provide a storage medium.
  • the storage medium includes a stored program, and the program code of the steps of the method in the embodiment can be executed while the program is running.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), and a mobile hard disk.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • Embodiments of the present invention also provide a processor.
  • the processor is used to execute a program, and the program code of the steps of the method in the embodiment can be executed when the program is running.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the first test signal corresponding to the test command sent by the first board is obtained, and the second test signal received by the second board through the connector is obtained, where the connector is connected to the first Between the single board and the second board; comparing the first test signal with the second test signal; determining, according to the comparison result, whether there is a fault in the pin on the connector.
  • the problem that the test solution for the backplane connector in the related art is high and cannot be applied to the connector test in the product being used is solved, thereby achieving the need to develop a test interface card, but on the existing product basis.
  • the purpose of the connector test is indirectly implemented through the service board connected to the connector, thereby achieving the technical effect of reducing the cost of developing the test interface card.

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Abstract

本发明提供一种连接器的测试方法，其中，该方法包括：获取第一单板发送的与测试指令对应的第一测试信号；获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；比较第一测试信号与第二测试信号；根据比较结果，确定连接器上的管脚是否存在故障。通过本发明实施例，解决了相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的问题，进而达到了不需要开发测试接口卡，而是在现有的产品基础上，通过与连接器相连的业务单板间接实现连接器测试的目的，从而实现了减少开发测试接口卡的成本的技术效果。

Description

连接器的测试方法、装置及存储介质
相关申请的交叉引用
本申请基于申请号为201710313872.7、申请日为2017年05月05日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明实施例涉及测试技术领域，尤其涉及一种连接器的测试方法、装置及存储介质。
背景技术
在大型电子设备中，通常需要多组件进行数据的相互通信。多个槽位的板卡通过背板相互连接，进行数据通信。有的电子设备中无背板，可以通过直接对接的方式相互连接。无论是有背板和无背板，多个槽位的单板之间的连接器的测试一直是电子设备加工和调试中一个非常重要的问题。
由于不同的背板有不同的型号的连接器，相关技术中的背板测试方法都需要开发专门的测试系统，成本非常高；而且，相关技术中的测试方案直接对背板连接器测试，测试过程中，连接器不能和产品同时使用，对于背板在使用过程中造成的背板连接器的针脚损坏的情况，或者背板安装到产品机框上使用的情况，只能通过人工目检检查背板上的针脚是否有损坏。
发明内容
有鉴于此，本发明实施例期望提供一种连接器的测试方法、装置及存储介质，以至少解决相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的技术问题。
根据本发明的一个实施例，提供了一种连接器的测试方法，包括：获取第一单板发送的与测试指令对应的第一测试信号；获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；比较第一测试信号与第二测试信号；根据比较结果，确定连接器上的管脚是否存在故障。
上述方案中，在获取第一单板发送的与测试指令对应的测试信号之前，方法还包括：产生测试指令；将测试指令发送给第一单板，其中，第一单板内预先存储有与测试指令对应的至少一种测试信号。
上述方案中，测试指令至少包括如下任意一种：第一故障测试指令，用于检测连接器的管脚与地管脚连接引起的低电平故障；第二故障测试指令，用于检测连接器的管脚与电源管脚连接引起的高电平故障；第三故障测试指令，用于检测连接器的管脚与相邻管脚连接引起的短路故障。
上述方案中，第一测试信号和第二测试信号为由1和0组成的序列，其中，与1码对应的管脚的电平为高电平，与0码对应的管脚的电平低电平。
上述方案中，在测试指令为第一故障测试指令的情况下，第一测试信号为全1序列，其中，根据比较结果，确定连接器上的管脚是否存在故障，包括：如果第二测试信号全为高电平，则确定连接器上的管脚不存在低电平故障；如果第二测试信号中至少有一位为低电平，则确定连接器上的管脚存在低电平故障，并且，连接器上与低电平对应的管脚位置为存在低电平故障的管脚位置。
上述方案中，在测试指令为第二故障测试指令的情况下，第一测试信号为全0序列，其中，根据比较结果，确定连接器上的管脚是否存在故障，包括：如果第二测试信号为全为低电平，则确定连接器上的管脚不存在高电平故障；如果第二测试信号中至少有一位为高电平，则确定连接器上的 管脚存在高电平故障，并且，连接器上与高电平对应的管脚位置为存在高电平故障的管脚位置。
上述方案中，在测试指令为第三故障测试指令的情况下，第一测试信号为0和1相间出现的序列，其中，根据比对结果，确定连接器上出现故障的管脚的位置，包括：如果读取到第二测试信号没有出现三个连续相等的电平，则确定连接器上的管脚不存在短路故障；如果读取到第二测试信号出现三个连续相等的电平，则确定连接器上与连续相等的电平对应的三个管脚中至少有两个管脚存在短路故障。
上述方案中，在确定连接器上与连续相等的电平对应的三个管脚中至少有两个管脚存在短路故障之后，方法还包括：将第一测试信号中与三个管脚中中间管脚对应的序列码设置为高电平或低电平，其他位设置为相反的电平；检测第二单板上的第二主芯片管脚接收到的第二测试信号；根据检测结果，确定连接器上存在短路故障的管脚。
上述方案中，根据检测结果，确定连接器上存在短路故障的管脚，包括：如果三个管脚中前两个管脚的电平相同，则确定连接器上与前两个管脚对应的两个管脚存在短路故障；如果三个管脚中后两个管脚的电平相同，则确定连接器上与前两个管脚对应的两个管脚存在短路故障；如果三个管脚中的三个管脚的电平均相同，则确定连接器上三个管脚均存在短路故障。
上述方案中，连接器一侧的管脚与第一单板内至少一个第一主芯片的管脚相连，连接器另一侧的管脚与第二单板内至少一个第二主芯片的管脚相连；其中，通过第一主芯片的Jtag接口将第一测试信号发送至第一主芯片的管脚；通过第二主芯片的Jtag接口读取第二主芯片的管脚接收到的第二测试信号。
根据本发明的另一个实施例，提供了一种连接器的测试装置，包括：第一获取模块，配置为获取第一单板发送的与测试指令对应的第一测试信 号；第二获取模块，配置为获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；比较模块，配置为比较第一测试信号与第二测试信号；确定模块，配置为比较第一单板发送的测试信号与第二单板接收到的测试信号。
上述方案中，装置还包括：生成模块，配置为产生测试指令；发送模块，配置为将测试指令发送给第一单板，其中，第一单板内预先存储有与测试指令对应的至少一种测试信号。
根据本发明的另一个实施例，提供了一种电子设备，包括：控制板，配置为产生测试指令；第一单板，与控制板连接，配置为发送与测试指令对应的第一测试信号；第二单板，与第一单板通过连接器连接，配置为接收通过连接器接收到的第二测试信号；其中，控制板配置为比较第一测试信号与第二测试信号，并根据比较结果，确定连接器上的管脚是否存在故障。
根据本发明的又一个实施例，还提供了一种存储介质。该存储介质包括存储的程序，程序运行时执行以下步骤的程序代码：获取第一单板发送的与测试指令对应的第一测试信号；获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；比较第一测试信号与第二测试信号；根据比较结果，确定连接器上的管脚是否存在故障。
根据本发明的又一个实施例，还提供了一种处理器。处理器配置为运行程序，程序运行时执行以下步骤的程序代码：获取第一单板发送的与测试指令对应的第一测试信号；获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；比较第一测试信号与第二测试信号；根据比较结果，确定连接器上的管脚是否存在故障。
应用本发明实施例所提供的上述测试方法、装置及存储介质，通过第 一单板将测试信号(即第一测试信号)发送到连接器上与第一单板相连一侧的管脚上，通过连接器的管脚将第一测试信号传递到与连接器另一侧管脚相连的第二单板，第二单板通过连接器接收测试信号(即第二测试信号)，最后通过比对第一单板发送的测试信号与第二单板通过连接器接收到的第二测试信号，达到了不需要开发测试接口卡，而是在现有的产品基础上，通过与连接器相连的业务单板间接实现连接器测试的目的，从而实现了减少开发测试接口卡的成本的技术效果，在产品使用的过程中进行在线测试的技术效果，进而解决了相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的技术问题。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1是本发明实施例的一种连接器的测试方法的计算机设备的硬件结构框图；
图2是根据本发明实施例的一种连接器的测试方法的流程图；
图3是根据本发明实施例的一种可选的有背板情况下的单板连接示意图；
图4是根据本发明实施例的一种可选的无背板情况下的单板连接示意图；
图5是根据本发明实施例的一种可选的连接器的测试方法的流程图；
图6是根据本发明实施例的一种可选的连接器的测试方法的流程图；
图7是根据本发明实施例的一种可选的连接器的测试方法的流程图；
图8是根据本发明实施例的一种可选的连接器的测试方法的流程图；
图9是根据本发明实施例的一种可选的连接器的测试方法的流程图；
图10是根据本发明实施例的一种可选的连接器的测试方法的流程图；
图11是根据本发明实施例的一种可选的固定0电平故障检测方法流程图；
图12是根据本发明实施例的一种可选的固定1电平故障检测方法流程图；
图13是根据本发明实施例的一种可选的短路故障检测方法流程图；
图14是根据本发明实施例的一种电子设备示意图；
图15是根据本发明实施例的一种可选的单板结构示意图；
图16是根据本发明实施例的一种可选的Jtag测试逻辑功能结构示意图；
图17是根据本发明实施例的一种连接器的测试装置的结构框图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
发明人在研究过程中发现，用于连接单板的连接器主要存在如下两个问题：一、由于背板连接器的管脚是由一根根的鱼眼形状的细针组成的，连接器加工的过程中需要把连接器上的一根根针和背板上的一个个小孔对齐，如果连接器上面的针脚(或管脚)不是垂直的，这样连接器的针脚不能放到过孔里，在机械按压的过程中就会把针脚压歪，这个压歪的针就会和周边的地管脚、电源管脚或其他信号管脚搭接在一起。如果连接器上的管脚与地管脚短接在一起，则在信号上表现为持续的低电平，即通常所说的固定0故障；如果连接器上的管脚与电源管脚短接在一起，则在信号上 表现为持续的高电平，即通常所说的固定1故障。二、由于某些场合的单板经常插拔(例如，交换机在使用的过程中会经常插拔第一单板和第二单板)，也会导致背板连接器针脚歪的情况。这种情况用肉眼仔细观察，也能发现背板上的连接器针脚歪了，由于连接器上面的针脚数量众多，人工检测的方案不适合生产过程中的自动化大批量检测。由此，对于背板连接器的检测通常会很困难，维修起来也非常麻烦。
在实际应用中，背板连接器的测试方法通常有如下几种：外观检测、飞针检测、在线检测(InCircuitTest，ICT)、功能测试和选通测试。下面为两种常用的对背板连接器的测试方案：一种是开发特定的测试系统实现背板的测试，该测试系统包括测试实现单元、控制单元和接口板，其中，接口板上包括选通模块和测量模块。这种测试方案主要是通过接口板上的选通模块打开模拟开关或继电器，控制单元负责把测试仪器万用表连接到接口板上，通过选通背板上的信号，通过测试背板信号的电阻阻值来判断背板信号的好坏；另外一种是通过控制台、控制单元和接口适配器实现背板的测试，这种测试方案通过接口适配器扫描背板网络得到网络关系数据，通过对比测试得到的网络关系数据和标准网络关系数据得到有问题的网络。
本申请实施例所提供的连接器的测试方法实施例可以在大型通讯设备、超高性能服务器和巨型计算机、工业计算机、高端存储设备等包含多组件进行数据通信的电子设备或者类似的装置中执行。其中，对于有背板的场景，连接器用于单板和背板垂直连接；对于无背板的场景，连接器用于单板之间对接。
以运行在计算机设备上为例，图1是本发明实施例的一种连接器的测试方法的计算机设备的硬件结构框图。如图1所示，计算机设备10可以包括一个或多个(图中仅示出一个)处理器102(处理器102可以包括但不限于微处理器(Microcontroller Unit，MCU)或可编程逻辑器件(Field－ Programmable Gate Array，FPGA)等的处理装置)、配置为存储数据的存储器104、以及配置为通信功能的传输装置106。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述电子装置的结构造成限定。例如，计算机设备10还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可配置为存储应用软件的软件程序以及模块，如本发明实施例中的连接器的测试方法对应的程序指令/模块，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机设备10。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106配置为经由一个网络接收或者发送数据。上述的网络实例可包括计算机设备10的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其配置为通过无线方式与互联网进行通讯。
在本实施例中提供了一种运行于上述计算机设备的连接器的测试方法，可以应用于有背板组件的电子设备的背板连接器的测试，无背板组件直接对接式设备连接器的相关测试中。图2是根据本发明实施例的一种连接器的测试方法的流程图，如图2所示，该流程包括如下步骤：
步骤S202，获取第一单板发送的与测试指令对应的第一测试信号；
步骤S204，获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；
步骤S206，比较第一测试信号与第二测试信号；
步骤S208，根据比较结果，确定连接器上的管脚是否存在故障。
在一实施例中，第一单板和第二单板可以为电子设备中通过连接器连接的业务单板，第一单板和第二单板可以通过连接器直接对接，也可以通过连接器分别与背板连接，如图3所示为根据本发明实施例的一种可选的有背板情况下的单板连接示意图，如图4所示为根据本发明实施例的一种可选的无背板情况下的单板连接示意图，无论哪种情况，由第一单板发送测试信号(即第一测试信号)，由通过连接器与第一单板连接(包括有背板和无背板的两种情况)的第二单板接收测试信号(即第二测试信号)，则可以通过比较第二单板接收到第二测试信号与第一单板发送的第一测试信号来确定连接于第一单板和第二单板之间的连接器是否发生故障。
基于上述步骤S102至S108公开的方案，通过同一连接器连接的第一单板和第二单板可以配置为检测连接于二者之间的连接器上的管脚(即针脚)是否发生故障，例如，连接器上管脚由于歪针导致与地管脚短接引起固定低电平故障(或称固定“0”电平故障，即与地管脚短接的管脚都呈现持续的低电平“0”)，或者与电源管脚短接引起固定高电平故障(或称固定“1”电平故障，即与电源管脚短接的管脚都呈现持续的高电平“1”)，或者与其他相邻的信号管脚短接引起短路故障(即两个短接信号管脚会构成短路)。
此处需要说明的是，图3是根据本发明实施例的一种可选的有背板情况下的单板连接示意图，图4是根据本发明实施例的一种可选的无背板情况下的单板连接示意图；如图3和4所示，第一单板和第二单板上都有至少一个主芯片，其中，每个主芯片都有Jtag接口，Jtag接口有4根线，TCK、 TMS、TDI和TDO，其中，TCK是时钟信号；TMS是Jtag模块的状态控制信号，控制芯片Jtag模块所处的状态；TDI是数据输入信号；TDO是数据输出信号。由此，作为一种可选的实施方式，连接器一侧的管脚可以与第一单板内至少一个第一主芯片的管脚相连，连接器另一侧的管脚与第二单板内至少一个第二主芯片的管脚相连；其中，通过第一主芯片的Jtag接口可以将第一测试信号发送至第一主芯片的管脚；通过第二主芯片的Jtag接口可以读取第二主芯片的管脚接收到的第二测试信号。
一种可选的实施例中，如果测试信号为由0和1构成的序列，其中，0对应的管脚电平为低电平，1对应的管脚电平为高电平，则上述第一单板发送的第一测试信号可以用于表征连接器一侧管脚的电平状态，上述第二单板通过连接器接收到的第二测试信号可以用于表征连接器另一侧管脚的电平状态。
由上可知，在本申请实施例1公开的方案中，通过第一单板将测试信号(即第一测试信号)发送到连接器上与第一单板相连一侧的管脚上，通过连接器的管脚将第一测试信号传递到与连接器另一侧管脚相连的第二单板，第二单板通过连接器接收测试信号(即第二测试信号)，最后通过比对第一单板发送的第一测试信号与第二单板通过连接器接收到的第二测试信号，则可以确定连接于第一单板与第二单板之间的连接器是否出现故障。
通过本申请实施例1公开的方案，达到了不需要开发测试接口卡，而是在现有的产品基础上，通过与连接器相连的业务单板间接实现连接器测试的目的，从而实现了减少开发测试接口卡的成本，在产品使用的过程中进行在线测试的技术效果，进而解决了相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的技术问题。
在一实施例中，如图5所示，在获取第一单板发送的与测试指令对应的测试信号之前，上述方法还可以包括如下步骤：
步骤S502，产生测试指令；
步骤S504，将测试指令发送给第一单板，其中，第一单板内预先存储有与测试指令对应的至少一种测试信号。
在一实施例中，上述测试指令至少包括如下任意一种：第一故障测试指令，用于检测连接器的管脚与地管脚连接引起的低电平故障；第二故障测试指令，用于检测连接器的管脚与电源管脚连接引起的高电平故障；第三故障测试指令，用于检测连接器的管脚与相邻管脚连接引起的短路故障。每种测试指令可以用于测试不同的故障类型，与每种测试指令对应的测试信号可以是一种或多种，预先存储在第一单板内，第一单板在接收到下发的测试指令后，可以获取相应的测试信号进行测试。
作为一种可选的实施例，在测试信号为由1和0组成的序列的情况下，与第一故障测试指令对应的测试信号可以为全1序列；与第二故障测试指令对应的测试信号可以为全0序列；与第三故障测试指令对应的测试信号可以为0和1相间出现的序列，其中，与1码对应的管脚的电平为高电平，与0码对应的管脚的电平低电平。例如，以8为序列码为例，与第一故障测试指令对应的测试信号可以为“11111111”，与第二故障测试指令对应的测试信号可以为“00000000”，与第三故障测试指令对应的测试信号可以是“10101010”，也可以是“01010101”。
基于上述实施例，在第一种可选的实施场景中，即在测试指令为第一故障测试指令的情况下，第一测试信号为全1序列，如图6所示，步骤S208，根据比较结果，确定连接器上的管脚是否存在故障，可以包括如下步骤：
步骤S602，如果第二测试信号全为高电平，则确定连接器上的管脚不存在低电平故障；
步骤S604，如果第二测试信号中至少有一位为低电平，则确定连接器上的管脚存在低电平故障，并且，连接器上与低电平对应的管脚位置为存 在低电平故障的管脚位置。
在一实施例中，步骤S602和S604的执行顺序是可以互换的，即可以先执行上步骤S604再执行步骤S602。
在一实施例中，上述第二测试信号为在第一单板发送全1序列的第一测试信号后，第二单板通过连接器接收到的测试信号(即第二单板中与连接器相连的至少一个主芯片的管脚电平)；上述固定低电平故障可以为连接器的管脚与地管脚连接引起的故障，也即固定“0”电平故障。由于第一单板发送的第一测试信号可以用于表征连接器一侧管脚的电平状态，第二单板通过连接器接收到的第二测试信号可以用于表征连接器另一侧管脚的电平状态，因而，如果第二测试信号为全为高电平(即全1序列)，则表明连接器两侧的管脚的电平状态一致，可以确定连接器上的管脚不存在固定低电平故障；如果第二测试信号中不全为高电平(即序列中至少有一位为0码)，则表明连接器两侧的管脚的电平状态不一致，由于发送的第一测试信号全1序列，则连接器上与第一单板连接的一侧的管脚都为高电平，而第二测试信号表明连接器上与第二单板连接的一侧的管脚中存在低电平的管脚，则说明该管脚与地管脚短接在一起，出现了固定低电平故障。
一种可选的实施例中，以图3或4所示的通过背板连接器连接的单板1和单板2为例，针对固定“0”电平故障的检测方法，如果连接器管脚出现歪针的情况，则在压接的时候，这个管脚与周边的地管脚搭接在一起，表现为低电平，即所说的固定0电平故障。如果一个管脚对地短路，则连接器对端接收到的信号必有一个信号是低电平，通过相与可以检测出出现低电平的位置。如图3或4所示，单板1测试逻辑模块，通过Jtag接口的相关Jtag命令，把8个连续的高电平，即8个1信号发送到背板连接器上面。即把发送的信号(即第一测试信号)表示为8’b11111111，与此同时，单板2上的Jtag测试逻辑通过芯片的Jtag接口，间接的接收8个信号，假设中 间第4位接收的为低电平，接收信号(即第二测试信号)表示为8’b11110111，通过8’b11111111按位与8’b11110111＝8’b11110111，然后一位一位检测为0的位，第4位为0说明检测的到第4位对应的管脚有问题，同理如果对应的管脚有对地短路问题，则对应的第几位一定为低电平，即表示为0。通过这样的方法就可以检测出对应的管脚有无对地短路的情况。
通过上述实施例，可以实现检测连接器上是否存在固定“0”故障的管脚，并可以确定存在固定“0”故障的管脚的位置。
基于上述实施例，在第二种可选的实施场景中，即在测试指令为第二故障测试指令的情况下，第一测试信号为全0序列，如图7所示，步骤S208，根据比较结果，确定连接器上的管脚是否存在故障，可以包括如下步骤：
步骤S702，如果第二测试信号为全为低电平，则确定连接器上的管脚不存在高电平故障；
步骤S704，如果第二测试信号中至少有一位为高电平，则确定连接器上的管脚存在高电平故障，并且，连接器上与高电平对应的管脚位置为存在高电平故障的管脚位置。
在一实施例中，步骤S702和S704的执行顺序是可以互换的，即可以先执行上步骤S704再执行步骤S702。
在一实施例中，上述第二测试信号为在第一单板发送全0序列的第一测试信号后，第二单板通过连接器接收到的测试信号(即第二单板中与连接器相连的至少一个主芯片的管脚电平)；上述固定高电平故障可以为连接器的管脚与电源管脚连接引起的故障，也即固定“1”电平故障。由于第一单板发送的第一测试信号可以用于表征连接器一侧管脚的电平状态，第二单板通过连接器接收到的第二测试信号可以用于表征连接器另一侧管脚的电平状态，因而，如果第二测试信号为全为低电平(即全0序列)，则表明连接器两侧的管脚的电平状态一致，可以确定连接器上的管脚不存在固定 高电平故障；如果第二测试信号中不全为低电平(即序列中至少有一位为1码)，则表明连接器两侧的管脚的电平状态不一致，由于发送的第一测试信号全0序列，则连接器上与第一单板连接的一侧的管脚都为低电平，而第二测试信号表明连接器上与第二单板连接的一侧的管脚中存在高电平的管脚，则说明该管脚与电源管脚短接在一起，出现了固定高电平故障。
一种可选的实施例中，仍以图3或4所示的通过背板连接器连接的单板1和单板2为例，针对固定“1”电平故障的检测方法，连接器管脚出现歪针的情况，在压接的时候，这个管脚与周边的电源管脚搭接在一起，表现为高电平，即所说的固定1电平故障。如果其中有一个管脚对电源短路，测对端接收到的信号一定会有一个是高电平，通过输入输出信号的或操作，检测出高电平的数据位置，就可以确定出现问题的管脚的位置。如图3或4所示，单板1测试逻辑模块，通过Jtag接口的相关Jtag命令，把8个连续的低电平，即8个0信号发送到背板连接器上面。即把发送的信号(即第一测试信号)表示为8’b00000000，与此同时，单板2上的Jtag测试逻辑通过芯片的Jtag接口，间接的接收8个信号，假设中间第4位接收的为高电平，接收信号(即第二测试信号)表示为8’b00001000，通过8’b00000000按位或8’b00001000＝8’b00001000,然后一位一位检测为1的位，第4位为1说明检测的到第4位对应的管脚有问题，同理如果对应的管脚有对电源短路问题，则对应的第几位一定为低电平，即表示为1。通过这样的方法就可以检测出对应的管脚有无对电源短路的情况。
通过上述实施例，可以实现检测连接器上是否存在固定“1”故障的管脚，并可以确定存在固定“1”故障的管脚的位置。
基于上述实施例，在第三种可选的实施场景中，即在测试指令为第三故障测试指令的情况下，第一测试信号为0和1相间出现的序列，如图8所示，步骤S208，根据比较结果，确定连接器上的管脚是否存在故障，可 以包括如下步骤：
步骤S802，如果读取到第二测试信号没有出现三个连续相等的电平，则确定连接器上的管脚不存在短路故障；
步骤S804，如果读取到第二测试信号出现三个连续相等的电平，则确定连接器上与连续相等的电平对应的三个管脚中至少有两个管脚存在短路故障。
在一实施例中，步骤S802和S804的执行顺序是可以互换的，即可以先执行上步骤S804再执行步骤S802。
在一实施例中，上述第二测试信号为在第一单板发送0和1相间出现的序列的第一测试信号后，第二单板通过连接器接收到的测试信号(即第二单板中与连接器相连的至少一个主芯片的管脚电平)；上述短路故障可以为连接器的管脚与相邻其他信号管脚连接引起的故障。由于第一单板发送的第一测试信号可以用于表征连接器一侧管脚的电平状态，第二单板通过连接器接收到的第二测试信号可以用于表征连接器另一侧管脚的电平状态，因而，如果第二测试信号没有出现三个连续相等的电平，则表明连接器两侧的管脚的电平状态一致，可以确定连接器上的管脚不存在固定高电平故障；如果第二测试信号中出现三个连续相等的电平(即序列中存在连续三个1码或三个0码)，则表明连接器两侧的管脚的电平状态不一致，由于发送的第一测试信号0和1相间出现的序列，则连接器上与第一单板连接的一侧的管脚应该高、低电平相间的电平状态，而第二测试信号表明连接器上与第二单板连接的一侧的管脚中存在连续三个高电平或连续三个低电平的管脚，则说明这三管脚中可能存在至少两个管脚短路的短路故障，可能是三个管脚中前两个管脚短路，也可能是后两个管脚短路，还可能出现三个管脚都短路的情况。
一种可选的实施例中，仍以图3和4所示的通过背板连接器连接的单 板1和单板2为例，针对相邻管脚短路的检测方法，相邻管脚短路是指两个相邻的管脚接收到的信号同时为00或同时为11。由于连接器的管脚压歪，出现两个信号管脚连接到一起。发送信号发送间隔为1010，即两相邻位为不同电平的信号，接收端如果检测到相邻位相同的信号，则出现相邻管脚短路的情况。在排除固定电平的故障之后，进行短路故障检测。检测过程如下，以8位测试信号为例，假设第4、5位管脚短路，如图3或4所示，单板1发送的信号(即第一测试信号)为8’b01010101，单板2接收到的信号(即第二测试信号)为8’01000101，其中，对第一测试信号和第二测试信号进行相与运算，即8’b01010101&8’b01000101＝8’b01000101，对结果进行两位检测，中间的4、5、6位为000说明第4、5两位或5、6两位短路。
在上述第三种可选的实施场景中，为了进一步确定三个管脚中存在短路故障的管脚位置，一种可选的实施例中，如图9所示，在确定连接器上与连续相等的电平对应的三个管脚中至少有两个管脚存在短路故障之后，上述方法还可以包括如下步骤：
步骤S902，将第一测试信号中与三个管脚中中间管脚对应的序列码设置为高电平或低电平，其他位设置为相反的电平；
步骤S904，检测第二单板上的第二主芯片管脚接收到的第二测试信号；
步骤S906，根据检测结果，确定连接器上存在短路故障的管脚。
在一实施例中，当确定连接器上与连续相等的电平对应的三个管脚中至少有两个管脚存在短路故障之后，可以将第一测试信号中与三个管脚中中间管脚对应的序列码设置为高电平(即1码)或低电平(即0码)，重新发送至与连接器另一侧相连的第二单板，并根据第二单板接收到的第二测试信号与第一测试信号的比较结果，确定连接器上存在短路故障的管脚。
其中，作为一种可选的实施方式，根据检测结果，确定连接器上存在短路故障的管脚，如图10所示，可以包括如下步骤：
步骤S9061，如果三个管脚中前两个管脚的电平相同，则确定连接器上与前两个管脚对应的两个管脚存在短路故障；
步骤S9063，如果三个管脚中后两个管脚的电平相同，则确定连接器上与前两个管脚对应的两个管脚存在短路故障；
步骤S9065，如果三个管脚中的三个管脚的电平均相同，则确定连接器上三个管脚均存在短路故障。
在一实施例中，步骤S9061、S9063和S9065的执行顺序是可以互换的，即可以先执行上步骤中的任意一个步骤。
仍以图3和4所示的通过背板连接器连接的单板1和单板2为例，在单板1发送的信号(即第一测试信号)为8’b01010101，单板2接收到的信号(即第二测试信号)为8’01000101后，由于中间的4、5、6位为000说明第4、5两位或5、6两位短路，之后，则通过单板1发送8’b11101111，即把中间可能短路的位即第5位发送低电平，其他为高电平，则单板2侧接收到的信号一定是8’b11100111，通过这种方法可以检测到4、5两位管脚短路。其他位置短路可以用相同的方法检测。
通过上述实施例，可以实现检测连接器上是否存在短路故障的管脚，并可以确定存在短路故障的管脚的位置。
需要说明的是，上述各个步骤的执行主体可以为电子设备中控制板等，但不限于此。
仍以图3和4所示的通过背板连接器连接的单板1和单板2为例，下面结合图11至13来说明本申请上述实施例，其中，图11是根据本发明实施例的一种固定0电平故障检测方法流程图，图12是根据本发明实施例的一种固定1电平故障检测方法流程图，图13是根据本发明实施例的一种短路故障检测方法流程图，其中，对于不同故障类型用到的检测码型如表1所示。
表1
Figure PCTCN2018074275-appb-000001
(1)固定0电平故障检测方案。
固定0电平是背板连接器压接的过程中经常出现的故障现象，主要是由于压接的时候，有个别的针没有对准背板pcb上的压接过孔，导致针被压歪，从而和周边的地短接，导致上电之后，该管脚拉低，形成了固定0电平故障。
固定0电平检测步骤如附图11中所示，步骤112中，控制板1先向单板1发送Jtag 0电平检测指令，单板1控制单元会通过本地总线控制EPLD中Jtag模块，Jtag模块通过与主芯片相连接的Jtag接口，使主芯片的所有 管脚输出高电平1的状态。主芯片状态通过背板高速连接器传输到单板2相应的背板连接器上。然后控制板通过通讯链路再向单板2发送指令，单板2控制单元通过Jtag采样主芯片背板连接器相关管脚的状态。步骤114中，控制板再通过通讯链路读取单板2检测状态，如果连接器正常，相应的状态应该是高电平“1”，如果是0说明，该管脚存在固定0电平故障。
(2)固定1电平故障检测方案。
固定1电平和固定0电平检测流程一致，检测方法也一样。固定1电平指管脚拉到高电平1，
固定1电平检测步骤如附图12中所示，步骤122中，控制板先向单板1发送Jtag 1电平检测指令，单板1控制单元会通过本地总线控制EPLD中Jtag模块，Jtag模块通过与主芯片相连接的Jtag接口，使主芯片的所有管脚输出高电平0的状态。主芯片状态通过背板高速连接器传输到单板2相应的背板连接器上。然后控制板通过通讯链路再向单板2发送指令，单板2控制单元通过Jtag采样主芯片背板连接器相关管脚的状态。步骤124中，控制板再通过通讯链路读取单板2检测状态，如果连接器正常，相应的状态应该是高电平“0”，如果是1说明，该管脚存在固定1电平故障。
(3)短路故障检测方案。
两个管脚短路，通常在连接器压接的过程中或在单板使用的过程中，背板连接器常常出现相邻的管脚倒针的情况，就会导致相邻的两个管脚的状态会同时变化，要么同时为高电平11，要么同时为低电平00
管脚短路检测步骤如附图13中所示，步骤132中，控制板先向单板1发送管脚短路检测指令，单板1控制单元会通过本地总线控制EPLD中Jtag模块，Jtag模块通过与主芯片相连接的Jtag接口，使主芯片的所有管脚输出高电平10101010的状态。主芯片状态通过背板高速连接器传输到单板2相应的背板连接器上。然后控制板通过通讯链路再向单板2发送指令，单 板2控制单元通过Jtag采样主芯片背板连接器相关管脚的状态。步骤134中，控制板再通过通讯链路读取单板2检测状态，如果连接器正常，相应的状态应该是高电平“10101010”，如果有出现连续的三个11或连续的三个00的状态，则对应的三个相应的管脚中的两个存在短路的故障。步骤136中，为了进一步确认短路的位置，控制板分别向单板1和单板2发送检测指令，单板1发送的检测码型中三个连续相等电平中间为1其他为0或中间为0其他都为1，步骤138中，主控板通过单板2读取检测到的状态，从而确认出两个管脚短路的故障。
需要说明的是，本实施例公开的连接器的测试方法，与现有的连接器测试方法在逻辑实现和测试结构的构思上存在根本差异。首先：在测试结构的构思上存在差异，之前的测试系统需要开发特定的测试单板和测试模具等，本发明只需要把Jtag相关的测试信号和Jtag测试逻辑模块嵌入当前的产品中就可以实现背板的测试，不需要开发特定测试系统。其次：在测试逻辑实现上，本发明中的测试模块通过Jtag接口的4根线，把测试信号发送到产品的主芯片的管脚上面，测试信号再通过主芯片与背板连接器相连的管脚，传递到背板连接器上面，接着背板另一侧的单板2上的测试逻辑通过Jtag接口接收到测试信号。而之前的方法是直接通过控制单元和接口适配器，发送测试数据。测试系统直接连接到背板管脚上面，本发明是间接实现测试。再次：之前的发明或是利用接口卡测试背板上的电阻或是通过接口适配卡测试出背板连接关系网络，通过对比网络对背板进行测试，本发明是利用Jtag接口直接发送不同的码型直接对背板中的故障进行测试。在产品使用过程中，测试逻辑与单板Jtag接口断开，不影响产品正常的功能。在需要进行调试定位的时候，测试逻辑通过Jtag接口进行测试，实现背板连接器的在线测试。综上所述，本发明在背板测试的构思上面与现有的技术构思不同。一个是直接测试，一个嵌入到产品中实现间接测试。在 测试逻辑中也有所不同，一个需要接口适配器直接发送测试信号测试，一个是通过产品中芯片的Jtag接口间接实现测试信号的发送接收。
此处还需要说明的是，本实施例提供的连接器的测试方法不需要开发专门的测试接口卡，而是利用业务单板芯片的Jtag接口和单板上的逻辑芯片实现背板连接器的测试，可以兼容现有的单板结构，只需要在在单板的逻辑中添加Jtag测试模块，就能实现背板的在线测试。本发明把测试模块嵌入到当前的产品中，所有的产品都可采用，不需要开发专门的测试系统，从而实现测试成本的大幅降低。在产品的所有单板中都会有Jtag接口，本发明中的Jtag测试方法可以适用所有产品中的背板相关测试，只要其他技术人员利用这种方法对背板进性测试，可能触发本发明所涉及的保护范围。本发明适用产品中所有单板相互连接的测试。产品中的不同槽位的单板可以通过背板连接，也可以无背板通过直连的方式连接，本发明都可以适用。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明各个实施例所述的方法。
本实施例还提供了一种电子设备，可以配置为执行上述连接器的测试方法。图14是根据本发明实施例的一种电子设备示意图，如图14所示，该电子设备包括：控制板141、第一单板143和第二单板145。
其中，控制板141，配置为产生测试指令；
第一单板143，与控制板连接，配置为发送与测试指令对应的第一测试 信号；
第二单板145，与第一单板通过连接器连接，配置为接收通过连接器接收到的第二测试信号；
其中，控制板配置为比较第一测试信号与第二测试信号，并根据比较结果，确定连接器上的管脚是否存在故障。
上述电子设备中第一单板和第二单板的连接结构可以包括图3中有背板的情况和图4中无背板的情况，控制板是整个电子设备产品的控制单元。第一单板、第二单板和控制板之间通过通信链路通信。
由上可知，在本申请实施例2公开的方案中，通过控制板141产生用于测试连接器故障的测试指令，并发送至第一单板143和第二单板145，其中，第一单板143在接收到测试指令后，获取与该测试指令对应的测试信号，并将测试信号(即第一测试信号)发送到连接器上，通过连接器将第一测试信号传递到与连接器相连的第二单板145，第二单板145通过连接器接收测试信号(即第二测试信号)，最后控制板141比对第一单板143发送的测试信号与第二单板145通过连接器接收到的第二测试信号，则可以确定连接于第一单板143与第二单板145之间的连接器是否存在故障。
通过本申请实施例公开的方案，达到了不需要开发测试接口卡，而是在现有的产品基础上，通过与连接器相连的业务单板间接实现连接器测试的目的，从而实现了减少开发测试接口卡的成本，在产品使用的过程中进行在线测试的技术效果，进而解决了相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的技术问题。
在一实施例中，上述第一单板可以包括：第一主芯片和配置为对第一主芯片的管脚进行测试的第一逻辑芯片，其中，第一主芯片具有第一Jtag接口，与第一逻辑芯片通过第一Jtag接口通信；上述第二单板可以包括：第二主芯片和配置为对第二主芯片的管脚电平进行测试的第二逻辑芯片， 其中，第二主芯片具有第二Jtag接口，与第二逻辑芯片通过第二Jtag接口通信。
在上述实施例中，上述第一主芯片可以为与背板连接器一侧相连的第一单板内的主芯片，上述第二主芯片可以为与背板连接器一侧相连的第二单板内的主芯片，第一主芯片和第二主芯片都有Jtag接口，其中，第一Jtag接口为第一主芯片与第一逻辑芯片通信的接口，第二Jtag接口为第二主芯片与第二逻辑芯片通信的接口。本发明中需要把背板两侧单板中的与背板连接器相连的主芯片的4个Jtag接口的信号线连接到单板的逻辑芯片上面。
作为一种可选的实施方式，上述第一主芯片和第一逻辑芯片的连接结构，以及二主芯片和第二逻辑芯片的连接结构可以为图3或4所示的连接结构。
在上述实施例中，连接器一侧的管脚与第一单板内至少一个第一主芯片的管脚相连，连接器另一侧的管脚与第二单板内至少一个第二主芯片的管脚相连。
在一实施例中，上述第一单板还可以包括：第一控制单元，配置为通过本地总线控制第一逻辑芯片；上述第二单板还可以包括：第二控制单元，配置为通过本地总线控制第二逻辑芯片。
在上述实施例中，在测试过程中，背板连接器一侧的第一单板中的第一控制单元通过Jtag接口把需要的测试数据(即第一测试信号)发送到与背板连接器相连的第一主芯片对应的管脚上，背板连接器另外一侧的交第二单板接收到测试数据(即通过背板连接器传递的与第一测试信号对应的电平状态)后，第二单板第二控制单元通过本地总线控制第二逻辑芯片读取第二主芯片管脚的电平状态，得到第二测试信号，的从而实现背板连接器的测试。
作为一种可选的实施方式，上述第一控制单元和第一控制单元在第一 单板和第二单板内的连接结构，可以如图3或4所示的连接结构。
一种可选的实施例中，图15示出了根据本发明实施例的一种单板结构示意图，可以作为上述第一单板或第二单板的结构，如图15所示，上述第一单板和第二单板可以包括控制单元和单板EPLD逻辑芯片，以及至少一个主芯片，其中，主芯片主要负责数据通信。其中，单板EPLD逻辑芯片中包含由用于进行Jtag测试的逻辑程序，如图15中的“Jtag测试”加粗框，主芯片的Jtag接口通过串行或并行的方式连接到EPLD逻辑芯片中的Jtag逻辑，从而通过Jtag逻辑实现测试。
其中，Jtag测试逻辑功能结构如附图16所示：本地总线接口部分负责和单板上面的控制单元通信。Jtag接口部分负责和单板上面的主芯片的Jtag接口进行通信。数据存储主要负责存储从控制单元接收到的测试信号。指令存储主要存储从控制单元接收到的测试指令。控制单元部分主要负责根据测试指令，向Jtag接口发送相关的测试命令，把测试信号通过Jtag接口发送到芯片上，从而传递到背板的连接器管脚上。
通过本实施例提供的电子设备，可以实现第一单板和第二单板之间的连接器如下任意一种故障检测：
一、针对固定“0”电平故障的检测：控制板控制单元通过通信接口和单板1的控制单元和本地总线接口，把“固定0电平故障”的测试指令和测试数据发送到逻辑芯片中的测试指令和数据的存储单元中，逻辑逻辑中根据测试指令，把需要发送的测试信号，发送到单板的主芯片上面，从而发送到背板连接器上。同时控制板控制单元通过第二单板上的Jtag测试逻辑把测试信号读取出来。通过比对确定背板连接器上有固定0电平故障的管脚位置。
二、针对固定“1”电平故障的检测：控制板控制单元通过通信接口，线路转发功能板的控制单元和本地总线接口，把“固定1电平故障”的测 试指令和测试数据发送到逻辑芯片中的测试指令和数据的存储单元中，逻辑逻辑中根据测试指令，把需要发送的测试信号，发送到单板的主芯片上面，从而发送到背板连接器上。同时控制板控制单元通过第二单板上的Jtag测试逻辑把测试信号读取出来。通过比对确定背板连接器上有固定1电平故障的管脚位置。
三、短路故障的检测：控制板控制单元通过通信接口，线路转发功能板的控制单元和本地总线接口，把“短路故障”的测试指令和测试数据发送到逻辑芯片中的测试指令和数据的存储单元中，逻辑逻辑中根据测试指令，把需要发送的测试信号，发送到单板的主芯片上面，从而发送到背板连接器上。同时控制板控制单元通过第二单板上的Jtag测试逻辑把测试信号读取出来。通过比对确定背板连接器上有短路故障的管脚位置。
通过本申请上述实施例公开的方案，在第一单板和第二单板上主芯片的Jtag接口都连接到单板的逻辑芯片中，第一单板的控制单元通过本地总线控制逻辑芯片中的Jtag测试模块，向单板的主芯片输入测试码流，第二单板的控制单元通过本地总线总线控制逻辑的Jtag模块，检测主芯片Jtag接口输入码流。如图3或4所示，控制板通过通信链路1和通信链路2分别控制第一单板和第二单板的控制单元，通过比对输入和输出的测试码流，来检测背板上高速连接器的管脚有没有出现上述故障情况。实现了在线检测背板连接器管脚是否存在“固定0电平”、“固定1电平”和“相邻管脚短路”的问题，满足背板在产品使用过程中对连接器的检测。
由上可知，本申请上述实施例，至少具有如下优点：一、不增加第一单板和第二单板的成本，只要把主芯片的Jtag接口引入单板逻辑中即可，只要增加相应的Jtag逻辑模块和增加相应的软件算法即可。二、单板可以在线检测，为快速定位背板crc相应的问题提供强有力的措施。
本实施例还提供了一种连接器的测试装置，该装置配置为实现上述连 接器的测试方法，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图17是本发明实施例提供的一种连接器的测试装置的结构框图，如图17所示，该装置包括：第一获取模块171、第二获取模块173、比较模块175和确定模块177。
其中，第一获取模块171，配置为获取第一单板发送的与测试指令对应的第一测试信号；
第二获取模块173，配置为获取第二单板通过连接器接收到的第二测试信号，其中，连接器连接于第一单板和第二单板之间；
比较模块175，配置为比较第一测试信号与第二测试信号；
确定模块177，配置为比较第一单板发送的测试信号与第二单板接收到的测试信号。
此处需要说明的是，上述第一获取模块171、第二获取模块173、比较模块175和确定模块177对应于实施例1中的步骤S202至S208，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
由上可知，在本申请实施例3公开的方案中，通过第一获取模块171获取第一单板发送的与测试指令对应的测试信号(即第一测试信号)，其中，第一测试信号被发送到连接器上与第一单板相连一侧的管脚上，连接器的管脚将第一测试信号传递到与连接器另一侧管脚相连的第二单板，通过第二获取模块173获取第二单板通过连接器接收到的测试信号(即第二测试信号)，最后通过比较模块175比对第一单板发送的第一测试信号与第二单 板通过连接器接收到的第二测试信号，则可以确定连接于第一单板与第二单板之间的连接器是否出现故障。
通过本申请实施例3公开的方案，达到了不需要开发测试接口卡，而是在现有的产品基础上，通过与连接器相连的业务单板间接实现连接器测试的目的，从而实现了减少开发测试接口卡的成本，在产品使用的过程中进行在线测试的技术效果，进而解决了相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的技术问题。
在一实施例中，上述装置还可以包括：生成模块，配置为产生测试指令；发送模块，配置为将测试指令发送给第一单板，其中，第一单板内预先存储有与测试指令对应的至少一种测试信号。
此处需要说明的是，上述生成模块和发送模块对应于上述实施例中的步骤S502至S504，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
在一实施例中，在测试指令为第一故障测试指令的情况下，第一测试信号采用全1序列，上述确定模块177可以包括：第一确定单元，配置为如果第二测试信号全为高电平，则确定连接器上的管脚不存在低电平故障；第二确定单元，配置为如果第二测试信号中至少有一位为低电平，则确定连接器上的管脚存在低电平故障，并且，连接器上与低电平对应的管脚位置为存在低电平故障的管脚位置。
此处需要说明的是，上述第一确定单元和第二确定单元对应于实施例1中的步骤S602至S604，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
在一实施例中，在测试指令为第二故障测试指令的情况下，第一测试 信号采用全0序列，上述确定模块177可以包括：第三确定单元，配置为如果第二测试信号为全为低电平，则确定连接器上的管脚不存在高电平故障；第四确定单元，配置为如果第二测试信号中至少有一位为高电平，则确定连接器上的管脚存在高电平故障，并且，连接器上与高电平对应的管脚位置为存在高电平故障的管脚位置。
此处需要说明的是，上述第三确定单元和第四确定单元对应于实施例1中的步骤S702至S704，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
在一实施例中，在测试指令为第三故障测试指令的情况下，第一测试信号采用0和1相间出现的序列，上述确定模块177可以包括：第五确定单元，配置为如果读取到第二测试信号没有出现三个连续相等的电平，则确定连接器上的管脚不存在短路故障；第六确定单元，配置为如果读取到第二测试信号出现三个连续相等的电平，则确定连接器上与连续相等的电平对应的三个管脚中至少有两个管脚存在短路故障。
此处需要说明的是，上述第五确定单元和第六确定单元对应于实施例中的步骤S802至S804，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
在一实施例中，在测试指令为第三故障测试指令的情况下，上述第六确定单元可以包括：设置单元，配置为将第一测试信号中与三个管脚中中间管脚对应的序列码设置为高电平或低电平，其他位设置为相反的电平；检测单元，配置为检测第二单板上的第二主芯片管脚接收到的第二测试信号；确定子单元，配置为根据检测结果，确定连接器上存在短路故障的管脚。
此处需要说明的是，上述设置单元、检测单元和确定子单元对应于实施例中的步骤S902至S906，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
在一实施例中，在测试指令为第三故障测试指令的情况下，上述确定子单元可以包括：第一子确定模块，配置为如果三个管脚中前两个管脚的电平相同，则确定连接器上与前两个管脚对应的两个管脚存在短路故障；第二子确定模块，配置为如果三个管脚中后两个管脚的电平相同，则确定连接器上与前两个管脚对应的两个管脚存在短路故障；第三子确定模块，配置为如果三个管脚中的三个管脚的电平均相同，则确定连接器上三个管脚均存在短路故障。
此处需要说明的是，上述第一子确定模块、第二子确定模块和第三子确定模块对应于实施例中的步骤S9061至S9065，上述模块与对应的步骤所实现的示例和应用场景相同，但不限于上述实施例所公开的内容。需要说明的是，上述模块作为装置的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
本发明的实施例还提供了一种存储介质。在本实施例中，该存储介质包括存储的程序，程序运行时可以执行实施例中的方法的步骤的程序代码。
在一实施例中，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本发明的实施例还提供了一种处理器。在本实施例中，该处理器用于运行程序，程序运行时可以执行实施例中的方法的步骤的程序代码。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的较佳实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例中获取第一单板发送的与测试指令对应的第一测试信号；获取第二单板通过连接器接收到的第二测试信号，其中，所述连接器连接于所述第一单板和所述第二单板之间；比较所述第一测试信号与所述第二测试信号；根据比较结果，确定所述连接器上的管脚是否存在故障。如此，解决了相关技术中针对背板连接器的测试方案成本高且无法应用于正在使用的产品中连接器测试的问题，进而达到了不需要开发测试接口卡，而是在现有的产品基础上，通过与连接器相连的业务单板间接实现连接器测试的目的，从而实现了减少开发测试接口卡的成本的技术效果。

Claims (18)

  1. 一种连接器的测试方法，包括：
    获取第一单板发送的与测试指令对应的第一测试信号；
    获取第二单板通过连接器接收到的第二测试信号，其中，所述连接器连接于所述第一单板和所述第二单板之间；
    比较所述第一测试信号与所述第二测试信号；
    根据比较结果，确定所述连接器上的管脚是否存在故障。
  2. 根据权利要求1所述的方法，其中，在获取第一单板发送的与测试指令对应的测试信号之前，所述方法还包括：
    产生所述测试指令；
    将所述测试指令发送给所述第一单板，其中，所述第一单板内预先存储有与所述测试指令对应的至少一种测试信号。
  3. 根据权利要求2中所述的方法，其中，所述测试指令至少包括如下任意一种：
    第一故障测试指令，用于检测所述连接器的管脚与地管脚连接引起的低电平故障；
    第二故障测试指令，用于检测所述连接器的管脚与电源管脚连接引起的高电平故障；
    第三故障测试指令，用于检测所述连接器的管脚与相邻管脚连接引起的短路故障。
  4. 根据权利要求3中所述的方法，其中，所述第一测试信号和所述第二测试信号为由1和0组成的序列，其中，与1码对应的管脚的电平为高电平，与0码对应的管脚的电平为低电平。
  5. 根据权利要求4所述的方法，其中，在所述测试指令为第一故障测试指令的情况下，所述第一测试信号为全1序列，其中，根据比较结果， 确定所述连接器上的管脚是否存在故障，包括：
    如果所述第二测试信号全为高电平，则确定所述连接器上的管脚不存在低电平故障；
    如果所述第二测试信号中至少有一位为低电平，则确定所述连接器上的管脚存在所述低电平故障，并且，所述连接器上与所述低电平对应的管脚位置为存在所述低电平故障的管脚位置。
  6. 根据权利要求4所述的方法，其中，在所述测试指令为第二故障测试指令的情况下，所述第一测试信号为全0序列，其中，根据比较结果，确定所述连接器上的管脚是否存在故障，包括：
    如果所述第二测试信号为全为低电平，则确定所述连接器上的管脚不存在高电平故障；
    如果所述第二测试信号中至少有一位为高电平，则确定所述连接器上的管脚存在所述高电平故障，并且，所述连接器上与所述高电平对应的管脚位置为存在所述高电平故障的管脚位置。
  7. 根据权利要求4所述的方法，其中，在所述测试指令为第三故障测试指令的情况下，所述第一测试信号为0和1相间出现的序列，其中，根据比较结果，确定所述连接器上的管脚是否存在故障，包括：
    如果读取到所述第二测试信号没有出现三个连续相等的电平，则确定所述连接器上的管脚不存在所述短路故障；
    如果读取到所述第二测试信号出现三个连续相等的电平，则确定所述连接器上与所述连续相等的电平对应的三个管脚中至少有两个管脚存在所述短路故障。
  8. 根据权利要求7所述的方法，其中，在如果读取到所述第二测试信号出现三个连续相等的电平，则确定所述连接器上与所述连续相等的电平对应的三个管脚中至少有两个管脚存在所述短路故障之后，所述方法还包 括：
    将所述第一测试信号中与所述三个管脚中中间管脚对应的序列码设置为高电平或低电平，其他位设置为相反的电平，重新发送至所述第一单板上的第一主芯片管脚；
    检测所述第二单板上的第二主芯片管脚接收到的第二测试信号；
    根据检测结果，确定所述连接器上存在所述短路故障的管脚。
  9. 根据权利要求8所述的方法，其中，根据检测结果，确定所述连接器上存在所述短路故障的管脚，包括：
    如果所述三个管脚中前两个管脚的电平相同，则确定所述连接器上与所述前两个管脚对应的两个管脚存在所述短路故障；
    如果所述三个管脚中后两个管脚的电平相同，则确定所述连接器上与所述前两个管脚对应的两个管脚存在所述短路故障；
    如果所述三个管脚中的三个管脚的电平均相同，则确定所述连接器上所述三个管脚均存在所述短路故障。
  10. 根据权利要求1所述的方法，其中，所述连接器一侧的管脚与所述第一单板内至少一个第一主芯片的管脚相连，所述连接器另一侧的管脚与所述第二单板内至少一个第二主芯片的管脚相连；
    其中，通过所述第一主芯片的Jtag接口将所述第一测试信号发送至所述第一主芯片的管脚；通过所述第二主芯片的Jtag接口读取所述第二主芯片的管脚接收到的第二测试信号。
  11. 一种连接器的测试装置，包括：
    第一获取模块，配置为获取第一单板发送的与测试指令对应的第一测试信号；
    第二获取模块，配置为获取第二单板通过连接器接收到的第二测试信号，其中，所述连接器连接于所述第一单板和所述第二单板之间；
    比较模块，配置为比较所述第一测试信号与所述第二测试信号；
    确定模块，配置为比较所述第一单板发送的测试信号与所述第二单板接收到的测试信号。
  12. 根据权利要求11所述的装置，其中，所述装置还包括：
    生成模块，配置为产生所述测试指令；
    发送模块，配置为将所述测试指令发送给所述第一单板，其中，所述第一单板内预先存储有与所述测试指令对应的至少一种测试信号。
  13. 一种电子设备，包括：
    控制板，配置为产生测试指令；
    第一单板，与所述控制板连接，配置为发送与所述测试指令对应的第一测试信号；
    第二单板，与所述第一单板通过连接器连接，配置为接收通过所述连接器接收到的第二测试信号；
    其中，所述控制板，配置为比较所述第一测试信号与所述第二测试信号，并根据比较结果，确定所述连接器上的管脚是否存在故障。
  14. 根据权利要求13所述的电子设备，其中，所述第一单板包括：第一主芯片和配置为对所述第一主芯片的管脚进行测试的第一逻辑芯片，其中，所述第一主芯片具有第一Jtag接口，与所述第一逻辑芯片通过所述第一Jtag接口通信；
    所述第二单板包括：第二主芯片和配置为对所述第二主芯片的管脚电平进行测试的第二逻辑芯片，其中，所述第二主芯片具有第二Jtag接口，与所述第二逻辑芯片通过所述第二Jtag接口通信。
  15. 根据权利要求14所述的电子设备，其中，所述连接器一侧的管脚与所述第一单板内至少一个第一主芯片的管脚相连，所述连接器另一侧的管脚与所述第二单板内至少一个第二主芯片的管脚相连。
  16. 根据权利要求15所述的电子设备，其中，
    所述第一单板还包括：第一控制单元，配置为通过本地总线控制所述第一逻辑芯片；
    所述第二单板还包括：第二控制单元，配置为通过本地总线控制所述第二逻辑芯片。
  17. 一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行权利要求1至10中任一项所述的连接器的测试方法。
  18. 一种连接器的测试装置，包括：处理器和存储器；
    所述存储器，配置为保存进行熵解码的程序；
    所述处理器，配置为运行程序，其中，所述程序运行时执行权利要求1至10中任一项所述的连接器的测试方法。
PCT/CN2018/074275 2017-05-05 2018-01-26 连接器的测试方法、装置及存储介质 WO2018201763A1 (zh)

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