WO2018201690A1 - 扫描驱动电路及其驱动方法、阵列基板和显示装置 - Google Patents

扫描驱动电路及其驱动方法、阵列基板和显示装置 Download PDF

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Publication number
WO2018201690A1
WO2018201690A1 PCT/CN2017/111183 CN2017111183W WO2018201690A1 WO 2018201690 A1 WO2018201690 A1 WO 2018201690A1 CN 2017111183 W CN2017111183 W CN 2017111183W WO 2018201690 A1 WO2018201690 A1 WO 2018201690A1
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Prior art keywords
circuit
transistor
output
pole
node
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Ceased
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PCT/CN2017/111183
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English (en)
French (fr)
Inventor
赵剑
陈沫
高吉磊
张杨
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/062,763 priority Critical patent/US10950153B2/en
Publication of WO2018201690A1 publication Critical patent/WO2018201690A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display, and in particular, to a scan driving circuit and a driving method thereof, an array substrate, and a display device.
  • the Gate Driver On Array (GOA) technology can not only save the circuit board carrying the gate driver, but also realize the symmetrical design on both sides of the display panel, and can also eliminate the chip on the edge of the display panel.
  • the binding area and the wiring area such as the fan-out area facilitate the implementation of the narrow bezel design.
  • GOA technology can eliminate the chip bonding process in the row direction, it will also greatly help the overall productivity and yield improvement.
  • several stages of GOA units with the same structure are respectively connected to one row scanning line, and based on the cascade relationship between the GOA units, the scanning signal can be driven line by line on several line scanning lines driven by an external signal. Output.
  • TFTs Thin Film Transistors
  • the present disclosure provides a scan driving circuit and a driving method thereof, an array substrate, and a display device, which can further reduce the number of transistors required for a gate driver based on the existing GOA cell structure.
  • the present disclosure provides a scan driving circuit including an m-level output terminal, an m-level input circuit, and q shift register circuits, wherein q is a positive integer smaller than an integer m;
  • the first end of the input circuit of the i-th stage is connected to the output end of the i-1th stage, and the i is greater than 1 And any integer less than m+1;
  • Any one of the shift register circuits is respectively connected to the k output terminals, and is connected to the second ends of the k input circuits, wherein the k input circuits and the k output terminals have the same level Combination of sequence numbers, the sequence numbers in the same combination of sequence numbers have the same parity, the k is greater than 1 and less than m;
  • the shift register circuit is configured to be capable of outputting a scan signal to one of the connected k output terminals, and to which of the output end output scan signals is indicated by an external control signal.
  • the input circuit is configured to switch the shift register circuit connected to the second end to a charging state when the first end receives the scan signal; the shift register circuit is configured The scan signal is output to one of the connected k output terminals from the turn-off timing of the first clock signal after being switched to the charge state.
  • the scan driving circuit further includes an m-level reset circuit;
  • a first end of the reset circuit of the jth stage is connected to the output end of the j+1th stage, and the j is an arbitrary integer greater than 0 and less than m;
  • a shift register circuit respectively connected to the k output terminals is further connected to the second ends of the k reset circuits, wherein the k reset circuits and the k output terminals have the same combination of level numbers;
  • the reset circuit is configured to cause the shift register circuit connected to the second end to stop outputting the scan signal when the first end receives the scan signal.
  • the external control signal is provided by k control signal lines
  • the shift register circuit includes an output circuit unit and k transistors
  • the output circuit unit includes an output node
  • the output circuit unit is configured to be capable of outputting a scan signal to the output node
  • the first poles of the k transistors are all connected to the output node;
  • the gates of the k transistors are each connected to one of the k control signal lines;
  • the second poles of the k transistors are each connected to one of the k output terminals;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the shift register circuit includes an output circuit unit, and the output circuit unit includes an output node; the output circuit unit further includes a first transistor and a first capacitor, and the input circuit includes Two transistors; among them,
  • the gate of the first transistor is connected to the first node, and the second pole is connected to the output node; the first node is connected to the second ends of the k input circuits;
  • the first a first pole of the transistor is connected to the first clock signal line; in a shift register circuit in which the stage numbers in the corresponding stage number combination are all even, the first pole of the first transistor is connected to the second clock signal line;
  • the first clock signal line and the second clock signal line respectively provide one of a positive phase clock signal and an inverted clock signal;
  • the first end of the first capacitor is connected to the first node, and the second end is connected to the output node;
  • the gate of the second transistor is connected to the first end of the input circuit, the first pole is connected to the first level voltage line or the first end of the input circuit, and the second pole is connected to the second end of the input circuit;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the shift register circuit includes an output circuit unit, the output circuit unit includes an output node, and the output circuit unit further includes a first transistor, a first capacitor, a third transistor, and a fourth a transistor, the reset circuit comprising a fifth transistor;
  • the gate of the first transistor is connected to the first node, and the second pole is connected to the output node; the first node is connected to the second ends of the k input circuits;
  • the first pole of the first transistor is connected to the first clock signal line; the level numbers in the corresponding level number combination are all In the even shift register circuit, the first pole of the first transistor is connected to the second clock signal line; the first clock signal line and the second clock signal line respectively provide a positive phase clock signal and an inverted clock signal one of the;
  • the first end of the first capacitor is connected to the first node, and the second end is connected to the output node;
  • the gate of the third transistor is connected to the second ends of the k reset circuits, the first pole is connected to the first node, and the second pole is connected to the second level voltage line;
  • a gate of the fourth transistor is connected to the second ends of the k reset circuits, a first pole is connected to the output node, and a second pole is connected to the second level voltage line;
  • the gate of the fifth transistor and the first pole are connected to the first end of the reset circuit, and the second pole is connected to the second end of the reset circuit;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the output circuit unit further includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate of the sixth transistor is connected to the second node, the first pole is connected to the first node, and the second pole is connected to the second level voltage line;
  • a gate of the seventh transistor is connected to the second node, and a first pole is connected to the output node, The two poles are connected to the second level voltage line;
  • a gate of the eighth transistor is connected to the third node, and a second pole is connected to the second node; in the shift register circuit in which the serial number of the corresponding serial number combination is an odd number, the eighth transistor a first pole is connected to the second clock signal line; in a shift register circuit in which the stage numbers in the corresponding stage number combination are all even, the first pole of the eighth transistor is connected to the first clock signal line ;
  • a gate of the ninth transistor is connected to the first node, a first pole is connected to the second node, and a second pole is connected to a second level voltage line;
  • the gate and the first pole of the tenth transistor are both connected to the first pole of the eighth transistor, and the second pole is connected to the third node;
  • the gate of the eleventh transistor is connected to the first node, the first pole is connected to the third node, and the second pole is connected to the second level voltage line.
  • the shift register circuit includes an output circuit unit, the output circuit unit includes an output node, and the output circuit unit further includes a twelfth transistor.
  • the gate of the twelfth transistor is connected to the second clock signal line; the level numbers in the corresponding level number combination are all In the even shift register circuit, the gate of the twelfth transistor is connected to the first clock signal line; the first clock signal line and the second clock signal line respectively provide a positive phase clock signal and an inverted clock signal one of the;
  • a first pole of the twelfth transistor is connected to the output node, and a second pole of the twelfth transistor is connected to a second level voltage line;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the output circuit unit further includes a thirteenth transistor
  • the first node is connected to the second end of the k input circuits via the thirteenth transistor, and the first pole of the thirteenth transistor is connected to the second end of the k input circuits. a second pole of the thirteenth transistor is connected to the first node;
  • the gate of the thirteenth transistor is connected to the second clock signal line; the stage number in the corresponding level number combination In the even shift register circuit, the gate of the thirteenth transistor is connected to the first clock signal line.
  • the present disclosure further provides a driving method of any one of the above scan driving circuits, including:
  • p is any integer greater than 0 and less than m+1.
  • the present disclosure further provides a circuit unit of a scan driving circuit, the scan driving circuit includes an m-level output terminal, the circuit unit includes a shift register circuit and k input circuits, and the scan driving circuit The input circuit in the total of m stages, the k is greater than 1 and less than m;
  • a first end of the input circuit of the i-th stage is connected to the output end of the (i-1)th stage, and the i is an arbitrary integer greater than 1 and less than m+1;
  • the shift register circuit is respectively connected to the k output terminals, and is connected to the second ends of the k input circuits, and the k input circuits and the k output terminals have the same serial number combination , the sequence numbers in the same combination of sequence numbers have the same parity;
  • the shift register circuit is configured to be capable of outputting a scan signal to one of the connected k output terminals, and to which of the output end output scan signals is indicated by an external control signal.
  • the input circuit is configured to switch the shift register circuit connected to the second end to a charging state when the first end receives the scan signal; the shift register circuit is configured The scan signal is output to one of the connected k output terminals from the turn-off timing of the first clock signal after being switched to the charge state.
  • the circuit unit further includes k reset circuits, and the reset circuit in the scan driving circuit has a m level;
  • a first end of the reset circuit of the jth stage is connected to the output end of the j+1th stage, and the j is an arbitrary integer greater than 0 and less than m;
  • the shift register circuit is connected to the second ends of the k reset circuits, and the k reset circuits and the k output terminals have the same combination of stage numbers;
  • the reset circuit is configured to cause the shift register circuit connected to the second end to stop outputting the scan signal when the first end receives the scan signal.
  • the external control signal is provided by k control signal lines
  • the shift register circuit includes an output circuit unit and k transistors
  • the output circuit unit includes an output node
  • the output circuit unit is configured to be capable of outputting a scan signal to the output node
  • the first poles of the k transistors are all connected to the output node;
  • the gates of the k transistors are each connected to one of the k control signal lines;
  • the second poles of the k transistors are each connected to one of the k output terminals;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the shift register circuit includes an output circuit unit, and the output circuit unit includes an output node; the output circuit unit further includes a first transistor and a first capacitor, and the input circuit includes Two transistors; among them,
  • the first transistor has a gate connected to the first node, and a second node is connected to the output node; the first node is connected to the second end of the k input circuits;
  • the first pole of the first transistor is connected to the first clock signal line; the serial number in the corresponding level serial number combination In the shift register circuit of the even number, the first pole of the first transistor is connected to the second clock signal line; the first clock signal line and the second clock signal line respectively provide a positive phase clock signal and One of the inverted clock signals;
  • the first end of the first capacitor is connected to the first node, and the second end is connected to the output node;
  • the gate of the second transistor is connected to the first end of the input circuit, the first pole is connected to the first level voltage line or the first end of the input circuit, and the second pole is connected to the second end of the input circuit;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the shift register circuit includes an output circuit unit, the output circuit unit includes an output node, and the output circuit unit further includes a first transistor, a first capacitor, a third transistor, and a fourth a transistor, the reset circuit comprising a fifth transistor;
  • the first transistor has a gate connected to the first node, and a second node is connected to the output node; the first node is connected to the second end of the k input circuits;
  • the first pole of the first transistor is connected to the first clock signal line; the serial number in the corresponding level serial number combination In the shift register circuit of the even number, the first pole of the first transistor is connected to the second clock signal line; the first clock signal line and the second clock signal line respectively provide a positive phase clock signal and One of the inverted clock signals;
  • the first end of the first capacitor is connected to the first node, and the second end is connected to the output node;
  • a gate of the third transistor is connected to a second end of the k reset circuits, a first pole is connected to the first node, and a second pole is connected to a second level voltage line;
  • a gate of the fourth transistor is connected to the second end of the k reset circuits, a first pole is connected to the output node, and a second pole is connected to the second level voltage line;
  • the gate of the fifth transistor and the first pole are connected to the first end of the reset circuit, and the second pole is connected to the second end of the reset circuit;
  • first pole and the second pole are one of a source and a drain, respectively.
  • the present disclosure also provides an array substrate, including the scan driving circuit of any of the above.
  • the present disclosure also provides a display device comprising the array substrate of any of the above.
  • FIG. 1 is a structural block diagram of a scan driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a structural block diagram of a scan driving circuit provided by a comparative example of the present disclosure
  • FIG. 3 is a structural block diagram of a partial scan driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a structural block diagram of a partial scan driving circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a circuit structural diagram of a multiplexing group in a scan driving circuit according to an embodiment of the present disclosure
  • FIG. 6 is a circuit timing diagram of a multiplexing group in a scan driving circuit according to an embodiment of the present disclosure.
  • the scan driving circuit includes an m-level output terminal, an m-level input circuit, and q shift register circuits, where m is a positive integer greater than 1, and q is a positive integer less than m, and the specific value may be based on The actual application needs are determined.
  • the scan driving circuit includes an m-level output, an m-level input circuit, and q shift register circuits, the q being a positive integer less than an integer m, wherein:
  • the first end of the input circuit of the i-th stage is connected to the output of the i-1th stage, and the i is an arbitrary integer greater than 1 and less than m+1.
  • Any one of the shift register circuits is respectively connected to the k output terminals, and is connected to the second ends of the k input circuits, wherein the k input circuits and the k output terminals have the same level
  • the sequence numbers in the same combination of sequence numbers have the same parity
  • the k is greater than 1 and less than m.
  • the shift register circuit is configured to be capable of outputting a scan signal to one of the connected k output terminals, and to which of the output end output scan signals is indicated by an external control signal.
  • the scan driving circuit further includes an m-level reset unit and has a circuit structure as described below:
  • the input circuit and the output have the following connection relationship: for any integer i greater than 1 and less than m+1, the first end of the input circuit of the i-th stage is connected to the output of the i-1th stage.
  • the reset circuit and the output have the following connection relationship: for any integer j greater than 0 and less than m, the first end of the reset circuit of the jth stage is connected to the output of the j+1th stage.
  • the shift register circuit has a connection relationship: any shift register circuit is connected to each of the second ends of the k input circuits, connected to each of the second ends of the k reset circuits, and k outputs Each of the ends is connected (k is an integer greater than 1 and less than m). Moreover, the k input circuits and the k outputs have the same combination of stage numbers, and the k reset circuits and the k outputs also have the same combination of stage numbers. In addition, all of the sequence numbers in the same combination of stage numbers have the same parity.
  • the input circuit is configured to switch the shift register circuit connected to the second end to the charge state when the first end receives the scan signal; the shift register circuit is configured to be switched from being switched to the charge state The subsequent turning of the first clock signal begins to output a scan signal to one of the connected k output terminals, and to which of the output terminals the scan signal is indicated by an external control signal; the reset circuit is configured to be at the first end When the scan signal is received, the shift register circuit connected to the second terminal stops the output of the scan signal.
  • the above scan driving circuit has a structure as shown in FIG.
  • this paper uses a combination of capital letters "A” and numbers to indicate a certain level of input circuit (such as “A3” indicates the input circuit of level 3), and a combination of uppercase letter "B” and number indicates a certain level.
  • Reset circuit (such as "Bn” means the reset circuit of the nth stage), the combination of the uppercase letter “C” and the number represents the output of a certain stage (such as “Cn+1” represents the output of the n+1th stage ), a combination of the capital letter “G” and a number indicates a scan signal of a certain level (ie, corresponding to a certain stage number) (eg, "G0" indicates the start scan signal, and "G2" indicates the output of the second stage output. Scan signal).
  • the two reference nodes of the same scanning signal indicate the two nodes connected to each other (for example, the C1 connection G1 and the G1 connection A2 in FIG. 1 indicate that the output C1 of the first stage is connected to the second stage.
  • the scan driving circuit in this example includes a shift register unit SR_odd and a shift register unit SR_even.
  • the scan driver circuit also includes a 4-level output, a 4-level input circuit, and a 4-level complex.
  • a bit circuit wherein the shift register circuit SR_odd is connected to the second end of the two input circuits, is connected to the second end of the two reset circuits, and is respectively connected to the two output ends (the combination of the serial numbers is ⁇ 1, 3 ⁇ , The grade numbers are all odd numbers.
  • the first end of the input circuit A2 of the second stage is connected to the output C1 of the first stage, and the first end of the input circuit A3 of the third stage is connected to the output C2 of the second stage, the fourth stage
  • the first end of the input circuit A4 is connected to the output terminal C3 of the third stage, that is, the first end of the input circuit of the i-th stage is connected to the output end of the i-1th stage (1 ⁇ i ⁇ m+1) Connection relationship.
  • the first end of the reset circuit B1 of the first stage is connected to the output terminal C2 of the second stage, and the first end of the reset circuit B2 of the second stage is connected to the output terminal C3 of the third stage, the third stage
  • the first end of the reset circuit B3 is connected to the output terminal C4 of the fourth stage, that is, the connection having the above-mentioned "the first end of the reset circuit of the jth stage is connected to the output terminal of the j+1th stage" (0 ⁇ j ⁇ m) relationship.
  • the operation principle of the scan driving circuit of this example is as follows:
  • the shift register circuit SR_odd connected to the second terminal is switched to the charged state.
  • the shift register circuit SR_odd can start to output the scan signal G1 to the connected output terminal C1 at the time of the first clock signal turning (ie, the output terminal C1 is the shift register at this time).
  • the second input circuit A2 switches the shift register circuit SR_even connected to the second terminal to the charged state.
  • the shift register circuit SR_even can start to output the scan signal G2 to the connected output terminal C2 with the cooperation of the appropriate external control signal (ie, the output terminal C2 is shifted at this time).
  • the reset circuit B1 stops the output of the shift register circuit SR_odd connected to the second end.
  • the signal G1, and the input circuit A3 switches the shift register circuit SR_odd connected to the second end to the charged state, that is, the shift register circuit SR_odd is in the charged state but does not output the scan signal.
  • the shift register circuit SR_odd can start to output the scan signal G3 to the connected output terminal C3 with the cooperation of an appropriate external control signal (ie, at this time)
  • the output terminal C3 is an output terminal indicated by an external control signal among all the output terminals to which the shift register circuit SR_odd is connected.
  • the reset circuit B2 stops the output of the shift register circuit SR_even connected to the second end.
  • the signal G2, and the input circuit A4 switches the shift register circuit SR_even connected to the second terminal to the charged state, that is, the shift register circuit SR_even is in the charged state but does not output the scan signal.
  • the shift register circuit SR_even can start to output the scan signal G4 to the connected output terminal C4 with the cooperation of an appropriate external control signal (ie, the output terminal C4 is shifted at this time).
  • the reset circuit B3 stops the shift register circuit SR_odd connected to the second terminal from outputting the scan signal G3, and it is understood that The shift register circuit SR_odd does not output a scan signal until the next time it is switched to the charge state.
  • the scan driving circuit of the present example can realize the step-by-step output of the scan signal at the output terminals of the first to fourth stages with the cooperation of the above external signals.
  • the first end of the input circuit A1 of the first stage forms an input end of the scan driving circuit
  • the first end of the reset circuit B4 of the fourth stage forms a reset end of the scan driving circuit
  • the output ends of the first to fourth stages form a scan driving circuit 4 outputs.
  • clocking time of the clock signal may be the time at which the rising edge and/or the falling edge of the clock signal connected to the shift register circuit are located; it can be seen that the scanning signal is controlled by The timing of the stage outputs, so the clock signal can be configured at the time of implementation according to the timing required to be implemented.
  • a combination of a forward clock signal and an inverted clock signal may be used as a clock signal connected to the shift register circuit, and the timing at which the level is inverted is taken as the turn-over timing of the clock signal, and may not be limited thereto.
  • the above “external control signal” refers to an external signal connected to the shift register circuit, which can control which of the connected outputs is output by the shift register circuit.
  • the external control signal may be input into the scan driving circuit by a circuit structure such as a timing controller together with a clock signal, or may be connected to the scan driving circuit by an external circuit interface. And it is not limited to this.
  • charge state refers to an operating state of the shift register circuit, and the shift register circuit switched to the charge state starts to output the scan at the time of the first clock signal turning. signal.
  • the shift register circuit spontaneously recovers from the state of charge after stopping outputting the scan signal; in another implementation, the reset circuit receives the scan signal at the first end and the connected shift When the bit register circuit is not switched to the charge state by any one of the input circuits, the connected shift register circuit is restored from the charged state. Thereby, it is possible to reduce erroneous output or signal noise caused by the time during which the shift register circuit is maintained in the charged state is too long.
  • the scan driving circuit replaces two shift circuits with four stages of shift circuits SR_1, SR_2, SR_3, SR_4 on the basis of the structure shown in FIG. 1, and each shift The circuit is respectively connected with one input circuit, one reset circuit and one output terminal having the same serial number; the input circuit in this example is configured to move the second end when the first end receives the scan signal The bit circuit is switched to a charge state, and the shift circuit is configured to output a scan signal to the connected output terminal from a turn-off time of the first clock signal after being switched to the charge state, the reset circuit being configured to receive at the first end When the signal is scanned, the shift circuit connected to the second end stops the output of the scan signal.
  • the scan driving circuit in this example can achieve the same signal output as the scan driving circuit shown in Fig. 1 under the same external signal.
  • the shift register circuit SR_odd in the scan driving circuit shown in FIG. 1 realizes the functions of the shift circuit SR_1 and the shift circuit SR_3, and the shift register circuit.
  • SR_even realizes the functions of the shift circuit SR_2 and the shift circuit SR_4, that is, the scan drive circuit shown in FIG. 1 realizes the simplification of the internal structure of the scan drive circuit by multiplexing the circuit structure.
  • the scan driving circuit includes a plurality of sets of circuit structures as shown in FIG. 3 in addition to the circuit structure shown in FIG.
  • each group of circuit structures as shown in FIG. 3 can output a step-by-step output of the 4-level scan signal according to the same working principle as the circuit structure shown in FIG. 1.
  • the scan driving circuit may include a circuit structure as shown in FIG. Referring to FIG. 4, compared with the circuit structure shown in FIG. 3, the shift register circuit SR_even shown in FIG. 4 is connected to the second ends of the three input circuits, connected to the second ends of the three reset circuits, and The output terminals are respectively connected (the combination of the three input circuits, the three reset circuits and the three output terminals is ⁇ n+1, n+3, n+5 ⁇ , The sequence numbers are all odd or even. It is easily understood that the shift register circuit SR_even is functionally equivalent to a combination of three-stage shift circuits and has a similar operation principle to the shift register circuit SR_even shown in FIG.
  • a combination of the shift register circuit SR_even shown in FIG. 4 and the three input circuits connected thereto, three reset circuits, and three output terminals is hereinafter referred to as a multiplexing group, and the corresponding serial number combination is used. It may be a combination of any number of odd numbers in the range of 1 to m, or a combination of any number of even numbers in the range of 2 to m.
  • the scan drive circuit stage number shown in FIG. 1 is a combination of a multiplexing group of ⁇ 1, 3 ⁇ and a multiplexing group of a sequence number combination of ⁇ 2, 4 ⁇ ; the scan driving circuit shown in FIG. 3 includes a combination of level numbers.
  • the multiplexing group and the sequence number of ⁇ n, n+2 ⁇ are combined into a multiplexing group of ⁇ n+1, n+3 ⁇ ; the scan driving circuit shown in FIG. 4 includes the combination of the sequence numbers of ⁇ n, n+2
  • the multiplexing group and the stage number combination of ⁇ are a multiplexing group of ⁇ n+1, n+3, n+5 ⁇ .
  • ⁇ 1, 2, 3, ..., m ⁇ can be split into several groups of odd numbers.
  • a combination of sequence numbers and a number of combinations of sequence numbers consisting of even numbers for example, splitting ⁇ 1, 2, 3, ..., 10 ⁇ into ⁇ 1, 5, 9 ⁇ , ⁇ 3, 7 ⁇ , ⁇ 2, 8 ⁇ And ⁇ 4, 6, 10 ⁇ ), thereby forming a scan driving circuit by a multiplexing group corresponding to each stage number combination.
  • a plurality of individual stage numbers can also be split, and the shift circuit shown in FIG. 2 and its connected input circuit, reset circuit and output terminal form part of the circuit corresponding to the serial numbers of the scan drive circuit.
  • Structure for example, the input circuit, the reset circuit, the output terminal, and the shift circuit corresponding to the sequence number n+4 are set in the circuit structure as shown in FIG. 3 to receive the scan signal of the n+3th stage and output the first n+4 scan signal).
  • the structure of the scan driving circuit as described in any of the above general examples can be obtained.
  • the embodiment of the present disclosure can multiplex a shift register circuit between multiple stages, thereby maintaining signal input and output.
  • the circuit structure is simplified, and the number of transistors required for the gate driver is further reduced on the basis of the existing GOA unit structure, which helps to solve the problem that the space occupied by the GOA unit in the related art is difficult to compress and the frame is difficult to narrow. It is beneficial to simplify the structure of the gate driver, reduce the installation space of the gate driver, and break through the bottleneck of the related products in the narrowing of the frame.
  • FIG. 5 is a circuit structural diagram of a multiplexing group according to an embodiment of the present disclosure, that is, a circuit structure diagram of a circuit unit of a scan driving circuit according to an embodiment of the present disclosure, which is combined with the serial numbers of FIG. 3 and FIG.
  • the circuit structure of the multiplexing group of ⁇ n, n+2 ⁇ shows an optional circuit structure of the multiplexing group as an example.
  • the transistors shown in FIG. 5 are exemplarily all N-type transistors, that is, can be formed by the same fabrication process to reduce manufacturing costs.
  • the connection relationship between the source and the drain is respectively matched to the direction of the current flowing through the transistor; when the transistor has a structure in which the source and the drain are symmetric, the source and the drain can be regarded as not particularly distinguishing Two electrodes.
  • one of the source and the drain is referred to by the first pole and the second pole, respectively.
  • the output circuit unit MR has an output node PO connected to the first poles of the k control transistors.
  • the output circuit unit MR is configured to output a scan signal to the output node PO from a first clock inversion time after the shift register circuit is switched to the charge state; the gates of the k control transistors are each connected to the k control signal lines One, the second poles of the k control transistors are each connected to one of the k output terminals to form a circuit connection relationship as shown in FIG. It is easy to understand that for the multiplexing group with k>2, the number of control signal lines and control transistors is still consistent with k.
  • the driving method of the scan driving circuit in any of the above general examples may include: applying an external control signal to the scan driving circuit to input at the p-th stage When the circuit switches the connected shift register circuit to the charge state, the shift register circuit outputs a scan signal to the output end of the p-th stage from the turn-off time of the first clock signal after being switched to the state of charge; p is an arbitrary integer greater than 0 and less than m+1.
  • the output circuit unit MR includes a first transistor T1 and a first capacitor C1, wherein the gate of the first transistor T1 is connected to the first node PU, the first pole is connected to the first clock signal line CK1, and the second The pole is connected to the output node PO; the first node PU is indirectly connected to the second end of the k input circuits (in still another example, the first node PU may be directly connected to the second end of the k input circuits, and the first The setting of the thirteenth transistor M13); the first end of the first capacitor C1 is connected to the first node PU, and the second end is connected to the output node PO.
  • the output circuit unit MR can realize the above-described first pole output of the connected control transistor starting from the first clock inversion time after the shift register circuit is switched to the charged state.
  • the function of the scanning signal the specific implementation will be detailed in the working principle of the following.
  • the clock signal in the above specifically includes the positive phase clock signal provided by the first clock signal line CK1 and the inverted clock signal provided by the second clock signal line CK2 in the present embodiment (in yet another example)
  • the positive phase clock signal is provided by the second clock signal line CK2
  • the inverted clock signal is composed of the first clock signal line CK1), and the combination of the odd numbered combination of the number and the serial number combination is even.
  • the clock signals are connected between groups.
  • the first pole of the first transistor T1 is connected to the first clock signal line CK1
  • the first pole of a transistor T1 is connected to the second clock signal line CK2.
  • the description is made by taking an odd number in the combination of the sequence numbers as an example.
  • each of the input circuits - the input circuit An and the input circuit An + 2 each includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the first end of the input circuit
  • the first pole is connected to the first end of the input circuit
  • the second pole is connected to the second end of the input circuit.
  • the input circuit can implement the above-mentioned function of switching the shift register circuit connected to the second end to the charging state when the first end receives the scan signal, and the specific implementation manner will be described in detail in the following working principle.
  • the first pole of the second transistor T2 may be connected to the first level voltage line not shown in the drawing (for example, loading a high level voltage) without connecting the first end of the input circuit. Signal line), and may not be limited to this.
  • the output circuit unit MR further includes a third transistor T3 and a fourth transistor T4, and each of the reset circuits, the reset circuit Bn and the reset circuit Bn+2, respectively comprise a fifth transistor T5.
  • the gate of the third transistor T3 is connected to the second end of the k reset circuits, the first pole is connected to the first node PU, and the second pole is connected to the second level voltage line Vss (for example, a signal line for loading a low-level voltage)
  • the gate of the fourth transistor T4 is connected to the second end of the k reset circuits, the first pole is connected to the output node PO, the second pole is connected to the second level voltage line Vss; the gate of the fifth transistor T5 and the first pole are both The first end of the reset circuit is connected, and the second end is connected to the second end of the reset circuit.
  • the reset circuit can realize the function of stopping the output of the scan signal by the shift register circuit connected to the second end when the scan signal is received at the first end, and the specific implementation manner will
  • the output circuit unit MR further includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, wherein: the sixth transistor T6 The gate is connected to the second node PD, the first pole is connected to the first node PU, the second pole is connected to the second level voltage line Vss; the gate of the seventh transistor T7 is connected to the second node PD, and the first pole is connected to the output node PO, The second pole is connected to the second level voltage line Vss. The gate of the eighth transistor T8 is connected to the third node PC, the second pole is connected to the second node PD.
  • the first pole of the eighth transistor T8 is connected to the second clock signal line CK2; in the multiplexing group having even numbers in the combination of the stage numbers, the eighth transistor T8 One pole is connected to the first clock signal line CK1.
  • the gate of the ninth transistor T9 is connected to the first node PU, the first pole is connected to the second node PD, the second pole is connected to the second level voltage line Vss; the gate of the tenth transistor T10 is connected to the first pole to the eighth transistor T8 The first pole, the second pole is connected to the third node PC; the gate of the eleventh transistor T11 is connected to the first node PU, the first pole is connected to the third node PC, and the second pole is connected to the second level voltage line Vss.
  • the above output circuit unit MR can operate in a more stable state when the scan signal is not output, and the specific principle will be described in detail later in the working principle.
  • the output circuit unit MR further includes a twelfth transistor T12.
  • the gate of the twelfth transistor T12 is connected to the second clock signal line CK2;
  • the gate of the twelfth transistor T12 is connected to the first clock signal line CK1.
  • the first pole of the twelfth transistor T12 is connected to the output node PO, and the second pole of the twelfth transistor T12 is connected to the second level voltage line Vss. Based on this, the twelfth transistor T12 can assist in resetting the signal when the scan signal output is stopped, which is advantageous for improving the reset speed and the operational stability of the circuit, and the specific principle thereof will be described in detail in the following working principle.
  • the output circuit unit MR further includes a thirteenth transistor T13.
  • the first node PU and the second end of the k input circuits are further connected by a thirteenth transistor T13, and the first pole of the thirteenth transistor T13 is connected to the second end of the k input circuits, and the thirteenth transistor T13 The second pole is connected to the first node PU.
  • the gate of the thirteenth transistor T13 is connected to the second clock signal line CK2; in the multiplexing group which is even in the combination of the stage numbers, the thirteenth transistor T13 The gate is connected to the first clock signal line CK1.
  • the thirteenth transistor T13 can assist in switching and restoring the state of charge, which is advantageous for improving the charging speed, the recovery speed, and the operational stability of the circuit. The specific principle will be described in detail in the following working principle.
  • FIG. 6 is a circuit timing diagram of the multiplexing group in the scan driving circuit according to the embodiment of the present disclosure.
  • the working principle of the multiplexing group is as follows:
  • the scan signals involved in the multiplexing group are kept at a low level, so the second transistor T2, the fifth transistor T5, the third transistor T3, and the fourth transistor T4 are all kept off.
  • the clock signals on the first clock signal line CK1 and the second clock signal line CK2 are periodically inverted with each other, which causes the tenth transistor T10 of all the output circuit units MR to which they are connected to be periodically turned on, so that the third node PC is The period is periodically set to a high level, and then the eighth transistor T8 is turned on, so that the second node PD is also set to a high level.
  • the sixth transistor T6 and the seventh crystal are acted upon by the high level at the second node PD
  • the opening of the body tube T7 will keep the first node PU and the output node PO low.
  • the ninth transistor T9 and the eleventh transistor T11 remain off, and the potential pull-down of the second node PD and the third node PC is not performed; the first transistor T1 remains off, and the potential pull-up is not performed on the output node PO.
  • the clock signal causes the twelfth transistor T12 and the thirteenth transistor T13 to be periodically turned on, helping to maintain the second end of the k input circuits, at the first node PU, and at the output node PO low.
  • the first control signal line Ra and the second control signal line Rb are also loaded with a periodically inverted signal such that the two control transistors Ta and Tb are alternately turned on; and since the output node PO is kept at a low level, the output is The potential at the terminal Cn and the output terminal Cn+2 is also periodically pulled down, so that the output signal can be kept stable.
  • the scan signal Gn-1 is turned to a high level (ie, the output is started), the second clock signal line CK2 is at a high level, and the first clock signal line CK1 is at a low level, thereby inputting an circuit An.
  • the second transistor T2 is turned on, and the thirteenth transistor T13 is turned on, so that the first node PU is pulled up to a high level.
  • the first transistor T1, the ninth transistor T9, and the eleventh transistor T11 are turned on, and the second node PD and the third node PC are set to a low level, stopping at the first node PU and the output node PO The potential is pulled down.
  • the output node PO is kept at a low level by the cooperation of the first clock signal line CK1 and the second level voltage line Vss.
  • the first end of the first capacitor C1 is at a high level, and the second end is at a low level, that is, charging at both ends of the capacitor is completed (ie, switching to a charged state).
  • the scan signal Gn-1 is turned to a low level (ie, the output is stopped), the second clock signal line CK2 is at a low level, the first clock signal line CK1 is at a high level, and the twelfth transistor is T12 and the thirteenth transistor T13 are turned off.
  • the first node PU will jump to a higher level with a change from a low level to a high level on the first clock signal line CK1. .
  • This causes the first transistor T1 to be fully turned on, quickly completing the potential pull-up at the output node PO.
  • the first control signal line Ra is at a high level and the control transistor Ta is turned on, so that a high level is output at the output terminal Cn, that is, the scan signal Gn starts to be output.
  • the scan signal Gn+1 turns to a high level (ie, starts outputting), the second clock signal line CK2 is at a high level, the first clock signal line CK1 is at a low level, and the first control The signal line Ra is at a high level and the control transistor Ta is turned on.
  • the second transistor T2 in the input circuit An+2 and the fifth transistor T5 in the reset circuit Bn are turned on, so that the third transistor T3 pulls down the potential at the first node PU.
  • the second transistor T2 and the thirteenth transistor T13 perform a potential pull-up on the first node PU.
  • the device parameter relationship between T3 and the thirteenth transistor T13 enables the first node PU in this phase to be at a high level.
  • the first transistor T1, the fourth transistor T4, and the twelfth transistor T12 are turned on, so that the first and second poles of the control transistor Ta cooperate in the first clock signal line CK1 and the second level voltage line Vss.
  • the lower side is pulled down to a low level, that is, the scan signal Gn stops outputting.
  • the first end of the first capacitor C1 is at a high level
  • the second end is at a low level, that is, charging at both ends of the capacitor is completed (ie, switching to a charged state).
  • the source-drain equivalent resistances of the second transistor T2, the third transistor T3, and the thirteenth transistor T13 are R2, R3, and R13, respectively, and the high level voltage of the scan signal is Vgh, and the second power
  • the low level voltage on the flat voltage line Vss is Vgl, and the voltage at the first node PU is V1
  • the channel width-to-length ratio of the general transistor is larger, the source-drain equivalent resistance is smaller, so that the second transistor T2, the third transistor T3, and the thirteenth transistor T13 satisfy the above formula by the corresponding arrangement, satisfying the first
  • the node PU is in the third phase 3 requiring a high level.
  • the scan signal Gn+1 is turned to a low level (ie, the output is stopped), the second clock signal line CK2 is at a low level, the first clock signal line CK1 is at a high level, and the twelfth transistor is T12 and the thirteenth transistor T13 are turned off.
  • the first node PU will jump to a higher level with a change from a low level to a high level on the first clock signal line CK1. .
  • This causes the first transistor T1 to be fully turned on, quickly completing the potential pull-up at the output node PO.
  • the second control signal line Rb is at a high level and the control transistor Tb is turned on, so that a high level is output at the output terminal Cn+2, that is, the scan signal Gn+2 starts to be output.
  • the scan signal Gn+3 turns to a high level (ie, starts outputting), the second clock signal line CK2 is at a high level, the first clock signal line CK1 is at a low level, and the second control The signal line Rb is at a high level and the control transistor Tb is turned on.
  • the fifth transistor T5 in the reset circuit Bn+2 is turned on, so that the third transistor T3 pulls down the potential at the first node PU, and the fourth transistor T4 performs the output node PO.
  • the potential is pulled down. Since no second transistor T2 achieves a pull-up of the potential at the first node PU at this time, the first node PU is set to a low level.
  • the ninth transistor T9 stops pulling down the potential at the second node PD
  • the eleventh transistor T11 stops pulling down the potential at the third node PC.
  • the tenth transistor T10 is turned on and the third node PC is set to the high level
  • the eighth transistor T8 is turned on.
  • the two-node PD is set to a high level.
  • the opening of the sixth transistor T6 and the seventh transistor T7 causes the first node PU and the output node PO to be set low.
  • the first and second poles of the control transistor Tb are pulled down to a low level by the cooperation of the first clock signal line CK1 and the second level voltage line Vss. Thereafter, the reset group will continue to be in the operational state prior to the first phase 1 described above until the first phase 1 of the next cycle begins.
  • the input circuit, the reset circuit, and the shift register circuit all realize their respective functions.
  • the circuit structure of the reset group of other serial numbers combined can be obtained.
  • it can realize the functions of the above-described scan driving circuit in cooperation with the clock signal and the external control signal, and obviously can have fewer transistors than the existing structure.
  • the transistors included in the shift register circuit are not all necessary to realize their functions.
  • the thirteenth transistor T13 and the twelfth transistor T12 can still be realized without being set.
  • the circuit timing shown in Figure 6, but its setting helps to optimize the signal output characteristics of the shift register circuit.
  • the components included in the above shift register circuit need not all be disposed in the scan driving circuit, for example, the two control transistors Ta and Tb may be disposed at any position between the gate driver and the row scanning line.
  • the output circuit unit MR after the first clock signal line CK1 and the second clock signal line CK2 are exchanged can be used. It is used as the above-described shift circuit corresponding to the even-numbered serial number, and may not be limited thereto.
  • a reset transistor can be provided for the output end of each stage (the first end is connected to the output end of a certain stage, the second end is connected to the second level voltage line, and the second end of the reset circuit of the gate is connected to the same stage serial number) a second node in the shift register circuit of the same level or a clock signal that does not affect the output of the scan signal).
  • the functions of at least one of the reset transistor and the fourth transistor T4, the seventh transistor T7, and the twelfth transistor T12 are repeated to some extent, only one of them may be retained according to the application requirement, or two functions may be Implementations are combined with one another to achieve better signal output characteristics.
  • the first pole of any one or more of the fourth transistor T4, the seventh transistor T7, and the twelfth transistor T12 may be connected to the second end of the control transistor Ta or controlled.
  • the second end of the transistor Tb may also set the number of any one or more of the fourth transistor T4, the seventh transistor T7, and the twelfth transistor T12 to two, so that the first poles of the two transistors are uniquely Connected to the control transistor Ta
  • the second end and the second end of the control transistor Tb are used to better eliminate noise.
  • the setting of the m-level reset circuit can be replaced by the following manner, while the output timing of the scan driving circuit is unchanged: the shift register circuit is configured to receive The output of the scan signal is stopped when the first level on the connected reset clock signal line is reached.
  • the reset clock signal line to which it is connected is at a level other than the first level.
  • the reset clock signal line connected to the shift register circuit whose corresponding serial number is all odd is the second clock signal line, and the corresponding reset circuit signal line whose serial number is equal to the shift register circuit connected to the even number. Is the first clock signal line.
  • the gates of the third transistor T3 and the gate of the fourth transistor T4 may be connected to the second clock signal line CK2 on the basis of the circuit configuration shown in FIG.
  • the second clock signal line CK2 replaces the role of the scanning signal Gn+1 in the third stage 3, and can replace the effect of the scanning signal Gn+3 in the fifth stage 5, while not affecting the scanning in the second stage 2
  • the output of the signal Gn will not affect the output of the scan signal Gn+2 in the fourth stage 4, but only in the first stage 1 will hinder the potential pull-up at the first node PU, and will be based on the third In the phase 3, the first node PU is at the same high level, so that the first node PU in the first phase 1 is also at the high level.
  • the embodiment of the present disclosure can realize the shift register circuit at multiple levels based only on the connection of the shift register circuit with the multi-stage input circuit and the multi-stage output terminal.
  • the multiplexing between them makes it possible to simplify the circuit structure while maintaining the signal input/output relationship and to simplify the structure of the gate driver.
  • the configuration of the input circuit and the shift register circuit can be changed as follows, while the output timing of the scan driving circuit is unchanged: the input circuit is configured to be in the first When the terminal receives the scan signal, the shift register circuit is brought into the first mode, and the shift register circuit is configured to enter the second mode when the trigger signal is received in the first mode, and to the connected k outputs in the second mode.
  • the reset circuit can be configured to cause the shift register circuit to exit the second mode when the first end receives the scan signal. After exiting, if any input circuit connected to the shift register circuit is in an active state, the shift register circuit returns to the first mode; otherwise, the shift register circuit directly exits the second mode and the first mode until the next time A mode.
  • the first mode is the charging state described above
  • the trigger signal is the flipping of the clock signal described above
  • the second mode that is, the shift register circuit described above is The operating state when a scan signal is output to one of the k output terminals connected.
  • the shifting The output circuit unit in the register circuit is equivalent to a shift register
  • the first mode that is, the shift register stores a state of a level corresponding to the scan signal, that is, a trigger shift such as a falling edge or a rising edge
  • the register outputs the state of the level corresponding to the stored scan signal.
  • the embodiment of the present disclosure can implement the shift register circuit based on the connection of the shift register circuit with the multi-stage input circuit and the multi-stage output terminal, respectively. It is multiplexed between multiple stages, so that the circuit structure can be simplified while maintaining the signal input-output relationship, and the structure of the gate driver can be simplified.
  • an embodiment of the present disclosure further provides a circuit unit of a scan driving circuit, the scan driving circuit includes an m-level output terminal, and the circuit unit includes a shift register circuit and k input circuits.
  • the input circuit in the scan driving circuit has a total of m stages, and the k is greater than 1 and less than m;
  • a first end of the input circuit of the i-th stage is connected to the output end of the (i-1)th stage, and the i is an arbitrary integer greater than 1 and less than m+1;
  • the shift register circuit is respectively connected to the k output terminals, and is connected to the second ends of the k input circuits, and the k input circuits and the k output terminals have the same serial number combination , the sequence numbers in the same combination of sequence numbers have the same parity;
  • the shift register circuit is configured to be capable of outputting a scan signal to one of the connected k output terminals, and to which of the output end output scan signals is indicated by an external control signal.
  • the input circuit is configured to switch the shift register circuit connected to the second end to a charging state when the first end receives the scan signal; the shift register circuit is configured The scan signal is output to one of the connected k output terminals from the turn-off timing of the first clock signal after being switched to the charge state.
  • the circuit unit further includes k reset circuits, and the reset circuit in the scan driving circuit has a m level;
  • a first end of the reset circuit of the jth stage is connected to the output end of the j+1th stage, and the j is an arbitrary integer greater than 0 and less than m;
  • the shift register circuit is connected to the second ends of the k reset circuits, and the k reset circuits and the k output terminals have the same combination of stage numbers;
  • the reset circuit is configured to cause the shift register circuit connected to the second end to stop outputting the scan signal when the first end receives the scan signal.
  • any of the multiplexing groups described above may be considered as a circuit of an embodiment of the present disclosure.
  • An implementation example of the unit, and the manner in which the multiplexing group is repeated in the scan driving circuit has been described in detail, and details are not described herein again.
  • the embodiment of the present disclosure can make a shift register circuit multiplex between multiple stages, so that The circuit structure is simplified while maintaining the signal input/output relationship, and the number of transistors required for the gate driver is further reduced on the basis of the existing GOA unit structure, which is advantageous for simplifying the structure of the gate driver and reducing the installation space of the gate driver.
  • an embodiment of the present disclosure further provides an array substrate including the scan driving circuit of any of the above. Based on the small footprint of the scan driver circuit, the GOA area on the array substrate can be designed to be smaller, which helps to achieve a narrower display frame.
  • an embodiment of the present disclosure further provides a display device including any array substrate.
  • the display device in the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device can have a narrower display bezel based on the small footprint of the scan driving circuit.

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Abstract

一种扫描驱动电路及其驱动方法、阵列基板和显示装置，属于显示领域。该扫描驱动电路包括m级输出端、m级输入电路和q个移位寄存电路；第i级的输入电路的第一端连接第i-1级的输出端，i为大于1且小于m+1的任意整数；任一移位寄存电路分别连接k个输出端，并与k个输入电路的第二端相连，k个输入电路与k个输出端之间具有相同的级序号组合，相同的级序号组合中的级序号均具有相同的奇偶性，k大于1且小于m；移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个输出端输出扫描信号由外部控制信号指示。

Description

扫描驱动电路及其驱动方法、阵列基板和显示装置
本公开要求于2017年5月5日提交中国国家知识产权局、申请号为201710312219.9、发明名称为“扫描驱动电路及其驱动方法、阵列基板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示领域，特别涉及一种扫描驱动电路及其驱动方法、阵列基板和显示装置。
背景技术
阵列基板行驱动(Gate driver On Array，GOA)技术相较于传统工艺而言，不仅能省去承载栅极驱动器的电路板、实现显示面板两边对称的设计，还能省去显示面板边缘上芯片绑定区域和例如扇出区的布线区域，有利于窄边框设计的实现。同时，由于GOA技术可以省去行方向上的芯片绑定工艺，对整体的产能、良率提升也有很大的帮助。在相关GOA设计中，结构相同的若干级GOA单元各自连接一条行扫描线，基于GOA单元之间的级联关系，能够在外部信号的驱动下使扫描信号在若干条行扫描线上逐行地输出。
随着显示技术的快速发展，市场对显示产品的美观程度提出了更高的要求，这使得进一步窄化边框成为了众多显示产品的重要需求。而随着GOA单元内部电路结构的不断精简，每个GOA单元中薄膜晶体管(Thin Film Transistor，TFT)的数量已经很难在满足应用需求的前提下进一步减少。
发明内容
本公开提供一种扫描驱动电路及其驱动方法、阵列基板和显示装置，可以在现有GOA单元结构的基础上进一步减少栅极驱动器所需的晶体管数量。
第一方面，本公开提供了一种扫描驱动电路，包括m级输出端、m级输入电路和q个移位寄存电路，所述q为小于整数m的正整数；其中，
第i级的所述输入电路的第一端连接第i-1级的所述输出端，所述i为大于1 且小于m+1的任意整数；
任一所述移位寄存电路分别连接k个所述输出端，并与k个所述输入电路的第二端相连，k个所述输入电路与k个所述输出端之间具有相同的级序号组合，所述相同的级序号组合中的级序号均具有相同的奇偶性，所述k大于1且小于m；
所述移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。
在一种可能的实现方式中，所述输入电路被配置为在第一端接收到扫描信号时，将第二端所连接的移位寄存电路切换至充电态；所述移位寄存电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始，向所连接的k个输出端中的一个输出扫描信号。
在一种可能的实现方式中，所述扫描驱动电路还包括m级复位电路；其中，
第j级的所述复位电路的第一端连接第j+1级的所述输出端，所述j为大于0且小于m的任意整数；
分别连接k个所述输出端的移位寄存电路还与k个所述复位电路的第二端相连，k个所述复位电路与k个所述输出端之间具有相同的级序号组合；
所述复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出。
在一种可能的实现方式中，所述外部控制信号由k条控制信号线提供，所述移位寄存电路包括输出电路单元和k个晶体管，所述输出电路单元包括输出节点；其中，
所述输出电路单元被配置为能够向所述输出节点输出扫描信号；
所述k个晶体管的第一极均与所述输出节点相连；
所述k个晶体管的栅极各自连接所述k条控制信号线中的一条；
所述k个晶体管的第二极各自连接k个所述输出端中的一个；
其中，所述第一极和第二极分别是源极和漏极中的一个。
在一种可能的实现方式中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管和第一电容，所述输入电路包括第二晶体管；其中，
所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接k个所述输入电路的第二端；
在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第一 晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
所述第二晶体管的栅极连接所述输入电路的第一端，第一极连接第一电平电压线或者所在输入电路的第一端，第二极连接所在输入电路的第二端；
其中，所述第一极和第二极分别是源极和漏极中的一个。
在一种可能的实现方式中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管、第一电容、第三晶体管和第四晶体管，所述复位电路包括第五晶体管；其中，
所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接k个所述输入电路的第二端；
在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
所述第三晶体管的栅极连接k个所述复位电路的第二端，第一极连接所述第一节点，第二极连接第二电平电压线；
所述第四晶体管的栅极连接k个所述复位电路的第二端，第一极连接所述输出节点，第二极连接第二电平电压线；
所述第五晶体管的栅极和第一极均连接所在复位电路的第一端，第二极连接所在复位电路的第二端；
其中，所述第一极和第二极分别是源极和漏极中的一个。
在一种可能的实现方式中，所述输出电路单元还包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第十一晶体管；其中，
所述第六晶体管的栅极连接第二节点，第一极连接所述第一节点，第二极连接第二电平电压线；
所述第七晶体管的栅极连接所述第二节点，第一极连接所述输出节点，第 二极连接第二电平电压线；
所述第八晶体管的栅极连接第三节点，第二极连接所述第二节点；在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第八晶体管的第一极连接所述第二时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第八晶体管的第一极连接所述第一时钟信号线；
所述第九晶体管的栅极连接所述第一节点，第一极连接所述第二节点，第二极连接第二电平电压线；
所述第十晶体管的栅极和第一极均连接所述第八晶体管的第一极，第二极连接所述第三节点；
所述第十一晶体管的栅极连接所述第一节点，第一极连接所述第三节点，第二极连接第二电平电压线。
在一种可能的实现方式中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第十二晶体管，
在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第十二晶体管的栅极连接第二时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第十二晶体管的栅极连接第一时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
所述第十二晶体管的第一极连接所述输出节点，所述第十二晶体管的第二极连接第二电平电压线；
其中，所述第一极和第二极分别是源极和漏极中的一个。
在一种可能的实现方式中，所述输出电路单元还包括第十三晶体管，
所述第一节点与k个所述输入电路的第二端之间经由所述第十三晶体管连接，所述第十三晶体管的第一极连接k个所述输入电路的第二端，所述第十三晶体管的第二极连接所述第一节点；
在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第十三晶体管的栅极连接所述第二时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第十三晶体管的栅极连接所述第一时钟信号线。
第二方面，本公开还提供了上述任意一种扫描驱动电路的驱动方法，包括：
向所述扫描驱动电路施加所述外部控制信号，以在第p级的所述输入电路 将所连接的移位寄存电路切换至充电态时，使该移位寄存电路从被切换至充电态之后的首个时钟信号的翻转时刻开始向第p级的所述输出端输出扫描信号；
其中，所述p为大于0且小于m+1的任意整数。
第三方面，本公开还提供了一种扫描驱动电路的电路单元，所述扫描驱动电路包括m级输出端，所述电路单元包括一个移位寄存电路和k个输入电路，所述扫描驱动电路中的所述输入电路共有m级，所述k大于1且小于m；其中，
第i级的所述输入电路的第一端连接第i-1级的所述输出端，所述i为大于1且小于m+1的任意整数；
所述移位寄存电路分别连接k个所述输出端，并与所述k个输入电路的第二端相连，所述k个输入电路与k个所述输出端之间具有相同的级序号组合，所述相同的级序号组合中的级序号均具有相同的奇偶性；
所述移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。
在一种可能的实现方式中，所述输入电路被配置为在第一端接收到扫描信号时，将第二端所连接的移位寄存电路切换至充电态；所述移位寄存电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始，向所连接的k个输出端中的一个输出扫描信号。
在一种可能的实现方式中，所述电路单元还包括k个复位电路，所述扫描驱动电路中的所述复位电路共有m级；其中，
第j级的所述复位电路的第一端连接第j+1级的所述输出端，所述j为大于0且小于m的任意整数；
所述移位寄存电路与所述k个复位电路的第二端相连，所述k个复位电路与k个所述输出端之间具有相同的级序号组合；
所述复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出。
在一种可能的实现方式中，所述外部控制信号由k条控制信号线提供，所述移位寄存电路包括输出电路单元和k个晶体管，所述输出电路单元包括输出节点；其中，
所述输出电路单元被配置为能够向所述输出节点输出扫描信号；
所述k个晶体管的第一极均与所述输出节点相连；
所述k个晶体管的栅极各自连接所述k条控制信号线中的一条；
所述k个晶体管的第二极各自连接k个所述输出端中的一个；
其中，所述第一极和第二极分别是源极和漏极中的一个。
在一种可能的实现方式中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管和第一电容，所述输入电路包括第二晶体管；其中，
所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接所述k个输入电路的第二端；
在所对应的级序号组合中的级序号均为奇数的所述移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的所述移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
所述第二晶体管的栅极连接所述输入电路的第一端，第一极连接第一电平电压线或者所在输入电路的第一端，第二极连接所在输入电路的第二端；
其中，所述第一极和第二极分别是源极和漏极中的一个。
在一种可能的实现方式中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管、第一电容、第三晶体管和第四晶体管，所述复位电路包括第五晶体管；其中，
所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接所述k个输入电路的第二端；
在所对应的级序号组合中的级序号均为奇数的所述移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的所述移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
所述第三晶体管的栅极连接所述k个复位电路的第二端，第一极连接所述第一节点，第二极连接第二电平电压线；
所述第四晶体管的栅极连接所述k个复位电路的第二端，第一极连接所述输出节点，第二极连接第二电平电压线；
所述第五晶体管的栅极和第一极均连接所在复位电路的第一端，第二极连接所在复位电路的第二端；
其中，所述第一极和第二极分别是源极和漏极中的一个。
第四方面，本公开还提供了一种阵列基板，包括上述任意一种的扫描驱动电路。
第五方面，本公开还提供了一种显示装置，包括上述任意一种的阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，这些附图的合理变型也都涵盖在本公开的保护范围中。
图1是本公开一个实施例提供的扫描驱动电路的结构框图；
图2是本公开一个对比示例提供的扫描驱动电路的结构框图；
图3是本公开一个实施例提供的部分扫描驱动电路的结构框图；
图4是本公开一个实施例提供的部分扫描驱动电路的结构框图；
图5是本公开一个实施例提供的扫描驱动电路中复用组的电路结构图；
图6是本公开一个实施例提供的扫描驱动电路中复用组的电路时序图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。图1至图3示出了有关本公开一个实施例中的扫描驱动电路的几种电路结构。在本公开实施例中，扫描驱动电路包括m级输出端、m级输入电路和q个移位寄存电路，其中m是大于1的正整数，q是小于m的正整数，具体取值可以根据实际应用需求确定。
在本公开的一个概括性示例中，所述扫描驱动电路包括m级输出端、m级输入电路和q个移位寄存电路，所述q为小于整数m的正整数，其中：
第i级的所述输入电路的第一端连接第i-1级的所述输出端，所述i为大于1且小于m+1的任意整数。
任一所述移位寄存电路分别连接k个所述输出端，并与k个所述输入电路的第二端相连，k个所述输入电路与k个所述输出端之间具有相同的级序号组合，所述相同的级序号组合中的级序号均具有相同的奇偶性，所述k大于1且小于m。
所述移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。
在本公开的又一个概括性示例中，所述扫描驱动电路还包括m级复位单元，并具有如下所述的电路结构：
输入电路与输出端之间具有如下连接关系：对于大于1且小于m+1的任意整数i，第i级的输入电路的第一端连接第i-1级的输出端。
复位电路与输出端之间具有如下连接关系：对于大于0且小于m的任意整数j，第j级的复位电路的第一端连接第j+1级的输出端。
移位寄存电路具有如下连接关系：任一个移位寄存电路与k个输入电路的第二端中的每一个相连、与k个复位电路的第二端中的每一个相连，并且与k个输出端中的每一个分别相连(k为大于1小于m的整数)。而且，k个输入电路与k个输出端之间具有相同的级序号组合，k个复位电路和k个输出端之间也具有相同的级序号组合。此外，该相同的级序号组合中的所有级序号均具有相同的奇偶性。
在各电路的功能上，输入电路被配置为在第一端接收到扫描信号时将第二端所连接的移位寄存电路切换至充电态；移位寄存电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示；复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出。
在一个示例中，上述扫描驱动电路具有如图1所示的结构。为叙述方便，本文以大写字母“A”和数字的组合表示某一级的输入电路(比如“A3”表示第3级的输入电路)，以大写字母“B”和数字的组合表示某一级的复位电路(比如“Bn”表示第n级的复位电路)，以大写字母“C”和数字的组合表示某一级的输出端(比如“Cn+1”表示第n+1级的输出端)，以大写字母“G”和数字的组合表示某一级(即对应于某一级序号)的扫描信号(比如“G0”表示起始扫描信号，“G2”表示第2级输出端所输出的扫描信号)。为图示清晰，附图中以同一扫描信号的附图标记表示相互连接的两个节点(比如图1中C1连线G1、G1连线A2表示第一级的输出端C1连接第2级的输入电路A2的第一端)。
参见图1，本示例中的扫描驱动电路包括移位寄存单元SR_odd、移位寄存单元SR_even。此外，扫描驱动电路还包括4级输出端、4级输入电路和4级复 位电路，其中移位寄存电路SR_odd与2个输入电路的第二端相连、与2个复位电路的第二端相连，并分别连接2个输出端(级序号组合均为{1,3}，其中的级序号均为奇数)。移位寄存电路SR_even与2个输入电路的第二端相连、与2个复位电路的第二端相连，并分别连接2个输出端(级序号组合均为{2,4}，其中的级序号均为偶数)。可以看出，本示例中m＝4，q＝2，k＝2。
如图1所示，第2级的输入电路A2的第一端连接第1级的输出端C1，第3级的输入电路A3的第一端连接第2级的输出端C2，第4级的输入电路A4的第一端连接第3级的输出端C3，即均具有上述“第i级的输入电路的第一端连接第i-1级的输出端”(1<i<m+1)的连接关系。
如图1所示，第1级的复位电路B1的第一端连接第2级的输出端C2，第2级的复位电路B2的第一端连接第3级的输出端C3，第3级的复位电路B3的第一端连接第4级的输出端C4，即均具有上述“第j级的复位电路的第一端连接第j+1级的输出端”(0<j<m)的连接关系。
基于上述各电路的功能，参照图1，本示例的扫描驱动电路的工作原理如下：
在第一级的输入电路A1的第一端接收到外部提供的起始扫描信号G0时，将第二端所连接的移位寄存电路SR_odd切换至充电态。在适当的外部控制信号的配合下，移位寄存电路SR_odd能够在此后第一次的时钟信号的翻转时刻开始向所连接的输出端C1输出扫描信号G1(即此时输出端C1是移位寄存电路SR_odd所连接的所有输出端中由外部控制信号指示的输出端)。同时，由于输出端C1输出的扫描信号G1会连接至第二输入电路A2的第一端，因此第二输入电路A2会将第二端所连接的移位寄存电路SR_even切换至充电态。
在此后的第二次的时钟信号的翻转时刻，移位寄存电路SR_even能够在适当的外部控制信号的配合下开始向所连接的输出端C2输出扫描信号G2(即此时输出端C2是移位寄存电路SR_even所连接的所有输出端中由外部控制信号指示的输出端)。同时，由于输出端C2输出的扫描信号G2会连接至输入电路A3的第一端和复位电路B1的第一端，因此复位电路B1会使第二端所连接的移位寄存电路SR_odd停止输出扫描信号G1，而输入电路A3会将第二端所连接的移位寄存电路SR_odd切换至充电态，即此时移位寄存电路SR_odd处于充电态但不输出扫描信号。
在此后的第三次的时钟信号的翻转时刻，移位寄存电路SR_odd能够在适当的外部控制信号的配合下开始向所连接的输出端C3输出扫描信号G3(即此时 输出端C3是移位寄存电路SR_odd所连接的所有输出端中由外部控制信号指示的输出端)。同时，由于输出端C3输出的扫描信号G3会连接至输入电路A4的第一端和复位电路B2的第一端，因此复位电路B2会使第二端所连接的移位寄存电路SR_even停止输出扫描信号G2，而输入电路A4会将第二端所连接的移位寄存电路SR_even切换至充电态，即此时移位寄存电路SR_even处于充电态但不输出扫描信号。
在此后的第四次的时钟信号的翻转时刻，移位寄存电路SR_even能够在适当的外部控制信号的配合下开始向所连接的输出端C4输出扫描信号G4(即此时输出端C4是移位寄存电路SR_even所连接的所有输出端中由外部控制信号指示的输出端)。同时，由于输出端C4输出的扫描信号G4会连接至复位电路B3的第一端，因此复位电路B3会使第二端所连接的移位寄存电路SR_odd停止输出扫描信号G3，并且可以理解的是移位寄存电路SR_odd在下一次被切换至充电态之前都不会输出扫描信号。
例如在此后的第四次的时钟信号的翻转时刻开始，从扫描驱动电路的外部向复位端B4输入扫描信号，从而复位电路B4会使第二端所连接的移位寄存电路SR_even停止输出扫描信号G4，可以理解的是移位寄存电路SR_even在下一次被切换至充电态之前都不会输出扫描信号。
基于上述工作原理可知，本示例的扫描驱动电路能够在上述外部信号的配合下实现扫描信号在第1至4级输出端处的逐级输出。第1级的输入电路A1的第一端形成扫描驱动电路的输入端，第4级的复位电路B4的第一端形成扫描驱动电路的复位端，第1至4级的输出端形成扫描驱动电路的4个输出端。
在上述工作原理中需要说明的是，上述“时钟信号的翻转时刻”可以是连接到移位寄存电路的时钟信号的上升沿和/或下降沿所在的时刻；能够看出其控制了扫描信号逐级输出的时序，因此在实施时可以根据所需要实现的时序来配置时钟信号。例如，可以将正向时钟信号与反相时钟信号的组合作为连接到移位寄存电路的时钟信号，其电平翻转的时刻作为上述时钟信号的翻转时刻，并且可以不仅限于此。
在上述工作原理中还需要说明的是，上述“外部控制信号”指的是连接到移位寄存电路的外部信号，其可以控制移位寄存电路向所连接的输出端中的哪一个输出扫描信号。外部控制信号可由例如时序控制器的电路结构配合时钟信号一起输入到扫描驱动电路中，也可由外部电路接口接入到扫描驱动电路中， 并且可以不仅限于此。
在上述工作原理中还需要说明的是，上述“充电态”指的是移位寄存电路的一种工作状态，被切换至充电态的移位寄存电路会在首次时钟信号的翻转时刻开始输出扫描信号。在一种实现方式下，移位寄存电路在停止输出扫描信号之后会自发地从充电态中恢复；在另一种实现方式下，复位电路会在第一端接收到扫描信号且所连接的移位寄存电路没有被任何一个输入电路切换至充电态时使所连接的移位寄存电路从充电态中恢复。由此，可以减少由于移位寄存电路维持在充电态的时间过长而引起的误输出或信号噪声。
参见图2，在一个对比示例中，扫描驱动电路在图1所示的结构的基础上将2个移位电路替换为4级的移位电路SR_1、SR_2、SR_3、SR_4，且每个移位电路分别连接与其具有相同级序号的1个输入电路、1个复位电路和1个输出端；本示例中的输入电路被配置为在第一端接收到扫描信号时将第二端所连接的移位电路切换至充电态，移位电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始向所连接的输出端输出扫描信号，复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位电路停止扫描信号的输出。
容易推知，本示例中的扫描驱动电路可以在同样的外部信号下实现与图1所示的扫描驱动电路相同的信号输出。而对比图1与图2所示的电路结构和工作原理可知，图1所示的扫描驱动电路中移位寄存电路SR_odd实现了移位电路SR_1和移位电路SR_3的功能，而移位寄存电路SR_even实现了移位电路SR_2和移位电路SR_4的功能，即图1所示的扫描驱动电路通过电路结构的复用，实现了扫描驱动电路的内部结构的简化。
在又一示例中，扫描驱动电路除了包括图1所示的电路结构之外，还包括若干组如图3所示的电路结构。比如，n＝5，9，13，…，4x+1(x为正整数)的图3的电路结构可以与图1所示的电路结构组成具有4x+4级的输出端的扫描驱动电路，并且仅包含2x+2个移位寄存电路。其中，每一组如图3所示的电路结构都可以按照与图1所示的电路结构相同的工作原理输出实现4级扫描信号的逐级输出。
在又一示例中，扫描驱动电路可以包括如图4所示的电路结构。参见图4，相比于图3所示的电路结构，图4所示的移位寄存电路SR_even与3个输入电路的第二端相连、与3个复位电路的第二端相连，并且与3个输出端分别相连(3个输入电路、3个复位电路和3个输出端的级序号组合均为{n+1,n+3,n+5}， 其中的级序号均为奇数或均为偶数)。容易理解的是，该移位寄存电路SR_even在功能上相当于3级移位电路的组合，具有与图1所示的移位寄存电路SR_even类似的工作原理。
为描述方便，下文将例如图4所示的移位寄存电路SR_even及其所连接的3个输入电路、3个复位电路和3个输出端的组合称为复用组，其所对应的级序号组合可以是1～m范围内任意数量的奇数的组合，或者2～m范围内任意数量的偶数的组合。比如，图1所示的扫描驱动电路级序号组合为{1,3}的复用组和级序号组合为{2,4}的复用组；图3所示的扫描驱动电路包括级序号组合为{n,n+2}的复用组和级序号组合为{n+1,n+3}的复用组；图4所示的扫描驱动电路包括级序号组合为{n,n+2}的复用组和级序号组合为{n+1,n+3,n+5}的复用组。
基于上述示例可以理解的是，为了实现第1级至第m级的扫描信号的逐级输出，可以将{1,2,3,...,m}拆分为若干组由奇数组成的级序号组合和若干组由偶数组成的级序号组合(比如将{1,2,3,...,10}拆分为{1,5,9}、{3,7}、{2,8}和{4,6,10})，从而由与每个级序号组合对应的复用组共同组成扫描驱动电路。而且，还可以拆分出来若干个单独的级序号，由如图2所示的移位电路及其连接的输入电路、复位电路和输出端来形成扫描驱动电路中与这些级序号对应的部分电路结构(比如将所对应级序号为n+4的输入电路、复位电路和输出端和移位电路设置到如图3所示的电路结构中，以接收第n+3级的扫描信号并输出第n+4级的扫描信号)。在至少拆分出一个级序号组合时，可以得到如上述任一个概括性示例所述的扫描驱动电路的结构。
可以看出的是，基于移位寄存电路分别与多级输入电路和多级输出端的连接，本公开实施例可使一个移位寄存电路在多级之间复用，从而可以在保持信号输入输出关系的情况下简化电路结构，在现有GOA单元结构的基础上进一步减少栅极驱动器所需的晶体管数量，有助于解决相关技术中GOA单元所占据的空间难以压缩、边框难以窄化的问题，有利于简化栅极驱动器的结构、缩小栅极驱动器的设置空间，并突破相关产品在边框窄化上的瓶颈。
图5是本公开一个实施例提供的复用组的电路结构图，亦即本公开一个实施例提供的扫描驱动电路的一个电路单元的电路结构图，其以图3和图4中级序号组合为{n,n+2}的复用组的电路结构作为示例展示了复用组的可选电路结构。需要说明的是，图5中示出的晶体管示例性地均为N型晶体管，即可以通过相同的制作工艺形成以降低制造成本。根据晶体管具体类型的不同，可以设 置其源极和漏极分别所具有的连接关系，以与流过晶体管的电流的方向相匹配；在晶体管具有源极与漏极对称的结构时，源极和漏极可以视为不作特别区分的两个电极。下文中，以第一极和第二极分别指代源极和漏极中的一个。
参见图5，在本实施例的复用组中：
上述外部控制信号由第一控制信号线Ra和第二控制信号线Rb来提供，控制信号线的数量为k＝2；而上述移位寄存电路SR_odd包括输出电路单元MR和用于控制输出电路单元MR连接到哪个输出端的晶体管Ta和Tb(下文统称为“控制晶体管”)，控制晶体管的数量同样为k＝2。其中，该输出电路单元MR具有输出节点PO，该输出节点PO连接k个控制晶体管的第一极。该输出电路单元MR被配置为从移位寄存电路被切换至充电态之后的首个时钟翻转时刻开始向输出节点PO输出扫描信号；k个控制晶体管的栅极各自连接k条控制信号线中的一条，k个控制晶体管的第二极各自连接k个输出端中的一个，形成如图5中所示的电路连接关系。容易理解的是，对于k>2的复用组来说，控制信号线和控制晶体管的设置数量仍与k保持一致。
基于这一部分的电路结构，在k条控制信号线中仅有一条输出栅极开启电压时，其所连接的控制晶体管即可打开并将输出电路单元MR连接至对应的输出端处，即实现了向外部控制信号指示的输出端输出扫描信号。而为了实现上述如图1所示的扫描驱动电路的工作过程，上述任一个概括性示例中的扫描驱动电路的驱动方法可以包括：向扫描驱动电路施加外部控制信号，以在第p级的输入电路将所连接的移位寄存电路切换至充电态时，使该移位寄存电路从被切换至充电态之后的首个时钟信号的翻转时刻开始向第p级的输出端输出扫描信号；其中，p为大于0且小于m+1的任意整数。比如，上述图1所示的扫描驱动电路的工作原理就分别涉及了p＝1、p＝2、p＝3和p＝4的情形，并且向扫描驱动电路施加外部控制信号的波形示例将会在后文给出。
在本实施例中，上述输出电路单元MR包括第一晶体管T1和第一电容C1，其中，第一晶体管T1的栅极连接第一节点PU，第一极连接第一时钟信号线CK1，第二极连接输出节点PO；第一节点PU间接地连接k个输入电路的第二端(在又一示例中，可以使第一节点PU直接地连接k个输入电路的第二端，并省去第十三晶体管M13的设置)；第一电容C1的第一端连接第一节点PU，第二端连接输出节点PO。基于此，输出电路单元MR能够实现上述从移位寄存电路被切换至充电态之后的首个时钟翻转时刻开始向所连接的控制晶体管的第一极输出 扫描信号的功能，具体实现方式将在后文的工作原理中详述。
需要说明的是，上文中的时钟信号在本实施例中具体包括由第一时钟信号线CK1提供的正相时钟信号，和由第二时钟信号线CK2提供的反相时钟信号(在又一示例中，正相时钟信号由第二时钟信号线CK2提供，反相时钟信号由第一时钟信号线CK1)，并且级序号组合中均为奇数的复用组与级序号组合中均为偶数的复用组之间在时钟信号的连接方式上具有差别。例如，在级序号组合中均为奇数的复用组中，上述第一晶体管T1的第一极连接第一时钟信号线CK1，而在级序号组合中均为偶数的复用组中，上述第一晶体管T1的第一极连接第二时钟信号线CK2。本实施例中，以级序号组合中均为奇数作为示例进行描述。
在本实施例中，每一个输入电路——输入电路An和输入电路An+2各自包括一个第二晶体管T2。每个输入电路中，第二晶体管T2的栅极连接所在输入电路的第一端，第一极连接所在输入电路的第一端，第二极连接输入电路的第二端。基于此，输入电路能够实现上述在第一端接收到扫描信号时将第二端所连接的移位寄存电路切换至充电态的功能，具体实现方式将在后文的工作原理中详述。在其他实现方式中，上述第二晶体管T2的第一极可以不连接输入电路的第一端而改为连接未在附图中示出的第一电平电压线(例如是加载高电平电压的信号线)，并且可以不仅限于此。
在本实施例中，上述输出电路单元MR还包括第三晶体管T3和第四晶体管T4，每一个复位电路——复位电路Bn和复位电路Bn+2各自包括一个第五晶体管T5。其中，第三晶体管T3的栅极连接k个复位电路的第二端，第一极第一节点PU，第二极连接第二电平电压线Vss(例如是加载低电平电压的信号线)；第四晶体管T4的栅极连接k个复位电路的第二端，第一极连接输出节点PO，第二极连接第二电平电压线Vss；第五晶体管T5的栅极和第一极均连接所在复位电路的第一端，第二极连接所在复位电路的第二端。基于此，复位电路可以实现上述在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出的功能，具体实现方式将在后文的工作原理中详述。
本实施例中，上述输出电路单元MR还包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10和第十一晶体管T11，其中：第六晶体管T6的栅极连接第二节点PD，第一极连接第一节点PU，第二极连接第二电平电压线Vss；第七晶体管T7的栅极连接第二节点PD，第一极连接输出节点PO，第二极连接第二电平电压线Vss。第八晶体管T8的栅极连接第三节点 PC，第二极连接第二节点PD。在级序号组合中均为奇数的复用组中，第八晶体管T8的第一极连接第二时钟信号线CK2；在级序号组合中均为偶数的复用组中，第八晶体管T8的第一极连接第一时钟信号线CK1。第九晶体管T9的栅极连接第一节点PU，第一极连接第二节点PD，第二极连接第二电平电压线Vss；第十晶体管T10的栅极和第一极连接第八晶体管T8的第一极，第二极连接第三节点PC；第十一晶体管T11的栅极连接第一节点PU，第一极连接第三节点PC，第二极连接第二电平电压线Vss。基于此，上述输出电路单元MR可以在不输出扫描信号时工作在更加稳定的状态上，具体原理将在后文的工作原理中详述。
本实施例中，上述输出电路单元MR还包括第十二晶体管T12，在级序号组合中均为奇数的复用组中，第十二晶体管T12的栅极连接第二时钟信号线CK2；在级序号组合中均为偶数的复用组中，第十二晶体管T12的栅极连接第一时钟信号线CK1。第十二晶体管T12的第一极连接输出节点PO，第十二晶体管T12的第二极连接第二电平电压线Vss。基于此，第十二晶体管T12可以辅助进行停止扫描信号输出时的信号复位，有利于提升复位速度和电路的工作稳定性，其具体原理将在后文的工作原理中详述。
本实施例中，上述输出电路单元MR还包括第十三晶体管T13。上述第一节点PU与k个输入电路的第二端之间进一步藉由第十三晶体管T13连接，第十三晶体管T13的第一极连接k个输入电路的第二端，第十三晶体管T13的第二极连接第一节点PU。在级序号组合中均为奇数的复用组中，第十三晶体管T13的栅极连接第二时钟信号线CK2；在级序号组合中均为偶数的复用组中，第十三晶体管T13的栅极连接第一时钟信号线CK1。基于此，第十三晶体管T13可以辅助进行充电态的切换和复原，有利于提升充电速度、复原速度和电路的工作稳定性，其具体原理将在后文的工作原理中详述。
对应于图5所示的复用组的电路结构，图6是本公开实施例提供的扫描驱动电路中复用组的电路时序图。参见图5和图6，该复用组的工作原理如下所述：
第一阶段①之前：复用组所涉及的扫描信号均保持为低电平，因此第二晶体管T2、第五晶体管T5、第三晶体管T3、第四晶体管T4均保持关闭。第一时钟信号线CK1和第二时钟信号线CK2上的时钟信号周期性相互翻转，这使得其所连接的所有输出电路单元MR中的第十晶体管T10周期性打开，使得第三节点PC处被周期性置为高电平，继而第八晶体管T8打开，使得第二节点PD处也被置为高电平。在第二节点PD处的高电平作用下，第六晶体管T6和第七晶 体管T7的打开会使得第一节点PU处和输出节点PO处保持为低电平。第九晶体管T9和第十一晶体管T11保持关闭，不对第二节点PD和第三节点PC进行电位的下拉；第一晶体管T1保持关闭，不对输出节点PO处进行电位的上拉。此外，时钟信号会使第十二晶体管T12和第十三晶体管T13周期性打开，帮助保持k个输入电路的第二端处、第一节点PU处，以及输出节点PO处保持为低电平。而且，第一控制信号线Ra和第二控制信号线Rb上也加载着周期性翻转的信号，使得两个控制晶体管Ta和Tb交替打开；而由于输出节点PO处保持为低电平，因此输出端Cn处和输出端Cn+2处的电位也会被周期性下拉，从而可以保持输出信号的稳定。
第一阶段①中：扫描信号Gn-1转为高电平(即开始输出)，第二时钟信号线CK2上为高电平，第一时钟信号线CK1上为低电平，从而输入电路An中的第二晶体管T2打开，并且第十三晶体管T13打开，使得第一节点PU处被上拉至高电平。由此，第一晶体管T1、第九晶体管T9、第十一晶体管T11打开，第二节点PD处和第三节点PC处被置为低电平，停止对第一节点PU处和输出节点PO处的电位下拉。由于第十二晶体管T12打开且第一晶体管T1打开，输出节点PO处在第一时钟信号线CK1和第二电平电压线Vss的共同作用下保持为低电平。而在此阶段内，第一电容C1的第一端为高电平、第二端为低电平，即在此阶段内完成了电容两端的充电(即切换至充电态)。
第二阶段②中：扫描信号Gn-1转为低电平(即停止输出)，第二时钟信号线CK2上为低电平，第一时钟信号线CK1上为高电平，第十二晶体管T12和第十三晶体管T13关闭。而在第一电容C1的电荷保持作用下，第一节点PU处会随着第一时钟信号线CK1上由低电平转为高电平的变化跳变至一电位更高的高电平上。这使得第一晶体管T1完全打开，快速完成输出节点PO处的电位上拉。此时第一控制信号线Ra上为高电平而控制晶体管Ta打开，因而输出端Cn处会输出高电平，即扫描信号Gn开始输出。
第三阶段③中：扫描信号Gn+1转为高电平(即开始输出)，第二时钟信号线CK2上为高电平，第一时钟信号线CK1上为低电平，而且第一控制信号线Ra上为高电平而控制晶体管Ta打开。扫描信号Gn+1的高电平作用下，输入电路An+2中的第二晶体管T2和复位电路Bn中的第五晶体管T5打开，使得第三晶体管T3对第一节点PU处进行电位下拉，第二晶体管T2和第十三晶体管T13对第一节点PU处进行电位上拉。这里，通过设置第二晶体管T2、第三晶体管 T3和第十三晶体管T13之间的器件参数关系，可使此阶段内的第一节点PU处为高电平。此时，第一晶体管T1、第四晶体管T4和第十二晶体管T12打开，使得控制晶体管Ta的第一极和第二极在第一时钟信号线CK1和第二电平电压线Vss的共同作用下被下拉为低电平，即扫描信号Gn停止输出。而在此阶段内，第一电容C1的第一端为高电平、第二端为低电平，即在此阶段内完成了电容两端的充电(即切换至充电态)。
在一种实现方式中，设第二晶体管T2、第三晶体管T3和第十三晶体管T13的源漏等效电阻分别为R2、R3和R13，扫描信号的高电平电压为Vgh，第二电平电压线Vss上的低电平电压为Vgl，第一节点PU处的电压为V1，那么有：
(Vgh-Vgl)/(R2+R3+13)＝(Vgh-V1)/(R2+R13)
如果第一节点PU处为高电平等价于V1>0，那么由结合两式可以推得：
R3*Vgh+(R2+R13)*Vgl>0
由于一般晶体管的沟道宽长比越大，源漏等效电阻就越小，因此通过相应的设置能够使得第二晶体管T2、第三晶体管T3和第十三晶体管T13满足上式，满足第一节点PU处在第三阶段③中须为高电平的需求。
第四阶段④中：扫描信号Gn+1转为低电平(即停止输出)，第二时钟信号线CK2上为低电平，第一时钟信号线CK1上为高电平，第十二晶体管T12和第十三晶体管T13关闭。而在第一电容C1的电荷保持作用下，第一节点PU处会随着第一时钟信号线CK1上由低电平转为高电平的变化跳变至一电位更高的高电平上。这使得第一晶体管T1完全打开，快速完成输出节点PO处的电位上拉。此时第二控制信号线Rb上为高电平而控制晶体管Tb打开，因而输出端Cn+2处会输出高电平，即扫描信号Gn+2开始输出。
第五阶段⑤中：扫描信号Gn+3转为高电平(即开始输出)，第二时钟信号线CK2上为高电平，第一时钟信号线CK1上为低电平，而且第二控制信号线Rb上为高电平而控制晶体管Tb打开。扫描信号Gn+3的高电平作用下，复位电路Bn+2中的第五晶体管T5打开，使得第三晶体管T3对第一节点PU处进行电位下拉，第四晶体管T4对输出节点PO处进行电位下拉。由于此时没有第二晶体管T2实现对第一节点PU处电位的上拉，因此第一节点PU处会被置为低电平。从而，第九晶体管T9停止对第二节点PD处的电位下拉，第十一晶体管T11停止对第三节点PC处的电位下拉。在第二时钟信号线CK2上的高电平作用下，第十晶体管T10打开而第三节点PC处被置为高电平，第八晶体管T8打开而第 二节点PD处被置为高电平。在第二节点PD处的高电平作用下，第六晶体管T6和第七晶体管T7的打开会使得第一节点PU处和输出节点PO处被置为低电平。从而，控制晶体管Tb的第一极和第二极在第一时钟信号线CK1和第二电平电压线Vss的共同作用下被下拉为低电平。此后，复位组将会持续性地处于上述第一阶段①之前的工作状态，直到下一个周期的第一阶段①开始。
从上述工作原理中可以看出，输入电路、复位电路、移位寄存电路都实现了各自的功能，基于图5所示的复位组示例，可以得到其他级序号组合的复位组的电路结构。在此基础之上，其可以在与时钟信号和外部控制信号的配合下实现上述扫描驱动电路的功能，并显然可以比现有结构具有更少的晶体管数量。
在上述工作原理中需要说明的是，移位寄存电路所包含的晶体管并不都是实现其功能所必要的，例如第十三晶体管T13和第十二晶体管T12在不设置的情况下仍然可以实现图6所示的电路时序，但是其设置有助于优化移位寄存电路的信号输出特性。而且，上述移位寄存电路中的所包含的元件并不需要全部都设置在扫描驱动电路中，比如两个控制晶体管Ta和Tb可以设置在栅极驱动器与行扫描线之间的任意位置上。另外，如图5所示的输出电路单元MR可以作为与奇数的级序号对应的上述移位电路来使用，将第一时钟信号线CK1与第二时钟信号线CK2交换之后的输出电路单元MR可以作为与偶数的级序号对应的上述移位电路来使用，并且可以不仅限于此。
此外，由于控制晶体管Ta和Tb的设置在一定程度上将输出电路单元的信号输出端与行扫描线之间分隔开，因此例如第四晶体管T4、第七晶体管T7、第十二晶体管T12等元件所发挥的降噪功能将在一定程度上被削弱。由此，可以针对每一级的输出端设置复位晶体管(第一极连接某一级的输出端、第二极连接第二电平电压线、栅极连接同一级序号的复位电路的第二端、同一级序号的移位寄存电路中的第二节点、或者不影响扫描信号输出的时钟信号)。而且，在复位晶体管与上述第四晶体管T4、第七晶体管T7、第十二晶体管T12中的至少一个的功能一定程度重复的情况下，可以依照应用需求仅保留其中一种，或者将两种功能实现方式相互组合以实现更优的信号输出特性。比如对于图5所示的复用组，可以将第四晶体管T4、第七晶体管T7、第十二晶体管T12中任意一个或多个的第一极改接至控制晶体管Ta的第二端或者控制晶体管Tb的第二端，也可以将第四晶体管T4、第七晶体管T7、第十二晶体管T12中任意一个或多个的数量设置为两个，以将两个晶体管的第一极分别唯一地连接至控制晶体管Ta 的第二端和控制晶体管Tb的第二端，以更好地消除噪声。
在本文所提供的任一种扫描驱动电路的基础上，可以通过下述方式替代m级复位电路的设置，同时使扫描驱动电路的输出时序不变：将所述移位寄存电路配置为在接收到所连接的复位时钟信号线上的第一电平时停止扫描信号的输出。在移位寄存电路向所连接的输出端输出扫描信号时，其所连接的复位时钟信号线上为第一电平以外的电平。在一个示例中，所对应级序号均为奇数的移位寄存电路所连接的复位时钟信号线为第二时钟信号线，所对应级序号均为偶数的移位寄存电路所连接的复位时钟信号线为第一时钟信号线。
例如，可以在图5所示的电路结构的基础上，将第三晶体管T3栅极和第四晶体管T4的栅极改为与第二时钟信号线CK2相连。如图6所示，第二时钟信号线CK2在第三阶段③替代扫描信号Gn+1的作用，并能在第五阶段⑤替代扫描信号Gn+3的作用，同时不在第二阶段②影响扫描信号Gn的输出，也不会在第四阶段④影响扫描信号Gn+2的输出，而仅是在第一阶段①中会对第一节点PU处的电位上拉造成阻碍，并且会基于第三阶段③中第一节点PU处为高电平相同的理由而使第一阶段①中第一节点PU处也为高电平。
可以看出的是，即便脱离于上述m级复位电路的设置，本公开实施例仍然能够仅仅基于移位寄存电路分别与多级输入电路和多级输出端的连接，实现移位寄存电路在多级之间复用，从而可以在保持信号输入输出关系的情况下简化电路结构，实现栅极驱动器结构的简化。
在本文所提供的任一种扫描驱动电路的基础上，可以按照下述方式改变输入电路和移位寄存电路的配置，同时使扫描驱动电路的输出时序不变：将输入电路配置为在第一端接收到扫描信号时使移位寄存电路进入第一模式，将移位寄存电路配置为在第一模式下接收到触发信号时进入第二模式，在第二模式下向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。此时，可将复位电路配置为在第一端接收到扫描信号时使移位寄存电路退出第二模式。退出后，如果移位寄存电路所连接的任一输入电路处于工作状态，则移位寄存电路返回第一模式；否则，移位寄存电路直接退出第二模式和第一模式，直至下一次进入第一模式。
在一个示例中，所述第一模式即上文所述的充电态，所述触发信号即上文所述的时钟信号的翻转，所述第二模式即上文所述的移位寄存电路在向所连接的k个输出端中的一个输出扫描信号时的工作状态。在又一示例中，所述移位 寄存电路中的输出电路单元等效于一个移位寄存器，所述第一模式即移位寄存器存储扫描信号所对应的电平的状态，所述触发信号即例如下降沿或者上升沿的触发移位寄存器输出所存储的扫描信号所对应的电平的状态。
可以看出的是，即便按照上述方式改变上述输入电路和移位寄存电路的配置，本公开实施例仍然能够基于移位寄存电路分别与多级输入电路和多级输出端的连接实现移位寄存电路在多级之间复用，从而可以在保持信号输入输出关系的情况下简化电路结构，实现栅极驱动器结构的简化。
基于同样的发明构思，本公开实施例还提供了一种扫描驱动电路的电路单元，所述扫描驱动电路包括m级输出端，所述电路单元包括一个移位寄存电路和k个输入电路，所述扫描驱动电路中的所述输入电路共有m级，所述k大于1且小于m；其中，
第i级的所述输入电路的第一端连接第i-1级的所述输出端，所述i为大于1且小于m+1的任意整数；
所述移位寄存电路分别连接k个所述输出端，并与所述k个输入电路的第二端相连，所述k个输入电路与k个所述输出端之间具有相同的级序号组合，所述相同的级序号组合中的级序号均具有相同的奇偶性；
所述移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。
在一种可能的实现方式中，所述输入电路被配置为在第一端接收到扫描信号时，将第二端所连接的移位寄存电路切换至充电态；所述移位寄存电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始，向所连接的k个输出端中的一个输出扫描信号。
在一种可能的实现方式中，所述电路单元还包括k个复位电路，所述扫描驱动电路中的所述复位电路共有m级；其中，
第j级的所述复位电路的第一端连接第j+1级的所述输出端，所述j为大于0且小于m的任意整数；
所述移位寄存电路与所述k个复位电路的第二端相连，所述k个复位电路与k个所述输出端之间具有相同的级序号组合；
所述复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出。
应理解的是，上文所述的任意一种复用组都可以视作本公开实施例的电路 单元的一种实现方式示例，而且上文中复用组在扫描驱动电路中的重复方式也已经详细说明，在此不再赘述。
可以看出，可以看出的是，基于移位寄存电路分别与多级输入电路和多级输出端的连接，本公开实施例可使一个移位寄存电路在多级之间复用，从而可以在保持信号输入输出关系的情况下简化电路结构，在现有GOA单元结构的基础上进一步减少栅极驱动器所需的晶体管数量，有利于简化栅极驱动器的结构、缩小栅极驱动器的设置空间，突破相关产品在边框窄化上的瓶颈。
基于同样的发明构思，本公开实施例还提供了一种阵列基板，该阵列基板包括上述任意一种的扫描驱动电路。基于扫描驱动电路所具有所占空间小的特点，阵列基板上的GOA区域可以设计的更小，有助于实现更窄的显示边框。
基于同样的发明构思，本公开实施例还提供了一种显示装置，该显示装置包括任一种阵列基板。本公开实施例中的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。基于扫描驱动电路所具有的所占空间小的特点，显示装置可以具有更窄的显示边框。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (18)

  1. 一种扫描驱动电路，其中，包括m级输出端、m级输入电路和q个移位寄存电路，所述q为小于整数m的正整数；其中，
    第i级的所述输入电路的第一端连接第i-1级的所述输出端，所述i为大于1且小于m+1的任意整数；
    任一所述移位寄存电路分别连接k个所述输出端，并与k个所述输入电路的第二端相连，k个所述输入电路与k个所述输出端之间具有相同的级序号组合，所述相同的级序号组合中的级序号均具有相同的奇偶性，所述k大于1且小于m；
    所述移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述输入电路被配置为在第一端接收到扫描信号时，将第二端所连接的移位寄存电路切换至充电态；所述移位寄存电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始，向所连接的k个输出端中的一个输出扫描信号。
  3. 根据权利要求1所述的扫描驱动电路，其中，所述扫描驱动电路还包括m级复位电路；其中，
    第j级的所述复位电路的第一端连接第j+1级的所述输出端，所述j为大于0且小于m的任意整数；
    分别连接k个所述输出端的移位寄存电路还与k个所述复位电路的第二端相连，k个所述复位电路与k个所述输出端之间具有相同的级序号组合；
    所述复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出。
  4. 根据权利要求1所述的扫描驱动电路，其中，所述外部控制信号由k条控制信号线提供，所述移位寄存电路包括输出电路单元和k个晶体管，所述输出电路单元包括输出节点；其中，
    所述输出电路单元被配置为能够向所述输出节点输出扫描信号；
    所述k个晶体管的第一极均与所述输出节点相连；
    所述k个晶体管的栅极各自连接所述k条控制信号线中的一条；
    所述k个晶体管的第二极各自连接k个所述输出端中的一个；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  5. 根据权利要求1所述的扫描驱动电路，其中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管和第一电容，所述输入电路包括第二晶体管；其中，
    所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接k个所述输入电路的第二端；
    在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
    所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
    所述第二晶体管的栅极连接所述输入电路的第一端，第一极连接第一电平电压线或者所在输入电路的第一端，第二极连接所在输入电路的第二端；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  6. 根据权利要求3所述的扫描驱动电路，其中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管、第一电容、第三晶体管和第四晶体管，所述复位电路包括第五晶体管；其中，
    所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接k个所述输入电路的第二端；
    在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
    所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
    所述第三晶体管的栅极连接k个所述复位电路的第二端，第一极连接所述第一节点，第二极连接第二电平电压线；
    所述第四晶体管的栅极连接k个所述复位电路的第二端，第一极连接所述输出节点，第二极连接第二电平电压线；
    所述第五晶体管的栅极和第一极均连接所在复位电路的第一端，第二极连接所在复位电路的第二端；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  7. 根据权利要求6所述的扫描驱动电路，其中，所述输出电路单元还包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第十一晶体管；其中，
    所述第六晶体管的栅极连接第二节点，第一极连接所述第一节点，第二极连接第二电平电压线；
    所述第七晶体管的栅极连接所述第二节点，第一极连接所述输出节点，第二极连接第二电平电压线；
    所述第八晶体管的栅极连接第三节点，第二极连接所述第二节点；在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第八晶体管的第一极连接所述第二时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第八晶体管的第一极连接所述第一时钟信号线；
    所述第九晶体管的栅极连接所述第一节点，第一极连接所述第二节点，第二极连接第二电平电压线；
    所述第十晶体管的栅极和第一极均连接所述第八晶体管的第一极，第二极连接所述第三节点；
    所述第十一晶体管的栅极连接所述第一节点，第一极连接所述第三节点，第二极连接第二电平电压线。
  8. 根据权利要求1至7中任一项所述的扫描驱动电路，其中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第十二晶体管，
    在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第十二晶体管的栅极连接第二时钟信号线；在所对应的级序号组合中的级序号均为 偶数的移位寄存电路中，所述第十二晶体管的栅极连接第一时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
    所述第十二晶体管的第一极连接所述输出节点，所述第十二晶体管的第二极连接第二电平电压线；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  9. 根据权利要求5至7中任一项所述的扫描驱动电路，其中，所述输出电路单元还包括第十三晶体管，
    所述第一节点与k个所述输入电路的第二端之间经由所述第十三晶体管连接，所述第十三晶体管的第一极连接k个所述输入电路的第二端，所述第十三晶体管的第二极连接所述第一节点；
    在所对应的级序号组合中的级序号均为奇数的移位寄存电路中，所述第十三晶体管的栅极连接所述第二时钟信号线；在所对应的级序号组合中的级序号均为偶数的移位寄存电路中，所述第十三晶体管的栅极连接所述第一时钟信号线。
  10. 一种如权利要求1至9中任一项所述的扫描驱动电路的驱动方法，其中，包括：
    向所述扫描驱动电路施加所述外部控制信号，以在第p级的所述输入电路将所连接的移位寄存电路切换至充电态时，使该移位寄存电路从被切换至充电态之后的首个时钟信号的翻转时刻开始向第p级的所述输出端输出扫描信号；
    其中，所述p为大于0且小于m+1的任意整数。
  11. 一种扫描驱动电路的电路单元，其中，所述扫描驱动电路包括m级输出端，所述电路单元包括一个移位寄存电路和k个输入电路，所述扫描驱动电路中的所述输入电路共有m级，所述k大于1且小于m；其中，
    第i级的所述输入电路的第一端连接第i-1级的所述输出端，所述i为大于1且小于m+1的任意整数；
    所述移位寄存电路分别连接k个所述输出端，并与所述k个输入电路的第二端相连，所述k个输入电路与k个所述输出端之间具有相同的级序号组合， 所述相同的级序号组合中的级序号均具有相同的奇偶性；
    所述移位寄存电路被配置为能够向所连接的k个输出端中的一个输出扫描信号，向哪一个所述输出端输出扫描信号由外部控制信号指示。
  12. 根据权利要求11所述的电路单元，其中，所述输入电路被配置为在第一端接收到扫描信号时，将第二端所连接的移位寄存电路切换至充电态；所述移位寄存电路被配置为从被切换至充电态之后的首个时钟信号的翻转时刻开始，向所连接的k个输出端中的一个输出扫描信号。
  13. 根据权利要求11所述的电路单元，其中，所述电路单元还包括k个复位电路，所述扫描驱动电路中的所述复位电路共有m级；其中，
    第j级的所述复位电路的第一端连接第j+1级的所述输出端，所述j为大于0且小于m的任意整数；
    所述移位寄存电路与所述k个复位电路的第二端相连，所述k个复位电路与k个所述输出端之间具有相同的级序号组合；
    所述复位电路被配置为在第一端接收到扫描信号时使第二端所连接的移位寄存电路停止扫描信号的输出。
  14. 根据权利要求11所述的电路单元，其中，所述外部控制信号由k条控制信号线提供，所述移位寄存电路包括输出电路单元和k个晶体管，所述输出电路单元包括输出节点；其中，
    所述输出电路单元被配置为能够向所述输出节点输出扫描信号；
    所述k个晶体管的第一极均与所述输出节点相连；
    所述k个晶体管的栅极各自连接所述k条控制信号线中的一条；
    所述k个晶体管的第二极各自连接k个所述输出端中的一个；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  15. 根据权利要求11所述的电路单元，其中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管和第一电容，所述输入电路包括第二晶体管；其中，
    所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第 一节点连接所述k个输入电路的第二端；
    在所对应的级序号组合中的级序号均为奇数的所述移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的所述移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
    所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
    所述第二晶体管的栅极连接所述输入电路的第一端，第一极连接第一电平电压线或者所在输入电路的第一端，第二极连接所在输入电路的第二端；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  16. 根据权利要求13所述的电路单元，其中，所述移位寄存电路包括输出电路单元，所述输出电路单元包括输出节点；所述输出电路单元还包括第一晶体管、第一电容、第三晶体管和第四晶体管，所述复位电路包括第五晶体管；其中，
    所述第一晶体管的栅极连接第一节点，第二极连接所述输出节点；所述第一节点连接所述k个输入电路的第二端；
    在所对应的级序号组合中的级序号均为奇数的所述移位寄存电路中，所述第一晶体管的第一极连接第一时钟信号线；在所对应的级序号组合中的级序号均为偶数的所述移位寄存电路中，所述第一晶体管的第一极连接第二时钟信号线；所述第一时钟信号线和所述第二时钟信号线分别提供正相时钟信号和反相时钟信号中的一个；
    所述第一电容的第一端连接所述第一节点，第二端连接所述输出节点；
    所述第三晶体管的栅极连接所述k个复位电路的第二端，第一极连接所述第一节点，第二极连接第二电平电压线；
    所述第四晶体管的栅极连接所述k个复位电路的第二端，第一极连接所述输出节点，第二极连接第二电平电压线；
    所述第五晶体管的栅极和第一极均连接所在复位电路的第一端，第二极连接所在复位电路的第二端；
    其中，所述第一极和第二极分别是源极和漏极中的一个。
  17. 一种阵列基板，其中，包括如权利要求1至9中任一项所述的扫描驱动电路。
  18. 一种显示装置，其中，包括如权利要求17所述的阵列基板。
PCT/CN2017/111183 2017-05-05 2017-11-15 扫描驱动电路及其驱动方法、阵列基板和显示装置 Ceased WO2018201690A1 (zh)

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