WO2018196084A1 - 扫描驱动电路、阵列基板与显示面板 - Google Patents

扫描驱动电路、阵列基板与显示面板 Download PDF

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Publication number
WO2018196084A1
WO2018196084A1 PCT/CN2017/086185 CN2017086185W WO2018196084A1 WO 2018196084 A1 WO2018196084 A1 WO 2018196084A1 CN 2017086185 W CN2017086185 W CN 2017086185W WO 2018196084 A1 WO2018196084 A1 WO 2018196084A1
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Prior art keywords
signal
scan
pull
electrically connected
transistor
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PCT/CN2017/086185
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English (en)
French (fr)
Inventor
赵莽
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武汉华星光电技术有限公司
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Priority to US15/552,277 priority Critical patent/US10417977B2/en
Priority to KR1020197035158A priority patent/KR102405060B1/ko
Priority to JP2019556673A priority patent/JP7048037B2/ja
Priority to EP17907808.4A priority patent/EP3618048A4/en
Publication of WO2018196084A1 publication Critical patent/WO2018196084A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of displays, and more particularly to the field of display image display scan driving.
  • one pixel is divided into two sub-pixels, that is, one main pixel and one sub-pixel, which use different optical characteristics of two pixels to form different optical characteristics to improve the visual difference.
  • the driving structure of the pixel structure of the architecture mainly uses different data lines to provide different driving voltages (image data voltages) of the main pixels and the sub-pixels at different times of the same scanning period.
  • This pixel structure can be called 1G2D (1Gate 2dots).
  • the present invention provides a scan drive circuit having a simple structure.
  • the present invention also provides an array substrate and a display panel having the aforementioned scan driving circuit.
  • a scan driving circuit includes n scan driving units sequentially connected to each other, each scan driving unit at least comprising a start trigger end, a scan signal output end and a plurality of clock signal ends, wherein the scan drive unit in the i-th stage
  • the start trigger end is electrically connected to the scan signal output end of the i-1th stage, and the scan signal output end is used for outputting the scan signal and electrically connected to the i+1th start trigger end.
  • Each scan drive unit includes:
  • the startup trigger terminal is electrically connected to the input unit; and an output unit electrically connected to the scan signal output end.
  • the input unit is configured to receive the startup trigger signal and transmit it to the output unit, and control the output unit to be in a scanning state.
  • the scan drive The moving unit further includes a scanning signal modulation unit having a plurality of diode-connected transistors, wherein the plurality of transistors are connected to the plurality of clock signal terminals and output a clock modulation signal according to the plurality of clock signals, the clock modulation signal including And at least two first potentials separated by a predetermined period of time, the output unit outputs a scan driving signal from the scan signal output end corresponding to the clock modulation signal when in a scan state, the scan signal includes two intervals of the predetermined a sub-scanning signal of a time period, each of the sub-scanning signals corresponding to a first potential of the clock-modulated signal, wherein the two sub-scanning signals are used to control an image signal received by one pixel unit in one scanning period, the pixel unit including Two sub-pixel units, n is a natural number greater than 1, and i is a natural number less than n.
  • An array substrate wherein the array substrate includes a first region and a second region, wherein the first region includes 2n scan lines and a plurality of pixel units electrically connected to the scan lines, The 2n scanning lines are parallel to each other and insulated in order.
  • the second area is provided with the foregoing scan driving circuit, each scan driving unit is electrically connected to one scan line to output the scan signal to the pixel unit electrically connected to the scan line point to control the
  • the pixel unit receives the image signal to be displayed, wherein two scan driving circuits are disposed at opposite ends of the 2n scan lines, and two adjacent scan lines are respectively disposed opposite to the two scan driving units An electrical connection, wherein the scan driving circuit and the pixel unit are formed by the same process.
  • a display panel comprising the foregoing array substrate and a counter substrate disposed opposite to the array substrate, the display panel including a display area serving as an image display and a non-display area surrounding the display area, wherein the A first area of the array substrate corresponds to the display area, and the second area corresponds to the non-display area.
  • FIG. 2 is a schematic plan view showing the planar structure of the array substrate in the display panel shown in FIG. 1.
  • FIG. 4 is a schematic view showing the connection of the scan driving circuit and the scanning line in the display panel shown in FIG. 2.
  • FIG. 5 is a schematic diagram showing the specific circuit structure of any one of the scan driving units SDn in the scan driving circuit shown in FIG. 4.
  • FIG. 6 is a timing chart showing the operation of the scan driving unit SDn in the scan driving circuit in the display panel shown in FIGS. 3-5.
  • FIG. 7 is a schematic diagram showing the circuit structure of a scan driving unit SDi according to a modified embodiment of the present invention.
  • FIG. 1 is a schematic perspective view of a display device according to an embodiment of the invention.
  • the display device 10 includes a display panel 11 and an optical module (not shown), wherein the display panel 11 includes an image display area 11a and a non-display area 11b.
  • the display area 11a is used as an image display
  • the non-display area 11b is circumferentially disposed around the display area 11a
  • the non-display area 11b is a non-light-emitting area, and is not used for image display.
  • the display panel 11 further includes an array substrate 11c and a counter substrate 11d, and a liquid crystal layer 11e interposed between the array substrate 11c and the opposite substrate 11d.
  • the display device 10 and the display panel 11 use liquid crystal as a display medium.
  • the display device 10 and the display panel 11 may also be an organic light emitting semiconductor (OLED) as a display medium, and are not limited thereto.
  • OLED organic light emitting semiconductor
  • FIG. 2 is a schematic plan view of the array substrate 11 c in the display panel 11 shown in FIG. 1 .
  • the first area (not labeled) of the corresponding image display area 11a in the array substrate 11c includes a plurality of 2m*2n pixel units (Pixel) 110 and 2m (Data Line) data lines arranged in a matrix (Scan).
  • Line) 120 and 2n scan lines 130, m, n are natural numbers greater than one.
  • the plurality of data lines 120 are insulated from each other and arranged in parallel along the first direction Y by a first predetermined distance.
  • the plurality of scan lines 130 are also insulated and parallel to each other along the second direction X by a second predetermined distance.
  • the plurality of scan lines 130 are insulated from the plurality of data lines 120, and the first direction X and the second direction Y are perpendicular to each other.
  • the 2m data lines 120 are defined as D1, D2, ..., D2m-1, D2m, respectively; and the 2n scan lines 130 are defined as G1, G2, ..., G2n-1, G2n, respectively.
  • a plurality of the pixel units 110 are respectively located in a matrix formed by the plurality of data lines 120 and the scan lines 130, and are electrically connected to the corresponding data lines 120 and the scan lines 130.
  • the display device 10 further includes a control circuit 101 for driving the pixel matrix 110 for image display, a data driver circuit (Data Driver) 102, and a scan driver circuit (Scan Driver) 103 disposed on the array.
  • the data driving circuit 102 is electrically connected to the plurality of data lines 120 for transmitting image data for display to the plurality of pixel units 110 in the form of data voltages through the plurality of data lines 120.
  • the scan driving circuit 103 is configured to be electrically connected to the plurality of scan lines 130 for outputting scan signals through the plurality of scan lines 130 for controlling when the pixel unit 110 receives image data for image display.
  • the control circuit 101 is electrically connected to the data driving circuit 102 and the scan driving circuit 103 for controlling the working timing of the data driving circuit 102 and the scan driving circuit 103, that is, outputting the corresponding timing control signal to the data driving circuit 102 and scanning.
  • Drive circuit 103 is electrically connected to the data driving circuit 102 and the scan driving circuit 103 for controlling the working timing of the data driving circuit 102 and the scan driving circuit 103, that is, outputting the corresponding timing control signal to the data driving circuit 102 and scanning.
  • Drive circuit 103 is electrically connected to the data driving circuit 102 and the scan driving circuit 103 for controlling the working timing of the data driving circuit 102 and the scan driving circuit 103, that is, outputting the corresponding timing control signal to the data driving circuit 102 and scanning.
  • the display panel 11 is described by taking a liquid crystal display panel as an example, and each pixel unit 110 has at least one thin film transistor (TFT) switching element.
  • TFT thin film transistor
  • the gate of the TFT is electrically connected to the data line 120.
  • the data line 120 is referred to as a source line.
  • the scan line 130 is also referred to as a gate line.
  • the data driving circuit 102 is referred to as a source driver circuit
  • the scan driving circuit 103 is also referred to as a gate driver circuit.
  • the display device 10 further includes other auxiliary circuits for jointly performing display of an image, such as an image processing processing unit (GPU), a power supply circuit, and the like. It will not be described in detail in the example.
  • GPU image processing processing unit
  • FIG. 3 is a schematic diagram showing the electrical connection structure of a pixel unit 110 and the data line 120 and the scan line 130 as shown in FIG.
  • one pixel unit 110 includes two sub-pixels, and the two sub-pixels are defined as a first sub-pixel unit 111 and a second sub-pixel unit 113, respectively.
  • the first sub-pixel unit 111 includes a first thin film transistor Ta as a switching element and a first sub-pixel Px1.
  • the first sub-pixel Px1 is electrically connected to a drain (not labeled) of the first thin film transistor Ta, and the first thin film
  • the source (not shown) of the transistor Ta is electrically connected to the data line Dj
  • the gate (not labeled) of the first thin film transistor Ta is electrically connected to the scan line Gi.
  • the second sub-pixel unit 113 includes a second thin film transistor Tb and a second sub-pixel Px2.
  • the second sub-pixel Px is electrically connected to the drain (not labeled) of the first thin film transistor Tb, and the source (not labeled) of the second thin film transistor Tb is electrically connected to the data line Dj+1, and the gate of the second thin film transistor Tb
  • the pole (not shown) is also electrically connected to the scanning line Gi.
  • the scan signal Sc1 transmitted by the scan line Gn controls the first thin film transistor Ta to be turned on, and the data voltage (image signal) on the data line Dj is transmitted to the first sub-pixel Px1 So that the first sub-pixel Px1 performs image display.
  • the scan signal Sc2 transmitted by the scan line Gn controls the second thin film transistor Tb to be turned on, and the data voltage (image signal) on the data line Dj+1 is transmitted to the second sub-pixel Px2, so that the second sub-pixel Px1 Perform image display.
  • the first time period is separated from the second time period by a buffering time, so that the two sub-pixel units stably receive the data voltage.
  • i is a natural number less than 2n
  • j is a natural number less than 2m.
  • FIG. 4 is a schematic diagram of the connection between the scan driving circuit 103 and the scan line 130 in the display panel 11 as shown in FIG. 2 .
  • the two scan driving circuits 103 are respectively placed at positions corresponding to the non-display areas 11b on opposite sides of the array substrate 11c.
  • the two scan drive circuits 103 are defined as a first scan drive circuit 103a and a second scan drive circuit 103b, respectively.
  • the first scan driving circuit 103L and the second scan driving circuit 103R are electrically connected to the n scan lines, that is, the scan lines 130 are divided into two sets of n scan lines, and the two sets of scan lines are spaced apart from each other.
  • the two groups are electrically connected to the first scan driving circuit 103a and the second scan driving circuit 103b, respectively.
  • n is 1920.
  • each scan driving circuit 103 includes n scan driving units SD1 SDSDn, and n scan driving units SD1 DDn are electrically connected to n scan lines 130, respectively, and output pairs according to timing.
  • the n scan signals Sc are applied to the corresponding scan lines 130, thereby controlling the pixel unit 110 electrically connected thereto to be in a state in which the data voltage can be received.
  • the n scan driving units SD1 SD SDn are sequentially cascaded with each other, that is, the scan output terminal Gn-1 of the n-1th scan driving unit SDn-1 and the input trigger pin Pin of the nth scan driving unit SDn.
  • the electrical connection of the scan output terminal Gn of the nth scan driving unit SDn is electrically connected to the input trigger pin Pin of the n+1th scan driving unit SDn+1, and so on, and details are not described herein again.
  • the scan driving units SD1 - Dn are electrically connected to the scan lines G1, G3, ..., G2n-1, respectively, and output corresponding scan signals Sc1, Sc3, ... ...Sc2n-3, Sc2n-1;
  • the second scan driving circuit 103b they are electrically connected to the scanning lines Sc2, Sc4, ... Sc2n-2, Sc2n, respectively.
  • the two scan lines 130 are electrically connected to the first scan driving circuit 103a and the second scan driving circuit 103b, respectively, thereby effectively reducing the complexity of the trace when the scan line 130 is connected to the scan driving circuit 103. area.
  • the first scan driver 103a includes at least 12 signal control terminals, which are start signal terminal STV_L, reset signal terminal Reset, timing control signal terminals CT4_L, CT3_L, CT2_L, CT1_L, CC2_L, CC1_L, CK3_L, CK1_L, high voltage terminal VGH_L, And the low voltage end VGL_L.
  • the start signal terminal STV_L, the reset signal terminal Reset, the timing control signal terminals CT4_L, CT3_L, CT2_L, CT1_L, CC2_L, CC1_L, CK3_L, CK1_L are all electrically connected to the control circuit 101, respectively receiving the control signals output by the sub-control circuit 101. With timing signals. In the present embodiment, for convenience of explanation, the output control signal and the timing signal have the same sign.
  • the timing control signal terminals CT4_L, CT3_L, CT2_L, CT1_L, CC2_L, CC1_L, CK3_L, and CK1_L are divided into two groups, wherein the timing control signal terminals CT2_L, CT1_L, CC1_L, CK3_L, and CK1_L are the first group, and the timing control signal terminal is CT4_L, CT3_L, CC2_L, CK1_L, CK3_L are divided into a second group, the even-numbered scan driving unit SD2i is electrically connected to the first group of clock control signal terminals, and the odd-numbered scan driving unit SD2i-1 and the second group of clocks are controlled.
  • the signal terminals are electrically connected.
  • the second scan driver 103b includes at least 12 signal control terminals, which are the start signal terminal STV_R, the reset signal terminal Reset, the timing control signal terminals CT4_R, CT3_R, CT2_R, CT1_R, CC2_R, CC1_R, CK4_R, CK2_R. , high voltage terminal VGH_R, and low voltage terminal VGL_R.
  • the start signal terminal STV_R, the reset signal end Reset, the timing control signal terminals CT4_R, CT3_R, CT2_R, CT1_R, CC2_R, CC1_R, CK3_R, CK1_R are electrically connected to the control circuit 101, respectively receive the control signal output by the sub-control circuit 101. And timing signal.
  • the high voltage terminal VGH is used to output the high voltage signal VGH of the first reference voltage, the first reference voltage is 3.5V or more; and the low voltage terminal VGL is used to output the low voltage signal VGL of the second reference potential, the second reference voltage It is 0V.
  • the timing control signal terminals CC2_L, CC1_L, CC2_R, CC1_R can be used as the buffer clock signal end, and the buffer clock signal outputted by the timing control signal is used to control the corresponding scan driving unit to suspend the output of the scan signal.
  • CT4_L, CT3_L, CT2_L, CT1_L, CK3_L, CT4_R, CT3_R, CT2_R, CT1_R, CK3_R can be used as the scan clock signal end, and the output scan clock signal is used to control the corresponding scan drive unit to output the scan signal.
  • CK1_L and CK3_R are used as pull-down clock signal ends, and the output pull-down clock signal is used to control the preparation of the corresponding scan drive or to stop outputting the scan drive signal.
  • FIG. 5 is a schematic diagram of a specific circuit structure of any one of the scan driving units SDn in the scan driving circuit shown in FIG. 4 .
  • the scan driving unit SDn includes an input unit 100, a pull-down control unit 200, a voltage stabilizing unit 300, a first pull-down unit 400, an output unit 500, a scan signal modulation unit 600, and a second pull-down unit 700.
  • the scan driving unit SDn respectively constitutes the foregoing circuit unit through the first-seventeenth transistor T1-T17 and the capacitors C1-C4, and further, the scan driving unit SDn further includes an output control point Q(N) located in the foregoing circuit unit. a first pull-down control point P(N), a first control point H(N), a signal adjustment output point C(N), and a second pull-down control point T(N).
  • the first to seventeenth transistors T1-T17 are all N-Metal-Oxide-Semiconductors.
  • the circuit structure of the scan driving unit is specifically described by taking the nth-level scan driving unit SDn as an example. It can be understood that the circuit structures of other scan driving units are the same.
  • the input unit 100 is configured to receive the startup trigger signal STV-L, and output a corresponding control signal according to the startup trigger signal to achieve transmission of the scan signal Scn-2 output by the upper-stage scan driving unit SDn-2.
  • the input unit 100 includes a first input terminal 101, a first output terminal 103, and a first transistor T1.
  • the first input terminal 101 is configured to receive a scan signal Scn-2 transmitted to the scan line Gn-2.
  • a gate (not labeled) of a transistor T1 is electrically connected to the first input terminal 101.
  • a source (not labeled) of the first transistor T1 is electrically connected to the high voltage terminal VGH, and a drain (not labeled) of the first transistor T1 is electrically connected.
  • the first output terminal 103 is connected.
  • the input unit 101 outputs a corresponding driving signal from the first output end 103 according to the scan signal Scn-2 received by the first input terminal 101.
  • the first transistor T1 serves as an input transistor.
  • the pull-down control unit 200 is for controlling the stable output pull-down signal of the first pull-down unit 400.
  • the control unit 200 includes a second transistor T2 and an eleventh transistor T11, wherein a gate (not labeled) of the second transistor T2 is electrically connected to the first output terminal 103, and a source of the second transistor T2 is electrically connected.
  • the clock signal terminal CK1, the drain of the second transistor T2 is electrically connected to the first pull-down control point P(N) of the output control unit 400.
  • the gate (not labeled) of the eleventh transistor T11 is electrically connected to the clock signal terminal CK1, the source of the eleventh transistor T11 is electrically connected to the high voltage terminal VGH, and the drain of the eleventh transistor T11 is electrically connected to the output control unit 400.
  • the second transistor T11 serves as a first pull-down control transistor, and the eleventh transistor T11 serves as a second pull-down control transistor.
  • the voltage stabilizing unit 300 is configured to convert the input trigger signal into a more stable high voltage signal and transmit it to the output control point Q(N) of the output unit 500, so that the output unit 500 stably outputs the scan driving signal Scn to the scan signal output terminal Gn.
  • the voltage stabilizing unit 300 includes a third transistor T3, wherein the gate of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the source is electrically connected to the output control point Q(N) of the output unit 500, and the drain electrical property The first output terminal 103 is connected.
  • the third transistor T3 functions as a voltage stabilizing transistor.
  • the output unit 500 is configured to stably output the scan signal Scn according to the output control point Q(N).
  • the output unit 500 includes a fourth transistor T4 and a first capacitor C1.
  • the gate of the fourth transistor T4 is electrically connected to the output signal control point Q(N), the source is electrically connected to the signal adjustment output point C(N), and the drain is electrically connected to the scan signal output terminal Gn.
  • the first capacitor C1 is electrically connected between the signal control point Q(N) and the scan line signal output terminal Gn for maintaining the output control point Q(N) in the scanning state.
  • the fourth transistor T4 serves as an output control transistor, and the first capacitor C1 functions as a capacitor holding capacitor. In addition, when the output control point Q(N) is maintained in the scanning state, that is, the output unit 500 is in the scanning signal Output status.
  • the gate and the drain of the fifth transistor T5 are directly short-circuited and electrically connected to the clock signal terminal CT2 at the same time, the source is electrically connected to the signal regulating output point C(N); the gate and the drain of the sixth transistor T6 are Directly shorted and simultaneously connected to the clock signal terminal CT1, the source is electrically connected to the signal regulating output point C(N); the gate and drain of the seventh transistor T7 are directly shorted and simultaneously with the clock signal terminal CT2 Sex connection, source electrical connection signal adjustment output point C (N), that is, the fifth-seventh transistor T5-T7 are diode-connected.
  • the gate of the eighth transistor T8 is electrically connected to the clock signal terminal CC1, the drain electrode is connected to the signal regulating output point C(N), and the source is electrically connected to the high voltage terminal VGH.
  • the eighth transistor T8 serves as a buffer transistor.
  • the second pull-down unit 700 is electrically connected to the scan signal output terminal Gn for controlling the scan signal Scn at which the scan signal output terminal Gn stops outputting, in other words, for ensuring that the scan signal Scn is in the non-image display period when the control pixel unit 110 is in control Signal stability.
  • the pull-down unit 700 includes a fourteenth transistor T14, a sixteenth transistor T16, a seventeenth transistor T17, and a fourth capacitor C4.
  • the gate of the fourteenth transistor T14 is electrically connected to the second pull-down control point T(N), the source is electrically connected to the low voltage terminal VGL, and the drain is electrically connected to the scan line signal output terminal Gn.
  • the gate of the seventeenth transistor T17 electrically receives a start trigger signal, which is a scan line signal Scn-2 outputted by the scan line signal output terminal Gn-1 in the scan driving unit SDn-1.
  • the source of the seventeenth transistor T17 is electrically connected to the high voltage terminal VGH, and the drain is electrically connected to the second pull-down control point T(N).
  • the gate of the sixteenth transistor 16 is electrically connected to the clock signal terminal CK3, the source is electrically connected to the low voltage terminal VGL, and the drain is electrically connected to the second pull-down control point T(N).
  • the fourteenth transistor T14 functions as a second pull-down transistor
  • the seventeenth transistor T17 functions as a third pull-down transistor
  • the sixteenth transistor T16 functions as a fourth pull-down transistor.
  • FIG. 6 is an operation timing diagram of the scan driving unit corresponding to two adjacent scan lines 130 on the left and right ends of the scan driving circuit 103 in the scan driving circuit 103 in the display panel 11 as shown in FIG.
  • the scan driving unit SDn shown in FIG. 6 only shows the timing of driving the image display by driving one pixel unit 110 on the two adjacent scan lines SDn and SDn+1 in one frame image display.
  • symbols STV_L, Reset, CT4_L, CT3_L, CT2_L, CT1_L, CC2_L, CC1_L, CK3_L, and CK1_L in the figure indicate one scan driving unit driving timing on the left side;
  • STV_R, CT4_R, CT3_R, CT2_R, CT1_R, CC2_R, CC1_R, CK4_R and CK2_R indicate the driving timing of one scanning driving unit on the right side, and the circuit waveform diagram corresponding to the above symbol indicates the waveform of the output signal.
  • the waveform corresponding to the scan driving circuit SDn includes STV_L, Reset, CT2_L, CT1_L, CC1_L, CK3_L, and CK1_L.
  • the driving timing of one of the scanning driving units SDn on the left side of the scanning line 130 will be described as an example.
  • the reset terminal Reset is in an enabled state, so that all circuit elements of the scan driving unit SDn in the scan driving circuit 103 are in an initial operating state.
  • the STV_L as the start trigger signal is in a high potential state, wherein the start trigger signal STV_L for the scan driving unit SDn is the scan drive of the scan driving unit SDn-1. Signal Gn-2.
  • the clock signal CK1_L is also in a high potential state. Therefore, referring to FIG. 5 and FIG. 4, the first transistor T1 is turned on under the high potential driving of the start signal STV_L, and the high voltage signal VGH is transmitted to the drain through the source of the first transistor T1. That is, it is transmitted to the first output terminal 103.
  • the voltage stabilizing unit 300 transmits the high potential of the first output terminal 103 to the output control point Q(N), and the output control point Q(N) maintains the high potential state via the first capacitor C1.
  • the fourth transistor T4 is placed in an on state. Accordingly, the clock signals CT2, CT1, and CK3 are all in a low potential state, whereby the signal adjustment output point C(N) outputs a low potential adjustment signal to the scan signal output terminal Gn.
  • the second transistor T2 is in an on state under the high potential control of the first output terminal 103, whereby the clock signal CK1_L is transmitted to the first pull-down control point P(N) via the source of the second transistor T2, and
  • the eleven transistor T11 is in an on state under the control of the high potential clock signal CK1_L, and also synchronously transmits the high voltage signal VGH to the first control point P(N), and the third capacitor is used to maintain the first pull-down control point P(N) The high potential state.
  • the thirteenth transistor T13 is in an on state under the control of the first pull-down control point P(N) of the high potential, and the low voltage signal VGL is transmitted from the source of the thirteenth transistor T13 to the output of the scan signal, thereby ensuring the scan signal.
  • the fifteenth transistor T15 under the control of the high potential STV_L, the fifteenth transistor T15 is in an on state, and the low voltage VGL is transmitted from the source of the fifteenth transistor T15 to the first control point H(N), thereby making the first control point H(N) is at a low potential.
  • the seventeenth transistor T17 under the control of the high potential STV_L, the seventeenth transistor T17 is in an on state, and the high voltage signal VGH is transmitted from the source of the seventeenth transistor to the second pull-down control point electrically connected to the drain.
  • the fourth capacitor C4 maintains the high potential state of the second pull-down control point T(N).
  • the triggering of the start trigger signal STV_L is completed, and the high potential jumps to the low potential.
  • the clock signal CK3_L is in the trigger state, that is, the high potential state.
  • the first transistor T1 is in an off state, and the output control terminal Q(N) is maintained in a high potential state.
  • the clock signal CC1_L stops the enable state transition to the low potential, and the clock signal CT1_L is in the enable state, that is, the clock signal CT1_L jumps to the high potential.
  • the sixth transistor T6 in the scan signal adjusting unit 600 is in an on state.
  • the high potential clock signal CT1_L is transmitted to the adjustment signal output terminal C(N) through the sixth transistor T6, thereby causing the scan line signal output terminal Gn to be in the first
  • the fifth sub-scanning signal Sc2 is outputted by the second sub-scanning signal Sc2, and the second sub-scanning line signal Sc2 is used to drive the second sub-pixel Px2, that is, the control thin film transistor Tb is in an on state, so that the data voltage Dm+ to be displayed is displayed. 1 is transmitted to the first sub-pixel 111.
  • the clock signal CT1_L stops the enable state transition to a low potential, and the clock signal CT2_L is in an enabled state, that is, the clock signal CT2_L jumps to a high potential.
  • the fifth transistor T5 in the scan signal adjusting unit 600 is in an on state. Therefore, the high potential clock signal CT1_L is again transmitted to the adjustment signal output terminal C(N) through the fifth transistor T5, so that the scan line signal output terminal Gn is The sixth sub-scanning signal Sc2 is still outputted in the sixth period t6, so that the first sub-pixel 111 receives the display data voltage Dm+1 extension.
  • the second time period t5 and the sixth time period t6 continuously output the two second sub-scanning signals Sc2 as another sub-scanning signal whose duration is twice the first sub-scanning line signal Sc1.
  • FIG. 7 is a schematic structural diagram of a circuit of a scan driving unit SDi according to a modified embodiment of the present invention.
  • the circuit structure of the scan driving unit SDi is basically the same as that of the scan driving unit SDn, and the difference lies only in the first-seventh transistor.
  • T1-T17 are both P-channel Metal Oxide Semiconductor (PMOS).

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Abstract

公开了一种扫描驱动电路以及具有该扫描驱动电路的阵列基板与显示面板。该扫描驱动电路包括多个依次相互级联的多个扫描驱动单元。每一个扫描驱动单元包括输入单元（100）及与输出单元（500）。输入单元（100）用于接收启动触发信号并将启动触发信号传输至输出单元（500）并控制输出单元（500）处于扫描状态。扫描驱动单元还包括具有多个以二极管方式连接的晶体管的扫描信号调制单元（600），多个晶体管依据多个时钟信号输出时钟调制信号，时钟调制信号包括至少两个间隔预订时间段的第一电位。输出单元（500）对应时钟调制信号自扫描信号输出端输出扫描驱动信号。扫描信号包括对应第一电位的两个子扫描信号从而控制在一个扫描周期内的一个像素单元接收图像信号。

Description

扫描驱动电路、阵列基板与显示面板
本发明要求2017年4月27日递交的发明名称为“扫描驱动电路与阵列基板”的申请号201710290786.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示器领域，尤其涉及显示器图像显示扫描驱动领域。
背景技术
为解决显示器视角色差(color washout)的问题，将一个像素划分为两个子像素，即一个主像素，一个次像素，利用两像素的驱动电压不同，组成不同的光学特性来达到改善视角色差的目的。此架构的像素结构的驱动方式主要利用不同的数据线在同一个扫描周期的不同时间提供主像素与次像素不同的驱动电压(图像数据电压)，此像素结构可称为1G2D(1Gate 2dots)。但是前述1G2D像素架构的扫描驱动电路(Scan Driver/Gate Driver)输出的扫描信号无法灵活调整两个子像素接收驱动电压的时间，使得此类架构的扫描驱动电路结构复杂。
发明内容
为解决前述技术问题，本发明提供一种结构简单的扫描驱动电路。
进一步地，本发明还提供具有前述扫描驱动电路的阵列基板与显示面板。
一种扫描驱动电路，包括依次相互级联的n个扫描驱动单元，每一个扫描驱动单元至少包括启动触发端、扫描信号输出端与多个时钟信号端，其中，处于第i级的扫描驱动单元的启动触发端与第i-1级的扫描信号输出端电性连接，扫描信号输出端用于输出扫描信号且与第i+1的启动触发端电性连接，每一个扫描驱动单元包括：与所述启动触发端电性连接输入单元；及与所述扫描信号输出端电性连接的输出单元。其中，所述输入单元用于接收所述启动触发信号并将其传输至所述输出单元，并控制所述输出单元处于扫描状态。所述扫描驱 动单元还包括具有多个以二极管方式连接的晶体管的扫描信号调制单元，多个所述晶体管连接于多个所述时钟信号端并依据多个时钟信号输出时钟调制信号，所述时钟调制信号包括至少两个间隔预定时间段的第一电位，所述输出单元在处于扫描状态时对应所述时钟调制信号自所述扫描信号输出端输出扫描驱动信号，所述扫描信号包括两个间隔所述预定时间段的子扫描信号，每一个子扫描信号均对应时钟调制信号的第一电位，两个所述子扫描信号用于控制在一个扫描周期内的一个像素单元接收图像信号，所述像素单元包括两个子像素单元，n为大于1的自然数，i为小于n的自然数。
一种阵列基板，其特征在于，所述阵列基板包括第一区域与第二区域，其中，所述第一区域包括2n条扫描线以及与所述扫描线电性连接的多个像素单元，所述2n条扫描线相互平行且绝缘依次排列。所述第二区域设置有前述的扫描驱动电路，每一个扫描驱动单元电性连接一条扫描线以输出所述扫描信号至与所述扫描线点电性连接的所述像素单元，以控制所述像素单元接收待显示图像信号，其中，两个所述扫描驱动电路设置于所述2n条扫描线的相对两端，任意相邻的两条扫描线分别与相对设置的两个所述扫描驱动单元电性连接，其中，所述扫描驱动电路与所述像素单元采用相同的制程形成。
一种显示面板，包括前述阵列基板以及与所述阵列基板正对设置的对向基板，所述显示面板包括用作图像显示的显示区与环绕所述显示区的非显示区，其中，所述阵列基板的第一区域对应所述显示区域，所述第二区域对应所述非显示区。
相较于现有技术，扫描驱动电路通过至少两个二极管方式连接的晶体管调节扫描信号的波形，使其能够灵活、稳定地针对一个像素单元中的两个子像素进行扫描线，使其在不同时间段内接收待显示的图像数据电压从而进行图像显示。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例所述的显示装置的立体结构图。
图2为图1所示显示面板中阵列基板的平面结构示意图。
图3为如图2所示一个像素单元与数据线、扫描线的电性连接结构示意图。
图4为如图2所示显示面板中扫描驱动电路与扫描线的连接示意图。
图5为如图4所示扫描驱动电路中任意一个扫描驱动单元SDn的具体地电路结构示意图。
图6为如图3-5所示显示面板中扫描驱动电路中扫描驱动单元SDn的工作时序图。
图7为本发明一变更实施例扫描驱动单元SDi的电路结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1为本发明一实施例中所述的显示装置立体结构示意图。如图1所示，显示装置10包括显示器面板11与光学模组(未标示)，其中，显示面板11包括图像用显示区11a与非显示区11b。显示区11a用作图像显示，非显示区11b环绕设置于显示区11a周围，非显示区11b为非出光区域，并不用作图像显示。其中，显示面板11还包括有阵列基板11c与对向基板11d，以及夹设于阵列基板11c与对向基板11d的液晶层11e。本实施例中，显示装置10以及显示面板11以液晶作为显示介质。当然，在本发明其他变更实施例中，显示装置10与显示面板11也可以有机发光半导体材料(Organic Electroluminescence Diode，OLED)作为显示介质，并不以此为限。
请参阅图2，其为图1所示显示面板11中阵列基板11c的平面结构示意图。如图2所示，阵列基板11c中对应图像显示区11a的第一区域(未标示)包括多个呈矩阵排列的2m*2n像素单元(Pixel)110、2m条(Data Line)数据线(Scan Line)120以及2n条扫描线130，m、n为大于1的自然数。其中，该多条数据线120沿第一方向Y间隔第一预定距离相互绝缘且平行排列，该多条扫描线130沿第二方向X亦间隔第二预定距离相互绝缘且平行排列，并且所 该多条扫描线130与该多条数据线120相互绝缘，所述第一方向X与第二方向Y相互垂直。为便于说明，所述2m条数据线120分别定义为D1、D2、……，D2m-1、D2m；所述2n条扫描线130分别定义为G1、G2、……，G2n-1、G2n。多个所述像素单元110分别位于该多条数据线120、扫描线130构成的矩阵中，并且与对应的其中数据线120以及扫描线130电性连接。
对应显示面板11的非显示区11b，显示装置10进一步包括的用于驱动像素矩阵110进行图像显示的控制电路101、数据驱动电路(Data Driver)102以及扫描驱动电路(Scan Driver)103设置于阵列基板11c的第二区域(未标示)。其中，数据驱动电路102与该多条数据线120电性连接，用于将待显示用的图像数据通过该多条数据线120以数据电压的形式传输至该多个像素单元110。扫描驱动电路103用于与该多条扫描线130电性连接，用于通过该多条扫描线130输出扫描信号用于控制像素单元110何时接收图像数据进行图像显示。控制电路101分别与数据驱动电路102和扫描驱动电路103电性连接，用于控制数据驱动电路102与扫描驱动电路103的工作时序，也即是输出对应的时序控制信号至数据驱动电路102以及扫描驱动电路103。
本实施例中，扫描驱动电路103直接设置于显示面板11的非显示区11b(未标示)中，控制电路101与数据驱动电路102则独立于阵列基板11c设置于其他的承载电路板板上。本实施例中，扫描驱动电路103中的电路元件与显示面板11中的像素单元110同一制程制作于显示面板11中，也即是GOA(Gate on Array)技术。另外，像素单元110对应包括的薄膜晶体管、像素电极等可采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)制程形成，当然，扫描驱动电路103也均一并采用LTPS制程形成。
其中，需要说明的，本实施例中，显示面板11是以液晶显示面板为例进行说明的，同时每一个像素单元110中至少具有一个薄膜晶体管(Thin Film Transistor，TFT)的开关元件，因此，其中，所述TFT的栅极电性扫描线130，源极电性连接数据线120，由此，数据线120称为源极线(Source Line)，扫描线130又称为栅极线(Gate Line)；对应地，数据驱动电路102称为源极驱动电路(Source Driver)，扫描驱动电路103又称为栅极驱动电路(Gate driver)。
可以理解，显示装置10还包括有其他辅助电路用于共同完成图像的显示，例如图像接收处理电路(Graphics Processing Unit，GPU)、电源电路等，本实 施例中不再对其进行赘述。
进一步，请参阅图3，图3为如图2所示一个像素单元110与数据线120、扫描线130的电性连接结构示意图。
如图3所示，一个像素单元110包括两个子像素，两个所述子像素分别定义为第一子像素单元111与第二子像素单元113。其中，第一子像素单元111包括作为开关元件的第一薄膜晶体管Ta以及第一子像素Px1，第一子像素Px1与第一薄膜晶体管Ta的漏极(未标示)电性连接，第一薄膜晶体管Ta的源极(未标示)电性连接数据线Dj，第一薄膜晶体管Ta的栅极(未标示)电性连接扫描线Gi。
第二子像素单元113包括第二薄膜晶体管Tb以及第二子像素Px2。第二子像素Px与第一薄膜晶体管Tb的漏极(未标示)电性连接，第二薄膜晶体管Tb的源极(未标示)电性连接数据线Dj+1，第二薄膜晶体管Tb的栅极(未标示)也电性连接扫描线Gi。
在一帧图像的一个扫描周期内，第一时间段，扫描线Gn传输的扫描信号Sc1控制第一薄膜晶体管Ta导通，数据线Dj上的数据电压(图像信号)传输至第一子像素Px1，从而使得第一子像素Px1进行图像显示。第二时间段，扫描线Gn传输的扫描信号Sc2控制第二薄膜晶体管Tb导通，数据线Dj+1上的数据电压(图像信号)传输至第二子像素Px2，从而使得第二子像素Px1进行图像显示。其中，第一时间段与第二时间段间隔一缓冲时间，以便于两个子像素单元稳定的接收数据电压。i为小于2n的自然数，j为小于2m的自然数。
请参阅图4，其为如图2所示显示面板11中扫描驱动电路103与扫描线130的连接示意图。如图4所示，两个扫描驱动电路103，分别置于阵列基板11c相对两侧对应非显示区11b的位置。
两个所述扫描驱动电路103分别定义为第一扫描驱动电路103a与第二扫描驱动电路103b。第一扫描驱动电路103L与第二扫描驱动电路103R分别电性连接n条扫描线，也即是将扫描线130分为两组n条扫描线，所述两组扫描线相互间隔设置，所述两组分别电性连接第一扫描驱动电路103a与第二扫描驱动电路103b。本实施例中，n为1920。
具体地，每一个扫描驱动电路103包括n个扫描驱动单元SD1～SDn，n个扫描驱动单元SD1～Dn分别与n条扫描线130电性连接，且按照时序输出对 应的n个扫描信号Sc至对应的扫描线130，进而控制与其电性连接的像素单元110处于可接收数据电压的状态。所述的n个扫描驱动单元SD1～SDn依次相互级联，也即是第n-1个扫描驱动单元SDn-1的扫描输出端Gn-1与第n个扫描驱动单元SDn的输入触发端Pin电性连接，第n个扫描驱动单元SDn的扫描输出端Gn电性连接第n+1个扫描驱动单元SDn+1的输入触发端Pin电性连接，依次类推，在此不再赘述。当然，对于第一扫描驱动电路103a而言，其个扫描驱动单元SD1～Dn分别依次与扫描线G1、G3，……，G2n-1电性连接，并且输出对应的扫描信号Sc1、Sc3，……Sc2n-3，Sc2n-1；对于第二扫描驱动电路103b而言，其分别与扫描线Sc2、Sc4，……Sc2n-2，Sc2n电性连接。可见，任意相邻得了两个扫描线130分别与第一扫描驱动电路103a与第二扫描驱动电路103b电性连接，从而有效减小扫描线130与扫描驱动电路103连接时走线的复杂程度与面积。
第一扫描驱动器103a至少包括12个信号控制端，其分别为启动信号端STV_L，复位信号端Reset，时序控制信号端CT4_L、CT3_L、CT2_L、CT1_L、CC2_L、CC1_L、CK3_L、CK1_L、高压端VGH_L、以及低压端VGL_L。其中，启动信号端STV_L，复位信号端Reset，时序控制信号端CT4_L、CT3_L、CT2_L、CT1_L、CC2_L、CC1_L、CK3_L、CK1_L均与控制电路101电性连接，分别接收子控制电路101输出的控制信号与时序信号。本实施例中，为了便于说明，所输出的控制信号与时序信号的符号与其相同。
其中，时序控制信号端CT4_L、CT3_L、CT2_L、CT1_L、CC2_L、CC1_L、CK3_L、CK1_L分为两组，其中，时序控制信号端CT2_L、CT1_L、CC1_L、CK3_L、CK1_L为第一组，时序控制信号端CT4_L、CT3_L、CC2_L、CK1_L、CK3_L分为第二组，偶数级的扫描驱动单元SD2i与第一组时钟控制信号端电性连接，而奇数级的扫描驱动单元SD2i-1与第二组时钟控制信号端电性连接。
同理对应地，第二扫描驱动器103b至少包括12个信号控制端，其分别为启动信号端STV_R，复位信号端Reset，时序控制信号端CT4_R、CT3_R、CT2_R、CT1_R、CC2_R、CC1_R、CK4_R、CK2_R、高压端VGH_R、以及低压端VGL_R。其中，启动信号端STV_R，复位信号端Reset，时序控制信号端CT4_R、CT3_R、CT2_R、CT1_R、CC2_R、CC1_R、CK3_R、CK1_R均与控制电路101电性连接，分别接收子控制电路101输出的控制信号与时序 信号。其中，高压端VGH用于输出第一参考电压的高压信号VGH，所述第一参考电压为3.5V以上；而低压端VGL用于输出第二参考电位的低压信号VGL，所述第二参考电压为0V。时序控制信号端CC2_L、CC1_L、CC2_R、CC1_R可作为缓冲时钟信号端，其输出的缓冲时钟信号用于控制对应的扫描驱动单元暂停输出扫描信号。CT4_L、CT3_L、CT2_L、CT1_L、CK3_L、CT4_R、CT3_R、CT2_R、CT1_R、CK3_R可作为扫描时钟信号端，其输出的扫描时钟信号用于控制对应的扫描驱动单元输出扫描信号。CK1_L与CK3_R作为下拉时钟信号端，其输出的下拉时钟信号用于控制对应的扫描驱动的准备或者停止输出扫描驱动信号。
请参阅图5，其为如图4所示扫描驱动电路中任意一个扫描驱动单元SDn的具体地电路结构示意图。
如图5所示，扫描驱动单元SDn包括输入单元100、下拉控制单元200、稳压单元300、第一下拉单元400、输出单元500、扫描信号调制单元600以及第二下拉单元700。其中，扫描驱动单元SDn通过第一-第十七晶体管T1-T17以及电容C1-C4分别构成前述电路单元，另外，扫描驱动单元SDn还包括有位于前述电路单元中的输出控制点Q(N)、第一下拉控制点P(N)、第一控制点H(N)、信号调节输出点C(N)以及第二下拉控制点T(N)。本实施例中，第一-第十七晶体管T1-T17均为N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor)。
本实施例以第n级扫描驱动单元SDn为例具体说明扫描驱动单元的电路结构，可以理解，其他扫描驱动单元的电路结构与其相同。
输入单元100用于接收启动触发信号STV-L，并且依据启动触发信号输出对应的控制信号，以达到对上一级扫描驱动单元SDn-2输出的扫描信号Scn-2的传输。可以理解，具体地，输入单元100包括第一输入端101、第一输出端103以及第一晶体管T1，第一输入端101用于接收传输至扫描线Gn-2的扫描信号Scn-2，第一晶体管T1的栅极(未标示)电性连接第一输入端101，第一晶体管T1的源极(未标示)电性连接高压端VGH，第一晶体管T1的漏极(未标示)电性连接第一输出端103。其中，输入单元101依据第一输入端101接收的扫描信号Scn-2自第一输出端103输出对应的驱动信号。其中，第一晶体管T1作为输入晶体管。
下拉控制单元200用于控制第一下拉单元400的稳定输出下拉信号。具体地，控制单元200包括第二晶体管T2与第十一晶体管T11，其中，第二晶体管T2的栅极(未标示)电性连第一输出端103，第二晶体管T2的源极电性连接时钟信号端CK1，第二晶体管T2的漏极电性连接输出控制单元400的第一下拉控制点P(N)。第十一晶体管T11的栅极(未标示)电性连时钟信号端CK1，第十一晶体管T11的源极电性连接高压端VGH，第十一晶体管T11的漏极电性连接输出控制单元400的第一下拉控制点P(N)端。其中，第二晶体管T11作为第一下拉控制晶体管，而第十一晶体管T11作为第二下拉控制晶体管。
稳压单元300用于将输入触发信号转换为更为稳定的高压信号传输至输出单元500的输出控制点Q(N)，使得输出单元500稳定输出扫描驱动信号Scn至扫描信号输出端Gn。具体地，稳压单元300包括第三晶体管T3，其中，第三晶体管T3的栅极电性连接高压端VGH，源极电性连接输出单元500的输出控制点Q(N)，漏极电性连接第一输出端103。其中，第三晶体管T3作为稳压晶体管。
第一下拉单元400用于输出下拉信号至控制输出单元500，以控制输出单元500与扫描信号输出端Gn停止输出扫描信号Scn。具体地，第一下拉单元400包括第九晶体管T9、第十晶体管T10、第十二晶体管T12、第十五晶体管T15、第二电容C2以及第三电容C3。其中，第九晶体管T9电性连接第一控制点H(N)、源极电性连接第一输出端103，漏极电性连接第十二晶体管T12的源极。第十晶体管T10的栅极与漏极直接电性连接至信号调节输出点C(N)，第十晶体管T10的源极电性连接第一控制点H(N)。其中，第十晶体管T10采用二极管连接方式。第十二晶体管T12的栅极第一下拉控制点P(N)。其中，第十三晶体管T13作为第一下拉晶体管，第三电容C3作为下拉维持电容。
输出单元500用于依据输出控制点Q(N)稳定输出扫描信号Scn。具体地，输出单元500包括第四晶体管T4以及第一电容C1。其中，第四晶体管T4的栅极电性连接输出信号控制点Q(N)，源极电性连接信号调节输出点C(N)，漏极电性连接扫描信号输出端Gn。第一电容C1电性连接于信号控制点Q(N)以及扫描线信号输出端Gn之间，用于维持输出控制点Q(N)维持在扫描状态。其中，第四晶体管T4作为输出控制晶体管，第一电容C1作为电容维持电容。另外，当输出控制点Q(N)维持在扫描状态，即输出单元500处于扫描信号的 输出状态。
扫描信号调制单元600用于依据多个时序控制信号输出一时钟调制信号，用于控制扫描驱动单元SDn输出的扫描线信号Scn的波形，从而使得扫描信号Scn能够控制像素单元110中两个子像素单元的图像显示。具体地，扫描信号调节单元600包括第六晶体T5、第七晶体管T6、第七晶体管T7以及第八晶体管T8。其中，第五晶体管T5的栅极与漏极直接短接并且同时与时钟信号端CT2电性连接，源极电性连接信号调节输出点C(N)；第六晶体管T6的栅极与漏极直接短接并且同时与时钟信号端CT1电性连接，源极电性连接信号调节输出点C(N)；第第七晶体管T7的栅极与漏极直接短接并且同时与时钟信号端CT2电性连接，源极电性连接信号调节输出点C(N)，也即是第五-第七晶体管T5-T7均采用二极管连接方式。第八晶体管T8的栅极电性连接时钟信号端CC1，漏极电性连信号调节输出点C(N)，源极电性连接高压端VGH。其中，第八晶体管T8作为缓冲晶体管。
第二下拉单元700电性连接于扫描信号输出端Gn，用于控制扫描信号输出端Gn停止输出的扫描信号Scn，换句话说，用于保证扫描信号Scn处于控制像素单元110处于非图像显示期间信号的稳定性。具体地，下拉单元700包括第十四晶体管T14、第十六晶体管T16、第十七晶体管T17以及第四电容C4。其中，第十四晶体管T14的栅极电性连接第二下拉控制点T(N)，源极电性连接低压端VGL，漏极电性连连接扫描线信号输出端Gn。第十七晶体管T17的栅极电性接收启动触发信号，所述启动触发信号为扫描驱动单元SDn-1中的扫描线信号输出端Gn-1输出的扫描线信号Scn-2。第十七晶体管T17的源极电性连接高压端VGH，漏极电性连接第二下拉控制点T(N)。第十六晶体管16的栅极电性连接时钟信号端CK3，源极电性连接低压端VGL，漏极电性连接第二下拉控制点T(N)。其中，第十四晶体管T14作为第二下拉晶体管，第十七晶体管T17作为第三下拉晶体管，第十六晶体管T16作为第四下拉晶体管。
请参与图6，其为如图3-5所示显示面板11中扫描驱动电路103中处于扫描线130相对的左右两端两个相邻扫描线130对应的扫描驱动单元的工作时序图。其中，需要说明是，图6所示的扫描驱动单元SDn仅示出一帧图像显示中驱动二条相邻扫描线SDn、SDn+1上一个像素单元110进行图像显示的时序 图。另外，图中的符号STV_L，Reset，CT4_L、CT3_L、CT2_L、CT1_L、CC2_L、CC1_L、CK3_L、CK1_L表示左侧的一个扫描驱动单元驱动时序；STV_R，CT4_R、CT3_R、CT2_R、CT1_R、CC2_R、CC1_R、CK4_R、CK2_R表示右侧的一个扫描驱动单元驱动时序，前述符号所对应的电路波形图表示其输出信号的波形。当然，对应扫描驱动电路SDn的波形则包括STV_L、Reset，CT2_L、CT1_L、CC1_L、CK3_L、CK1_L。
由于两个扫描驱动单元的驱动方式相同，现以扫描线130左侧的其中一个扫描驱动单元SDn的驱动时序为例进行说明。
如图6所示，在复位时间段Tr，复位端Reset处于使能状态，使得扫描驱动电路103中的扫描驱动单元SDn的所有电路元件均处于初始工作状态。
进一步，在第一时间段t1，也即是启动触发阶段，作为启动触发信号的STV_L处于高电位状态，其中，针对扫描驱动单元SDn的启动触发信号STV_L即为扫描驱动单元SDn-1的扫描驱动信号Gn-2。同时，时钟信号CK1_L亦处于高电位状态。由此，一并参阅图5与图4可知，第一晶体管T1在启动出发信号STV_L的高电位驱动下处于导通状态，高压信号VGH则通过第一晶体管T1的源极传输至漏极，也即是传输至第一输出端103。当第一输出端103处于高电位时，稳压单元300将第一输出端103的高电位传输至输出控制点Q(N)，输出控制点Q(N)经由第一电容C1保持高电位状态从而使得第四晶体管T4处于导通状态。相应地，时钟信号CT2、CT1以及CK3均为低电位状态，由此信号调节输出点C(N)输出低电位的调节信号至扫描信号输出端Gn。
同时，第二晶体管T2在第一输出端103高电位控制下处于导通状态，由此，时钟信号CK1_L经由第二晶体管T2的源极传输至第一下拉控制点P(N)，以及第十一晶体管T11在高电位的时钟信号CK1_L控制下处于导通状态，亦将高压信号VGH同步传输至第一控制点P(N)，第三电容用于维持第一下拉控制点P(N)的高电位状态。第十三晶体管T13在高电位的第一下拉控制点P(N)控制下处于导通状态，则低压信号VGL自第十三晶体管T13的源极传输至扫描信号输出端，保证了扫描信号Scn的稳定性。
另外，在高电位的STV_L的控制下，第十五晶体管T15处于导通状态，低电压VGL自第十五晶体管T15的源极传输至第一控制点H(N)，从而使得第一控制点H(N)处于低电位。
对应下拉单元700中，在高电位的STV_L的控制下，第十七晶体管T17处于导通状态，高压信号VGH自第十七晶体管的源极传输至与漏极电性连接的第二下拉控制点T(N)，第四电容C4维持第二下拉控制点T(N)的高电位状态。
在t2时间段，时钟信号CK1_L跳变为低电位，时钟信号STV_L保持高电位，从而使得输出控制点Q(N)保持高电位，导通的第二晶体管T2将低电位的时钟信号CK1_L传输至第一下拉控制点P(N)，从而使得第一下拉控制点P(N)维持低电位。高压信号VGH通过导通的第十七晶体管T17使得下拉点T(N)维持高电位，进而使得扫描信号输出端Gn维持稳定的低电位状态，而不会出现悬空状态。
在第三时间段t3，启动触发信号STV_L触发完成，由高电位跳变为低电位，同时，时钟信号CK3_L处于触发状态，也即是高电位状态。第一晶体管T1处于截止状态，输出控制端Q(N)维持高电位状态。同时，第七晶体管T7处于导通状态并呈现内阻较小的电阻特性，从而将使得信号调节点C(N)输出高电位信号，并且通过第四晶体管T4传输至扫描信号输出端Gn，从而使得扫描线信号输出端Gn在第三时间段t3输出第一子扫描信号Sc1，所述第一子扫描线信号Sc1则用于驱动第一子像素Px1，也即是控制薄膜晶体管Ta处于导通状态，使得待显示数据电压Dm传输至第一子像素111。
由此，第三输出端103在输出控制端Q(N)控制处于高电位状态，低电位的时钟信号CK1_L自第二晶体管T2的源极传输至第一下拉控制点P(N)。与此同时，信号调节点C(N)输出高电位信号使得二极管连接的第十晶体管T10处于导通状态，从而使得第一控制点H(N)处于高电位状态。
对应下拉单元700，第十七晶体管T17在启动触发信号STV_L处于截止状态，第十六晶体管T16在时钟信号CK3_L控制处于导通状态，，低电压信号自第十六晶体管T16的源极传输至与其漏极电性连接的第二下拉控制点T(N)，使得第二下拉控制点T(N)处于低电位，使得第十四晶体管14处于截止状态。
在第四时间段t4，时钟信号CK3_L跳变为低电位，时钟信号CC1_L处于使能状态，也即是时钟信号CC1_L跳变为高电位。扫描信号调节单元600中的第八晶体管T8处于导通状态，低电位VGL自第八晶体管T8的源极传输至与其漏极电性连接的调节信号输出端C(N)。由于输出控制点Q(N)一直维持在 高电位，也即是第四晶体管T4仍然处于导通状态，调节信号输出端C(N)的低电位则通过第四晶体管T4传输至扫描信号输出端Gn，从而使得扫描信号在此时间段输出低电位的缓冲扫描信号Sct，从而控制第一子像素Px1停止接收数据电压。其中，所述第四时间段t4作为前述的预定时间段。
在第五时间段t5，时钟信号CC1_L停止使能状态跳变为低电位，时钟信号CT1_L处于使能状态，也即是时钟信号CT1_L跳变为高电位。扫描信号调节单元600中的第六晶体管T6处于导通状态，因此，高电位的时钟信号CT1_L通过第六晶体管T6传输至调节信号输出端C(N)，进而使得扫描线信号输出端Gn在第五时间段t5输出第二子扫描信号Sc2，所述第二子扫描线信号Sc2则用于驱动第二子像素Px2，也即是控制薄膜晶体管Tb处于导通状态，使得待显示数据电压Dm+1传输至第一子像素111。
较佳地，在第六时间段T6，时钟信号CT1_L停止使能状态跳变为低电位，时钟信号CT2_L处于使能状态，也即是时钟信号CT2_L跳变为高电位。扫描信号调节单元600中的第五晶体管T5处于导通状态，因此，高电位的时钟信号CT1_L通过第五晶体管T5再次传输至调节信号输出端C(N)，进而使得扫描线信号输出端Gn在第六时间段t6仍然输出第二子扫描信号Sc2，使得第一子像素111接收显示数据电压Dm+1延长。
当然，第五时间段t5与第六时间段t6连续输出两个第二子扫描信号Sc2也以为作为一个持续时间是第一子扫描线信号Sc1两倍的另外一个子扫描信号。
最后，在第七时间段t7，时钟信号CK1再次处于使能状态，也即是跳变为高电位，第一下拉控制点P(N)通过处于导通状态的第二晶体管T2跳变为高电位，从而将低电压VGL通过导通的第十三晶体管T13传输至扫描信号输出端Gn，从而完成对一个像素单元110的一帧图像的驱动。其中，需要说明的，时间段t1-t7依次连续并无时间间隔，且在时间段t1-t7构成一个扫描周期内的完整扫描信号。
相较于现有技术，扫描驱动电路103通过至少两个二极管方式连接的晶体管调节扫描信号的波形，使其能够灵活、稳定地针对一个像素单元中的两个子像素进行扫描，使其间隔所述预定时间段的两个不同时间段内接收待显示的图像数据电压从而进行图像显示。
请参阅图7，其为本发明一变更实施例扫描驱动单元SDi的电路结构示意图，扫描驱动单元SDi的电路结构与扫描驱动单元SDn的电路结构基本相同，区别仅在于第一-第十七晶体管T1-T17均为P沟道金属氧化物半导体(P-channel Metal Oxide Semiconductor,PMOS)。
可以理解，以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (17)

  1. 一种扫描驱动电路，包括依次相互级联的n个扫描驱动单元，每一个扫描驱动单元至少包括启动触发端、扫描信号输出端与多个时钟信号端，其中，处于第i级的扫描驱动单元的启动触发端与第i-1级的扫描信号输出端电性连接，扫描信号输出端用于输出扫描信号且与第i+1的启动触发端电性连接，每一个扫描驱动单元包括：
    与所述启动触发端电性连接输入单元；及
    与所述扫描信号输出端电性连接的输出单元，其中，所述输入单元用于接收所述启动触发信号并将其传输至所述输出单元，并控制所述输出单元处于扫描状态，其特征在于：
    所述扫描驱动单元还包括具有多个以二极管方式连接的晶体管的扫描信号调制单元，多个所述晶体管连接于多个所述时钟信号端并依据多个时钟信号输出时钟调制信号，所述时钟调制信号包括至少两个间隔预定时间段的第一电位，所述输出单元在处于扫描状态时对应所述时钟调制信号自所述扫描信号输出端输出扫描驱动信号，所述扫描信号包括两个间隔所述预定时间段的子扫描信号，每一个子扫描信号均对应时钟调制信号的第一电位，两个所述子扫描信号用于控制在一个扫描周期内的一个像素单元接收图像信号，所述像素单元包括两个子像素单元，n为大于1的自然数，i为小于n的自然数。
  2. 根据权利要求1所述的扫描驱动电路，其特征在于，所述时钟调制信号包括至少两个间隔预定时间段的第一电位，每一个子扫描信号均对应时钟调制信号的第一电位。
  3. 根据权利要求2所述的扫描驱动电路，其特征在于，所述扫描信号调制单元包括信号调节输出点，所述扫描信号调制单元包括至少两个以二极管方式连接的晶体管与至少一个缓冲晶体管，所述两个二极管连接的晶体管的源极均电性连接所述信号调节输出点，漏极分别电性连接对应数量的扫描时钟信号端；所述缓冲晶体管的漏极电性连接所述信号调节输出点，栅极电性连接缓冲时钟信号端，源极电性连接具有第二电位的缓冲电压端；其中，所述扫描信号输出端加载的扫描时钟信号通过所述至少两个晶体管控制所述时钟调制信号具有第一电位，所述缓冲时钟端加载的缓冲时钟信号在所述预定时间段内使得 所述时钟调制信号具有第二电位，所述第二电位使得扫描信号输出端停止输出扫描信号而输出缓冲扫描信号，所述缓冲扫描信号控制所述像素单元停止接收图像信号。
  4. 根据权利要求3所述的扫描驱动电路，其特征在于，所述扫描信号调制单元包括三个二极管方式连接的晶体管，所述三个二极管方式连接的晶体管中的其中一个在所述预定时间段之前控制时钟调制信号具有第一电位，另外两个在所述预定时间段之后控制时钟调制信号具有第一电位，从而使得所述时钟调制信号在所述预定时间段前后具有第一定位的持续时间不同，两个所述子扫描信号的持续时间不同。
  5. 根据权利要求4所述的扫描驱动电路，其特征在于，所述输出单元具有输出控制点、输出控制晶体管与一电位维持电容，所述输出控制点用于接收启动触发信号，所述电位维持电容用于维持输出控制点维持在扫描状态，所述输出控制晶体管的栅极电性连接所述输出控制点，源极电性连接所述信号调节输出点，漏极电性连接所述扫描信号输出端，当所述输出控制点处于扫描状态时所述输出控制晶体管处于导通状态，对应所述时钟调制信号输出所述扫描信号。
  6. 根据权利要求5所述的扫描驱动电路，其特征在于，所述输入单元具有输入晶体管，所述输入晶体管的栅极电性所述启动触发端用于接收启动出发信号，所述输入晶体管的源极接收第一参考电压，当启动触发信号控制所述输入晶体管导通时，所述第一参考电压通过所述输入晶体管的漏极输出，所述第一参考电压用于控制输出控制点处于扫描状态。
  7. 根据权利要求6所述的扫描驱动电路，其特征在于，所述扫描驱动单元还包括稳压单元，所述稳压单元电性连接所述输入晶体管的漏极与所述输出控制点之间，所述稳压单元包括稳压晶体管，所述稳压晶体管的栅极接收第一参考电压并使得所述稳压晶体管在第一参考电压控制下处于导通状态，所述稳压晶体管的源极电性所述输入晶体管的漏极，所述稳压晶体管的漏极电性连接所述输出控制点。
  8. 根据权利要求5所述的扫描驱动电路，其特征在于，所述扫描驱动单元还包括第一下拉单元，所述第一下拉单元包括第一下拉控制点、第一下拉晶体管与下拉维持电容，所述第一下拉控制点用于接收下拉控制信号，所述第一下拉晶体管的栅极电性连接所述第一下拉控制点，所述第一下拉晶体管的源极电 性连接第二参考电压端，所述第二参考电压端具有所述第二电位，所述第一下拉晶体管的漏极电性连接所述扫描信号输出端，所述第一下拉控制信号用于控制所述扫描信号输出端输出具有第二电位的缓冲信号，所述缓冲信号控制所述像素单元处于暂停接收数据电压状态。
  9. 根据权利要求8所述的扫描驱动电路，其特征在于，所述扫描驱动单元还包括下拉控制单元，所述下拉控制单元用于输出下拉控制信号，所述下拉控制单元包括第一下拉控制晶体管与第二下拉控制晶体管，第一下拉控制晶体管的栅极电性连接所述输出控制点，源极电性连接下拉时钟信号端用于接收下拉时钟信号，漏极电性连接于所述第一控制点；所述第二下拉控制晶体管的栅极电性连接所述下拉时钟信号端，源极电性电性连接第一参考电压端，漏极电性连接所述第一控制点；在所述扫描驱动单元接收到所述启动触发信号时，所述下拉时钟信号在所述扫描驱动单元接收到所述启动触发信号时，与扫描信号端输出完成两个所述扫描信号后处于第一电位的使能状态，所述下拉时钟信号用于控制所述下拉控制信号具有第一电位，具有第一电位的所述控制信号控制所述扫描信号输出端输出具有第二电位的缓冲信号。
  10. 根据权利要求5所述的扫描驱动电路，其特征在于，所述扫描驱动单元还包括第二下拉单元，所述第二下拉单元包括第二下拉控制点、第二下拉晶体管、第三下拉晶体管、第四下拉晶体管与下拉维持电容，所述第二下拉控制点在接收到下拉控制信号时控制所述扫描信号输出端停止输出扫描信号，第二下拉晶体管的栅极电性连接所述第一控制点，所述第二下拉晶体管的源极电性连接第二参考电压端，所述第二下拉晶体管的漏极电性连接所述扫描信号输出端，所述下拉控制信号用于控制所述扫描信号输出端，所述缓冲信号控制所述像素单元处于暂停接收数据电压状态；第三下拉晶体管的栅极电性连接启动触发端，所述第三下拉晶体管的源极电性连接第一参考电压，所述第三下拉晶体管的漏极电性连接第二下拉控制点，所述第四晶体管的栅极电性连接所述扫描时钟信号端，所述第四晶体管的源极电性连接第二参考电压端，所述第四晶体管的漏极电性连接所述第二下拉控制点。
  11. 根据权利要求1所述的扫描驱动电路，其特征在于，多个所述扫描驱动单元包括处于奇数级的扫描驱动单元的第一组扫描驱动单元与处于偶数级的扫描驱动单元第二组扫描驱动单元，所述第一组扫描驱动单元连接至相同的第一组时钟信号端，所述第二组扫描驱动单元连接至相同的第二组时钟信号 端，其中，所述第一组时钟信号端与所述第二组时钟信号端部分相同。
  12. 一种阵列基板，其特征在于，所述阵列基板包括第一区域与第二区域，其中，所述第一区域包括2n条扫描线以及与所述扫描线电性连接的多个像素单元，所述2n条扫描线相互平行且绝缘依次排列，所述第二区域设置有两个如权利要求1所述的扫描驱动电路，每一个扫描驱动单元电性连接一条扫描线以输出所述扫描信号至与所述扫描线点电性连接的所述像素单元，以控制所述像素单元接收待显示图像信号，其中，两个所述扫描驱动电路设置于所述2n条扫描线的相对两端，任意相邻的两条扫描线分别与相对设置的两个所述扫描驱动单元电性连接，其中，所述扫描驱动电路与所述像素单元采用相同的制程形成。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述时钟调制信号包括至少两个间隔预定时间段的第一电位，每一个子扫描信号均对应时钟调制信号的第一电位。
  14. 根据权利要求13所述的阵列基板，其特征在于，所述扫描信号调制单元包括信号调节输出点，所述扫描信号调制单元包括至少两个以二极管方式连接的晶体管与至少一个缓冲晶体管，所述两个二极管连接的晶体管的源极均电性连接所述信号调节输出点，漏极分别电性连接对应数量的扫描时钟信号端；所述缓冲晶体管的漏极电性连接所述信号调节输出点，栅极电性连接缓冲时钟信号端，源极电性连接具有第二电位的缓冲电压端；其中，所述扫描信号输出端加载的扫描时钟信号通过所述至少两个晶体管控制所述时钟调制信号具有第一电位，所述缓冲时钟端加载的缓冲时钟信号在所述预定时间段内使得所述时钟调制信号具有第二电位，所述第二电位使得扫描信号输出端停止输出扫描信号而输出缓冲扫描信号，所述缓冲扫描信号控制所述像素单元停止接收图像信号。
  15. 根据权利要求14所述的阵列基板，其特征在于，所述扫描信号调制单元包括三个二极管方式连接的晶体管，所述三个二极管方式连接的晶体管中的其中一个在所述预定时间段之前控制时钟调制信号具有第一电位，另外两个在所述预定时间段之后控制时钟调制信号具有第一电位，从而使得所述时钟调制信号在所述预定时间段前后具有第一定位的持续时间不同，两个所述子扫描信号的持续时间不同。
  16. 如权利要求15所述的阵列基板，其特征在于，所述第一区域包括2m 条相互平行且绝缘依次排列的数据线，其中，所述数据线的设置方向垂直于所述扫描线的设置方向，多个所述像素单元分别与所述扫描线及所述数据线电性连接，每一个像素单元包括两个子像素单元，两个所述子像素单元连接于同一条扫描线，且分别连接于相邻的两条数据线，两个所述子像素单元在一帧图像的一个扫描周期内间隔所述预定时间接收两个所述扫描信号，其中m为大于1的自然数。
  17. 一种显示面板，其特征在于，包括如权利要求16所述的阵列基板以及与所述阵列基板正对设置的对向基板，所述显示面板包括用作图像显示的显示区与环绕所述显示区的非显示区，其中，所述阵列基板的第一区域对应所述显示区域，所述第二区域对应所述非显示区。
PCT/CN2017/086185 2017-04-27 2017-05-26 扫描驱动电路、阵列基板与显示面板 WO2018196084A1 (zh)

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