WO2018196020A1 - Goa驱动电路和液晶显示面板 - Google Patents

Goa驱动电路和液晶显示面板 Download PDF

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Publication number
WO2018196020A1
WO2018196020A1 PCT/CN2017/083061 CN2017083061W WO2018196020A1 WO 2018196020 A1 WO2018196020 A1 WO 2018196020A1 CN 2017083061 W CN2017083061 W CN 2017083061W WO 2018196020 A1 WO2018196020 A1 WO 2018196020A1
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Prior art keywords
unit
goa driving
trigger
thin film
film transistor
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PCT/CN2017/083061
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English (en)
French (fr)
Inventor
冯托
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/539,727 priority Critical patent/US10347203B2/en
Publication of WO2018196020A1 publication Critical patent/WO2018196020A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA driving circuit and a liquid crystal display panel.
  • the first K scanning clocks (CK, Clock) are turned on during the high level.
  • the signal is always at a high level, causing the potential of the first K scan control signals Q(k) (as shown in Figure 2) to be weakened by the coupling effect of the bootstrap capacitor, so that the first K gate lines (Gate) are reached.
  • the time required for the high potential is long, resulting in poor charging, which in turn adversely affects the display effect and quality of the display.
  • the present invention provides a GOA driving circuit and a liquid crystal display panel, which improve the front K GOA driving units by adding a thin film transistor that controls the turn-on signal input to the triggering units of the first K GOA driving units.
  • the thin film transistor in the output unit is not fully opened, thereby improving the quality of the display screen.
  • a GOA driving circuit including a plurality of GOA driving units, each of which includes a trigger unit and an output unit connected to each other;
  • the trigger unit includes a first thin film transistor and a second thin film transistor;
  • m is an integer satisfying 0 ⁇ m ⁇ M, where M is the number of GOA driving units.
  • the trigger unit for a trigger unit in each GOA driving unit subsequent to the K+1th GOA driving unit, includes a fourth thin film transistor; wherein, a gate of the fourth thin film transistor The drain is connected to the trigger signal corresponding to the trigger unit, and the source of the fourth thin film transistor is connected to the control end of the output unit connected to the trigger unit.
  • the K is equal to three.
  • the GOA driving circuit described in this embodiment can be used to make the front K line
  • the potential of the scanning control signal Q(k) is boosted by the coupling effect of the bootstrap capacitor, so that the charging failure of the scanning line of the first K line due to the opening signal not being turned off in time can be avoided.
  • Applying the GOA driving circuit described in this embodiment can improve the condition of poor charging of the front K-line scanning line, thereby improving the quality of the display screen.
  • FIG. 2 is a schematic structural diagram of a GOA driving circuit having N scanning clocks in an embodiment of the present invention
  • FIG. 3 is another schematic structural diagram of a GOA driving circuit having N scanning clocks in an embodiment of the present invention.
  • Figure 5 is a timing chart showing the operation of a GOA driving circuit having eight scanning clocks in an embodiment of the present invention.
  • the main structure of the first stage GOA driving unit 210 includes a trigger unit 211, an output unit 212, and a pull down unit 213.
  • the trigger unit 211 is mainly used to control the turn-on time of the output unit 212 to implement progressive scan of the liquid crystal display panel.
  • the trigger unit 211 is composed of a first thin film transistor T11 and a second thin film transistor T21.
  • T11 is used to output the turn-on signal STV as a trigger signal.
  • the gate of T11 is connected to the trigger clock, the drain is connected to the turn-on signal STV, and the source thereof generates a trigger signal.
  • the source of T11 is connected to the gate and drain of T21.
  • T21 is used to output the scan control signal Q(1) of the first line.
  • the gate and drain of T21 are connected together for receiving a trigger signal generated by the source of T11, and the source thereof generates a scan control signal Q(1) of the first row.
  • the source of T21 is coupled to the control terminal of output unit 212.
  • the output unit 212 is mainly used to output the first scan clock signal CK(1) as the scan signal G(1) of the first row.
  • the output unit 212 is composed of a sixth thin film transistor T61 and a bootstrap capacitor C.
  • the gate of T61 receives the scan control signal Q(1) of the first row generated by the trigger unit 211 as the control terminal of the output unit 212.
  • the drain of T61 receives the first scan clock signal CK(1) as an input of output unit 212.
  • the source of T61 serves as an output terminal of the output unit 212, and is connected to the scanning line G(1) of the first row for generating and outputting the scanning signal G(1) of the first row.
  • the bootstrap capacitor C has one end connected to the gate of T61 and the other end connected to the source of T61.
  • the trigger clock to which the gate of T11 is connected is configured such that when the scan clock signal CK(1) received at the input terminal of the output unit 212 is at a high potential, the control trigger unit 211 is turned off. Specifically, in a period of time before the scan clock signal CK(1) changes from a low potential to a high potential, the trigger clock is controlled to be in an on state, and the scan clock signal CK(1) is changed from a low potential to a low potential. While remaining at a high potential, the trigger clock is controlled to control the trigger unit 211 to be in a closed state.
  • the trigger clock is controlled to be in an ON state, and the scan clock signal CK(1) is changed from a low potential to a hold. During high potential, the trigger clock is controlled to turn T11 off.
  • the trigger clock to which the gate of T11 is connected in order to make the control simple and convenient, it is preferable to set the trigger clock to which the gate of T11 is connected to any one of the scan clocks remaining after the first scan clock CK(1) is removed from the H scan clocks.
  • the trigger clock connected to the gate of T11 in this embodiment may be any one of the remaining H-1 scan clocks after CK(1) is removed.
  • the trigger clock connected to the gate of T11 in this embodiment is the second scan clock CK(2).
  • the gate of T71 is connected to the gate of T81 and is connected to the scan line G(2) of the second row, that is, the scan line signal G(2) of the second row is received, and the scan line of the second row is valid.
  • the signal G(2) controls the scanning signal G(1) of the first line to be turned off to realize progressive scanning.
  • the source of T71 and the source of T81 are commonly connected to a DC low level VSS.
  • the main structure of the w-th stage GOA driving unit 210 includes a trigger unit 211, an output unit 212, and a pull-down unit 213.
  • the gate of T61 receives the scan control signal Q(w) of the wth row generated by the trigger unit 211 as the control terminal of the output unit 212.
  • the drain of T61 receives the qth scan clock signal CK(q) as an input of the output unit 212.
  • the source of T61 serves as an output terminal of the output unit 212, and is connected to the scanning line G(w) of the wth row for generating and outputting the scanning signal G(w) of the wth row.
  • the bootstrap capacitor C has one end connected to the gate of T61 and the other end connected to the source of T61.
  • the function of the bootstrap capacitor C is to store the voltage of the gate terminal of T61 when Q(w) is high level, and to raise the gate of T61 twice when G(w) outputs the scan signal G(w) of the wth row.
  • the voltage of the pole ie, the scanning clock CK(q) of the stage is high level
  • the potential of the scanning control signal Q(w) of the wth line is boosted by the coupling effect of the bootstrap capacitor C) to ensure that the T61 can
  • the scanning signal G(w) of the wth line is reliably turned on and output.
  • the pull-down unit 213 is for immediately lowering the source potential and the gate potential of the sixth thin film transistor T61 to a low potential, that is, turning off the scan signal G(w) of the wth line.
  • the pull-down unit 213 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(w) of the wth row
  • the drain of T81 is connected to the output terminal of the output unit 212, that is, to the scanning line G(w) of the wth row.
  • T71 is used to pull down the scan control signal Q(w) of the wth line to turn off the sixth thin film transistor T61.
  • the drain of T71 is coupled to the control terminal of output unit 212.
  • the gate of T71 is connected to the gate of T81, and is connected to the scan line G(w+1) of the w+1th row, that is, the scan line signal G(w+1) of the w+1th row is received,
  • the valid scan line signal G(w+1) of the w+1th line controls the off of the scan signal G(w) of the wth line to realize progressive scan.
  • the source of T71 and the source of T81 are commonly connected to a DC low level VSS.
  • the GOA driving circuit 200 of the present embodiment can apply the potential of the scan control signal Q(1) of the first row to the bootstrap capacitor C.
  • the coupling effect is raised, so that the scanning line G(1) of the first row can be prevented from being poorly charged due to the opening signal STV not being turned off in time.
  • Applying the GOA driving circuit 200 according to the present embodiment can improve the situation in which the scanning line G(1) of the first row is poorly charged, thereby improving the quality of the display screen.
  • FIG. 2 is a schematic structural diagram of a GOA driving circuit 300 in the embodiment, which has N scanning clock signals, where N is an integer greater than zero.
  • the GOA driving circuit 300 includes a plurality of GOA driving units 310, wherein the triggering units 311 of the first N/2 GOA driving units 310 are all triggered by the ON signal STV, and the output signal of the mth GOA driving unit 310 is the m+N Tr trigger signals of /2 drive units 310.
  • the GOA driving circuit 300 described above is capable of solving the problem of significant attenuation of the output signal due to excessive cascading of the GOA driving unit.
  • the turn-on signal STV is always at a high potential, so that the scan control signals in the front N/2-1 GOA driving units 310 are high.
  • the potential of the Q point ie, the scan control signal output by the front N/2-1 trigger unit 311 cannot be raised by the coupling effect of the bootstrap capacitor C, and can only maintain the same potential as the turn-on signal STV, thereby causing the front N /2-1 scan lines (ie, output signals of the front N/2-1 output units 312) are poorly charged, affecting the quality of the display screen. Therefore, the GOA driving circuit 400 of the present invention is further improved based on the structure of the GOA driving circuit 300 in FIG. 2, thereby improving the state of poor charging of the front N/2-1 scanning lines and improving the quality of the display screen.
  • the drive circuit 400 includes a plurality of GOA drive units 410.
  • the trigger signals of the first N/2-1 GOA driving units 410 are generated by the trigger clock control
  • the trigger signals of the N/2th GOA driving unit 410 are the ON signals STV
  • the output of the mth GOA driving unit 410 is a trigger signal of the m+N/2th GOA driving unit 410.
  • the trigger unit 411 is mainly used to control the turn-on time of the output unit 412 to implement progressive scan of the liquid crystal display panel.
  • the trigger unit 411 includes a first thin film transistor T11 and a second thin film transistor T21.
  • T11 is used to output the turn-on signal STV as a trigger signal.
  • the gate of T11 is connected to the trigger clock, the drain is connected to the turn-on signal STV, and the source thereof generates a trigger signal.
  • the source of T11 is connected to the gate and drain of T21.
  • T21 is used to output the scan control signal Q(k) of the kth line.
  • the gate and drain of T21 are connected together for receiving a trigger signal generated by the source of T11, and the source thereof generates a scan control signal Q(k) of the kth row. Control of source and output unit 412 of T21 Connected to the end.
  • the output unit 412 is mainly used to output the kth scan clock signal CK(k) as the scan signal G(k) of the kth row.
  • the output unit 412 is composed of a sixth thin film transistor T61 and a bootstrap capacitor C.
  • the gate of T61 receives the scan control signal Q(k) of the kth row generated by the trigger unit 411 as the control terminal of the output unit 412.
  • the drain of T61 receives the kth scan clock signal CK(k) as an input of the output unit 412.
  • the source of T61 serves as an output terminal of the output unit 412, and is connected to the scanning line G(k) of the kth row for generating and outputting the scanning signal G(k) of the kth row.
  • the bootstrap capacitor C has one end connected to the gate of T61 and the other end connected to the source of T61.
  • the function of the bootstrap capacitor C is to store the voltage of the T61 gate terminal when Q(k) is high, and to raise the T61 gate twice when G(k) outputs the scan signal G(k) of the kth row.
  • the voltage of the pole ie, CK(k) is high level
  • the potential of the scanning control signal Q(k) point of the kth line is raised by the coupling effect of the bootstrap capacitor C) to ensure that the T61 can be reliably turned on and
  • the scanning signal G(k) of the kth line is output.
  • the trigger clock to which the gate of T11 is connected is configured such that when the scan clock signal CK(k) received at the input terminal of the output unit 412 is high, the control trigger unit 411 is turned off. Specifically, in a period of time before the scan clock signal CK(k) changes from a low potential to a high potential, the trigger clock is controlled to be in an on state, and the scan clock signal CK(k) is changed from a low potential to a low potential. While remaining at a high potential, the trigger clock is controlled to control the trigger unit 411 to be in an off state.
  • T11 and T21 are preferably N-type thin film transistors. Then, first, for a period of time before the scan clock signal CK(k) changes from a low potential to a high potential, the trigger clock is kept high to turn on T11 and generate a trigger signal, thereby making T21 at its gate and drain. After receiving the trigger signal, the scan control signal Q(k) of the kth line can be turned on and generated. Then, while the scan clock CK(k) changes from low to high and remains high, the trigger clock is held low to turn T11 off, so that the potential at Q(k) is high when CK(k) is high. It can be lifted by the coupling effect of the bootstrap capacitor C. Therefore, the present embodiment can avoid the charging failure caused by the scan line G(k) of the kth row due to the STV not being turned off in time by increasing the first thin film transistor T11 controlled by the trigger clock.
  • the trigger clock to which the gate of T11 in order to make the control simple and convenient, it is preferable to set the trigger clock to which the gate of T11 is connected to the k+N/2th scan clock CK(k+N/2).
  • a clock signal as the trigger clock to which the gate of T11 is connected, as long as the clock signal is within a period of time before the scan clock CK(k) of the output unit 412 changes from a low potential to a high potential.
  • the trigger unit 411 can be controlled to be in an on state, and at the output unit 412
  • the scan clock CK(k) is changed from the low potential to the high potential period, and the trigger unit 411 can be controlled to be in the off state. Therefore, in a specific implementation process, a person skilled in the art can set the trigger clock to which the gate of T11 is connected according to actual needs.
  • the pull-down unit 413 is for immediately lowering the source potential and the gate potential of the sixth thin film transistor T61 to a low potential, that is, turning off the scanning signal G(k) of the kth row.
  • the pull-down unit 413 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(k) of the kth row
  • the drain of T81 is connected to the output terminal of the output unit 412, that is, to the scanning line G(k) of the kth row.
  • T71 is used to pull down the scanning control signal Q(k) of the kth line to turn off the sixth thin film transistor T61.
  • the main structure of the K+1th GOA driving unit 410 includes a triggering unit 411, an output unit 412, and a pull-down unit 413.
  • the trigger unit 411 is mainly used to control the turn-on time of the output unit 412 to implement progressive scan of the liquid crystal display panel.
  • the trigger unit 411 is configured by the third thin film transistor T31 for outputting the scan control signal Q(K+1) of the K+1th row.
  • the gate and drain of T31 are connected to the turn-on signal STV, and the source thereof generates the scan control signal Q(K+1) of the K+1th row.
  • the source of T31 is coupled to the control terminal of output unit 412.
  • the output unit 412 is mainly used to output the K+1th scan clock signal CK(K+1) as the scan signal G(K+1) of the K+1th row.
  • the output unit 412 includes a sixth thin film transistor T61 and a bootstrap capacitor C.
  • the gate of T61 receives the scan control signal Q(K+1) of the K+1th row generated by the trigger unit 411 as the control terminal of the output unit 412.
  • the drain of T61 receives the K+1th scan clock signal CK(K+1) as an input of the output unit 412.
  • the source of T61 serves as an output terminal of the output unit 412, and is connected to the scanning line G(K+1) of the K+1th row for generating and outputting the scanning signal G(K+1) of the K+1th row.
  • the bootstrap capacitor C has one end connected to the gate of T61 and the other end connected to the source of T61.
  • the function of the bootstrap capacitor C is to store the voltage of the gate terminal of T61 when Q(K+1) is high, and to output the scan signal G(K+1 of the K+1th row when G(K+1) is output.
  • the voltage of the gate of T61 is raised twice (ie, CK(K+1) is high level, the potential of the scanning control signal Q(K+1) of the K+1th row is affected by the coupling effect of the bootstrap capacitor C. The action is raised) to ensure that the T61 can be reliably turned on and output the K+1th scan signal G(K+1).
  • the pull-down unit 413 is configured to immediately lower the source potential and the gate potential of the sixth thin film transistor T61 to a low potential. That is, the scanning signal G(K+1) of the K+1th line is turned off.
  • the pull-down unit 413 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(K+1) of the K+1th row, and the drain of T81 is connected with the output end of the output unit 412, that is, the scanning line G (K) acting on the K+1th row.
  • T71 is used to pull down the scan control signal Q(K+1) of the K+1th line to turn off the sixth thin film transistor T61.
  • the drain of T71 is connected to the control terminal of output unit 412.
  • the gate of T71 is connected to the gate of T81 and is connected to the scanning line G(K+2) of the K+2 row, that is, the scanning line signal G(K+2) of the K+2th row is received,
  • the valid scan line signal G(K+2) of the K+2th line controls the off of the scan signal G(K+1) of the K+1th line to realize progressive scan.
  • the source of T71 and the source of T81 are commonly connected to a DC low level VSS.
  • the structure of the GOA driving unit 410 after the K+1th is performed by taking the structure of the fth GOA driving unit 410 as an example. Description, where f is an integer satisfying K+1 ⁇ f ⁇ M.
  • the main structure of the fth GOA driving unit 410 includes a trigger unit 411, an output unit 412, and a pull-down unit 413.
  • the output unit 412 is composed of a sixth thin film transistor T61 and a bootstrap capacitor C. The gate of T61 receives the scan control signal Q(f) of the fth row generated by the trigger unit 411 as the control terminal of the output unit 412.
  • the drain of T61 receives the e-th scan clock signal CK(e) as an input of the output unit 412.
  • the source of T61 serves as an output terminal of the output unit 412, and is connected to the scanning line G(f) of the f-th row for generating and outputting the scanning signal G(f) of the f-th row.
  • the bootstrap capacitor C has one end connected to the gate of T61 and the other end connected to the source of T61. Wherein, the function of the bootstrap capacitor C is to store the voltage of the gate terminal of T61 when Q(f) is high, and to raise the gate of T61 twice when G(f) outputs the scan signal G(f) of the fth row.
  • the pull-down unit 413 is configured to immediately lower the source potential and the gate potential of the sixth thin film transistor T61 to a low potential. That is, the scanning signal G(f) of the fth line is turned off.
  • the pull-down unit 413 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(f) of the fth row
  • the drain of T81 is connected to the output terminal of the output unit 412, that is, to the scanning line G(f) of the fth row.
  • T71 is used to pull down the scan control signal Q(f) of the fth line to turn off the sixth thin film transistor T61.
  • the GOA driving circuit 400 described in this embodiment can apply the potential of the Q-point of the scan control signal of the front N/2-1 line to the bootstrap capacitor.
  • the coupling effect of C is raised, so that the charging line of the front N/2-1 line can be prevented from being poorly charged due to the fact that the turn-on signal STV is not turned off in time.
  • Applying the GOA driving circuit 400 according to the present embodiment can improve the condition of poor charging of the front N/2-1 line scanning line, thereby improving the quality of the display screen.
  • the present embodiment further defines the number of scan clocks.
  • the GOA driving circuit 500 includes a plurality of GOA driving units 510.
  • the trigger signals of the first three GOA driving units 510 are generated by the trigger clock control
  • the trigger signal of the fourth GOA driving unit 510 is the turn-on signal STV
  • the output signal of the mth GOA driving unit 510 is the m+4 Trigger signals of the GOA driving unit 510.
  • the specific structure of the drive circuit 500 will be described in detail below with reference to FIG.
  • the trigger unit 511 is mainly used to control the turn-on time of the output unit 512 to implement progressive scan of the liquid crystal display panel.
  • the trigger unit 511 includes a first thin film transistor T11 and a second thin film transistor T21.
  • T11 is used to output the turn-on signal STV as a trigger signal.
  • the gate of T11 is connected to the trigger clock, and the drain is connected to the turn-on signal STV. Its source generates a trigger signal.
  • the source of T11 is connected to the gate and drain of T21.
  • T21 is used to output the scan control signal Q(k) of the kth line.
  • the gate and drain of T21 are connected together for receiving a trigger signal generated by the source of T11, and the source thereof generates a scan control signal Q(k) of the kth row.
  • the source of T21 is coupled to the control terminal of output unit 512.
  • the output unit 512 is mainly used to output the kth scan clock signal CK(k) as the scan signal G(k) of the kth row.
  • the output unit 512 is composed of a sixth thin film transistor T61 and a bootstrap capacitor C.
  • the gate of T61 receives the scan control signal Q(k) of the kth row generated by the trigger unit 511 as the control terminal of the output unit 512.
  • the drain of T61 receives the kth scan clock signal CK(k) as an input of the output unit 512.
  • the source of T61 serves as an output terminal of the output unit 512, and is connected to the scanning line G(k) of the kth row for generating and outputting the scanning signal G(k) of the kth row.
  • the pull-down unit 513 is for immediately lowering the source potential and the gate potential of the sixth thin film transistor T61 to a low potential, that is, turning off the scanning signal G(k) of the kth row.
  • the pull-down unit 513 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(k) of the kth row
  • the drain of T81 is connected to the output terminal of the output unit 512, that is, to the scanning line G(k) of the kth row.
  • T71 is used to pull down the scanning control signal Q(k) of the kth line to turn off the sixth thin film transistor T61.
  • the drain of T71 is connected to the control terminal of output unit 512.
  • the gate of T71 is connected to the gate of T81, and is connected to the scanning line G(k+1) of the k+1th row, that is, the scanning line signal G(k+1) of the k+1th row is received,
  • the valid scan line signal G(k+1) of the k+1th line controls the scan signal G(k) of the kth line to be turned off, thereby implementing progressive scan.
  • the source of T71 and the source of T81 are commonly connected to a DC low level VSS.
  • the main structure of the fourth GOA driving unit 510 includes a trigger unit 511, an output unit 512, and a pull-down unit 513.
  • the output unit 512 is mainly used to output the fourth scan clock signal CK(4) as the scan signal G(4) of the fourth row.
  • the output unit 512 includes a sixth thin film transistor T61 and a bootstrap capacitor C.
  • the gate of T61 receives the scan control signal Q(4) of the fourth row generated by the trigger unit 511 as the control terminal of the output unit 512.
  • the drain of T61 receives the fourth scan clock signal CK(4) as an input of the output unit 512.
  • the source of T61 serves as an output terminal of the output unit 512, and is connected to the scanning line G(4) of the fourth row for generating and outputting the scanning signal G(4) of the fourth row.
  • the bootstrap capacitor C has one end connected to the gate of T61 and the other end connected to the source of T61.
  • the pull-down unit 513 is for immediately lowering the source potential and the gate potential of the sixth thin film transistor T61 to a low potential, that is, turning off the scan signal G(4) of the fourth row.
  • the pull-down unit 513 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(4) of the fourth row
  • the drain of T81 is connected to the output terminal of the output unit 512, that is, to the scanning line G(4) of the fourth row.
  • T71 is used to pull down the scan control signal Q(4) of the fourth row to turn off the sixth thin film transistor T61.
  • the drain of T71 is connected to the control terminal of output unit 512.
  • the gate of T71 is connected to the gate of T81 and is connected to the scanning line G(5) of the fifth row, that is, receives the scanning line signal G(5) of the fifth row, and the scanning line signal G of the effective fifth row ( 5) Control the closing of the scanning signal G(4) of the fourth line to realize progressive scanning.
  • the source of T71 and the source of T81 are commonly connected to a DC low level VSS.
  • the trigger unit 511 is mainly used to control the turn-on time of the output unit 512 to implement progressive scan of the liquid crystal display panel.
  • the trigger unit 511 is constituted by a fourth thin film transistor T41 for outputting the scan control signal Q(f) of the fth line.
  • the gate and the drain of T41 are connected together for receiving the scan signal G(f-4) of the f-4th line of the output of the f-4th GOA driving unit, and the source generates the scan control signal of the fth line Q(f).
  • the source of T41 is coupled to the control terminal of output unit 512.
  • the potential of the scanning control signal Q(f) at the f-th row is coupled by the bootstrap capacitor C The effect is raised) to ensure that the T61 can be reliably turned on and output the scan signal G(f) of the fth line.
  • the pull-down unit 513 is for immediately lowering the source potential and the gate potential of the sixth thin film transistor T61 to a low potential, that is, turning off the scan signal G(f) of the f-th row.
  • the pull-down unit 513 is composed of a seventh thin film transistor T71 and an eighth thin film transistor T81.
  • T81 is used to pull down the potential of the scanning signal G(f) of the fth row
  • the drain of T81 is connected to the output terminal of the output unit 512, that is, to the scanning line G(f) of the fth row.
  • T71 is used to pull down the scan control signal Q(f) of the fth line to turn off the sixth thin film transistor T61.
  • the drain of T71 is connected to the control terminal of output unit 512.
  • the gate of T71 is connected to the gate of T81, and is connected to the scanning line G(f+1) of the f+1th row, that is, the scanning line signal G(f+1) of the f+1th row is received,
  • the valid scan line signal G(f+1) of the f+1th line controls the off of the scan signal G(f) of the fth line to realize progressive scan.
  • the source of T71 and the source of T81 are commonly connected to a DC low level VSS.
  • FIG. 5 shows an operation timing chart of the GOA driving circuit 500. The above driving process will be described in detail below with reference to FIGS. 4 and 5.
  • the trigger unit 511 in the first GOA driving unit 510 is turned on and outputs the scan control signal Q(1) of the first line. While STV is at a high level, T31 in the fourth GOA driving unit 510 is turned on and outputs a scan control signal Q(4) of the fourth line.
  • CK(6) and STV are at a high level
  • the trigger unit 511 in the second GOA driving unit 510 is turned on and outputs the scan control signal Q(2) of the second line.
  • CK(5) and STV are at a high level
  • the trigger unit 511 in the first GOA driving unit 510 is still in an on state and outputs a scan control signal Q(1) of the first row;
  • STV is a high level
  • T31 in the four GOA driving units 510 is still in an on state and outputs a scan control signal Q(4) of the fourth line.
  • CK(1) and Q(1) are at a high level, and T61 in the first GOA driving unit 510 is turned on and outputs the scanning signal G(1) of the first line.
  • T61 in the first GOA driving unit 510 is turned on and outputs the scanning signal G(1) of the first line.
  • T11 in the first GOA driving unit 510 is turned off, so the potential of the scanning control signal Q(1) of the first row can be raised by the coupling effect of the bootstrap capacitor C.
  • the scanning signal G(1) of the first row is sufficiently charged.
  • T41 in the fifth GOA drive unit 510 is turned on and the scan control signal Q(5) of the fifth line is output.
  • CK(2) and Q(2) are at a high level, and T61 in the second GOA driving unit 510 is turned on and outputs the scanning signal G(2) of the second line.
  • T11 in the second GOA driving unit 510 is turned off, so the potential of the scanning control signal Q(2) of the second row can be raised by the coupling effect of the bootstrap capacitor C.
  • the scanning signal G(2) of the second row is sufficiently charged.
  • T71 and T81 in the first GOA driving unit 510 are turned on, and then G(1) and Q(1) are pulled low to low.
  • the scanning line G(1) of the first row of pixels is turned off; on the other hand, T41 in the sixth GOA driving unit 510 is turned on and the scanning control signal Q(6) of the sixth row is output.
  • CK(7) and STV are at a high level, and the trigger unit 511 in the third GOA driving unit 510 is still in an on state and outputs a scan control signal Q(3) of the third row; STV is at a high level.
  • T31 in the fourth GOA driving unit 510 is still in an on state and outputs a scan control signal Q(4) of the fourth line.
  • CK(3) and Q(3) are at a high level, and T61 in the third GOA driving unit 510 is turned on and outputs the scanning signal G(3) of the third line.
  • T11 in the third GOA driving unit 510 is turned off, so the potential of the scanning control signal Q(3) of the third row can be raised by the coupling effect of the bootstrap capacitor C.
  • the scanning signal G(3) of the third row is sufficiently charged.
  • T71 and T81 in the second GOA driving unit 510 are turned on, and then G(2) and Q(2) are pulled low to low.
  • T61 in the sixth GOA driving unit 510 is turned on and the scanning signal G(6) of the sixth line is output.
  • T71 and T81 in the fifth GOA driving unit 510 are turned on, and then G(5) and Q(5) are pulled low to low.
  • the scanning line G (5) of the fifth row of pixels is turned off; on the other hand, T41 in the tenth GOA driving unit 510 is turned on and the scanning control signal Q (10) of the tenth row is output.
  • the driving mode of the scanning lines of each row is similar to that of the above-mentioned t7 to t8 time period. To reduce redundancy, no further details are provided herein. Therefore, the GOA driving circuit 500 in the present embodiment realizes the progressive scanning, and avoids the charging failure of the scanning lines of the first three rows due to the fact that the ON signal STV is not turned off in time.
  • the GOA driving circuit 500 described in this embodiment can apply the potential of the Q-point of the scan control signal of the first three rows to be boosted by the coupling effect of the bootstrap capacitor C. Therefore, it is possible to prevent the charging line of the first three lines from being poorly charged due to the opening signal STV not being turned off in time.
  • the application of the GOA driving circuit 500 according to the present embodiment can improve the condition of poor charging of the first three lines of scanning lines, thereby improving the quality of the display screen.
  • the invention also provides a liquid crystal display panel.
  • the liquid crystal display panel of this embodiment includes the GOA driving circuit 200 of the first embodiment.
  • the liquid crystal display panel according to the embodiment can apply the potential of the scan control signal Q(1) of the first row to the bootstrap capacitor C.
  • the coupling effect is raised, so that the scanning line G(1) of the first row can be prevented from being poorly charged due to the opening signal STV not being turned off in time.
  • the liquid crystal display panel according to the embodiment can improve the state of poor charging of the scanning line G(1) in the first row, thereby improving the quality of the display screen.
  • the invention also provides a liquid crystal display panel.
  • the liquid crystal display panel of this embodiment includes the GOA driving circuit 400 of the second embodiment or the GOA driving circuit 500 of the third embodiment.
  • the liquid crystal display panel described in this embodiment can apply the potential of the Q-point of the scan control signal of the front N/2-1 line to the bootstrap capacitor C.
  • the coupling effect is raised, so that the charging line of the front N/2-1 line can be prevented from being poorly charged due to the opening signal STV not being turned off in time.
  • the liquid crystal display panel according to the embodiment can improve the charging condition of the front N/2-1 line scanning line, thereby improving the quality of the display screen. the amount.

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Abstract

一种GOA驱动电路（400），包括多个GOA驱动单元（410），对于前K个GOA驱动单元（410）中的每个触发单元（411），其包括第一薄膜晶体管（T11）,其中，第一薄膜晶体管（T11）的栅极连接触发单元（411）对应的触发时钟,触发时钟被配置为：在触发单元（411）对应的输出单元（412）的扫描时钟为高电位时，控制触发单元（411）关闭。

Description

GOA驱动电路和液晶显示面板
本申请要求享有2017年04月25日提交的名称为“GOA驱动电路和液晶显示面板”的中国专利申请CN201710278620.5的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种GOA驱动电路和液晶显示面板。
背景技术
在液晶显示器不断向着低成本高品质方向发展的背景下，阵列基板行驱动(GOA，Gate Driver On Array)技术以其低成本和高集成度等优点得到了广泛的应用。
然而，在现有的GOA驱动电路中，当若干个GOA驱动单元的触发单元均由开启信号(STV，Start Vertical)触发时，由于前K个扫描时钟(CK，Clock)为高电平期间开启信号一直处于高电平，从而造成前K个扫描控制信号Q(k)点(如图2)的电位受自举电容的耦合(Couple)效应减弱，使得前K条栅极线(Gate)达到所需高电位的时间较长，造成充电不良，进而对显示的显示效果和质量造成不利的影响。
综上所述，亟需一种新的GOA驱动电路设计方案以解决上述问题。
发明内容
针对上述技术问题，本发明提出了一种GOA驱动电路和液晶显示面板，通过在前K个GOA驱动单元的触发单元中增加一个控制开启信号输入的薄膜晶体管，来改善前K个GOA驱动单元的输出单元中薄膜晶体管打开不充分的状况，从而来提高显示画面的质量。
根据本发明的一个方面，提供了一种GOA驱动电路，包括多个GOA驱动单元，每个GOA驱动单元包括彼此连接的触发单元和输出单元；其中，
对于前K个GOA驱动单元中的每个触发单元，所述触发单元包括第一薄膜晶体管和第二薄膜晶体管；
其中，所述第一薄膜晶体管的栅极连接所述触发单元对应的触发时钟，所述第一薄膜晶体管的漏极连接开启信号，所述第一薄膜晶体管的源极连接所述第二薄膜晶体管的栅极 和漏极，所述第二薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端，K为大于0的整数；其中，
所述触发时钟被配置为：在所述输出单元的扫描时钟为高电位时，控制所述触发单元关闭。
根据本发明的实施例，第m个GOA驱动单元的输出信号为第m+N/2个GOA驱动单元的触发信号，其中，N为所述GOA驱动电路中扫描时钟的个数，且N＝2(K+1)；
m为满足0<m≤M的整数，其中，M为GOA驱动单元的个数。
根据本发明的实施例，第K+1个GOA驱动单元中的触发单元包括第三薄膜晶体管；其中，所述第三薄膜晶体管的栅极和漏极连接所述开启信号，所述第三薄膜晶体管的源极连接第K+1个GOA驱动单元中的输出单元的控制端。
根据本发明的实施例，对于第K+1个GOA驱动单元之后的每个GOA驱动单元中的触发单元，所述触发单元包括第四薄膜晶体管；其中，所述第四薄膜晶体管的栅极和漏极连接所述触发单元对应的触发信号，所述第四薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端。
根据本发明的实施例，第k个GOA驱动单元的触发单元对应的触发时钟，为第k+N/2个GOA驱动单元中的输出单元的扫描时钟，其中k为满足0<k≤K的整数。
根据本发明的实施例，所述K等于3。
根据本发明的实施例，其包括的所有GOA驱动单元依次连接；其中，上一级GOA驱动单元的输出信号为下一级GOA驱动单元的触发信号，且K＝1。
根据本发明的实施例，第一级GOA驱动单元的触发单元对应的触发时钟，为H个扫描时钟中除去第一级GOA驱动单元的扫描时钟后剩余中的任意一个，其中，H为所述GOA驱动电路中扫描时钟的个数。
根据本发明的实施例，对于第一级之后的每个GOA驱动单元中的触发单元，所述触发单元包括第五薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接所述触发单元对应的触发信号，所述第五薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端。
根据本发明的第二个方面，还提供了一种液晶显示面板，包括以上所述的GOA驱动电路。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
在前K个扫描时钟为高电位时，应用本实施例所述的GOA驱动电路能够使前K行 的扫描控制信号Q(k)点的电位受自举电容的耦合效应作用被抬升，从而可以避免前K行的扫描线因开启信号未及时关闭而产生的充电不良。应用本实施例所述的GOA驱动电路能够改善前K行扫描线充电不良的状况，进而提高显示画面的质量。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是本发明的实施例中具有H个扫描时钟的GOA驱动电路的结构示意图；
图2是本发明实施例中具有N个扫描时钟的GOA驱动电路的一种结构示意图；
图3是本发明的实施例中具有N个扫描时钟的GOA驱动电路的另一种结构示意图；
图4是本发明的实施例中具有八个扫描时钟的GOA驱动电路的结构示意图；
图5是本发明的实施例中具有八个扫描时钟的GOA驱动电路的工作时序图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一
图1是本发明的实施例中具有H个扫描时钟的GOA驱动电路的结构示意图，其中H为GOA驱动电路200中扫描时钟的个数，且H为大于0的整数。如图1所示，该驱动电路200包括多个GOA驱动单元210，所有GOA驱动单元210依次连接。具体地，上一级GOA驱动单元210的输出信号作为下一级GOA驱动单元210的触发信号，且第一级GOA驱动单元210的触发信号由一触发时钟控制生成。下面结合图1详细地说明该驱动电路200的具体结构。
首先，对第一级GOA驱动单元210的结构进行说明，第一级GOA驱动单元210的主要结构包括触发单元211、输出单元212和下拉单元213。
触发单元211主要用于控制输出单元212的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元211由第一薄膜晶体管T11和第二薄膜晶体管T21构成。其中，T11用于将开启信号STV输出为触发信号。T11的栅极连接触发时钟，漏极连接开启信号STV，其源极生成触发信号。并且T11的源极与T21的栅极和漏极相连。T21用于输出第一行的扫描控制信号Q(1)。T21的栅极和漏极连接在一起，用于接收T11的源极生成的触发信号，其源极生成第一行的扫描控制信号Q(1)。T21的源极与输出单元212的控制端相连。
输出单元212主要用于将第一个扫描时钟信号CK(1)输出为第一行的扫描信号G(1)。具体地，输出单元212由第六薄膜晶体管T61和自举电容C构成。其中，T61的栅极作为输出单元212的控制端接收由触发单元211生成的第一行的扫描控制信号Q(1)。T61的漏极作为输出单元212的输入端接收第一个扫描时钟信号CK(1)。T61的源极作为输出单元212的输出端，连接第一行的扫描线G(1)，用于生成并输出第一行的扫描信号G(1)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(1)为高电平时，存储T61栅源端的电压(栅源端的电压即栅极和源极的电压差)，并且当G(1)输出第一行的扫描信号G(1)后，二次抬升T61栅极的电压(即CK(1)为高电平时，第一行的扫描控制信号Q(1)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61能够可靠地被开启并输出第一行的扫描信号G(1)。
在本实施例中，T11的栅极所连接的触发时钟被配置为：在输出单元212的输入端接收到的扫描时钟信号CK(1)为高电位时，控制触发单元211关闭。具体而言，在扫描时钟信号CK(1)由低电位变为高电位之前的一段时间内，触发时钟要控制触发单元211处于开启状态，而在扫描时钟信号CK(1)由低电位变为并保持在高电位期间，触发时钟要控制触发单元211处于关闭状态。
进一步地讲，在扫描时钟信号CK(1)由低电位变为高电位之前的一段时间内，触发时钟要控制T11处于开启状态，而在扫描时钟信号CK(1)由低电位变为并保持在高电位期间，触发时钟要控制T11处于关闭状态。
在本实施例中，T11和T21优选地为N型薄膜晶体管。则，首先在扫描时钟信号CK(1)由低电位变为高电位之前的一段时间内，触发时钟要保持高电平以使T11开启并生 成触发信号，进而使T21在其栅极和漏极接收到该触发信号后能够开启并生成第一行的扫描控制信号Q(1)。然后在扫描时钟CK(1)由低电位变为并保持在高电位期间，触发时钟要保持低电平以使T11关闭，从而使Q(1)点的电位能够受自举电容C的耦合效应作用被抬升。因此，相比于现有技术，本实施例能够通过增加由触发时钟控制的第一薄膜晶体管T11来避免第一行的扫描线G(1)因STV未及时关闭而产生的充电不良。
本实施例为了使控制简单方便，优选地将T11的栅极所连接的触发时钟设定为，H个扫描时钟中除去第一个扫描时钟CK(1)后剩余的扫描时钟中的任意一个。换句话说，本实施例中T11的栅极所连接的触发时钟可以为除去CK(1)后的其余H-1个扫描时钟中的任意一个。进一步地，本实施例中T11的栅极所连接的触发时钟为第二个扫描时钟CK(2)。当然，也可以单独的设定一个时钟信号作为T11的栅极所连接的触发时钟，只要该时钟信号在输出单元212的扫描时钟CK(1)由低电位变为高电位的前一段时间内，能够控制触发单元211处于开启状态，并且在输出单元212的扫描时钟CK(1)由低电位变为并维持在高电位期间，能够控制触发单元211处于关闭状态即可。因此，在具体实施过程中，本领域技术人员可以根据实际需求来设定T11的栅极所连接的触发时钟。
下拉单元213用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位，即关闭第一行的扫描信号G(1)。具体地，下拉单元213由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第一行的扫描信号G(1)的电位，T81的漏极与输出单元212的输出端连接，即作用于第一行的扫描线G(1)。T71用于下拉第一行的扫描控制信号Q(1)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元212的控制端连接。T71的栅极与T81的栅极连接在一起，并与第二行的扫描线G(2)相连，即接收第二行的扫描线信号G(2)，由有效的第二行的扫描线信号G(2)控制第一行的扫描信号G(1)关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
其次，由于第一级之后的所有GOA驱动单元210的结构相同，因此下面以第w级GOA驱动单元210的结构为例，来对第一级之后的GOA驱动单元210的结构进行说明，其中w为满足1<w≤M的整数，且M为GOA驱动单元的个数。第w级GOA驱动单元210的主要结构包括触发单元211、输出单元212和下拉单元213。
触发单元211主要用于控制输出单元212的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元211由第五薄膜晶体管T51构成，用于输出第w行的扫描控制信号Q(w)。T51的栅极和漏极连接在一起，用于接收前一级GOA驱动单元输出的第w-1行 的扫描信号G(w-1)，其源极生成第w行的扫描控制信号Q(w)。T51的源极与输出单元212的控制端相连。
输出单元212主要用于将第q个扫描时钟信号CK(q)输出为第w行的扫描信号G(w)，其中q＝mod(w，H)，mod函数是一个求余函数即返回两数相除的余数，w为被除数，H为除数。在此需要说明的是，在本实施例中当w能够整除H时，令q＝H，即此时输出单元212用于将第H个扫描时钟信号CK(H)输出为第w行的扫描信号G(w)。具体地，输出单元212由第六薄膜晶体管T61和自举电容C构成。其中，T61的栅极作为输出单元212的控制端接收由触发单元211生成的第w行的扫描控制信号Q(w)。T61的漏极作为输出单元212的输入端接收第q个扫描时钟信号CK(q)。T61的源极作为输出单元212的输出端，连接第w行的扫描线G(w)，用于生成并输出第w行的扫描信号G(w)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(w)为高电平时，存储T61栅源端的电压，并且当G(w)输出第w行的扫描信号G(w)后，二次抬升T61栅极的电压(即该级的扫描时钟CK(q)为高电平时，第w行的扫描控制信号Q(w)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61能够可靠地被开启并输出第w行的扫描信号G(w)。
下拉单元213用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位，即关闭第w行的扫描信号G(w)。具体地，下拉单元213由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第w行的扫描信号G(w)的电位，T81的漏极与输出单元212的输出端连接，即作用于第w行的扫描线G(w)。T71用于下拉第w行的扫描控制信号Q(w)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元212的控制端连接。T71的栅极与T81的栅极连接在一起，并与第w+1行的扫描线G(w+1)相连，即接收第w+1行的扫描线信号G(w+1)，由有效的第w+1行的扫描线信号G(w+1)控制第w行的扫描信号G(w)的关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
综上，在第一个扫描时钟CK(1)为高电位时，应用本实施例所述的GOA驱动电路200能够使第一行的扫描控制信号Q(1)点的电位受自举电容C的耦合效应作用被抬升，从而可以避免第一行的扫描线G(1)因开启信号STV未及时关闭而产生的充电不良。应用本实施例所述的GOA驱动电路200能够改善第一行的扫描线G(1)充电不良的状况，进而提高显示画面的质量。
实施例二
针对现有技术中的GOA驱动电路在GOA驱动单元级联过多时会出现输出信号明显衰减的问题，本实施例对GOA驱动电路的结构进行了改进，如图2所示。图2为本实施例中的GOA驱动电路300的结构示意图，其具有N个扫描时钟信号，其中N为大于0的整数。该GOA驱动电路300包括多个GOA驱动单元310，其中前N/2个GOA驱动单元310的触发单元311均由开启信号STV触发，且第m个GOA驱动单元310的输出信号作为第m+N/2个驱动单元310的触发信号。其中，m为满足0<m≤M的整数，M为GOA驱动单元的个数。上述GOA驱动电路300能够解决因GOA驱动单元级联过多导致的输出信号明显衰减问题。然而，在上述GOA驱动电路300中，由于当前N/2-1个扫描时钟为高电位时，开启信号STV一直处于高电位，使得前N/2-1个GOA驱动单元310中的扫描控制信号Q点(即前N/2-1个触发单元311输出的扫描控制信号)的电位无法受自举电容C的耦合效应作用被抬升，只能保持和开启信号STV相同的电位，从而造成前N/2-1条扫描线(即前N/2-1个输出单元312的输出信号)充电不良，影响显示画面的质量。因此，本发明的GOA驱动电路400基于图2中的GOA驱动电路300的结构进行了进一步完善，从而来改善前N/2-1条扫描线充电不良的状况，提高显示画面的质量。
图3是本发明的实施例中具有N个扫描时钟的GOA驱动电路400的结构示意图。如图3所示，该驱动电路400包括多个GOA驱动单元410。具体地，前N/2-1个GOA驱动单元410的触发信号由触发时钟控制生成，第N/2个GOA驱动单元410的触发信号为开启信号STV，且第m个GOA驱动单元410的输出信号为第m+N/2个GOA驱动单元410的触发信号。下面结合图3详细地说明该驱动电路400的具体结构。
首先，由于前K个GOA驱动单元410的结构相同，因此下面以第k个GOA驱动单元410的结构为例，来对前K个GOA驱动单元410的结构进行说明，其中K为大于0的整数，k为满足0<k≤K的整数，且K＝N/2-1。第k个GOA驱动单元410的主要结构包括触发单元411、输出单元412和下拉单元413。
触发单元411主要用于控制输出单元412的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元411包括第一薄膜晶体管T11和第二薄膜晶体管T21。其中，T11用于将开启信号STV输出为触发信号。T11的栅极连接触发时钟，漏极连接开启信号STV，其源极生成触发信号。并且T11的源极与T21的栅极和漏极相连。T21用于输出第k行的扫描控制信号Q(k)。T21的栅极和漏极连接在一起，用于接收T11的源极生成的触发信号，其源极生成第k行的扫描控制信号Q(k)。T21的源极与输出单元412的控制 端相连。
输出单元412主要用于将第k个扫描时钟信号CK(k)输出为第k行的扫描信号G(k)。具体地，输出单元412由第六薄膜晶体管T61和自举电容C构成。其中，T61的栅极作为输出单元412的控制端接收由触发单元411生成的第k行的扫描控制信号Q(k)。T61的漏极作为输出单元412的输入端接收第k个扫描时钟信号CK(k)。T61的源极作为输出单元412的输出端，连接第k行的扫描线G(k)，用于生成并输出第k行的扫描信号G(k)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(k)为高电平时，存储T61栅源端的电压，并且当G(k)输出第k行的扫描信号G(k)后，二次抬升T61栅极的电压(即CK(k)为高电平时，第k行的扫描控制信号Q(k)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61能够可靠地被开启并输出第k行的扫描信号G(k)。
在本实施例中，T11的栅极所连接的触发时钟被配置为：在输出单元412的输入端接收到的扫描时钟信号CK(k)为高电位时，控制触发单元411关闭。具体而言，在扫描时钟信号CK(k)由低电位变为高电位之前的一段时间内，触发时钟要控制触发单元411处于开启状态，而在扫描时钟信号CK(k)由低电位变为并保持在高电位期间，触发时钟要控制触发单元411处于关闭状态。
进一步地讲，在扫描时钟信号CK(k)由低电位变为高电位之前的一段时间内，触发时钟要控制T11处于开启状态，而在扫描时钟信号CK(k)由低电位变为并保持在高电位期间，触发时钟要控制T11处于关闭状态。
在本实施例中，T11和T21优选地为N型薄膜晶体管。则，首先在扫描时钟信号CK(k)由低电位变为高电位之前的一段时间内，触发时钟要保持高电平以使T11开启并生成触发信号，进而使T21在其栅极和漏极接收到该触发信号后能够开启并生成第k行的扫描控制信号Q(k)。然后在扫描时钟CK(k)由低电位变为并保持在高电位期间，触发时钟要保持低电平以使T11关闭，从而使Q(k)点的电位在CK(k)为高电位时能够受自举电容C的耦合效应作用被抬升。因此，本实施例能够通过增加由触发时钟控制的第一薄膜晶体管T11来避免第k行的扫描线G(k)因STV未及时关闭而产生的充电不良。
本实施例为了使控制简单方便，优选地将T11的栅极所连接的触发时钟设定为第k+N/2个扫描时钟CK(k+N/2)。当然，也可以单独的设定一个时钟信号作为T11的栅极所连接的触发时钟，只要该时钟信号在输出单元412的扫描时钟CK(k)由低电位变为高电位的前一段时间内，能够控制触发单元411处于开启状态，并且在输出单元412 的扫描时钟CK(k)由低电位变为并维持高电位期间，能够控制触发单元411处于关闭状态即可。因此，在具体实施过程中，本领域技术人员可以根据实际需求来设定T11的栅极所连接的触发时钟。
下拉单元413用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位，即关闭第k行的扫描信号G(k)。具体地，下拉单元413由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第k行的扫描信号G(k)的电位，T81的漏极与输出单元412的输出端连接，即作用于第k行的扫描线G(k)。T71用于下拉第k行的扫描控制信号Q(k)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元412的控制端连接。T71的栅极与T81的栅极连接在一起，并与第k+1行的扫描线G(k+1)相连，即接收第k+1行的扫描线信号G(k+1)，由有效的第k+1行的扫描线信号G(k+1)控制第k行的扫描信号G(k)关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
其次，对第K+1个GOA驱动单元410的结构进行说明，第K+1个GOA驱动单元410的主要结构包括触发单元411、输出单元412和下拉单元413。
触发单元411主要用于控制输出单元412的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元411由第三薄膜晶体管T31构成，用于输出第K+1行的扫描控制信号Q(K+1)。其中，T31的栅极和漏极连接开启信号STV，其源极生成第K+1行的扫描控制信号Q(K+1)。T31的源极与输出单元412的控制端相连。
输出单元412主要用于将第K+1个扫描时钟信号CK(K+1)输出为第K+1行的扫描信号G(K+1)。具体地，输出单元412包括第六薄膜晶体管T61和自举电容C。其中，T61的栅极作为输出单元412的控制端接收由触发单元411生成的第K+1行的扫描控制信号Q(K+1)。T61的漏极作为输出单元412的输入端接收第K+1个扫描时钟信号CK(K+1)。T61的源极作为输出单元412的输出端，连接第K+1行的扫描线G(K+1)，用于生成并输出第K+1行的扫描信号G(K+1)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(K+1)为高电平时，存储T61栅源端的电压，并且当G(K+1)输出第K+1行的扫描信号G(K+1)后，二次抬升T61栅极的电压(即CK(K+1)为高电平时，第K+1行的扫描控制信号Q(K+1)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61能够可靠地被开启并输出第K+1行的扫描信号G(K+1)。
下拉单元413用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位， 即关闭第K+1行的扫描信号G(K+1)。具体地，下拉单元413由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第K+1行的扫描信号G(K+1)的电位，T81的漏极与输出单元412的输出端连接，即作用于第K+1行的扫描线G(K+1)。T71用于下拉第K+1行的扫描控制信号Q(K+1)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元412的控制端连接。T71的栅极与T81的栅极连接在一起，并与第K+2行的扫描线G(K+2)相连，即接收第K+2行的扫描线信号G(K+2)，由有效的第K+2行的扫描线信号G(K+2)控制第K+1行的扫描信号G(K+1)的关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
最后，由于第K+1个之后的所有GOA驱动单元410的结构相同，因此下面以第f个GOA驱动单元410的结构为例，来对第K+1个之后的GOA驱动单元410的结构进行说明，其中f为满足K+1<f≤M的整数。第f个GOA驱动单元410的主要结构包括触发单元411、输出单元412和下拉单元413。
触发单元411主要用于控制输出单元412的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元411由第四薄膜晶体管T41构成，用于输出第f行的扫描控制信号Q(f)。T41的栅极和漏极连接在一起，用于接收第f-N/2个GOA驱动单元输出的第f-N/2行的扫描信号G(f-N/2)，其源极生成第f行的扫描控制信号Q(f)。T41的源极与输出单元412的控制端相连。
输出单元412主要用于将第e个扫描时钟信号CK(e)输出为第f行的扫描信号G(f)，其中e＝mod(f，N)。在此需要说明的是，在本实施例中当f能够整除N时，令e＝N，即此时输出单元212用于将第N个扫描时钟信号CK(N)输出为第f行的扫描信号G(f)。具体地，输出单元412由第六薄膜晶体管T61和自举电容C构成。其中，T61的栅极作为输出单元412的控制端接收由触发单元411生成的第f行的扫描控制信号Q(f)。T61的漏极作为输出单元412的输入端接收第e个扫描时钟信号CK(e)。T61的源极作为输出单元412的输出端，连接第f行的扫描线G(f)，用于生成并输出第f行的扫描信号G(f)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(f)为高电平时，存储T61栅源端的电压，并且当G(f)输出第f行的扫描信号G(f)后，二次抬升T61栅极的电压(即第f个GOA驱动单元410的扫描时钟CK(e)为高电平时，第f行的扫描控制信号Q(f)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61能够可靠地被开启并输出第f行的扫描信号G(f)。
下拉单元413用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位， 即关闭第f行的扫描信号G(f)。具体地，下拉单元413由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第f行的扫描信号G(f)的电位，T81的漏极与输出单元412的输出端连接，即作用于第f行的扫描线G(f)。T71用于下拉第f行的扫描控制信号Q(f)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元412的控制端连接。T71的栅极与T81的栅极连接在一起，并与第f+1行的扫描线G(f+1)相连，即接收第f+1行的扫描线信号G(f+1)，由有效的第f+1行的扫描线信号G(f+1)控制第f行的扫描信号G(f)的关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
综上，在前N/2-1个扫描时钟为高电位时，应用本实施例所述的GOA驱动电路400能够使前N/2-1行的扫描控制信号Q点的电位受自举电容C的耦合效应作用被抬升，从而可以避免前N/2-1行的扫描线因开启信号STV未及时关闭而产生的充电不良。应用本实施例所述的GOA驱动电路400能够改善前N/2-1行扫描线充电不良的状况，进而提高显示画面的质量。
实施例三
本实施例对实施例二中的扫描时钟的个数进行了进一步优化。
在实施例二的基础上，本实施例对扫描时钟的个数进行了进一步地限定。优选地，扫描时钟的个数N＝8，如图4所示。图4是本发明的实施例中具有八个扫描时钟的GOA驱动电路500的结构示意图。如图4所示，该GOA驱动电路500包括多个GOA驱动单元510。具体地，前三个GOA驱动单元510的触发信号由触发时钟控制生成，第四个GOA驱动单元510的触发信号为开启信号STV，且第m个GOA驱动单元510的输出信号为第m+4个GOA驱动单元510的触发信号。下面结合图4详细地说明该驱动电路500的具体结构。
首先，由于前三个GOA驱动单元510的结构相同，因此下面以第k个GOA驱动单元510的结构为例，来对前三个GOA驱动单元510的结构进行说明，其中k为满足0<k≤3的整数。第k个GOA驱动单元510的主要结构包括触发单元511、输出单元512和下拉单元513。
触发单元511主要用于控制输出单元512的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元511包括第一薄膜晶体管T11和第二薄膜晶体管T21。其中，T11用于将开启信号STV输出为触发信号。T11的栅极连接触发时钟，漏极连接开启信号STV， 其源极生成触发信号。并且T11的源极与T21的栅极和漏极相连。T21用于输出第k行的扫描控制信号Q(k)。T21的栅极和漏极连接在一起，用于接收T11的源极生成的触发信号，其源极生成第k行的扫描控制信号Q(k)。T21的源极与输出单元512的控制端相连。
输出单元512主要用于将第k个扫描时钟信号CK(k)输出为第k行的扫描信号G(k)。具体地，输出单元512由第六薄膜晶体管T61和自举电容C构成。其中，T61的栅极作为输出单元512的控制端接收由触发单元511生成的第k行的扫描控制信号Q(k)。T61的漏极作为输出单元512的输入端接收第k个扫描时钟信号CK(k)。T61的源极作为输出单元512的输出端，连接第k行的扫描线G(k)，用于生成并输出第k行的扫描信号G(k)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(k)为高电平时，存储T61栅源端的电压，并且当G(k)输出第k行的扫描信号G(k)后，二次抬升T61栅极的电压(即CK(k)为高电平时，第k行的扫描控制信号Q(k)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61能够可靠地被开启并输出第k行的扫描信号G(k)。
在本实施例中，T11的栅极所连接的触发时钟被配置为：在输出单元512的输入端接收到的扫描时钟信号CK(k)为高电位时，控制触发单元511关闭。具体而言，在扫描时钟信号CK(k)由低电位变为高电位之前的一段时间内，触发时钟要控制触发单元511处于开启状态，而在扫描时钟信号CK(k)由低电位变为并保持在高电位期间，触发时钟要控制触发单元511处于关闭状态。
进一步地讲，在扫描时钟信号CK(k)由低电位变为高电位之前的一段时间内，触发时钟要控制T11处于开启状态，而在扫描时钟信号CK(k)由低电位变为并保持在高电位期间，触发时钟要控制T11处于关闭状态。
在本实施例中，T11和T21优选地为N型薄膜晶体管。则，首先在扫描时钟信号CK(k)由低电位变为高电位之前的一段时间内，触发时钟要保持高电平以使T11开启并生成触发信号，进而使T21在其栅极和漏极接收到该触发信号后能够开启并生成第k行的扫描控制信号Q(k)。然后在扫描时钟CK(k)由低电位变为并保持在高电位期间，触发时钟要保持低电平以使T11关闭，从而使Q(k)点的电位在CK(k)为高电位时能够受自举电容C的耦合效应作用被抬升。因此，本实施例能够通过增加由触发时钟控制的第一薄膜晶体管T11来避免第k行的扫描线G(k)因STV未及时关闭而产生的充电不良。
本实施例为了使控制简单方便，优选地将T11的栅极所连接的触发时钟设定为第k+4 个扫描时钟CK(k+4)。当然，也可以单独的设定一个时钟信号作为T11的栅极所连接的触发时钟，只要该时钟信号能够在输出单元512的扫描时钟CK(k)由低电位变为高电位的前一段时间内，能够控制触发单元511处于开启状态，并且在输出单元512的扫描时钟CK(k)由低电位变为并维持高电位期间，能够控制触发单元511处于关闭状态即可。因此，在具体实施过程中，本领域技术人员可以根据实际需求来设定T11的栅极所连接的触发时钟。
下拉单元513用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位，即关闭第k行的扫描信号G(k)。具体地，下拉单元513由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第k行的扫描信号G(k)的电位，T81的漏极与输出单元512的输出端连接，即作用于第k行的扫描线G(k)。T71用于下拉第k行的扫描控制信号Q(k)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元512的控制端连接。T71的栅极与T81的栅极连接在一起，并与第k+1行的扫描线G(k+1)相连，即接收第k+1行的扫描线信号G(k+1)，由有效的第k+1行的扫描线信号G(k+1)控制第k行的扫描信号G(k)关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
其次，对第四个GOA驱动单元510的结构进行说明，第四个GOA驱动单元510的主要结构包括触发单元511、输出单元512和下拉单元513。
触发单元511主要用于控制输出单元512的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元511由第三薄膜晶体管T31构成，用于输出第四行的扫描控制信号Q(4)。其中，T31的栅极和漏极连接开启信号STV，其源极生成第四行的扫描控制信号Q(4)。T31的源极与输出单元512的控制端相连。
输出单元512主要用于将第四个扫描时钟信号CK(4)输出为第四行的扫描信号G(4)。具体地，输出单元512包括第六薄膜晶体管T61和自举电容C。其中，T61的栅极作为输出单元512的控制端接收由触发单元511生成的第四行的扫描控制信号Q(4)。T61的漏极作为输出单元512的输入端接收第四个扫描时钟信号CK(4)。T61的源极作为输出单元512的输出端，连接第四行的扫描线G(4)，用于生成并输出第四行的扫描信号G(4)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(4)为高电平时，存储T61栅源端的电压，并且当G(4)输出第四行的扫描信号G(4)后，二次抬升T61栅极的电压(即CK(4)为高电平时，第四行的扫描控制信号Q(4)点的电位受自举电容C的耦合效应作用被抬升)，以保证T61 能够可靠地被开启并输出第四行的扫描信号G(4)。
下拉单元513用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位，即关闭第四行的扫描信号G(4)。具体地，下拉单元513由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第四行的扫描信号G(4)的电位，T81的漏极与输出单元512的输出端连接，即作用于第四行的扫描线G(4)。T71用于下拉第四行的扫描控制信号Q(4)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元512的控制端连接。T71的栅极与T81的栅极连接在一起，并与第五行的扫描线G(5)相连，即接收第五行的扫描线信号G(5)，由有效的第五行的扫描线信号G(5)控制第四行的扫描信号G(4)的关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
最后，由于第四个之后的所有GOA驱动单元510的结构相同，因此下面以第f个GOA驱动单元510的结构为例，来对第四个之后的GOA驱动单元510的结构进行说明，其中f为满足4<f≤M的整数。第f个GOA驱动单元510的主要结构包括触发单元511、输出单元512和下拉单元513。
触发单元511主要用于控制输出单元512的开启时间，实现液晶显示面板的逐行扫描。具体地，触发单元511由第四薄膜晶体管T41构成，用于输出第f行的扫描控制信号Q(f)。T41的栅极和漏极连接在一起，用于接收第f-4个GOA驱动单元输出的第f-4行的扫描信号G(f-4)，其源极生成第f行的扫描控制信号Q(f)。T41的源极与输出单元512的控制端相连。
输出单元512主要用于将第e个扫描时钟信号CK(e)输出为第f行的扫描信号G(f)，其中e＝mod(f，8)。在此需要说明的是，在本实施例中当f能够整除8时，令e＝8，即此时输出单元212用于将第八个扫描时钟信号CK(8)输出为第f行的扫描信号G(f)。具体地，输出单元512由第六薄膜晶体管T61和自举电容C构成。其中，T61的栅极作为输出单元512的控制端接收由触发单元511生成的第f行的扫描控制信号Q(f)。T61的漏极作为输出单元512的输入端接收第e个扫描时钟信号CK(e)。T61的源极作为输出单元512的输出端，连接第f行的扫描线G(f)，用于生成并输出第f行的扫描信号G(f)。自举电容C的一端与T61的栅极相连，另一端与T61的源极相连。其中，自举电容C的作用是在Q(f)为高电平时，存储T61栅源端的电压，并且当G(f)输出第f行的扫描信号G(f)后，二次抬升T61栅极的电压(即第f个GOA驱动单元410的扫描时钟CK(e)为高电平时，第f行的扫描控制信号Q(f)点的电位受自举电容C的耦合 效应作用被抬升)，以保证T61能够可靠地被开启并输出第f行的扫描信号G(f)。
下拉单元513用于即时将第六薄膜晶体管T61的源极电位和栅极电位拉低为低电位，即关闭第f行的扫描信号G(f)。具体地，下拉单元513由第七薄膜晶体管T71和第八薄膜晶体管T81构成。其中，T81用于下拉第f行的扫描信号G(f)的电位，T81的漏极与输出单元512的输出端连接，即作用于第f行的扫描线G(f)。T71用于下拉第f行的扫描控制信号Q(f)，以便关闭第六薄膜晶体管T61。T71的漏极与输出单元512的控制端连接。T71的栅极与T81的栅极连接在一起，并与第f+1行的扫描线G(f+1)相连，即接收第f+1行的扫描线信号G(f+1)，由有效的第f+1行的扫描线信号G(f+1)控制第f行的扫描信号G(f)的关闭，实现逐行扫描。T71的源极与T81的源极共同连接于直流低电平VSS。
在本实施例中，上述所有薄膜晶体管优选为N型薄膜晶体管。进一步地，图5给出了该GOA驱动电路500的工作时序图。下面结合图4和图5来详细说明上述驱动过程。
在t0到t1时间段内：CK(5)和STV为高电平，第一个GOA驱动单元510中的触发单元511被开启并输出第一行的扫描控制信号Q(1)。同时STV为高电平，第四个GOA驱动单元510中的T31被开启并输出第四行的扫描控制信号Q(4)。
在t1到t2时间段内：CK(6)和STV为高电平，第二个GOA驱动单元510中的触发单元511被开启并输出第二行的扫描控制信号Q(2)。同时，CK(5)和STV为高电平，第一个GOA驱动单元510中的触发单元511仍处于开启状态并输出第一行的扫描控制信号Q(1)；STV为高电平，第四个GOA驱动单元510中的T31仍处于开启状态并输出第四行的扫描控制信号Q(4)。
在t2到t3时间段内：其一，CK(1)和Q(1)为高电平，第一个GOA驱动单元510中的T61被开启并输出第一行的扫描信号G(1)。同时由于CK(5)为低电平，第一个GOA驱动单元510中的T11被关闭，因此第一行的扫描控制信号Q(1)的电位能够受自举电容C的耦合效应作用被抬升，使得第一行的扫描信号G(1)充分充电。并且，当输出第一行的扫描信号G(1)后，第五个GOA驱动单元510中的T41被开启并输出第五行的扫描控制信号Q(5)。其二，CK(7)和STV为高电平，第三个GOA驱动单元510中的触发单元511被开启并输出第三行的扫描控制信号Q(3)。其三，CK(6)和STV为高电平，第二个GOA驱动单元510中的触发单元511仍处于开启状态并输出第二行的扫描控制信号Q(2)；STV为高电平，第四个GOA驱动单元510中的T31仍处于开启状态并输出第四行的扫描控制信号Q(4)。
在t3到t4时间段内：其一，CK(2)和Q(2)为高电平，第二个GOA驱动单元510中的T61被开启并输出第二行的扫描信号G(2)。同时由于CK(6)为低电平，第二个GOA驱动单元510中的T11被关闭，因此第二行的扫描控制信号Q(2)的电位能够受自举电容C的耦合效应作用被抬升，使得第二行的扫描信号G(2)充分充电。并且，当输出第二行的扫描信号G(2)后：一方面，第一个GOA驱动单元510中的T71和T81被开启，进而将G(1)和Q(1)拉低为低电平，关闭第一行像素的扫描线G(1)；另一方面，第六个GOA驱动单元510中的T41被开启并输出第六行的扫描控制信号Q(6)。其二，CK(7)和STV为高电平，第三个GOA驱动单元510中的触发单元511仍处于开启状态并输出第三行的扫描控制信号Q(3)；STV为高电平，第四个GOA驱动单元510中的T31仍处于开启状态并输出第四行的扫描控制信号Q(4)。
在t4到t5时间段内：其一，CK(3)和Q(3)为高电平，第三个GOA驱动单元510中的T61被开启并输出第三行的扫描信号G(3)。同时由于CK(7)为低电平，第三个GOA驱动单元510中的T11被关闭，因此第三行的扫描控制信号Q(3)的电位能够受自举电容C的耦合效应作用被抬升，使得第三行的扫描信号G(3)充分充电。并且，当输出第三行的扫描信号G(3)后：一方面，第二个GOA驱动单元510中的T71和T81被开启，进而将G(2)和Q(2)拉低为低电平，关闭第二行像素的扫描线G(2)；另一方面，第七个GOA驱动单元510中的T41被开启并输出第七行的扫描控制信号Q(7)。其二，STV为高电平，第四个GOA驱动单元510中的T31仍处于开启状态并输出第四行的扫描控制信号Q(4)。
在t5到t6时间段内：CK(4)和Q(4)为高电平，第四个GOA驱动单元510中的T61被开启并输出第四行的扫描信号G(4)。同时由于STV为低电平，第四个GOA驱动单元510中的T31被关闭，因此第四行的扫描控制信号Q(4)的电位能够受自举电容C的耦合效应作用被抬升，使得第四行的扫描信号G(4)充分充电。并且，当输出第四行的扫描信号G(4)后：一方面，第三个GOA驱动单元510中的T71和T81被开启，进而将G(3)和Q(3)拉低为低电平，关闭第三行像素的扫描线G(3)；另一方面，第八个GOA驱动单元510中的T41被开启并输出第八行的扫描控制信号Q(8)。
在t6到t7时间段内：CK(5)和Q(5)为高电平，第五个GOA驱动单元510中的T61被开启并输出第五行的扫描信号G(5)。并且，当输出第五行的扫描信号G(5)后：一方面，第四个GOA驱动单元510中的T71和T81被开启，进而将G(4)和Q(4)拉低为低电平，关闭第四行像素的扫描线G(4)；另一方面，第九个GOA驱动单元510中的T41被开启并输出第九行的扫描控制信号Q(9)。
在t7到t8时间段内：CK(6)和Q(6)为高电平，第六个GOA驱动单元510中的T61被开启并输出第六行的扫描信号G(6)。并且，当输出第六行的扫描信号G(6)后：一方面，第五个GOA驱动单元510中的T71和T81被开启，进而将G(5)和Q(5)拉低为低电平，关闭第五行像素的扫描线G(5)；另一方面，第十个GOA驱动单元510中的T41被开启并输出第十行的扫描控制信号Q(10)。
接下来各行扫描线的驱动方式与上述t7到t8时间段内的驱动方式类似，为了减少冗余，在此不做赘述。因此，本实施例中的GOA驱动电路500实现了逐行扫描，并且避免了前三行的扫描线因开启信号STV未及时关闭而产生的充电不良。
综上，在前三个扫描时钟为高电平时，应用本实施例所述的GOA驱动电路500能够使前三行的扫描控制信号Q点的电位受自举电容C的耦合效应作用被抬升，从而可以避免前三行的扫描线因开启信号STV未及时关闭而产生的充电不良。应用本实施例所述的GOA驱动电路500能够改善前三行扫描线充电不良的状况，进而提高显示画面的质量。
实施例四
本发明还提供了一种液晶显示面板。本实施例的液晶显示面板包括实施例一所述的GOA驱动电路200。
综上，在第一个扫描时钟CK(1)为高电位时，应用本实施例所述的液晶显示面板能够使第一行的扫描控制信号Q(1)点的电位受自举电容C的耦合效应作用被抬升，从而可以避免第一行的扫描线G(1)因开启信号STV未及时关闭而产生的充电不良。应用本实施例所述的液晶显示面板能够改善第一行的扫描线G(1)充电不良的状况，进而提高显示画面的质量。
实施例五
本发明还提供了一种液晶显示面板。本实施例的液晶显示面板包括实施例二所述的GOA驱动电路400或实施例三所述的GOA驱动电路500。
综上，在前N/2-1个扫描时钟为高电位时，应用本实施例所述的液晶显示面板能够使前N/2-1行的扫描控制信号Q点的电位受自举电容C的耦合效应作用被抬升，从而可以避免前N/2-1行的扫描线因开启信号STV未及时关闭而产生的充电不良。应用本实施例所述的液晶显示面板能够改善前N/2-1行扫描线充电不良的状况，进而提高显示画面的质 量。
以上所述，仅为本发明的具体实施案例，本发明的保护范围并不局限于此，任何熟悉本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的保护范围之内。

Claims (20)

  1. 一种GOA驱动电路，包括多个GOA驱动单元，每个GOA驱动单元包括彼此连接的触发单元和输出单元；其中，
    对于前K个GOA驱动单元中的每个触发单元，所述触发单元包括第一薄膜晶体管和第二薄膜晶体管；
    其中，所述第一薄膜晶体管的栅极连接所述触发单元对应的触发时钟，所述第一薄膜晶体管的漏极连接开启信号，所述第一薄膜晶体管的源极连接所述第二薄膜晶体管的栅极和漏极，所述第二薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端，K为大于0的整数；其中，
    所述触发时钟被配置为：在所述输出单元的扫描时钟为高电位时，控制所述触发单元关闭。
  2. 根据权利要求1所述的GOA驱动电路，其中，第m个GOA驱动单元的输出信号为第m+N/2个GOA驱动单元的触发信号，其中，N为所述GOA驱动电路中扫描时钟的个数，且N＝2(K+1)；
    m为满足0<m≤M的整数，其中，M为GOA驱动单元的个数。
  3. 根据权利要求2所述的GOA驱动电路，其中，第K+1个GOA驱动单元中的触发单元包括第三薄膜晶体管；其中，所述第三薄膜晶体管的栅极和漏极连接所述开启信号，所述第三薄膜晶体管的源极连接第K+1个GOA驱动单元中的输出单元的控制端。
  4. 根据权利要求3所述的GOA驱动电路，其中，对于第K+1个GOA驱动单元之后的每个GOA驱动单元中的触发单元，所述触发单元包括第四薄膜晶体管；其中，所述第四薄膜晶体管的栅极和漏极连接所述触发单元对应的触发信号，所述第四薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端。
  5. 根据权利要求2所述的GOA驱动电路，其中，第k个GOA驱动单元的触发单元对应的触发时钟，为第k+N/2个GOA驱动单元中的输出单元的扫描时钟，其中k为满足0<k≤K的整数。
  6. 根据权利要求3所述的GOA驱动电路，其中，第k个GOA驱动单元的触发单元对应的触发时钟，为第k+N/2个GOA驱动单元中的输出单元的扫描时钟，其中k为满足0<k≤K的整数。
  7. 根据权利要求4所述的GOA驱动电路，其中，第k个GOA驱动单元的触发单元 对应的触发时钟，为第k+N/2个GOA驱动单元中的输出单元的扫描时钟，其中k为满足0<k≤K的整数。
  8. 根据权利要求5所述的GOA驱动电路，其中，所述K等于3。
  9. 根据权利要求6所述的GOA驱动电路，其中，所述K等于3。
  10. 根据权利要求7所述的GOA驱动电路，其中，所述K等于3。
  11. 根据权利要求1所述的GOA驱动电路，其中，其包括的所有GOA驱动单元依次连接；其中，上一级GOA驱动单元的输出信号为下一级GOA驱动单元的触发信号，且K＝1。
  12. 根据权利要求11所述的GOA驱动电路，其中，第一级GOA驱动单元的触发单元对应的触发时钟，为H个扫描时钟中除去第一级GOA驱动单元的扫描时钟后剩余中的任意一个，其中，H为所述GOA驱动电路中扫描时钟的个数。
  13. 根据权利要求11所述的GOA驱动电路，其中，对于第一级之后的每个GOA驱动单元中的触发单元，所述触发单元包括第五薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接所述触发单元对应的触发信号，所述第五薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端。
  14. 根据权利要求12所述的GOA驱动电路，其中，对于第一级之后的每个GOA驱动单元中的触发单元，所述触发单元包括第五薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接所述触发单元对应的触发信号，所述第五薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端。
  15. 一种液晶显示面板，包括GOA驱动电路，所述GOA驱动电路包括多个GOA驱动单元，每个GOA驱动单元包括彼此连接的触发单元和输出单元；其中，
    对于前K个GOA驱动单元中的每个触发单元，所述触发单元包括第一薄膜晶体管和第二薄膜晶体管；
    其中，所述第一薄膜晶体管的栅极连接所述触发单元对应的触发时钟，所述第一薄膜晶体管的漏极连接开启信号，所述第一薄膜晶体管的源极连接所述第二薄膜晶体管的栅极和漏极，所述第二薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端，K为大于0的整数；其中，
    所述触发时钟被配置为：在所述输出单元的扫描时钟为高电位时，控制所述触发单元关闭。
  16. 根据权利要求15所述的液晶显示面板，其中，第m个GOA驱动单元的输出信号为第m+N/2个GOA驱动单元的触发信号，其中，N为所述GOA驱动电路中扫描时钟的个数，且N＝2(K+1)；
    m为满足0<m≤M的整数，其中，M为GOA驱动单元的个数。
  17. 根据权利要求16所述的液晶显示面板，其中，第K+1个GOA驱动单元中的触发单元包括第三薄膜晶体管；其中，所述第三薄膜晶体管的栅极和漏极连接所述开启信号，所述第三薄膜晶体管的源极连接第K+1个GOA驱动单元中的输出单元的控制端。
  18. 根据权利要求17所述的液晶显示面板，其中，对于第K+1个GOA驱动单元之后的每个GOA驱动单元中的触发单元，所述触发单元包括第四薄膜晶体管；其中，所述第四薄膜晶体管的栅极和漏极连接所述触发单元对应的触发信号，所述第四薄膜晶体管的源极连接与所述触发单元相连的输出单元的控制端。
  19. 根据权利要求16所述的液晶显示面板，其中，第k个GOA驱动单元的触发单元对应的触发时钟，为第k+N/2个GOA驱动单元中的输出单元的扫描时钟，其中k为满足0<k≤K的整数。
  20. 根据权利要求17所述的液晶显示面板，其中，第k个GOA驱动单元的触发单元对应的触发时钟，为第k+N/2个GOA驱动单元中的输出单元的扫描时钟，其中k为满足0<k≤K的整数。
PCT/CN2017/083061 2017-04-25 2017-05-04 Goa驱动电路和液晶显示面板 Ceased WO2018196020A1 (zh)

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