WO2018192016A1 - 提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法 - Google Patents

提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法 Download PDF

Info

Publication number
WO2018192016A1
WO2018192016A1 PCT/CN2017/083463 CN2017083463W WO2018192016A1 WO 2018192016 A1 WO2018192016 A1 WO 2018192016A1 CN 2017083463 W CN2017083463 W CN 2017083463W WO 2018192016 A1 WO2018192016 A1 WO 2018192016A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
silicon island
substrate
solder ball
fatigue life
Prior art date
Application number
PCT/CN2017/083463
Other languages
English (en)
French (fr)
Inventor
曾清华
陈兢
金玉丰
Original Assignee
北京大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京大学 filed Critical 北京大学
Publication of WO2018192016A1 publication Critical patent/WO2018192016A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H01L23/4926—Bases or plates or solder therefor characterised by the materials the materials containing semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid

Definitions

  • the present invention relates to the field of manufacturing semiconductor devices, and more particularly to a silicon island array structure and a flip chip packaging method for improving solder ball fatigue life.
  • FC technology for integrated circuit (IC) chip packaging.
  • the FC technology is a package form in which an IC chip is actively facing down through a solder and a substrate or a printed circuit board (PCB).
  • PCB printed circuit board
  • FC technology can use more chip area for interconnection, instead of being limited to the periphery of IC chip, greatly improving the I/O number.
  • C4 Controlled Collapse Chip Connection
  • the solder ball acts as a layer when the package module undergoes thermal cycle loading.
  • the inter-interconnect structure is subject to an alternating load, which is prone to fatigue failure at the interface with the chip or at the interface with the PCB.
  • FIG. 3 is a schematic diagram of a flip chip package structure using a prior art, including a chip, a substrate, a die pad, a substrate pad, and a solder ball.
  • the die pad is located on the upper surface of the chip to extract the polarity of the chip;
  • the solder ball is located between the die pad and the substrate pad, and the electrode on the chip is taken out through the substrate through the connection relationship.
  • the solder ball is easily deformed when the temperature changes, and the deformation is related to factors such as the height of the solder ball, the size of the chip, and the thickness of the substrate, and the deformation of the solder ball. Will lead to fatigue fracture of the solder ball and electrical open circuit or short circuit, resulting in system failure.
  • the Chinese invention patent discloses a flip chip packaging method comprising setting a set of pads on a chip; Arranging a set of first connection structures and a set of second connection structures on the pads in a spaced manner; and placing the chips on a substrate, the chips passing through the first connection structure and the A second connection structure is coupled to the substrate. Taking the first connection structure with reduced hardness to bear the heat of the welding sphere due to the difference in thermal expansion coefficient between the chip and the substrate force.
  • an object of the present invention is to provide a silicon island array structure and a flip chip packaging method for improving the fatigue life of a solder ball.
  • the integrated circuit chip includes a silicon substrate, and the columnar or mesa silicon island is formed on the surface of the silicon substrate by etching.
  • a spacer groove is formed around the columnar or mesa silicon island during the etching.
  • the spacing groove is a square groove, a trapezoidal groove or a dovetail groove.
  • the spacer groove has a width ranging from 5 ⁇ m to 50 ⁇ m and a depth ranging from 5 ⁇ m to 50 ⁇ m.
  • a flip chip package structure comprising:
  • An integrated circuit chip having a silicon island array structure and disposed on a substrate;
  • connection structures forms an array distribution corresponding to the silicon island array structure.
  • the single connecting structure comprises a first bonding pad disposed on a surface of the silicon island, a second bonding pad disposed on the surface of the substrate, and a connecting component connecting the first bonding pad and the second bonding pad.
  • a flip chip packaging method includes the following steps:
  • the connecting structure in the step 3) comprises: a metal layer and an interconnect line formed on the surface of the silicon island; and a solder ball transferred to the surface of the silicon island by balling or surface printing.
  • connection structure in which the connection structure is disposed in the step 4) is interconnected with the substrate by flip-chip bonding.
  • the present invention arranges a silicon island array on an integrated circuit chip to provide a space for deformation in a deformation process caused by a difference in thermal expansion coefficient between an integrated circuit chip-solder ball-substrate or a printed circuit board. Thereby improving the thermo-mechanical reliability of the solder ball under thermal cycling load conditions and prolonging its fatigue life.
  • FIG. 1 is a schematic cross-sectional view of a prior art FCOB package structure in the prior art.
  • FIG. 2 is a schematic perspective view of a prior art FCOB package structure in the prior art.
  • FIG. 3 is a schematic diagram showing the three-dimensional structure of the active surface of the chip in the prior art FCOB package structure in the prior art.
  • FIG. 4 is a cross-sectional structural view of a flip chip package structure in accordance with an embodiment of the present invention.
  • FIG. 5 is a schematic perspective structural view of a flip chip package structure according to an embodiment of the invention.
  • FIG. 6 is a schematic perspective view showing a three-dimensional structure of a chip active surface in a flip chip package structure according to an embodiment of the invention.
  • FIGS. 7a-7i are flow diagrams showing a packaging process of a flip chip package structure according to an embodiment of the invention.
  • Figure 8 is a graph showing the thermal cycle load curve in the fatigue life verification time in an embodiment of the present invention.
  • FIG. 9 is a finite element mesh of a FCOB package form of a silicon-free island array structure in a fatigue life verification time according to an embodiment of the present invention.
  • Figure 10 is a finite element mesh of the FCOB package form with a silicon island array structure in a pair of proportional fatigue life verification times in the present invention.
  • 11 is a layer unit for calculating a non-elastic energy density at a solder ball/PCB interface in a fatigue life verification time according to an embodiment of the present invention.
  • Figure 12 is a graph showing the average equivalent creep strain versus time in the fatigue life verification time in an embodiment of the present invention.
  • Figure 13 is a graph showing the average equivalent plastic strain as a function of time in the fatigue life verification time in an embodiment of the present invention.
  • the present application is directed to a Flip-chip on Board (FCOB) of a silicon chip-solder ball-PCB, as shown in FIG. 4, FIG. 5 and FIG. 6, providing an active surface on a silicon chip.
  • Silicon island array structure An integrated circuit chip formed in a flip chip package structure includes: a plurality of columnar or mesa silicon islands arranged in an array.
  • the shape of the silicon island is columnar or mesa, including but not limited to a square column, a cylinder, a cylinder, a polygonal column, a truncated cone, an inverted frustum, a square frustum, etc., in consideration of processing complexity, the silicon island is preferably a square column in this embodiment.
  • the specific description of the examples below also refers to the silicon islands of the square columns. With other shapes of silicon islands, there are only a few process differences in the formation process.
  • the silicon island array structure provides a space for deformation during the deformation process caused by the difference in thermal expansion coefficient between the silicon chip and the solder ball-PCB, and can improve the thermo-mechanical reliability of the solder ball under the thermal cycle load condition, thereby improving the fatigue life.
  • the flip-chip package structure includes: an integrated circuit chip that is disposed on a substrate having the foregoing silicon island array structure; a set of connection structures that connect the substrate and the integrated circuit chip; and each connection structure forms a corresponding structure with the silicon island array structure The array distribution.
  • a single connection structure includes a first pad disposed on a surface of a silicon island, a second pad disposed on a surface of the substrate, and a connector connecting the first pad and the second pad.
  • the flip chip packaging method for obtaining the above package structure mainly comprises the following steps: first, dividing a silicon substrate of an integrated circuit chip into a plurality of array distributed regions; and then forming an edge on each surface of the silicon substrate surface by etching A spacer groove, thereby forming a plurality of array-arranged rectangular silicon islands on the surface of the substrate; and then, a connection structure is provided on each silicon island surface; finally, the silicon substrate on which the connection structure is disposed is interconnected with the substrate.
  • a) Prepare a silicon or silicon substrate, including diced, separated wafers, 4 inch wafers, 8 inch wafers, or 12 inch wafers.
  • etching is performed on the surface of the silicon substrate, and spacer grooves are formed around the columnar or mesa silicon island during the etching.
  • the etched region that is, the region where the spacer is formed has a depth of 5 ⁇ m to 50 ⁇ m and a width of 5 ⁇ m to 50 ⁇ m; after etching, the surface of the silicon substrate has a rectangular parallelepiped array shape, and the rectangular parallelepiped array of the surface of the substrate is collectively referred to as a silicon island array.
  • the specific dimensions, lateral spacing and longitudinal spacing of the formed silicon islands vary widely, and are selected according to the specific chip size and solder ball size.
  • the spacing groove is a square groove. In other embodiments, a trapezoidal groove or a dovetail groove can also be used.
  • this application uses the finite element simulation technology to compare the fatigue life of the solder ball with or without the silicon island array structure, and verifies the feasibility of improving the fatigue life of the solder ball by the silicon island array structure. Sex.
  • the finite element model of the FCOB package form with or without a silicon island array is shown in Figures 2 and 5.
  • the hexahedral meshing technique is used to ensure the consistency of mesh size and mesh seed density between models.
  • Model specific dimensions substrate size: length 4mm, width 4mm, height 0.8mm; chip size: length 1.705mm, width 1.18mm, height 0.498mm; solder ball size: solder ball radius 0.10mm, solder ball height 0.16mm; solder ball Spacing: The pitch along the length of the chip is 0.46 mm, the pitch along the width of the chip is 0.44 mm; the modeling ratio is 1:1.
  • the thermal cycle load curve (-55 ° C ⁇ 125 ° C) is shown in Figure 8, where the temperature is kept at the lowest temperature -55 ° C for 10 minutes, at the highest temperature of 125 ° C for 15 minutes, the temperature rise time is 1960 seconds, the temperature of the cooling process 1080 seconds.
  • a quarter model is used for calculation, and the meshed model is shown in Fig. 9 and Fig. 10.
  • the fatigue life of the solder balls in the FCOB package form with or without the silicon island array structure is predicted according to the strain-based Coffin-Manson model, which is shown in the following equation.
  • N f is the estimated fatigue life
  • ⁇ ⁇ p is the average inelastic strain, which is the sum of the average equivalent creep strain and the average equivalent plastic strain
  • n is the fatigue index
  • CEEQ average equivalent creep strain
  • PEEQ average equivalent plastic strain
  • the fatigue life of the solder balls in the FCOB package with the silicon island array structure can be found to be 2649 cycles.
  • the silicon island array structure design can greatly improve the fatigue life of the solder balls in the FCOB package form.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

一种提高焊球疲劳寿命的硅岛阵列结构，其形成于倒装芯片封装结构中的集成电路芯片的有源面，包括：若干阵列布置的柱状或台状硅岛。同时提供基于前述硅岛阵列结构的倒装芯片封装结构方法。在不改变焊接连接结构的前提下可有效避免封装结构在经历热膨胀过程中出现的连接失效问题。从而提高连接结构的疲劳寿命，确保倒装芯片封装结构的稳定性。

Description

提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法 技术领域
本发明涉及半导体器件的制造领域，尤其涉及一种提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法。
背景技术
1961年，IBM公司发明了应用于集成电路(Integrated Circuit,IC)芯片封装的倒装芯片(Flip-chip,FC)技术。FC技术是一种IC芯片有源面向下直接通过焊料与基板或印刷电路板(PrintedCircuit Board,PCB)互连的封装形式。与引线键合技术和载带自动键合技术等相比，FC技术可以将更多的芯片面积用于互连，而不是仅仅局限于IC芯片四周，极大地提高了I/O数。另外，得益于可控塌陷芯片连接(Controlled Collapse Chip Connection,C4)技术，FC技术在键合过程中具有良好的自对准性。然而，由于芯片材料热膨胀系数(2.5×10-6/K)和基板材料热膨胀系数(16～24×10-6/K)之间的差异，在封装模块经历热循环载荷时，焊球作为层间互连结构会受到交变载荷，容易在与芯片的互连界面或者与PCB的互连界面处发生疲劳失效。
具体可以参考图1至图3，三图绘示了采用现有技术的芯片倒装封装结构的示意图，其包括芯片，基板，芯片焊垫，基板焊垫和焊球。其中，芯片焊垫位于芯片的上表面，以将芯片的电极性引出；焊球位于芯片焊垫和基板焊垫之间，通过这种连接关系，将芯片上的电极性通过基板引出。
然而在实际应用中，由于芯片和基板的膨胀系数不同，因此，在温度变化时，焊球很容易发生形变，形变的大小与焊球高度，芯片大小以及基板厚度等因素相关，焊球的形变将导致焊球的疲劳断裂和电学上的开路或者短路，而造成系统的失效。
针对上述问题，本领域技术人员尝试作了一些努力进行改善，例如，中国发明专利(专利号：ZL201210428121.7)公开了一种倒装芯片封装方法，包括在一芯片上设置一组焊垫；将一组第一连接结构和一组第二连接结构依次间隔排列设置于所述焊垫之上；将所述芯片倒置于一基板上，所述芯片通过所述第一连接结构和所述第二连接结构与所述基板连接。以通过硬度减小的第一连接结构来承担由于芯片和基板的热膨胀系数不同而导致焊球形变的热应 力。然而，这种双焊球结构实际上会在一定程度上增加焊接结构的不稳定性，并且，第一连接结构与第二连接结构，即两个焊球之间仍然容易出现应力的集中，在封装结构经历热循环载荷过程中，由于热膨胀系统不同仍会导致两个焊球的连接部分应力集中，出现在该连接部分出现连接失效的可能。
发明内容
针对上述现有技术存在的问题，本发明的目的在于提供一种提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法。改变传统技术思路，在不改变焊接连接结构的前提下也可有效避免封装结构在经历热膨胀过程中出现的连接失效问题。从而提高连接结构的疲劳寿命，确保倒装芯片封装结构的稳定性。
为达上述目的，本发明采取的具体技术方案是：
一种提高焊球疲劳寿命的硅岛阵列结构，形成于倒装芯片封装结构中的集成电路芯片的有源面，包括：若干阵列布置的柱状或台状硅岛。
进一步地，所述集成电路芯片包括硅衬底，所述柱状或台状硅岛通过刻蚀的方式形成于的硅衬底的表面。
进一步地，所述刻蚀过程中在所述柱状或台状硅岛的周围形成间隔槽。
进一步地，所述间隔槽为方形槽、梯形槽或燕尾槽。
进一步地，所述间隔槽的宽度范围为5μm至50μm，深度范围为5μm至50μm。
一种倒装芯片封装结构，包括：
具有前述硅岛阵列结构的倒置于一基板的集成电路芯片；
连接前述基板及集成电路芯片的一组连接结构；
各连接结构与所述硅岛阵列结构形成对应的阵列分布。
进一步地，单个所述连接结构包括设置于一硅岛表面的一第一焊垫、设置于基板表面的一第二焊垫及连接第一焊垫与第二焊垫的一连接件。
一种倒装芯片封装方法，包括以下步骤：
1)将集成电路芯片的硅衬底划分为多个阵列分布的区域；
2)通过刻蚀在硅衬底表面各区域的边缘形成间隔槽，由此在衬底表面形成多个阵列分布的硅岛结构；
3)各硅岛结构表面设置连接结构；
4)将设置连接结构的硅衬底与基板互连。
进一步地，步骤3)中所述连接结构包括：形成于硅岛表面的金属层及互连线；通过植球或表面印刷的方式转移到硅岛表面的焊球。
进一步地，步骤4)中设置连接结构的硅衬底通过倒装键合的方式与基板互联。
通过采取上述技术方案，本发明在集成电路芯片布置硅岛阵列，以在集成电路芯片-焊球-基板或印刷电路板间因热膨胀系数差异导致的变形过程中提供变形的空间。从而提高焊球在热循环载荷条件下的热机械可靠性，延长其疲劳寿命。
附图说明
图1为背景技术中现有技术的FCOB封装结构的剖面结构示意图。
图2为背景技术中现有技术的FCOB封装结构的立体结构示意图。
图3为背景技术中现有技术的FCOB封装结构中芯片有源面俯面立体结构示意图。
图4为本发明一实施例中倒装芯片封装结构的剖面结构示意图。
图5为本发明一实施例中倒装芯片封装结构的立体结构示意图。
图6为本发明一实施例中倒装芯片封装结构中芯片有源面俯面立体结构示意图。
图7a至图7i为本发明一实施例中倒装芯片封装结构的封装工艺流程图。
图8为本发明一实施例中疲劳寿命验证时间中的热循环载荷曲线。
图9为本发明一实施例中疲劳寿命验证时间中的无硅岛阵列结构的FCOB封装形式的有限元网格。
图10为本发明一对比例中疲劳寿命验证时间中的有硅岛阵列结构的FCOB封装形式的有限元网格。
图11为本发明一实施例中疲劳寿命验证时间中的焊球/PCB界面处用于计算非弹性能量密度的层单元.
图12为本发明一实施例中疲劳寿命验证时间中的平均等效蠕变应变随时间变化曲线图。
图13为本发明一实施例中疲劳寿命验证时间中的平均等效塑性应变随时间变化曲线图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述。
本申请针对硅芯片-焊球-PCB的板上倒装芯片封装形式(Flip-chip on Board,FCOB)，如图4、图5和图6所示，提供了一种位于硅芯片有源面的硅岛阵列结构。形成于倒装芯片封装结构中的集成电路芯片，包括：若干阵列布置的柱状或台状硅岛。硅岛形状柱状或台状，包括但不限于方形柱、圆柱、类圆柱、多边形柱，圆锥台、倒锥台、方锥台等，考虑加工复杂程度，本实施例优选硅岛为方形柱，下文对于实施例的具体描述也参考方形柱的硅岛。而采用其他形状硅岛，其形成过程仅存在些许工艺差别。该硅岛阵列结构在硅芯片-焊球-PCB间因热膨胀系数差异导致的变形过程中提供变形的空间，能够提高焊球在热循环载荷条件下的热机械可靠性，从而提高其疲劳寿命。
应用倒装芯片封装结构，包括：具有前述硅岛阵列结构的倒置于一基板的集成电路芯片；连接前述基板及集成电路芯片的一组连接结构；各连接结构与所述硅岛阵列结构形成对应的阵列分布。
结合附图，单个连接结构包括设置于一硅岛表面的一第一焊垫、设置于基板表面的一第二焊垫及连接第一焊垫与第二焊垫的一连接件。
获得上述封装结构的倒装芯片封装方法，主要包括以下步骤：首先，将集成电路芯片的硅衬底划分为多个阵列分布的区域；然后，通过刻蚀在硅衬底表面各区域的边缘形成间隔槽，由此在衬底表面形成多个阵列分布的长方体硅岛；再然后，在各硅岛表面设置连接结构；最后，将设置连接结构的硅衬底与基板互连。
结合图7a～图7i，实现封装的具体工艺流程如下：
a)准备硅片或硅衬底，包括划片分离后的小片、4英寸晶圆、8英寸晶圆或者12英寸晶圆。
b)～d)在硅衬底表面进行刻蚀，刻蚀过程中在柱状或台状硅岛的周围形成间隔槽。刻蚀区域，即形成间隔槽的区域深度为5μm～50μm、宽度为5μm～50μm；刻蚀后，硅衬底表面呈长方体阵列状，这种衬底表面的长方体阵列状以下统称为硅岛阵列；所形成硅岛的具体尺寸、横向间距和纵向间距的数据变化范围较大，需根据具体的芯片尺寸和焊球尺寸进行选取。结合附图，本实施例中，间隔槽为方形槽，在其他实施例中，也可以选用梯形槽或燕尾槽形状的间隔槽。
e)～g)在刻蚀硅岛阵列后的硅衬底表面布线，包括焊球对应区域的金属层及互连线。
h)通过植球或者表面印刷等工艺将焊球转移到硅岛区域。
i)将带有焊球的硅衬底通过倒装键合工艺与PCB互连；至此，一种带有硅岛阵列的FCOB 封装形式完成。
为了验证硅岛阵列结构对焊球疲劳寿命的影响，本申请通过有限元仿真技术，对比有无硅岛阵列结构情况下的焊球疲劳寿命，验证了硅岛阵列结构提高焊球疲劳寿命的可行性。
有无硅岛阵列的FCOB封装形式的有限元模型如图2和图5所示。采用六面体网格划分技术，保证模型之间网格尺寸和网格划分种子密度等的一致性。模型具体尺寸：基板尺寸：长4mm、宽4mm、高0.8mm；芯片尺寸：长1.705mm、宽1.18mm、高0.498mm；焊球尺寸：焊球半径0.10mm、焊球高度0.16mm；焊球间距：沿芯片长度方向的间距为0.46mm，沿芯片宽度方向的间距为0.44mm；建模比例为1:1。
热循环载荷曲线(-55℃～125℃)如图8所示，其中，在最低温-55℃处保温10分钟，在最高温125℃处保温15分钟，升温过程时长1960秒，降温过程时长1080秒。
基于模型的对称性，采用四分之一模型计算，网格划分后的模型如图9及图10所示。
根据基于应变的Coffin-Manson模型预测有无硅岛阵列结构的FCOB封装形式中的焊球疲劳寿命，该模型如下式所示。
Figure PCTCN2017083463-appb-000001
其中，Nf是预估疲劳寿命；Δεp是平均非弹性应变，为平均等效蠕变应变和平均等效塑性应变之和；n是疲劳指数；C是材料系数。在仿真中，取n＝0.853，取C＝9.2，取焊球/PCB界面处的层单元的非弹性应变的平均值为Δεp。
以无硅岛阵列结构的模型为例，阐述计算过程。
取图11中下方标识a所指示区域的层单元，计算其平均等效蠕变应变(CEEQ)和平均等效塑性应变(PEEQ)，结果如表1和表2所示。
表1 平均等效蠕变应变
CEEQ Time CEEQ Time CEEQ Time CEEQ Time CEEQ Time
0 0 0.00147 1855.63 0.0102 4855.63 0.0168 7855.63 0.0224 10855.6
0 20 0.00148 2055.63 0.0115 5055.63 0.0180 8055.63 0.0224 11055.6
4.58E-07 40 0.00154 2255.63 0.0118 5255.63 0.0187 8255.63 0.0224 11255.6
2.96E-05 60 0.00192 2455.63 0.0118 5455.63 0.0189 8455.63 0.0226 11455.6
0.000125 90 0.00280 2655.63 0.0118 5655.63 0.0190 8655.63 0.0233 11655.6
0.000295 135 0.00390 2855.63 0.0118 5855.63 0.0190 8855.63 0.0242 11855.6
0.000558 202.5 0.00505 3055.63 0.0118 6055.63 0.0191 9055.63 0.0253 12055.6
0.000919 303.75 0.00621 3255.63 0.0118 6255.63 0.0196 9255.63 0.0264 12255.6
0.00127 455.625 0.00736 3455.63 0.0118 6455.63 0.0209 9455.63 0.0276 12455.6
0.00144 655.625 0.00842 3655.63 0.0118 6655.63 0.0221 9655.63 0.0287 12655.6
0.00147 855.625 0.00864 3855.63 0.0119 6855.63 0.0223 9855.63 0.0292 12855.6
0.00147 1055.63 0.00873 4055.63 0.0125 7055.63 0.0224 10055.6 0.0294 13055.6
0.00147 1255.63 0.00879 4255.63 0.0134 7255.63 0.0224 10255.6 0.0294 13255.6
0.00147 1455.63 0.00882 4455.63 0.0145 7455.63 0.0224 10455.6 0.0295 13455.6
0.00147 1655.63 0.00906 4655.63 0.0157 7655.63 0.0224 10655.6 0.0295 13620
表2 平均等效塑性应变
PEEQ Time PEEQ Time PEEQ Time PEEQ Time PEEQ Time
0 0 0.00651 1855.63 0.00674 4855.63 0.0109 7855.63 0.0147 10855.6
0 20 0.00651 2055.63 0.00677 5055.63 0.0109 8055.63 0.0147 11055.6
0 40 0.00656 2255.63 0.00814 5255.63 0.0109 8255.63 0.0147 11255.6
6.50E-07 60 0.00674 2455.63 0.00967 5455.63 0.0109 8455.63 0.0147 11455.6
2.54E-05 90 0.00674 2655.63 0.0109 5655.63 0.0109 8655.63 0.0147 11655.6
0.000192 135 0.00674 2855.63 0.0109 5855.63 0.0109 8855.63 0.0147 11855.6
0.000484 202.5 0.00674 3055.63 0.0109 6055.63 0.0109 9055.63 0.0147 12055.6
0.000951 303.75 0.00674 3255.63 0.0109 6255.63 0.0109 9255.63 0.0147 12255.6
0.00180 455.625 0.00674 3455.63 0.0109 6455.63 0.0109 9455.63 0.0147 12455.6
0.00322 655.625 0.00674 3655.63 0.0109 6655.63 0.0109 9655.63 0.0147 12655.6
0.00477 855.625 0.00674 3855.63 0.0109 6855.63 0.0123 9855.63 0.0147 12855.6
0.00632 1055.63 0.00674 4055.63 0.0109 7055.63 0.0138 10055.6 0.0147 13055.6
0.00651 1255.63 0.00674 4255.63 0.0109 7255.63 0.0147 10255.6 0.0147 13255.6
0.00651 1455.63 0.00674 4455.63 0.0109 7455.63 0.0147 10455.6 0.0147 13455.6
0.00651 1655.63 0.00674 4655.63 0.0109 7655.63 0.0147 10655.6 0.0147 13620
根据表1和表2，得到CEEQ和PEEQ随时间的变化曲线，如图12及图13所示。
将最后一步循环的CEEQ值和PEEQ值之和作为Δεp代入公式(1)，求得疲劳寿命Nf为 1977次循环。
同理，可以求得有硅岛阵列结构的FCOB封装形式中焊球的疲劳寿命为2649次循环。
综合以上仿真结果可以得出，硅岛阵列结构设计可以大大提高FCOB封装形式中焊球的疲劳寿命。
显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。

Claims (10)

  1. 一种提高焊球疲劳寿命的硅岛阵列结构，形成于倒装芯片封装结构中的集成电路芯片的有源面，包括：若干阵列布置的柱状或台状硅岛。
  2. 如权利要求1所述的提高焊球疲劳寿命的硅岛阵列结构，其特征在于，所述集成电路芯片包括硅衬底，所述柱状或台状硅岛通过刻蚀的方式形成于的硅衬底的表面。
  3. 如权利要求2所述的提高焊球疲劳寿命的硅岛阵列结构，其特征在于，所述刻蚀过程中在所述柱状或台状硅岛的周围形成间隔槽。
  4. 如权利要求3所述的提高焊球疲劳寿命的硅岛阵列结构，其特征在于，所述间隔槽为方形槽、梯形槽或燕尾槽。
  5. 如权利要求3所述的提高焊球疲劳寿命的硅岛阵列结构，其特征在于，所述间隔槽的宽度范围为5μm至50μm，深度范围为5μm至50μm。
  6. 一种倒装芯片封装结构，其特征在于，包括：
    具有如权利要求1至5任一项所述的硅岛阵列结构的集成电路芯片，其倒置于一基板；
    连接前述基板及集成电路芯片的一组连接结构；
    各连接结构与所述硅岛阵列结构形成对应的阵列分布。
  7. 如权利要求6所述的倒装芯片封装结构，其特征在于，单个所述连接结构包括设置于一硅岛表面的一第一焊垫、设置于基板表面的一第二焊垫及连接第一焊垫与第二焊垫的一连接件。
  8. 一种倒装芯片封装方法，包括以下步骤：
    1)将集成电路芯片的硅衬底划分为多个阵列分布的区域；
    2)通过刻蚀在硅衬底表面各区域的边缘形成间隔槽，由此在衬底表面形成多个阵列分布的硅岛结构；
    3)各硅岛结构表面设置连接结构；
    4)将设置连接结构的硅衬底与基板互连。
  9. 如权利要求8所述的倒装芯片封装方法，其特征在于，步骤3)中所述连接结构包括：形成于硅岛表面的金属层及互连线；通过植球或表面印刷的方式转移到硅岛表面的焊球。
  10. 如权利要求8所述的倒装芯片封装方法，其特征在于，步骤4)中设置连接结构的硅衬底通过倒装键合的方式与基板互联。
PCT/CN2017/083463 2017-04-21 2017-05-08 提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法 WO2018192016A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710267132.4A CN107275237A (zh) 2017-04-21 2017-04-21 提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法
CN2017102671324 2017-04-21

Publications (1)

Publication Number Publication Date
WO2018192016A1 true WO2018192016A1 (zh) 2018-10-25

Family

ID=60073811

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/083463 WO2018192016A1 (zh) 2017-04-21 2017-05-08 提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法

Country Status (2)

Country Link
CN (1) CN107275237A (zh)
WO (1) WO2018192016A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162013B (zh) * 2020-01-06 2021-08-24 亿芯微半导体科技(深圳)有限公司 一种半导体封装结构及一种半导体封装的制造方法
CN111146093B (zh) * 2020-01-06 2021-08-24 亿芯微半导体科技(深圳)有限公司 一种半导体堆叠封装结构及其制备方法
CN112309882B (zh) * 2020-09-21 2022-06-07 中国电子科技集团公司第十三研究所 三维集成器件焊接可靠性试验方法及监测系统
CN112464542A (zh) * 2020-12-22 2021-03-09 桂林电子科技大学 一种电子封装器件等效热导率的计算方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001094000A (ja) * 1999-09-21 2001-04-06 Fuji Photo Film Co Ltd 半導体装置
JP2006100534A (ja) * 2004-09-29 2006-04-13 Casio Micronics Co Ltd 半導体装置
JP2009071251A (ja) * 2007-09-18 2009-04-02 Yokogawa Electric Corp フリップチップｂｇａ基板
CN102569232A (zh) * 2012-01-13 2012-07-11 中国科学院上海微系统与信息技术研究所 圆片级芯片尺寸封装应力缓冲结构
CN205355041U (zh) * 2016-01-11 2016-06-29 华天科技（昆山）电子有限公司 带应力释放环的金属凸块结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001094000A (ja) * 1999-09-21 2001-04-06 Fuji Photo Film Co Ltd 半導体装置
JP2006100534A (ja) * 2004-09-29 2006-04-13 Casio Micronics Co Ltd 半導体装置
JP2009071251A (ja) * 2007-09-18 2009-04-02 Yokogawa Electric Corp フリップチップｂｇａ基板
CN102569232A (zh) * 2012-01-13 2012-07-11 中国科学院上海微系统与信息技术研究所 圆片级芯片尺寸封装应力缓冲结构
CN205355041U (zh) * 2016-01-11 2016-06-29 华天科技（昆山）电子有限公司 带应力释放环的金属凸块结构

Also Published As

Publication number Publication date
CN107275237A (zh) 2017-10-20

Similar Documents

Publication Publication Date Title
WO2018192016A1 (zh) 提高焊球疲劳寿命的硅岛阵列结构及倒装芯片封装方法
TWI450377B (zh) 具有經改善可靠度的直通矽晶穿孔
US10020267B2 (en) 2.5D electronic package
TWI581397B (zh) 晶片封裝、電腦系統、和電子裝置
US8736048B2 (en) Flexible heat sink with lateral compliance
US9385098B2 (en) Variable-size solder bump structures for integrated circuit packaging
KR101451495B1 (ko) 인터포저를 갖는 범프레스 빌드-업 층 패키지 디자인
US7989959B1 (en) Method of forming stacked-die integrated circuit
TWI503948B (zh) 高頻寬斜堆式晶片封裝
US10217712B2 (en) Semiconductor package and semiconductor process for manufacturing the same
US10224273B2 (en) Multi terminal capacitor within input output path of semiconductor package interconnect
US20200066680A1 (en) Integrated Circuit Chip Carrier with In-Plane Thermal Conductance Layer
TW200812038A (en) Semiconductor package and the method for fabricating thereof
US20160073493A1 (en) Stiffener ring for circuit board
JP5056085B2 (ja) 電子部品の実装構造
US10276535B2 (en) Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress
US10403578B2 (en) Electronic device package
US10770385B2 (en) Connected plane stiffener within integrated circuit chip carrier
JPWO2011021364A1 (ja) 半導体装置およびその製造方法
JP2009176885A (ja) 積層型半導体装置
CN112086408A (zh) 具有变化厚度的晶片级芯片规模封装
TWI525787B (zh) 晶片立體堆疊體之散熱封裝構造
US9478482B2 (en) Offset integrated circuit packaging interconnects
US7317254B2 (en) Semiconductor device mounting structure for reducing thermal stress and warpage
US10317296B2 (en) Method for estimating stress of electronic component

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17906509

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 13/02/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17906509

Country of ref document: EP

Kind code of ref document: A1