WO2018188388A1 - 阵列基板的制备方法、阵列基板、显示面板和显示装置 - Google Patents

阵列基板的制备方法、阵列基板、显示面板和显示装置 Download PDF

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WO2018188388A1
WO2018188388A1 PCT/CN2018/070781 CN2018070781W WO2018188388A1 WO 2018188388 A1 WO2018188388 A1 WO 2018188388A1 CN 2018070781 W CN2018070781 W CN 2018070781W WO 2018188388 A1 WO2018188388 A1 WO 2018188388A1
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Prior art keywords
layer
substrate
source
film layer
forming
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English (en)
French (fr)
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叶路路
姚磊
张凯
史大为
高娜娜
张盼盼
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US16/075,272 priority Critical patent/US11329075B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, a display panel, and a display device.
  • the display device generally comprises an array substrate and a color film substrate.
  • the interlayer dielectric layer as an insulating layer in the array substrate is located between the gate and the source and drain layers, and needs to be coated, activated, hydrogenated, mask exposed, and dry etched. And a stripping process to form the contact holes such that the source and drain lines can be connected to the polysilicon layer and transmit electrical signals.
  • an embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming an active layer on a substrate, the active layer facing the substrate or facing away from the substrate; A gate layer is formed on one side.
  • the preparation method further includes:
  • the interlayer dielectric layer includes a first film layer, a second film layer, which are sequentially stacked in a direction away from the substrate substrate, a third film layer and a fourth film layer;
  • the first film layer and the third film layer comprise silicon oxide
  • the second film layer and the fourth film layer comprise silicon nitride
  • the thickness of the fourth film layer is greater than or equal to 20 nanometers and less than or equal to 80 nanometers.
  • the first film layer, the second film layer, and the third film layer have a thickness of 80 nm or more and 1000 nm or less.
  • removing the fourth film layer in the portion of the interlayer dielectric layer that is not covered by the source and drain layers while forming the source and drain layers comprises:
  • the fourth film layer in the portion of the interlayer dielectric layer that is not covered by the source and drain layers is etched while forming the source and drain layers by an etching process.
  • the gate layer is located on a side of the active layer facing away from the substrate, and the manufacturing method further includes:
  • an embodiment of the present disclosure further provides an array substrate, including: a substrate, an active layer on the substrate, the active layer facing the substrate or facing away from a gate layer on one side of the substrate substrate, an interlayer dielectric layer on a side of the active layer away from the substrate substrate, and a source and a drain on a side of the interlayer dielectric layer facing away from the substrate substrate a pole layer, wherein the interlayer dielectric layer is provided with a via extending to the active layer, and the source and drain layers are connected to the active layer through the via.
  • the portion of the interlayer dielectric layer covered by the source and drain layers is directed to the source and drain directions along the active layer, and includes: a first film layer, a second film layer, and a third film which are sequentially stacked.
  • the layer and the fourth film layer, and the portion of the interlayer dielectric layer not covered by the source and the drain includes: a first film layer, a second film layer, and a third film layer which are sequentially stacked.
  • the first film layer and the third film layer comprise silicon oxide, and the second film layer comprises a silicon nitride layer.
  • the thickness of the fourth film layer is greater than or equal to 20 nanometers and less than or equal to 80 nanometers.
  • the first film layer, the second film layer, and the third film layer have a thickness of 80 nm or more and 1000 nm or less.
  • the gate layer is located on a side of the active layer facing away from the substrate, and the array substrate further includes:
  • the passivation layer being provided with a contact hole extending to the source and drain layers;
  • the second electrode being connected to the source and drain layers through the contact hole.
  • an embodiment of the present disclosure further provides a display panel including the above array substrate.
  • an embodiment of the present disclosure further provides a display device including the above display panel.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a gate layer formed during preparation of an array substrate according to an embodiment of the present disclosure
  • 3a, 3b, 3c and 3d are schematic structural diagrams showing a process of forming an interlayer dielectric layer according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of forming an interlayer dielectric layer during preparation and preparation of an array substrate according to an embodiment of the present disclosure
  • 5a, 5b, and 5c are schematic structural diagrams of source and drain formation processes according to embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of forming a source and a drain in an array substrate preparation process according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the interlayer dielectric layer is generally formed by a two-layer structure of silicon oxide SiO x and silicon nitride SiN x , but the interlayer dielectric layer of the two-layer structure has a phenomenon in which the large-view effect is severe, and silicon oxide is used.
  • the three-layer structure of SiO x , silicon nitride SiN x , and silicon oxide SiO x is easily affected by the shape of the underlying gate line and the stress difference of silicon nitride SiN x due to the upper silicon oxide SiO x at the edge of the gate line.
  • the source and drain forming materials may enter the crack of the interlayer dielectric layer, resulting in display panel failure.
  • the use of a three-layer structure in the interlayer dielectric layer due to the poor adhesion of silicon oxide to the photoresist, it is necessary to apply a photoresist adhesive before coating the photoresist, and the photoresist adhesive easily leads to the display panel. Multiple bright spots and dark spots have occurred.
  • an embodiment of the present disclosure provides a method for preparing an array substrate, including:
  • Step S101 A base substrate 1 is provided, an active layer 2 is formed on the base substrate 1, and a gate layer 7 is formed on a side of the active layer 2 facing the base substrate or facing away from the base substrate 1. Taking the gate layer on the side of the active layer facing away from the substrate, the structure formed after this step is shown in Fig. 2.
  • Other film layers such as the buffer layer 9, the light shielding layer 8, and the like may be disposed between the active layer 2 and the base substrate 1.
  • Step S102 forming an interlayer dielectric layer 3 on a side of the active layer 2 facing away from the base substrate 1.
  • the interlayer dielectric layer 3 formed in the direction away from the substrate 1 includes a first film layer 31, a second film layer 32, a third film layer 33, and a fourth film layer 34 which are sequentially stacked.
  • the first film layer 31 and the third film layer 33 are silicon oxide layers
  • the second film layer 32 and the fourth film layer 34 are silicon nitride layers, as shown in Fig. 3a.
  • each film can be formed by coating.
  • Step S103 forming a photoresist layer 4 on the interlayer dielectric layer 3; as shown in FIG. 3b.
  • Step S104 forming a via 5 extending from the interlayer dielectric layer 3 to the active layer 2.
  • the interlayer dielectric layer 3 coated with the photoresist layer 4 is exposed by a mask to remove a portion of the photoresist corresponding to the via 5 to be formed.
  • the interlayer dielectric layer 3 is etched to form the desired vias 5 and the excess photoresist is removed.
  • the specific shape of the mask used in the above mask exposure can be set as needed.
  • the applied photoresist may be a positive photoresist or a negative photoresist.
  • the structure of the array substrate formed after the completion of step S104 is as shown in FIG.
  • Step S105 Forming the source and drain layers 6 on the side of the interlayer dielectric layer 3 facing away from the substrate 1 .
  • the fourth film layer 34 in the portion of the interlayer dielectric layer 3 that is not covered by the source and drain layers 6 is removed while forming the source and drain layers 6, as shown in FIGS. 5a to 5c. Taking the gate layer on the side of the active layer facing away from the substrate, the array substrate formed after the step S105 is completed is shown in FIG. 6 .
  • the active layer may be a polysilicon layer or a single crystal silicon layer.
  • the formed fourth film layer 34 has a thickness of 20 nm or more and 80 nm or less. This makes it easy to etch and remove the fourth film layer 34 together when forming the source and the drain.
  • the thickness of the fourth film layer 34 may be 20 nm, 30 nm, 45 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc., and will not be repeated here.
  • the formed first film layer 31, second film layer 32, and third film layer 33 have a thickness of 80 nm or more and 1000 nm or less.
  • the thicknesses of the first film layer 31, the second film layer 32, and the third film layer 33 may be the same or different.
  • the thickness of the first film layer 31, the second film layer 32, and the third film layer 33 may be 80 nm, 150 nm, 300 nm, 500 nm, 600 nm, 850 nm, 900 nm, 1000 nm, etc. Repeat them one by one.
  • the thicknesses of the specific first film layer 31, the second film layer 32, and the third film layer 33 can be set according to actual product needs by those skilled in the art.
  • the fourth film layer 34 in the portion of the interlayer dielectric layer 3 not covered by the source and drain layers 6 is removed while forming the source and drain layers 6, including: forming a source by using an etching process At the same time as the drain layer 6, the fourth film layer 34 in the portion of the interlayer dielectric layer 3 that is not covered by the source and drain layers 6 is etched away.
  • a metal film is plated on the interlayer dielectric layer 3.
  • a photoresist is coated on the remaining region of the metal film, and the photoresist-coated metal film is etched to remove a region corresponding to the unnecessary metal film. While etching, some etching time is added as compared with the conventional process to remove the fourth film layer 34 covered by the region corresponding to the unnecessary metal film.
  • the photoresist on the remaining region of the metal film is finally peeled off to form the source and drain layers 6.
  • the gate layer is located on a side of the active layer facing away from the substrate, and the preparation method further comprises: forming the substrate 1 and the active layer 2, for example, by a coating process. A light shielding layer 8 therebetween, a buffer layer 9 between the light shielding layer 8 and the active layer 2, and a gate insulating layer 10 between the active layer 2 and the gate layer 7.
  • the preparation method further comprises: forming a planar layer 11 on the source and drain layers 6 by a plating process, for example; forming a first electrode 12 on the planar layer 11; for example, by a coating process a passivation layer 13 on the first electrode 12; forming a contact hole 14 extending from the passivation layer 13 to the source and drain layers 6 by, for example, mask exposure, etching, or the like; and forming on the passivation layer 13
  • the second electrode 15 is connected to the source and drain layers 6 through the contact hole 14.
  • the structure of the formed array substrate is as shown in FIGS. 7 and 8.
  • the first electrode may be a common electrode and the second electrode may be a pixel electrode.
  • the gate layer is located on a side of the active layer facing the substrate, and the method for preparing the array substrate further includes:
  • a flat layer on the source and drain layers is formed, for example, by a plating process.
  • Forming a passivation layer on the first electrode for example, by a coating process
  • a second electrode is formed on the passivation layer, wherein the second electrode is connected to the source and drain layers through the contact hole.
  • the first electrode is a common electrode and the second electrode is a pixel electrode.
  • a light shielding layer and a buffer layer may be formed between the gate layer and the base substrate.
  • the present disclosure also provides an array substrate comprising: a base substrate, an active layer on the base substrate, a gate layer on the side of the active layer facing the substrate substrate or facing away from the substrate substrate, and the active layer An interlayer dielectric layer on a side away from the substrate substrate and a source and a drain layer on a side of the interlayer dielectric layer facing away from the substrate substrate, wherein: the interlayer dielectric layer is provided with a via extending to the active layer, the source, The drain layer is connected to the active layer through the via hole;
  • the portion along the source layer and the drain direction along the active layer, and the portion of the interlayer dielectric layer covered by the source and drain layers includes: a first film layer, a second film layer, a third film layer, and a fourth film layer, which are sequentially stacked.
  • the portion of the dielectric layer not covered by the source and the drain includes: a first film layer, a second film layer, and a third film layer which are sequentially stacked, wherein the first film layer and the third film layer comprise silicon oxide, and the second film The layer and the fourth film layer comprise silicon nitride.
  • the array substrate includes a substrate substrate 1 and is active on the substrate substrate 1 .
  • the layer 2 is located on the gate layer 7 of the active layer 2 facing away from the substrate 1 , the interlayer dielectric layer 3 on the side of the gate layer 7 facing away from the substrate 1 , and the interlayer dielectric layer 3 facing away from the substrate Source and drain layers 6 on one side.
  • the interlayer dielectric layer 3 is provided with a via 5 extending to the active layer 2, and the source and drain layers 6 are connected to the active layer 2 through the via 5;
  • the portion of the interlayer dielectric layer 3 covered by the source and drain layers 6 along the active layer 2 is directed to the source and drain layers, and includes a first film layer 31, a second film layer 32, and a third film layer 33 which are sequentially stacked.
  • the portion of the interlayer dielectric layer 3 that is not covered by the source and the drain includes: a first film layer 31, a second film layer 32, and a third film layer 33 which are sequentially stacked, wherein the first film layer 31 and the third film layer 33 include Silicon oxide, and the second film layer 32 and the fourth film layer 34 comprise silicon nitride.
  • the array substrate provided by the present disclosure forms an interlayer dielectric layer between the gate and the source and drain by using four layers, so as to prevent the original three-layer film from being adhered to the top layer of silicon oxide and the photoresist. Poor properties require the problem of additional coating of the photoresist adhesive. This can save costs while reducing the occurrence of multiple bright and dark spots due to the application of photoresist adhesive.
  • the formed interlayer dielectric layer is located on a portion of the region where the source and the drain are not covered, and the fourth film layer (silicon nitride film layer) is etched away while forming a source and a drain through an etching process.
  • the region in which the interlayer dielectric layer 3 is not covered by the source and the drain is still a three-layer film layer (silicon oxide layer, silicon nitride layer, silicon oxide layer), so that the display device may not be in a big view.
  • the method for preparing the array substrate provided by the present disclosure can reduce the occurrence of multiple bright spots and dark spots on the display device without increasing the bias of the large-view character, thereby improving the display effect of the display device.
  • the active layer may be a polysilicon layer or a single crystal silicon layer.
  • the thickness of the fourth film layer 34 is greater than or equal to 20 nanometers and less than or equal to 80 nanometers. This makes it easy to etch and remove the fourth film layer 34 together when forming the source and the drain.
  • the thickness of the fourth film layer 34 may be 20 nm, 30 nm, 45 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc., and will not be repeated here.
  • the thickness of the first film layer 31, the second film layer 32, and the third film layer 33 is greater than or equal to 80 nanometers and less than or equal to 1000 nanometers.
  • the thicknesses of the first film layer 31, the second film layer 32, and the third film layer 33 may be the same or different.
  • the thickness of the first film layer 31, the second film layer 32, and the third film layer 33 may be 80 nm, 150 nm, 300 nm, 500 nm, 600 nm, 850 nm, 900 nm, 1000 nm, etc. Repeat them one by one.
  • the thicknesses of the specific first film layer 31, the second film layer 32, and the third film layer 33 can be set according to actual product needs by those skilled in the art.
  • the gate layer is located on a side of the active layer facing away from the substrate, and the array substrate further includes:
  • the second electrode 15 on the passivation layer 13 is connected to the source and drain layers 6 through the contact hole 14.
  • the gate layer is located on a side of the active layer facing the substrate, and the array substrate further includes:
  • the contact layer having a contact hole extending to the source and drain layers
  • a second electrode on the passivation layer the second electrode being connected to the source and drain layers through the contact hole.
  • a light shielding layer and a buffer layer may be provided between the gate layer and the base substrate.
  • the present disclosure also provides a display panel comprising the array substrate of any of the above.
  • the display panel provided by the present disclosure has a better display effect because the array substrate can reduce the occurrence of multiple bright spots and dark spots on the display device and improve the display effect of the display device.
  • the display panel may be a touch panel, and the touch panel may be an in-cell touch panel.
  • the touch electrodes in the in-cell touch panel can be formed in synchronization with the source and drain electrodes.
  • the present disclosure also provides a display device including the above display panel.
  • the display device has a better display effect.
  • the display device provided by the embodiment of the present disclosure may be any one of a mobile phone, a tablet computer, an electronic paper, and an electronic photo frame.

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Abstract

一种阵列基板的制备方法、阵列基板、显示面板和显示装置。该制备方法包括在衬底基板（1）上形成有源层（2），在有源层（2）朝向衬底基板（1）或背离衬底基板（1）的一侧形成栅极层（7）；在有源层（2）背离衬底基板（1）的一侧形成层间介质层（3），该层间介质层（3）包括沿远离衬底基板（1）方向依次堆叠的第一膜层（31）、第二膜层（32）、第三膜层（33）以及第四膜层（34）；形成位于层间介质层（3）上的光刻胶层（4）；形成从层间介质层（3）延伸至有源层（2）的过孔（5）；以及形成位于层间介质层（3）背离衬底基板（1）一侧的源、漏极层（6），其中在形成源、漏极层（6）的同时去除层间介质层（3）中未被源、漏极层（6）覆盖的部分内的第四膜层（34）。

Description

阵列基板的制备方法、阵列基板、显示面板和显示装置
相关专利申请
本申请主张于2017年4月12日提交的中国专利申请No.201710236527.8的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示器技术领域，尤其涉及一种阵列基板的制备方法、阵列基板、显示面板和显示装置。
背景技术
显示装置一般包括阵列基板和彩膜基板，阵列基板内作为绝缘作用的层间介质层位于栅极与源、漏极层之间，需要经镀膜、活化、氢化、掩模曝光、干法刻蚀以及剥离工序以形成接触孔，使得源、漏极线可以与多晶硅层相连并传输电信号。
发明内容
在一方面，本公开实施例提供了一种阵列基板的制备方法，包括：在衬底基板上形成有源层，在所述有源层朝向所述衬底基板或背离所述衬底基板的一侧形成栅极层。该制备方法还包括：
在所述有源层背离所述衬底基板的一侧形成层间介质层，其中所述层间介质层包括沿远离所述衬底基板方向依次层叠的第一膜层、第二膜层、第三膜层以及第四膜层；
形成位于所述层间介质层上的光刻胶层；
形成从所述层间介质层延伸至所述有源层的过孔；以及
形成位于所述层间介质层背离所述衬底基板一侧的源、漏极层，其中在形成所述源、漏极层的同时去除所述层间介质层中未被所述源、漏极层覆盖的部分内的第四膜层。
在一些可选的实施方式中，所述第一膜层和所述第三膜层包括氧化硅，并且所述第二膜层和所述第四膜层包括氮化硅。
在一些可选的实施方式中，所述第四膜层的厚度大于等于20纳米且小于等于80纳米。
在一些可选的实施方式中，所述第一膜层、所述第二膜层以及所述第三膜层的厚度大于等于80纳米且小于等于1000纳米。
在一些可选的实施方式中，在形成所述源、漏极层的同时去除所述层间介质层中未被所述源、漏极层覆盖的部分内的第四膜层，包括：
在采用刻蚀工艺形成源、漏极层的同时、刻蚀掉所述层间介质层中未被所述源、漏极层覆盖的部分内的第四膜层。
在一些可选的实施方式中，所述栅极层位于所述有源层背离所述衬底基板的一侧，并且所述制备方法还包括：
形成位于所述衬底基板与所述有源层之间的遮光层；
形成位于所述遮光层和所述有源层之间的缓冲层；
形成位于所述有源层和所述栅极层之间的栅极绝缘层；
形成位于所述源、漏极层上的平坦层；
形成位于所述平坦层上的第一电极；
形成位于所述第一电极上的钝化层；
形成从所述钝化层延伸至源、漏极层的接触孔；以及
形成位于所述钝化层上的第二电极，其中所述第二电极通过所述接触孔与所述源、漏极层连接。
在另一方面，本公开实施例还提供了一种阵列基板，包括：衬底基板，位于所述衬底基板上的有源层，位于所述有源层朝向所述衬底基板或背离所述衬底基板一侧的栅极层，位于所述有源层远离所述衬底基板一侧的层间介质层以及位于所述层间介质层背离所述衬底基板一侧的源、漏极层，其中所述层间介质层上设有延伸至所述有源层的过孔，并且所述源、漏极层通过所述过孔与所述有源层连接。沿所述有源层指向所述源、漏极方向，所述层间介质层被所述源、漏极层覆盖的部分包括：依次层叠的第一膜层、第二膜层、第三膜层以及第四膜层，并且所述层间介质层未被所述源、漏极覆盖的部分包括：依次层叠的第一膜层、第二膜层、第三膜层。
在一些可选的实施方式中，所述第一膜层和所述第三膜层包括氧化硅，并且所述第二膜层所述第四膜层包括氮化硅。
在一些可选的实施方式中，所述第四膜层的厚度大于等于20纳米且小于等于80纳米。
在一些可选的实施方式中，所述第一膜层、所述第二膜层以及所 述第三膜层的厚度大于等于80纳米且小于等于1000纳米。
在一些可选的实施方式中，所述栅极层位于所述有源层背离所述衬底基板的一侧，并且所述阵列基板还包括：
位于所述衬底基板与所述有源层之间的遮光层；
位于所述遮光层和所述有源层之间的缓冲层；
位于所述有源层和所述栅极层之间的栅极绝缘层；
位于所述源、漏极层上的平坦层；
位于所述平坦层上的第一电极；
位于所述第一电极上的钝化层，所述钝化层上设有延伸至源、漏极层的接触孔；以及
位于所述钝化层上的第二电极，所述第二电极通过所述接触孔与所述源、漏极层连接。
在又一方面，本公开实施例还提供了一种显示面板，包括上述的阵列基板。
在再一方面，本公开实施例还提供了一种显示装置，包括上述的显示面板。
附图说明
图1为本公开实施例提供的阵列基板的制备方法流程图；
图2为本公开实施例提供的阵列基板的制备过程中形成栅极层后的结构示意图；
图3a、3b、3c和3d为本公开实施例提供的层间介质层的形成过程结构示意图；
图4为本公开实施例提供的阵列基板制备制备过程中形成层间介质层后的结构示意图；
图5a、5b和5c为本公开实施例提供的源、漏极形成过程结构示意图；
图6为本公开实施例提供的阵列基板制备制备过程中形成源、漏极后的结构示意图；
图7为本公开实施例提供的阵列基板的一种结构示意图；以及
图8为本公开实施例提供的阵列基板的另一种结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护范围。
附图标记：
1-衬底基板                        2-有源层
3-层间介质层                      31-第一膜层
32-第二膜层                       33-第三膜层
34-第四膜层                       4-光刻胶层
5-过孔                            6-源、漏极层
7-栅极层                          8-遮光层
9-缓冲层                          10-栅极绝缘层
11-平坦层                         12-第一电极
13-钝化层                         14-接触孔
15-第二电极                       16-触控电极。
在低温多晶硅技术工艺中，层间介质层一般采用氧化硅SiO x和氮化硅SiN x两层结构形成，但是两层结构的层间介质层存在大视角色偏严重的现象，而使用氧化硅SiO x、氮化硅SiN x、氧化硅SiO x三层结构，又容易因上层的氧化硅SiO x位于栅极线边缘的部分受底层栅极线的形状、氮化硅SiN x所受应力差异等原因产生断裂，若层间介质层存在裂纹，在层间介质层上形成源、漏极时，源、漏极的形成材料会进入层间介质层的裂纹中，导致显示面板显示不良，且采用三层结构在层间介质层，由于氧化硅对光刻胶的吸附性较差，故需要在涂布光刻胶前涂布光刻胶粘合剂，而光刻胶粘合剂容易导致显示面板多个亮点和暗点不良现象的发生。
如图1所示，本公开实施例提供了一种阵列基板的制备方法，包括：
步骤S101：提供一衬底基板1，在衬底基板1上形成有源层2，在有源层2朝向衬底基板或背离衬底基板1的一侧形成栅极层7。以栅极层位于有源层背离衬底基板的一侧为例，此步骤后形成的结构如图2 所示。有源层2与衬底基板1之间还可以设置其它膜层，例如缓冲层9、遮光层8等。
步骤S102：在有源层2背离衬底基板1的一侧形成层间介质层3。沿远离衬底基板1方向，所形成的层间介质层3包括依次层叠的第一膜层31、第二膜层32、第三膜层33以及第四膜层34。第一膜层31和第三膜层33为氧化硅层，第二膜层32和第四膜层34为氮化硅层，如图3a所示。例如，每层膜可以采用镀膜的方式形成。
步骤S103：形成位于层间介质层3上的光刻胶层4；如图3b所示。
步骤S104：形成从层间介质层3延伸至有源层2的过孔5。如图3c所示，对涂覆有光刻胶层4的层间介质层3利用掩模进行曝光，去掉待形成的过孔5对应的部分光刻胶。如图3d所示，对层间介质层3进行刻蚀以形成所需的过孔5，并去除多余的光刻胶。上述掩模曝光中所用的掩模的具体形状可以根据需要设定。所涂覆的光刻胶可以为正性光刻胶也可以为负性光刻胶。步骤S104完成后形成的阵列基板的结构如图4所示。
步骤S105：形成位于层间介质层3背离衬底基板1一侧的源、漏极层6。在形成源、漏极层6的同时去除层间介质层3中未被源、漏极层6覆盖的部分内的第四膜层34，如图5a～图5c所示。以栅极层位于有源层背离衬底基板的一侧为例，步骤S105完成后形成的阵列基板如图6所示。
上述有源层可以为多晶硅层，也可以为单晶硅层。
可选的，形成的第四膜层34的厚度大于等于20纳米且小于等于80纳米。这样可以在形成源、漏极时便于将第四膜层34一起刻蚀去除。例如：第四膜层34的厚度可以为20纳米、30纳米、45纳米、50纳米、60纳米、70纳米、80纳米等，这里就不再一一赘述。
可选的，形成的第一膜层31、第二膜层32以及第三膜层33的厚度大于等于80纳米且小于等于1000纳米。第一膜层31、第二膜层32以及第三膜层33的厚度可以相同也可以不同。上述第一膜层31、第二膜层32、第三膜层33的厚度可以为80纳米、150纳米、300纳米、500纳米、600纳米、850纳米、900纳米、1000纳米等，这里就不再一一赘述。具体的第一膜层31、第二膜层32以及第三膜层33的厚度本领域普通技术人员可以根据实际产品需要设定。
上述步骤S106中，在形成源、漏极层6的同时去除层间介质层3中未被源、漏极层6覆盖的部分内的第四膜层34，包括：在采用刻蚀工艺形成源、漏极层6的同时、刻蚀掉层间介质层3中未被源、漏极层6覆盖的部分内的第四膜层34。
如图5a所示，在层间介质层3上镀金属膜。如图5b所示，在金属膜的保留区域上涂布光刻胶，并对涂布有光刻胶的金属膜进行刻蚀去除不需要的金属膜对应的区域。在刻蚀的同时，与常用工艺相比增加一些刻蚀时间以将不需要的金属膜对应的区域覆盖的第四膜层34去除。如图5c所示，最后将金属膜的保留区域上的光刻胶剥离，形成源、漏极层6。
本公开提供的一种具体实施方式中，栅极层位于有源层背离衬底基板的一侧，并且该制备方法还包括：例如通过镀膜工艺，形成位于衬底基板1与有源层2之间的遮光层8、位于遮光层8和有源层2之间的缓冲层9、以及位于有源层2和栅极层7之间的栅极绝缘层10。
在一实施例中，该制备方法还包括：例如通过镀膜工艺，形成位于源、漏极层6上的平坦层11；形成位于平坦层11上的第一电极12；例如通过镀膜工艺，形成位于第一电极12上的钝化层13；例如通过掩膜板曝光、刻蚀等工艺，形成从钝化层13延伸至源、漏极层6的接触孔14；以及形成位于钝化层13上的第二电极15，其中第二电极15通过接触孔14与源、漏极层6连接。形成的阵列基板的结构如图7和图8所示。
例如，上述第一电极可以为公共电极，并且第二电极为像素电极。
本公开提供的另一种具体实施方式中，栅极层位于有源层朝向衬底基板的一侧，并且阵列基板的制备方法还包括：
例如通过镀膜工艺，形成位于有源层和栅极层之间的栅极绝缘层；
例如通过镀膜工艺，形成位于源、漏极层上的平坦层。
形成位于平坦层上的第一电极；
例如通过镀膜工艺，形成位于第一电极上的钝化层；
例如通过掩膜板曝光、刻蚀等工艺，形成从钝化层延伸至源、漏极层的接触孔；以及
形成位于钝化层上的第二电极，其中该第二电极通过接触孔与源、漏极层连接。
例如，上述第一电极为公共电极，并且第二电极为像素电极。在此种结构的阵列基板中，也可以在栅极层和衬底基板之间形成遮光层和缓冲层。
本公开还提供了一种阵列基板，包括：衬底基板，位于衬底基板上的有源层，位于有源层朝向衬底基板或背离衬底基板一侧的栅极层，位于有源层远离衬底基板一侧的层间介质层以及位于层间介质层背离衬底基板一侧的源、漏极层，其中：层间介质层上设有延伸至有源层的过孔，源、漏极层通过过孔与有源层连接；
沿有源层指向源、漏极方向，层间介质层被源、漏极层覆盖的部分包括：依次层叠的第一膜层、第二膜层、第三膜层以及第四膜层，层间介质层未被源、漏极覆盖的部分包括：依次层叠的第一膜层、第二膜层、第三膜层，其中第一膜层和第三膜层包括氧化硅，并且第二膜层和第四膜层包括氮化硅。
以栅极层位于有源层背离衬底基板一侧为例，如图5c以及图7所示，本公开还提供的阵列基板，包括：衬底基板1，位于衬底基板1上的有源层2，位于有源层2背离衬底基板1一侧的栅极层7，位于栅极层7背离衬底基板1一侧的层间介质层3以及位于层间介质层3背离衬底基板1一侧的源、漏极层6。层间介质层3上设有延伸至有源层2的过孔5，源、漏极层6通过过孔5与有源层2连接；
沿有源层2指向源、漏极方向，层间介质层3被源、漏极层6覆盖的部分包括：依次层叠的第一膜层31、第二膜层32、第三膜层33以及第四膜层34。层间介质层3未被源、漏极覆盖的部分包括：依次层叠的第一膜层31、第二膜层32、第三膜层33，其中第一膜层31和第三膜层33包括氧化硅，并且第二膜层32和第四膜层34包括氮化硅。
本公开提供的阵列基板，将位于栅极和源漏极之间的层间介质层采用四层膜层形成，这样可以避免原有的三层膜层位于顶层的氧化硅与光刻胶粘附性差，需要额外涂布光刻胶粘合剂的问题。这可以节省成本，同时可以减少由于涂布光刻胶粘合剂产生的多个亮点和暗点现象的发生。此外，形成的层间介质层位于源、漏极未覆盖的区域的部分上的第四膜层(氮化硅膜层)在经过刻蚀工艺形成源、漏极的同时被刻蚀掉，可以使得层间介质层3未被源、漏极覆盖的区域仍为三层膜层(氧化硅层、氮化硅层、氧化硅层)，这样可以不引起显示装置 大视角色差。
故，本公开提供的阵列基板的制备方法，可以在不引起大视角色偏的基础上，减少显示装置多个亮点和暗点现象的发生，提高显示装置的显示效果。
上述有源层可以为多晶硅层也可以为单晶硅层。
可选的，第四膜层34的厚度大于等于20纳米且小于等于80纳米。这样可以在形成源、漏极时便于将第四膜层34一起刻蚀去除。例如：第四膜层34的厚度可以为20纳米、30纳米、45纳米、50纳米、60纳米、70纳米、80纳米等，这里就不再一一赘述。
可选的，第一膜层31、第二膜层32以及第三膜层33的厚度大于等于80纳米且小于等于1000纳米。第一膜层31、第二膜层32以及第三膜层33的厚度可以相同也可以不同。上述第一膜层31、第二膜层32、第三膜层33的厚度可以为80纳米、150纳米、300纳米、500纳米、600纳米、850纳米、900纳米、1000纳米等，这里就不再一一赘述。具体的第一膜层31、第二膜层32以及第三膜层33的厚度本领域普通技术人员可以根据实际产品需要设定。
如图7所示，一种具体实施方式中，栅极层位于有源层背离衬底基板的一侧，并且阵列基板还包括：
位于衬底基板1与有源层2之间的遮光层8；
位于遮光层8和有源层2之间的缓冲层9；
位于有源层2和栅极层7之间的栅极绝缘层10；
位于源、漏极层6上的平坦层11；
位于平坦层11上的第一电极12；
位于第一电极12上的钝化层13，钝化层13上设有延伸至源、漏极层6的接触孔14；以及
位于钝化层13上的第二电极15，第二电极15通过接触孔14与源、漏极层6连接。
另一种具体实施方式中，栅极层位于有源层朝向衬底基板的一侧，阵列基板还包括：
位于有源层和栅极层之间的栅极绝缘层；
位于源、漏极层上的平坦层；
位于平坦层上的第一电极；
位于第一电极上的钝化层，钝化层上设有延伸至源、漏极层的接触孔；以及
位于钝化层上的第二电极，第二电极通过接触孔与源、漏极层连接。此种结构的阵列基板中，也可以在栅极层和衬底基板之间设置遮光层和缓冲层。
本公开还提供了一种显示面板，包括上述任一项所述的阵列基板。由于上述阵列基板可以在不引起大视角色偏的基础上，减少显示装置多个亮点和暗点现象的发生，提高显示装置的显示效果，故本公开提供的显示面板具有较好的显示效果。
上述显示面板可以为触控面板，该触控面板可以为内嵌式触控面板。上述内嵌式触控面板内的触控电极可以与源、漏电极同步形成。
本公开还提供了一种显示装置，包括上述显示面板。该显示装置具有较好的显示效果。
本公开实施例提供的显示装置可以为手机、平板电脑、电子纸、电子相框中的任意一种。
显然，本领域普通技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种阵列基板的制备方法，包括：在衬底基板上形成有源层，并且在所述有源层朝向所述衬底基板或背离所述衬底基板的一侧形成栅极层，其中该制备方法还包括：
    在所述有源层背离所述衬底基板的一侧形成层间介质层，其中所述层间介质层包括沿远离所述衬底基板方向依次层叠的第一膜层、第二膜层、第三膜层以及第四膜层；
    形成位于所述层间介质层上的光刻胶层；
    形成从所述层间介质层延伸至所述有源层的过孔；以及
    形成位于所述层间介质层背离所述衬底基板一侧的源、漏极层，其中在形成所述源、漏极层的同时去除所述层间介质层中未被所述源、漏极层覆盖的部分内的第四膜层。
  2. 如权利要求1所述的制备方法，其中所述第一膜层和所述第三膜层包括氧化硅，并且所述第二膜层和所述第四膜层包括氮化硅。
  3. 如权利要求1所述的制备方法，其中所述第四膜层的厚度大于等于20纳米且小于等于80纳米。
  4. 如权利要求1所述的制备方法，其中所述第一膜层、所述第二膜层以及所述第三膜层的厚度大于等于80纳米且小于等于1000纳米。
  5. 如权利要求1所述的制备方法，其中在形成所述源、漏极层的同时去除所述层间介质层中未被所述源、漏极层覆盖的部分内的第四膜层，包括：
    在采用刻蚀工艺形成源、漏极层的同时、刻蚀掉所述层间介质层中未被所述源、漏极层覆盖的部分内的第四膜层。
  6. 如权利要求1～5中任一项所述的制备方法，其中所述栅极层位于所述有源层背离所述衬底基板的一侧，并且所述制备方法还包括：
    形成位于所述衬底基板与所述有源层之间的遮光层；
    形成位于所述遮光层和所述有源层之间的缓冲层；
    形成位于所述有源层和所述栅极层之间的栅极绝缘层；
    形成位于所述源、漏极层上的平坦层；
    形成位于所述平坦层上的第一电极；
    形成位于所述第一电极上的钝化层；
    形成从所述钝化层延伸至源、漏极层的接触孔；以及
    形成位于所述钝化层上的第二电极，其中所述第二电极通过所述接触孔与所述源、漏极层连接。
  7. 一种阵列基板，包括：衬底基板，位于所述衬底基板上的有源层，位于所述有源层朝向所述衬底基板或背离所述衬底基板一侧的栅极层，位于所述有源层远离所述衬底基板一侧的层间介质层以及位于所述层间介质层背离所述衬底基板一侧的源、漏极层，其中所述层间介质层上设有延伸至所述有源层的过孔，并且所述源、漏极层通过所述过孔与所述有源层连接；
    其中沿所述有源层指向所述源、漏极方向，所述层间介质层被所述源、漏极层覆盖的部分包括：依次层叠的第一膜层、第二膜层、第三膜层以及第四膜层，并且所述层间介质层未被所述源、漏极覆盖的部分包括：依次层叠的第一膜层、第二膜层、第三膜层。
  8. 如权利要求7所示的阵列基板，其中所述第一膜层和所述第三膜层包括氧化硅，并且所述第二膜层所述第四膜层包括氮化硅。
  9. 如权利要求7所示的阵列基板，其中所述第四膜层的厚度大于等于20纳米且小于等于80纳米。
  10. 如权利要求7所述的阵列基板，其中所述第一膜层、所述第二膜层以及所述第三膜层的厚度大于等于80纳米且小于等于1000纳米。
  11. 如权利要求7～10中任一项所述的阵列基板，其中所述栅极层位于所述有源层背离所述衬底基板的一侧，并且所述阵列基板还包括：
    位于所述衬底基板与所述有源层之间的遮光层；
    位于所述遮光层和所述有源层之间的缓冲层；
    位于所述有源层和所述栅极层之间的栅极绝缘层；
    位于所述源、漏极层上的平坦层；
    位于所述平坦层上的第一电极；
    位于所述第一电极上的钝化层，所述钝化层上设有延伸至源、漏极层的接触孔；以及
    位于所述钝化层上的第二电极，所述第二电极通过所述接触孔与所述源、漏极层连接。
  12. 一种显示面板，包括如权利要求1～11中任一项所述的阵列基板。
  13. 一种显示装置，包括如权利要求12所述的显示面板。
PCT/CN2018/070781 2017-04-12 2018-01-04 阵列基板的制备方法、阵列基板、显示面板和显示装置 Ceased WO2018188388A1 (zh)

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