WO2018171015A1 - 栅极驱动电路 - Google Patents

栅极驱动电路 Download PDF

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Publication number
WO2018171015A1
WO2018171015A1 PCT/CN2017/083983 CN2017083983W WO2018171015A1 WO 2018171015 A1 WO2018171015 A1 WO 2018171015A1 CN 2017083983 W CN2017083983 W CN 2017083983W WO 2018171015 A1 WO2018171015 A1 WO 2018171015A1
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Prior art keywords
coupled
transistor
pole
output
module
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Ceased
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PCT/CN2017/083983
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English (en)
French (fr)
Inventor
张盛东
马一华
廖聪维
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Priority to US16/496,427 priority Critical patent/US11270624B2/en
Publication of WO2018171015A1 publication Critical patent/WO2018171015A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of active matrix display technology, and more particularly to a gate driving circuit.
  • TFT Thin Film Transistor
  • TFT technologies for implementing integrated gate drive circuits are mainly classified into three types: hydrogenated amorphous silicon TFTs, low temperature polysilicon TFTs, and oxide TFTs.
  • Hydrogenated amorphous silicon TFT is the mainstream TFT technology in the display field, but its mobility is low, and it is mainly used in low resolution displays.
  • Low temperature polysilicon TFT is an emerging TFT technology with high mobility but poor uniformity.
  • oxide TFTs are considered as next-generation TFT technology, with high mobility and uniformity, and the manufacturing process is compatible with amorphous silicon, suitable for high-resolution displays. .
  • the development of these TFT technologies has also pushed the display closer to the realization of the SOP target.
  • the present application provides a switched capacitor voltage bootstrap circuit as a high stability, low power shift register unit, and utilizes a shift register unit including such a unit to implement a gate drive circuit and a display design.
  • the present application provides a shift register unit circuit including an input memory module configured to receive an input signal at an input and store the input signal; a memory extraction module configured to be at least under the influence of the first clock signal The input storage module extracts the input signal; an output driving module configured to transmit the input signal to an output under control of the storage extraction module; and a pull-down and maintenance module configured to be after outputting Will The voltage at the output pulls down to a low level and maintains the output voltage low before the output driver module receives the next input signal.
  • the input storage module includes: the storage capacitor is configured to store the input signal, the first end of the storage capacitor is coupled to the input end through a first switch, and the second end is coupled to the second end through a second switch Level-coupled, the first switch and the second switch are turned on or off under the control of the input signal;
  • the output driving module includes a first transistor, and the first transistor includes a high-level coupling a first pole, and a second pole coupled to the output terminal and the pull-down and sustain module, and a third pole coupled to the memory extraction module;
  • the memory extraction module includes, coupled to a third switch between the first end of the storage capacitor and the third electrode of the first transistor, and a fourth switch coupled between the second end of the storage capacitor and the output end, wherein the first switch The clock signal affects the switching states of the third and fourth switches.
  • the output driving module further includes a second transistor, the first electrode of the second transistor is coupled to the high level, the second electrode is coupled to the second output, and the third electrode is coupled to the first a third pole of a transistor, wherein the size of the first transistor is greater than the size of the second transistor.
  • the first switch is a third transistor including a first pole and a third pole coupled to the input terminal, and a second pole coupled to the first end of the storage capacitor;
  • the second switch Is a fourth transistor comprising a first pole coupled to the second end of the storage capacitor, a second pole coupled to the low level, and a third pole coupled to the input terminal when the input signal is high At the level, the first and second switches are turned on and the storage capacitor is charged.
  • the third switch is a fifth transistor, including a first pole coupled to the first end of the storage capacitor, a second pole coupled to the third pole of the first transistor, and coupled to the first a third pole of the clock signal input;
  • the fourth switch is a sixth transistor, including a first pole coupled to the second end of the storage capacitor, coupled to the second pole of the output, and coupled to the a third pole of the clock signal input; the first clock signal reaches a high level after the storage capacitor is charged, and the third and fourth switches are turned on.
  • the memory extraction module further includes a seventh transistor and an eighth transistor, wherein the first and third electrodes of the seventh transistor are coupled to the first clock signal input end, and the second electrode is coupled to the first a third transistor of the fifth transistor and the sixth transistor, the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, the second electrode is coupled to the low level, and the third electrode is coupled to the discharge control signal
  • the input is such that the third and fourth switches are in a closed state during charging of the storage capacitor.
  • the pull-down and sustain module includes a ninth transistor and a tenth transistor, wherein the ninth transistor includes a first pole coupled to the third pole of the first transistor, coupled to a second low level Pole, and coupled to pull down and Maintaining a third pole of the control signal input, the tenth transistor includes a first pole coupled to the output terminal, a second terminal coupled to the low level, and a third coupled to the pull-down and sustain control signal input terminal pole.
  • the pull-down and maintenance module includes a pull-down sub-module and a maintenance sub-module, wherein the pull-down sub-module includes the pull-down sub-module including eleventh and twelfth transistors, and the second poles of the two transistors are coupled Receiving a low level, the third pole is coupled to a pull-down control signal input terminal, wherein a first pole of the eleventh transistor is coupled to the third pole of the first transistor, and the first pole of the twelfth transistor a second pole coupled to the first transistor and the output terminal; the sustaining sub-module includes fourteenth and fifteenth transistors, the second poles of the two transistors are coupled to a low level, a third pole The first pole of the fourteenth transistor is coupled to the third pole of the first transistor, and the first pole of the fifteenth transistor is coupled to the second pole of the first transistor and The output.
  • the pull-down and sustain module includes a pull-down sub-module and a sustain sub-module;
  • the pull-down sub-module includes eleventh, twelfth, and thirteenth transistors, and the second poles of the three transistors are coupled to a low a third pole is coupled to a pull-down control signal input terminal, wherein a first pole of the eleventh transistor is coupled to the third transistor of the first transistor and the second transistor, and the first of the twelfth transistor a pole is coupled to the second pole of the first transistor and the output end, the first pole of the thirteenth transistor is coupled to the second pole of the second transistor and the second output;
  • the maintaining submodule includes 14.
  • the fifteenth and sixteenth transistors, the second poles of the three transistors are coupled to a low level, and the third pole is coupled to the second clock signal input end, wherein the first of the fourteenth transistors The pole is coupled to the third pole of the first transistor and the second transistor, the first pole of the fifteenth transistor is coupled to the second pole of the first transistor and the output end, and the first pole of the sixteenth transistor is coupled To the second pole of the second transistor and the second output.
  • the present application also provides a gate drive circuit comprising a shift register, the shift register comprising M cascaded cells, wherein the cells of the first to M-1 stages comprise any of the preceding claims
  • the circuit wherein the input end of the Nth stage is coupled to the second output end of the N-1th stage, and the pull-down control signal end of the Nth stage is coupled to the second output end of the N+1th stage, the Nth stage
  • the discharge control signal input end is coupled to the second output of the N-2th stage, wherein M is a positive integer greater than 4, and N is a positive integer less than or equal to M-1 but not less than 3;
  • the first stage shift register The input end of the unit receives the initial input signal, the discharge control signal input end of the first stage receives the initial discharge control signal, and the pull-down control signal input end of the first stage is coupled to the second output end of the second stage; and the second The discharge control signal input of the stage receives the initial input signal, the input of the second stage is coupled to the second output of the first stage
  • the output of the Mth stage shift register unit is only configured to provide a pull down control signal to the M-1th stage unit.
  • the present application also provides a display comprising a pixel matrix, a data driving circuit coupled to the pixel matrix, and a gate driving circuit coupled to the pixel matrix as described above.
  • the display is a TFT display
  • the gate driving circuit is formed on the same substrate as the pixel matrix.
  • the present application also provides a method of generating a display gate drive signal, comprising: performing, by each of the shift registers in a gate drive module of the display, each of the shift register units including an input memory module, a storage extraction module, an output driving module, and a pull-down maintaining module; the input storage module receives and stores the input signal; the storage extraction module transmits the stored input signal to the output driving module at least under the influence of the clock signal; and the output driving module is in the storage The input signal is transmitted to the output under the control of the extraction module; the pull-down and maintenance module pulls the voltage of the output to a low level after the output ends and before the output drive module receives the next input signal The output voltage is maintained at a low level.
  • the gate driving circuit and the display introduced in the present application avoid the direct connection of the output transistor for driving the load to the clock signal, thereby suppressing the clock feedthrough effect and the dynamic power consumption, thereby greatly reducing the power consumption and reducing the circuit. Voltage fluctuations in the internal nodes during the level maintenance phase; on the other hand, low-power design goals can be achieved with a low level, reducing wiring complexity and overall circuit area.
  • 1 is a circuit diagram of a shift register unit according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram showing the operation timing of the circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a shift register unit according to an embodiment of the present application.
  • FIG. 4 is a circuit diagram of a shift register unit according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram showing the operation timing of the circuit shown in FIG. 3 or FIG. 4;
  • FIG. 6 is a schematic diagram of a gate driving circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a gate driving circuit according to another embodiment of the present application.
  • FIG. 8 is a schematic diagram showing the operation timing of the gate driving circuit shown in FIG. 6;
  • Figure 9 is a schematic illustration of a display in accordance with one embodiment of the present application.
  • FIG. 10 is a flow chart of a method of generating a gate drive signal in accordance with an embodiment of the present application.
  • GOA Gate driver On Array
  • This structure obtains a large overdrive voltage of an output transistor for driving a load by bootstrapping the gate voltage.
  • various institutions have conducted extensive research on the basis of this structure. Since current mainstream TFT technology only provides N-type transistors, voltage bootstrap technology is required when charging an output node such as a GOA structure.
  • the current structure of the voltage bootstrap circuit faces dynamic power consumption and clock feedthrough problems, which are particularly affected by the Etch Stop Layer (ESL) process.
  • ESL Etch Stop Layer
  • the first pole of the output transistor such as the GOA structure employed in the current gate driving circuit directly connects the clock signal, and the dynamic power consumption is caused by the periodic variation of the clock signal and the existence of the parasitic capacitance of the output transistor.
  • the voltage of the internal nodes of the circuit will also periodically generate periodic fluctuations, thereby generating a clock feedthrough phenomenon.
  • the front gate drive circuit is an urgent problem to be solved.
  • the transistor may be a transistor of any structure, such as a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT).
  • FET Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • the first pole refers to the drain
  • the second pole refers to the source
  • the third pole refers to the gate
  • the transistor in the display device can be a TFT device.
  • the light emitting device may be an organic light emitting diode OLED, or may be other types of light emitting devices.
  • the transistors used in this application are N-type field effect transistors or NPN type bipolar transistors.
  • the circuit includes an input storage module 11, a storage extraction module 12, an output drive module 13 and a pull-down and maintenance module 14.
  • the input storage module 11 may include a storage capacitor C1 coupled to the switch S1 between the first end of C1 and the signal input terminal VI, and coupled between the second end of C1 and the low level VSS. Switch S2. The opening and closing of switches S1 and S2 is controlled by the input signal received by input terminal VI.
  • the storage extraction module 12 may include a switch S3 coupled between the C1 first end Q1 node and the output drive module 13, and a switch S4 coupled between the C1 second end and the output drive module 13.
  • the switch control terminal SW node is responsible for receiving control signals that control the opening and closing of S3 and S4. According to one embodiment, this control signal can be a clock signal as shown in FIG.
  • the output driving module 13 may include an output transistor T1 having a first pole coupled to a high level VDD, a third pole coupled to the switch S3 at a point Q2, and a second pole coupled to the output terminal OUT.
  • the output terminal OUT is coupled to the switch S4 as shown in FIG. 2 .
  • the pull-down and sustain module 14 may include transistors T2 and T3.
  • the first pole of the transistor T2 is coupled to the third pole of the output transistor T1, and the first pole of the T3 is coupled to the output terminals OUT, T2 and T3.
  • the second poles are all coupled to a low level VSS, and the third poles of T2 and T3 are coupled to a sub-module 141 that generates a pull-down and sustain control signal.
  • FIG. 2 is an exemplary operational timing diagram of the circuit of FIG. 1.
  • the circuit of Figure 1 can be The working timing is divided into a pre-charging phase P1, a pull-up phase P2, a pull-down phase P3 and a low-level sustaining phase P4, and the working processes of the four phases are described in detail below.
  • the input signal received by the input VI is at a high level, switches S1 and S2 are turned on, and capacitor C1 is charged.
  • the signal received by the control terminal SW is low, the switches S3 and S4 are turned off, the voltages of the third and Q2 nodes of the output transistor T1 are maintained at a low level, and T1 is turned off, thereby the voltage of the output terminal OUT.
  • a low level the signal received by the control terminal SW is low, the switches S3 and S4 are turned off, the voltages of the third and Q2 nodes of the output transistor T1 are maintained at a low level, and T1 is turned off, thereby the voltage of the output terminal OUT.
  • the input signal received by the input VI goes low, switches S1 and S2 are turned off, and the input signal is no longer received.
  • the control signal received by the control terminal SW becomes a high level, the switches S3 and S4 are turned on, the capacitor C1 is discharged, the voltage on the Q1 node is transmitted to the Q2 node, the voltage of the Q2 node is raised, and the output transistor T1 is turned on, and the output terminal is turned on. OUT is charged.
  • the second end is coupled to the output terminal OUT, and as the voltage of the OUT node rises to a high level, the voltage of the floating Q1 node is also raised, and the voltage of the Q2 node is raised. It also rises to a voltage level higher than the high level VDD, such as Vq, to ensure the rising speed of the output voltage. This phenomenon is called voltage bootstrap.
  • the control signal received by the control terminal SW goes low, S3 and S4 are turned off, the output transistor T1 is turned off, and the pull-down signal Dis received by the third poles of the transistors T2 and T3 becomes high at this stage.
  • Level, output OUT and Q2 nodes are pulled down to low VSS.
  • the Q1 node does not discharge to a low level at this stage, but falls to, for example, a high level VDD.
  • the control signal received by the control terminal SW is, for example, a clock signal. This signal is at a low level during this phase, so the Q1 node is not connected to the Q2 node, and thus the voltage of the Q1 node. Unable to drop to VSS at this stage.
  • the output terminal OUT voltage has been pulled down to a low level, the voltage at the Q1 point drops from Vq to VDD under the action of capacitive coupling.
  • the low level sustain signal KLL received by the third pole of T2 and T3 goes high at this stage, maintaining the output OUT and Q2 nodes low.
  • the signal at the SW terminal reaches a high level at this stage, and the Q1 node is connected to the Q2 node in this phase and discharged to a low level.
  • the low-level sustain signal KLL shown in Figure 2 is low in the P2 and P3 phases, in other stages. The segment is high.
  • the KLL signal can be in other forms as long as it is guaranteed to be low during the P2 phase.
  • the voltage is stored and transferred by the capacitor, so that the output transistor of the driving load also realizes the voltage bootstrap when the first pole is coupled to the fixed positive voltage source VDD, thereby ensuring the circuit speed.
  • the serious dynamic power consumption and clock feedthrough effect caused by the direct connection of the output transistor and the clock signal in the conventional structure are avoided. Therefore, this structure can greatly reduce the overall power consumption of the circuit and enhance the stability of the circuit.
  • the signal received by the switch control terminal SW is very important.
  • the circuit in FIG. 2 is mainly used to describe the characteristics of the switched capacitor bootstrap circuit structure, and is not limited to using the clock as the The SW node controls the signals of switches S3 and S4. That is to say, as long as the memory extraction module is adopted, instead of directly connecting the output transistor to the high level, and the operation of controlling the memory extraction module is affected by the clock signal, the bootstrap circuit or the shift register unit circuit structure is The scope of the claimed invention. As for what kind of circuit is used to generate the switch control signal, it can be changed according to different applications and requirements. Below we will detail some examples.
  • FIG. 3 illustrates a shift register unit circuit in accordance with an embodiment of the present application.
  • the circuit may include an input storage module 31, a storage extraction module 32, an output drive module 33, a pull-down module 34, and a low level maintenance module 35.
  • the input storage module 31 may include a storage capacitor C1 and transistors T311 and T312.
  • the first and third poles of the transistor T311 are both coupled to the input terminal VI1, and the second pole is coupled to the first end of the capacitor C1.
  • the node Q1; the first end of the transistor T312 is coupled to the second end of the capacitor C1, the second end of the T312 is coupled to the low level VSS, and the third end of the T312 is coupled to the input terminal VI1.
  • the memory extraction module 32 may include transistors T321 and T322 for transferring a storage voltage, the first electrode of the transistor T321 is coupled to the first end of the capacitor C1 and the node Q1, and the first pole of the T322 is coupled to the capacitor The second end of C1.
  • the third poles of transistors T321 and T322 are both coupled to node SW, and control signal input SW is configured to receive control signals that control the operation of transistors T321 and T322.
  • the memory extraction module 32 may further include transistors T323 and T324.
  • the first and third poles of T323 are both coupled to the first clock signal input terminal CLK1, and the second pole of T323 is coupled to the T321 and T322.
  • the third pole is coupled to the second pole of T323, the second pole of T324 is coupled to the low level VSS, and the third pole is coupled to the discharge control signal input terminal VI0.
  • the output drive module 33 may include an output transistor T331 and an output transistor T332.
  • the first poles of T331 and T332 are both coupled to a high level VDD, and the third pole is coupled to the second pole of T321 and node Q2.
  • the second pole of T331 is coupled to the cascade output terminal COUT, and the second pole of T332 is coupled to the signal output terminal OUT.
  • the signal output by the cascaded output COUT is not used to drive the load and is only used for output to other stages of the shift register unit for input or control.
  • the size of the output transistor T332 is greater than the size of the output T331.
  • the pull-down module 34 may include a pull-down transistor T341 at the Q2 point, a pull-down transistor T342 at the COUT terminal, and a pull-down transistor T343 at the OUT terminal.
  • the second poles of the three transistors are coupled to the low level VSS, the third pole. Both are coupled to the pull-down control signal input terminal VR1, except that the first pole of T341 is coupled to Q2, the first pole of T342 is coupled to COUT, and the first pole of T343 is coupled to OUT.
  • the low level maintenance module 35 may include transistors T351, T352 and T353, the second pole of which is coupled to the low level VSS, and the third pole is coupled to the second clock signal input terminal CLK2, the difference
  • the first pole of T351 is coupled to the Q2 node
  • the first pole of T352 is coupled to COUT
  • the first pole of T353 is coupled to OUT.
  • FIG. 5 is a diagram showing an exemplary operational timing diagram of the shift register unit shown in FIG. 3 according to an embodiment of the present application. As shown in the figure, the operation of the shift register unit can be divided into the following five stages: a discharge phase P0, a precharge phase P1, a pull-up phase P2, a pull-down phase P3, and a low-level sustain phase P4, which are described in detail below. The five stages of the work process.
  • the input received at the input signal terminal VI 1 is low, the signal received by the discharge control signal input terminal VI0 is high, the T324 transistor is turned on, and the SW node voltage is discharged to a low level. This is to ensure that when the storage capacitor C1 is charged, T321 and T322 are turned off, thus causing the output transistor to be turned on early to cause logic confusion.
  • this step of discharge operation can also be carried out in the P1 phase, but in this case there may be a situation in which the SW node is charged and discharged at the same time, which increases the leakage power consumption.
  • the input signal received by the input signal terminal VI1 becomes a high level
  • the T311 tube and the T312 tube are turned on, and the capacitor C1 is charged.
  • the first clock signal received by the first clock signal input terminal CLK1 is at a low level
  • the SW point continues to remain at a low level
  • the T321 tube and the T322 tube are turned off.
  • No high level is transmitted to the third poles of the output transistors T331 and T332, and T331 and T332 are in an off state.
  • the clock signal received by the second clock signal input terminal CLK2 is at a high level, the Q2 node, the output terminal OUT, and the cascade output terminal. COUT is maintained at low VSS.
  • the input signal received by the input signal terminal VI1 goes low, and the transistors T311 and T312 are turned off.
  • the clock signal received by the first clock signal terminal CLK1 is at a high level at this stage, the transistor T323 is turned on, the discharge control signal input terminal VI0 is at a low level at this stage, and the transistor T324 is turned off, so that the SW node voltage is from When the low level goes high, the switching transistors T321 and T322 are turned on, and the voltage on the Q1 node is transmitted to the Q2 node.
  • the output transistors T331 and T332 are turned on, charging the output terminal OUT and the cascade output terminal COUT.
  • the output terminal OUT and the cascaded output COUT voltage rise to a high level, due to the parasitic capacitance of the output transistor T331 and the presence of the capacitor C1, the voltage of the floating Q1 node and the Q2 node will rise above the bootstrap level.
  • the voltage of the high level VDD is, for example, Vq.
  • transistor T323 turns on to charge the SW node to a high level VDD, and due to the voltage rise of the Q1 and Q2 nodes, the voltage at the SW node is raised to, for example, Vq due to capacitive coupling.
  • the voltages of the Q1 node, the Q2 node, and the SW node are both raised to a level higher than VDD, for example, the voltage Vq, which ensures that the switching transistor T321 and the output transistor T331 are both turned on at this stage, ensuring the output transistor.
  • VDD voltage
  • Vq voltage
  • T323 since the first and third poles of the transistor T323 are both coupled to VDD, T323 is equivalent to one diode. Therefore, even if the voltage of the SW node reaches a level higher than VDD, the phenomenon of backflow does not occur.
  • the clock signal received by the first clock signal input terminal CLK1 falls to a low level, and the pull-down control signal received by the pull-down control signal input terminal VR1 is at a high level, and the transistors T341, T342 and T343 are turned on.
  • the output terminal OUT, the cascade output terminal COUT, the Q1 node and the Q2 node are discharged to a low level.
  • the voltage of the SW node is not pulled down to a low level at this stage but is pulled down to a voltage level lower than the high level VDD and higher than the low level VSS, for example, Vx.
  • the second clock signal received by the second clock signal input terminal CLK2 is at a high level, and the transistors T351, T352 and T353 are turned on.
  • the cascaded output COUT, the output terminal OUT, the Q1 node, and the Q2 node are all maintained at a low level VSS.
  • the second clock signal may be any clock signal that does not overlap the first clock signal.
  • the first clock signal received by CLK1 may be three-phase, and thus the second clock signal may be CLK2 or CLK2' which differs from each other by one phase as shown in FIG.
  • the voltage at the SW node that controls the switching transistors T321 and T322 in the circuit of the embodiment shown in Fig. 3 can be bootstrapped, allowing the Q1 point and the Q2 point to be more efficiently connected to ensure the bootstrap effect.
  • the circuit in this embodiment avoids the clock feedthrough effect of the internal node and the dynamic power consumption caused by the clock signal on the output transistor compared to the conventional bootstrap circuit that directly connects the first pole of the output transistor to the clock signal. .
  • the circuit 4 shows a shift register unit circuit in accordance with an embodiment of the present application. This type of circuit can load relatively small application scenarios.
  • the circuit may include an input storage module 41, a storage extraction module 42, an output drive module 43, a pull-down module 44, and a low level maintenance module 45.
  • the input storage module 41 may include a storage capacitor C1 and transistors T411 and T412.
  • the first and third poles of the transistor T411 are both coupled to the input terminal VI1, and the second electrode is coupled to the first end of the capacitor C1.
  • the node Q1; the first end of the transistor T412 is coupled to the second end of the capacitor C1, the second end of the T412 is coupled to the low level VSS, and the third end of the T412 is coupled to the input terminal VI1.
  • the memory extraction module 42 may include transistors T421 and T422 for transferring a storage voltage, the first electrode of the transistor T421 is coupled to the first end of the capacitor C1 and the node Q1, and the first pole of the T422 is coupled to the capacitor The second end of C1.
  • the third poles of transistors T421 and T422 are both coupled to node SW, and control signal input SW is configured to receive control signals that control the operation of transistors T421 and T422.
  • the memory extraction module 42 may further include transistors T423 and T424.
  • the first and third poles of T423 are both coupled to the first clock signal input terminal CLK1, and the second pole of T423 is coupled to the T421 and T422.
  • the third pole is coupled to the second pole of T423, the second pole of T424 is coupled to the low level VSS, and the third pole is coupled to the discharge control signal input terminal VI0.
  • the output drive module 43 may include an output transistor T431.
  • the first pole of T431 is coupled to a high level VDD, and the third pole is coupled to a second pole of T421 and node Q2.
  • the second pole of the T431 is coupled to the output terminal OUT/COUT. This output signal is used both for driving the load and for outputting to other stages of the shift register unit for input or control.
  • the pull-down module 44 may include a pull-down transistor T441 at the Q2 point and a pull-down transistor T442 at the OUT/COUT terminal.
  • the second poles of the two transistors are coupled to a low level VSS, and the third pole is coupled to the pull-down.
  • the control signal input terminal VR1 is different in that the first pole of T441 is coupled to Q2, and the first pole of T442 is coupled to OUT/COUT.
  • the low level maintenance module 45 may include transistors T451 and T452, the second pole of which is coupled to the low level VSS, and the third pole is coupled to the second clock signal input terminal CLK2, the difference being T451
  • the first pole is coupled to the Q2 node, and the first pole of T452 is coupled to OUT/COUT.
  • FIG. 5 is a diagram showing an exemplary operational timing diagram of the shift register unit shown in FIG. 4 according to an embodiment of the present application. As shown in the figure, the operation of the shift register unit can be divided into the following five stages: a discharge phase P0, a precharge phase P1, a pull-up phase P2, a pull-down phase P3, and a low-level sustain phase P4, which are described in detail below. The five stages of the work process.
  • the input received at the input signal terminal VI 1 is low, the signal received by the discharge control signal input terminal VI0 is high, the T424 transistor is turned on, and the SW node voltage is discharged to a low level. This is to ensure that when the storage capacitor C1 is charged, T421 and T422 are turned off, thus causing the output transistor to be turned on early to cause logic confusion.
  • this step of discharge operation can also be carried out in the P1 phase, but in this case there may be a situation in which the SW node is charged and discharged at the same time, which increases the leakage power consumption.
  • the input signal received by the input signal terminal VI1 goes high, the T411 tube and the T412 tube are turned on, and the capacitor C1 is charged.
  • the first clock signal received by the first clock signal input terminal CLK1 is at a low level, the SW point continues to remain at a low level, and the T421 tube and the T422 tube are turned off. No high level is transmitted to the third poles of the output transistors T431 and T432, and T431 and T432 are in an off state.
  • the clock signal received by the second clock signal input terminal CLK2 is at a high level, and both the Q2 node and the output terminal OUT/COUT are maintained at a low level VSS.
  • the input signal received by the input signal terminal VI1 goes low, and the transistors T411 and T412 are turned off.
  • the clock signal received by the first clock signal terminal CLK1 is at a high level at this stage, the transistor T423 is turned on, the discharge control signal input terminal VI0 is at a low level at this stage, and the transistor T424 is turned off, so that the SW node voltage is from When the low level goes high, the switching transistors T421 and T422 are turned on, and the voltage on the Q1 node is transmitted to the Q2 node.
  • the output transistor T431 As the voltage at the Q2 node rises, the output transistor T431 is turned on, charging the output terminal OUT/COUT. As the output OUT/COUT voltage rises to a high level, due to the parasitic capacitance of the output transistor T431 and the power In the presence of the capacitor C1, the voltage of the floating Q1 node and the Q2 node is raised by the bootstrap to a voltage higher than the high level VDD such as Vq. For the SW node, transistor T323 turns on to charge the SW node to a high level VDD, and due to the voltage rise of the Q1 and Q2 nodes, the voltage at the SW node is raised to, for example, Vq due to capacitive coupling. As can be seen from FIG.
  • the voltages of the Q1 node, the Q2 node, and the SW node are both raised to a level higher than VDD, for example, the voltage Vq, which ensures that the switching transistor T421 and the output transistor T431 are both turned on at this stage, ensuring the output transistor.
  • VDD voltage
  • Vq voltage
  • T423 since the first and third poles of the transistor T423 are both coupled to VDD, T423 is equivalent to a diode. Therefore, even if the voltage of the SW node reaches a level higher than VDD, the phenomenon of backflow does not occur.
  • the clock signal received by the first clock signal input terminal CLK1 falls to a low level, and the pull-down control signal received by the pull-down control signal input terminal VR1 is at a high level, and the transistors T441 and T442 are turned on, The output terminals OUT/COUT, Q1 node and Q2 node are discharged to a low level.
  • the voltage of the SW node is not pulled down to a low level at this stage but is pulled down to a voltage level lower than the level VDD but higher than the low level VSS, for example, Vx.
  • the second clock signal received by the second clock signal input terminal CLK2 is at a high level, and the transistors T451 and T452 are turned on.
  • the output terminals OUT/OUT, Q1 node and Q2 node are both maintained at a low level VSS.
  • the second clock signal may be any clock signal that does not overlap the first clock signal.
  • the first clock signal received by the first clock signal input terminal CLK1 may be three-phase, and thus the second clock signal may be CLK2 or CLK2' which differs from each other by one phase as shown in FIG.
  • the embodiment shown in FIG. 4 provides another shift register unit circuit scheme which also generates a stable control signal at the SW node, which avoids the clock feedthrough effect of the internal node and is connected to the clock signal. Dynamic power generated on the output transistor. Compared with the circuit shown in FIG. 3, the number of transistors is used, the circuit structure is simpler, and it is suitable for the case where the driving load is small.
  • the gate driving circuit may include a shift register and a plurality of signal lines.
  • the shift register can be made up of M diagrams 3 or 4 M of the illustrated shift register unit may be a positive integer greater than or equal to four.
  • the gate driving circuit may include five input signal lines: a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, a first initial pulse signal STV0, and a second initial pulse signal STV1.
  • a positive voltage source VDD and a negative voltage source VSS are also provided.
  • the discharge control signal input terminal VI0 may be configured to receive the first initial pulse signal STV0, and the input terminal VI1 may be configured to receive the second initial pulse signal STV1,
  • a clock signal input terminal CLK1 may be configured to receive the first clock signal CK1
  • the second clock signal input terminal CLK2 may be configured to receive the second clock signal CK2
  • the pull-down control signal input terminal VR1 may be coupled to the second stage shift The cascaded output C ⁇ 2> of the bit register unit.
  • the discharge control signal input terminal VI0 can be configured to receive the second initial pulse signal STV1, and the input terminal VI1 can be configured to be coupled to the first stage shift register.
  • the cascaded output terminal C ⁇ 1> of the unit, the first clock signal input terminal CLK1 may be configured to receive the second clock signal CK2, and the second clock signal input terminal CLK2 may be configured to receive the third clock signal CK3, the pull-down control signal Input VR1 can be coupled to the cascaded output C ⁇ 3> of the third stage shift register unit.
  • the discharge control signal terminal VI0 can be coupled.
  • the input terminal VI1 can be coupled to the cascaded output terminal C ⁇ N-1> of the N-1th shift register unit.
  • the pull-down control signal input terminal VR1 may be coupled to the cascade output terminal C ⁇ N+1> of the (N+1)th stage shift register.
  • the first clock signal input terminal CLK1 may be configured to receive the first clock signal CK1, and the second clock signal input terminal CLK2 may be configured to receive the second The clock signal CK2; for the shift register unit of the Nth stage, the first clock signal input terminal CLK1 may be configured to receive the second clock signal CK2, and the second clock signal input terminal CLK2 may be configured to receive the third clock signal CK3.
  • the clock signals received by the first clock signal input terminal CLK1 of the shift register units of the adjacent two stages differ by at least one phase, and the second clock signal input of the cells of the adjacent two stages is input.
  • the clock signal received by the terminal CLK2 is also at least one phase apart.
  • the cascaded output signal of the next stage is used as the pull-down control signal, and it is not necessary to wait until the next stage of the cascaded output signal is completely output to implement the pull-down, only
  • the next-stage cascaded output signal for example, a rising edge can trigger a pull-down operation, so the above connection method can be completely Meet the needs of pull-down operations at all levels.
  • the last stage shift register unit such as stage M, may not be used to drive the load, but only to generate a cascaded output signal for supply to the M-1 stage as a pull down control signal. Since the shift register unit of the Mth stage does not need to drive the load, the circuit of the output terminal OUT and the drive output terminal OUT may not be set, and the pull-down control signal output terminal VR of the output terminal OUT and the corresponding pull-down and maintenance may not be required. Transistor.
  • FIG. 7 shows a gate drive circuit in accordance with another embodiment of the present application. Similar to the gate driving circuit shown in FIG. 6, the gate driving circuit may include a shift register and a plurality of signal lines.
  • the shift register may be composed of M shift register units shown in FIG. 3 or FIG. 4, and M may be a positive integer greater than or equal to 4.
  • the first clock signal input terminal CLK1 may be configured to receive the first clock signal CK1, and the second clock signal input terminal CLK2 may be configured to receive the third clock signal CK3; for the Nth stage shift register unit, the first clock signal input terminal CLK1 may be configured to receive the second clock signal CK2, and the second clock signal input terminal CLK2 may be It is configured to receive the first clock signal CK1.
  • the second clock signal input terminal of the shift register unit of two adjacent stages The signals received by CLK2 are also at least one phase apart.
  • FIG. 8 is a diagram showing an exemplary timing waveform of the gate driving circuit shown in FIG. 6. It can be seen that the first, second and third clocks CK1, CK2 and CK3 can be a set of three-phase clocks which differ from each other by one phase.
  • the discharge control signal STV0 first reaches the high level, thereby realizing the discharge to the SW node. Operation ensures that switching transistors T321 and T322 are not turned on during the charging phase.
  • STV1 reaches a high level, charging C1 while CK1 is at a low level.
  • the global wiring uses only one positive voltage source and one negative voltage source, which reduces power consumption and enhances circuit stability, and enhances circuit performance while reducing the area cost of layout wiring.
  • FIG. 9 illustrates a display in accordance with one embodiment of the present application.
  • the display may include a gate drive circuit 91, a data drive circuit 92, a pixel matrix 93, a gate drive line 94, and a data drive line 95.
  • a display may be a liquid crystal display, an organic light emitting display, a quantum dot light emitting display or an electronic paper display.
  • the gate driving circuit 91 generates a scanning signal and transmits it to the pixel matrix 93 through the gate driving line 94, and controls the pixel matrix 93 to be turned on line by line to write data.
  • the data driving circuit 92 generates the data voltage required for each row, and transmits it to the pixel matrix through the data driving line 95.
  • the gate driving circuit in this embodiment may include a shift register provided by the present application, as shown in FIG. 6 or FIG.
  • the shift register in the gate drive module of the display includes a multi-stage shift register unit. This method can perform the following operations by any shift register unit except the last stage, where each shift
  • the register unit includes an input storage module, a storage extraction module, an output drive module, and a pull-down maintenance module.
  • the input storage module receives and stores the input signal
  • the storage extraction module transmits the stored input signal to the output driver module under the influence of the clock signal
  • step 1006 the output driver module transmits the input signal to the output terminal under the control of the storage extraction module
  • the pull-down and hold module pulls the voltage at the output to a low level after the output is complete and maintains the output voltage at a low level before the output drive module receives the next input signal.

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Abstract

一种移位寄存器单元电路，包括输入存储模块（11），被配置为在输入端（VI）接收输入信号并存储所述输入信号；存储提取模块（12），被配置为至少在第一时钟信号的控制下从所述输入存储模块（11）提取所述输入信号；输出驱动模块（13），被配置为在所述存储提取模块（12）的控制下将所述输入信号传输到输出端（OUT）；以及下拉和维持模块（14），被配置为在输出结束后将所述输出端（OUT）的电压下拉到低电平并在所述输出驱动模块（13）接收到下一个输入信号之前将所述输出端电压维持在低电平。以及一种包括前述移位寄存器单元的栅极驱动电路以及产生栅极驱动信号的方法。

Description

栅极驱动电路 技术领域
本申请涉及有源矩阵显示技术领域，更具体地，涉及一种栅极驱动电路。
背景技术
随着显示器向高分辨率、窄边框方向发展，集成驱动电路的显示器成为了显示器驱动领域研究的热点。当前，薄膜晶体管(Thin Film Transistor,TFT)已经被应用于显示器的制造之中，运用TFT技术来实现显示器的驱动电路可以减少外围驱动芯片的数量和简化工艺流程，从而降低成本；能够提高模组的集成度，增强机械可靠性，以便于制造质量轻，厚度薄的窄边框甚至无边框的显示器。集成驱动电路的显示技术的研究，最终目标是实现屏上全集成系统(System on Panel,SOP)。
栅极驱动电路的集成最早得到了学者研究和产业化应用。实现集成栅极驱动电路的TFT技术主要分为三种:氢化非晶硅TFT，低温多晶硅TFT和氧化物TFT。氢化非晶硅TFT是显示领域中主流的TFT技术，但其迁移率低，主要应用于分辨率较低的显示器中，低温多晶硅TFT是一种新兴的TFT技术，其迁移率高但均匀性差，主要应用在小尺寸高分辨率的显示器中，而氧化物TFT则被认为是下一代TFT技术，其迁移率高均匀性好，制造工艺与非晶硅兼容，适合应用于高分辨率的显示器中。这些TFT技术的发展，也推动了显示器不断接近SOP目标的实现。
发明内容
本申请提供了一种开关电容电压自举电路作为高稳定性、低功耗的移位寄存器单元，并利用包含就这种单元的移位寄存器单元实现栅极驱动电路以及显示器的设计。
本申请提供了一种移位寄存器单元电路，包括输入存储模块，被配置为在输入端接收输入信号并存储所述输入信号；存储提取模块，被配置为至少在第一时钟信号的影响下从所述输入存储模块提取所述输入信号；输出驱动模块，被配置为在所述存储提取模块的控制下将所述输入信号传输到输出端；以及下拉和维持模块，被配置为在输出结束后将所 述输出端的电压下拉到低电平并在所述输出驱动模块接收到下一个输入信号之前将所述输出端电压维持在低电平。
特别的，所述输入存储模块包括，存储电容被配置为存储所述输入信号，所述存储电容的第一端通过第一开关与所述输入端耦接，第二端通过第二开关与低电平耦接，所述第一开关和第二开关在所述输入信号的控制下开启或关闭；所述输出驱动模块包括，第一晶体管，所述第一晶体管包括与高电平耦接的第一极，以及与所述输出端和所述下拉和维持模块耦接的第二极，以及与所述存储提取模块耦接的第三极；所述存储提取模块包括，耦接在所述存储电容第一端以及所述第一晶体管第三极之间的第三开关，以及耦接在所述存储电容第二端以及所述输出端之间的第四开关，其中，所述第一时钟信号影响所述第三和第四开关的开关状态。
特别的，所述输出驱动模块还包括第二晶体管，所述第二晶体管的第一极耦接到高电平，第二极耦接到第二输出端，第三极耦接到所述第一晶体管的第三极，其中所述第一晶体管的尺寸大于所述第二晶体管的尺寸。
特别的，所述第一开关是第三晶体管，包括耦接到所述输入端的第一极和第三极，以及耦接到所述存储电容第一端的第二极；所述第二开关是第四晶体管，包括耦接到所述存储电容第二端的第一极，耦接到低电平的第二极，和耦接到所述输入端的第三极，当所述输入信号为高电平时，所述第一和第二开关开启，所述存储电容充电。
特性的，所述第三开关是第五晶体管，包括耦接到所述存储电容第一端的第一极，耦接到所述第一晶体管第三极的第二极，和耦接到第一时钟信号输入端的第三极；所述第四开关是第六晶体管，包括耦接到所述存储电容第二端的第一极，耦接到所述输出端的第二极，和耦接到第一时钟信号输入端的第三极；所述第一时钟信号在所述存储电容充电结束后达到高电平，所述第三和第四开关开启。
特别的，所述存储提取模块还包括第七晶体管和第八晶体管，第七晶体管的第一极和第三极耦接到所述第一时钟信号输入端，第二极耦接到所述第五晶体管和第六晶体管的第三极，第八晶体管的第一极耦接到所述第七晶体管的第二极，第二极耦接到低电平，第三极耦接到放电控制信号输入端，使得在所述存储电容充电期间所述第三和第四开关处于关闭状态。
特别的，所述下拉和维持模块包括第九晶体管和第十晶体管，其中所述第九晶体管包括耦接到所述第一晶体管第三极的第一极，耦接到低电平的第二极，以及耦接到下拉和 维持控制信号输入端的第三极，所述第十晶体管包括耦接到所述输出端的第一极，耦接到低电平的第二端，以及耦接到下拉和维持控制信号输入端的第三极。
特别的，所述下拉和维持模块包括下拉子模块和维持子模块，其中所述下拉子模块包括所述下拉子模块包括第十一和第十二晶体管，该两个晶体管的第二极都耦接到低电平，第三极都耦接到一个下拉控制信号输入端，其中第十一晶体管的第一极耦接到所述第一晶体管的第三极，第十二晶体管的第一极耦接到第一晶体管的第二极和所述输出端；所述维持子模块包括第十四和第十五晶体管，该两个晶体管的第二极都耦接到低电平，第三极都耦接到第二时钟信号输入端，其中第十四晶体管的第一极耦接到第一晶体管的第三极，第十五晶体管的第一极耦接到第一晶体管的第二极和所述输出端。
特别的，所述下拉和维持模块包括下拉子模块和维持子模块；所述下拉子模块包括第十一、第十二和第十三晶体管，该三个晶体管的第二极都耦接到低电平，第三极都耦接到一个下拉控制信号输入端，其中第十一晶体管的第一极耦接到所述第一晶体管和第二晶体管的第三极，第十二晶体管的第一极耦接到第一晶体管的第二极和所述输出端，第十三晶体管的第一极耦接到第二晶体管的第二极和所述第二输出端；所述维持子模块包括第十四、第十五和第十六晶体管，该三个晶体管的第二极都耦接到低电平，第三极都耦接到第二时钟信号输入端，其中第十四晶体管的第一极耦接到第一晶体管和第二晶体管的第三极，第十五晶体管的第一极耦接到第一晶体管的第二极和所述输出端，第十六晶体管的第一极耦接到第二晶体管的第二极和所述第二输出端。
本申请还提供了一种栅极驱动电路，包括移位寄存器，所述移位寄存器包括M个级连的单元，其中第1至M-1级所述单元包括如前述任一权利要求所述的电路，其中第N级的输入端耦接到第N-1级的第二输出端，第N级的下拉控制信号端耦接到第N+1级的第二输出端，第N级的放电控制信号输入端耦接到第N-2级的第二输出端，其中M为大于4的正整数，N为小于等于M-1但不小于3的正整数；其中第1级移位寄存器单元的输入端接收初始的输入信号，第1级的放电控制信号输入端接收初始的放电控制信号，第1级的下拉控制信号输入端耦接到第2级的第二输出端；以及第2级的放电控制信号输入端接收初始的输入信号，第2级的输入端耦接到第1级的第二输出端，第2级的下拉控制信号输入端耦接到第3级的第二输出端。
特别的，第M级移位寄存器单元的其输出仅被配置向第M-1级单元提供下拉控制信号。
本申请还提供了一种显示器，包括像素矩阵，与所述像素矩阵耦接的数据驱动电路，以及与所述像素矩阵耦接的如前所述的栅极驱动电路。
特别的，所述显示器为TFT显示器，所述栅极驱动电路与所述像素矩阵形成在相同的基板上。
本申请还提供了一种产生显示器栅极驱动信号的方法，包括由显示器的栅极驱动模块中的移位寄存器中的每个单元执行以下操作，其中每个移位寄存器单元包括输入存储模块、存储提取模块、输出驱动模块和下拉维持模块；输入存储模块接收并存储输入信号；存储提取模块至少在时钟信号的影响下将所存储的输入信号传输到输出驱动模块；输出驱动模块在所述存储提取模块的控制下将所述输入信号传输到输出端；下拉和维持模块在输出结束后将所述输出端的电压下拉到低电平并在所述输出驱动模块接收到下一个输入信号之前将所述输出端电压维持在低电平。
本申请所介绍的栅极驱动电路和显示器，避免了将用于驱动负载的输出晶体管直接连接到时钟信号，从而抑制了时钟馈通效应和动态功耗，能够大大减少电路的功耗和减少低电平维持阶段内部节点的电压波动；另一方面，只需用一个低电平就能完成低功耗的设计目标，减少了布线的复杂度和总体的电路面积。
以下将参照附图对本申请的示例性实施例的详细描述。
附图说明
被结合在说明书中并构成说明书的一部分的附图示出了本申请的实施例，并且连同其说明一起用于解释本申请的原理。
图1所示为根据本申请一个实施例的移位寄存器单元电路示意图；
图2所示为图1所示的电路工作时序示意图；
图3所示为根据本申请一个实施例的移位寄存器单元电路示意图；
图4所示为根据本申请另一个实施例的移位寄存器单元电路示意图；
图5所示为图3或者图4所示电路的工作时序示意图；
图6所示为根据本申请一个实施例的栅极驱动电路示意图；
图7所示为根据本申请另一个实施例的栅极驱动电路示意图；
图8所示为图6所示的栅极驱动电路工作时序示意图；
图9所示为根据本申请一个实施例的显示器示意图；以及
图10所示为根据本申请一个实施例的产生栅极驱动信号的方法的流程图。
具体实施方式
以下将参照附图来详细描述本申请的各示例性实施例。应注意的是，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本申请的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。
应注意的是，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
目前的栅极驱动电路大多采用1993年Thomson公司提出的GOA(Gate driver On Array)结构，这种结构通过栅极电压的自举来获得用于驱动负载的输出晶体管的较大的过驱动电压，以提高电路的驱动能力。从那以后，各个机构在该结构的基础上进行了大量研究。由于当前主流的TFT技术只提供N型晶体管,在对例如GOA结构的输出节点进行充电时，需要用到电压自举技术。
然而，目前采用的电压自举电路的结构面临动态功耗和时钟馈通的问题，这些问题尤其是在蚀刻层阻挡(Etch Stop Layer，ESL)的工艺下会对电路性能造成很大影响。这是因为在当前栅极驱动电路中所采用的例如GOA结构的输出晶体管的第一极直接连接时钟信号，随着时钟信号的周期性变化以及输出晶体管的寄生电容的存在会导致动态功耗。在低电平维持阶段，由于时钟信号的周期性变化，电路内部节点的电压也会相应动的产生周期性的波动，从而产生时钟馈通的现象。另外，在传统的电路中需要采用两种不同的低电平，这是为了在低电平维持阶段，输出晶体管的第三极例如栅极的电压低于其第二级例如源极的电压，从而抑制输出晶体管的漏电功耗。但是低电压源数量的增加以及相应的布线安排都会增加电路的复杂度和面积。
因此，在保证电路驱动能力的基础上，抑制时钟馈通效应和减小动态功耗，是当 前栅极驱动电路亟待解决的问题。
下面通过具体实施方式结合附图对本申请作进一步详细说明。
首先对本申请中用到的一些术语进行说明。在本申请中，晶体管可以是任何结构的晶体管，如场效应晶体管(FET，Field Effect Transistor)或者双极型晶体管(BJT，Bipolar Junction Transistor)。当晶体管为FET时，第一极指漏极，第二极指源极，第三极指栅极；当晶体管为BJT时，第一极指集电极，第二极指发射极，第三极指基极。显示装置中的晶体管可以是TFT器件。当晶体管作为开关使用时，其第一极和第二极可以互换。在本申请中，发光器件可以是有机发光二极管OLED，也可以是其他类型的发光器件。除特别说明外，本申请中所用的晶体管为N型场效应管或NPN型双极晶体管。
以下以场效应晶体管为例进行说明。当然，以双极型晶体管实施以下的方案也属于本申请所要求保护的内容。
图1所示为根据本申请一个实施例的移位寄存器单元电路的示意图。根据一个实施例，该电路包括输入存储模块11，存储提取模块12，输出驱动模块13和下拉和维持模块14。
根据一个实施例，输入存储模块11可以包括存储电容C1，耦接在C1第一端和信号输入端VI之间的开关S1，和耦接在C1的第二端和低电平VSS之间的开关S2。开关S1和S2的开启和关闭受输入端VI接收到的输入信号的控制。
根据一个实施例，存储提取模块12可以包括耦接在C1第一端Q1节点和输出驱动模块13之间的开关S3，以及耦接在C1第二端和输出驱动模块之间13的开关S4，开关控制端SW节点负责接收控制S3和S4开启和关闭的控制信号。根据一个实施例，这个控制信号可以是一个时钟信号如图2所示。
根据一个实施例，输出驱动模块13可以包括输出晶体管T1，其第一极耦接到高电平VDD，其第三极与开关S3在Q2点耦接，第二极耦接到输出端OUT。另外，输出端OUT与开关S4耦接如图2所示。
根据一个实施例，下拉和维持模块14可以包括晶体管T2和T3，晶体管T2的第一极耦接至输出晶体管T1的第三极，T3的第一极耦接至输出端OUT，T2和T3的第二极都耦接至低电平VSS，T2和T3第三极都耦接至产生下拉和维持控制信号的子模块141。
图2为图1所示电路的示例性工作时序图。根据一个实施例，可以将图1中电路 的工作时序分为预充电阶段P1，上拉阶段P2，下拉阶段P3和低电平维持阶段P4，下面详细描述这四个阶段的工作过程。
(1)预充电阶段P1
在这个阶段内，输入端VI接收到的输入信号处在高电平，开关S1和S2开启，电容C1被充电。在这个过程中，控制端SW接收到的信号为低电平，开关S3和S4关闭，输出晶体管T1的第三极和Q2节点电压维持在低电平，T1关断，从而输出端OUT的电压处在低电平。
(2)上拉阶段P2
在这个阶段内，输入端VI接收到的输入信号变为低电平，开关S1和S2关闭，不再接收输入信号。控制端SW接收到的控制信号变为高电平，开关S3和S4开启，电容C1放电，Q1节点上的电压被传输到Q2节点，Q2节点电压升高，输出晶体管T1导通，对输出端OUT进行充电。由于电容C1的第一端Q1处于浮空状态，第二端与输出端OUT耦接，随着OUT节点电压的升至高电平，浮空的Q1节点的电压也会跟着抬升，Q2节点的电压也会抬升至高于高电平VDD的一个电压水平例如Vq，从而保证了输出端电压的上升速度，这种现象被称为电压自举。
(3)下拉阶段P3
在这个阶段内，控制端SW接收到的控制信号变为低电平，S3和S4关闭，输出晶体管T1关断，晶体管T2和T3的第三极接收到的下拉信号Dis在这个阶段变为高电平，输出端OUT和Q2节点被下拉至低电平VSS。在这个实施示例中，Q1节点在这一阶段并没有放电至低电平，而是下降到例如高电平VDD。这是因为，如图2所示，控制端SW接收到的控制信号是一个例如时钟信号，这个信号在这个阶段内处于低电平，因此Q1节点与Q2节点并没有相连，因此Q1节点的电压无法在这个阶段下降到VSS。但是由于输出端OUT电压已经下拉到了低电平，在电容耦合的作用下，Q1点的电压从Vq下降到了VDD。
(4)低电平维持阶段P4
在这个阶段内和这个阶段后，T2和T3的第三极接收到的低电平维持信号KLL在这个阶段变为高电平，将输出端OUT和Q2节点维持在低电平。在这个实施示例中，如图2所示，SW端的信号在这个阶段达到高电平，Q1节点在这一阶段内与Q2节点相连，并放电至低电平。如图2所示低电平维持信号KLL在P2和P3阶段是低电平，在其他阶 段是高电平。当然,KLL信号还可以是其他形式的，只要确保其在P2阶段是低电平即可。
在本实施例中的电路，通过电容存储和传递电压，使得驱动负载的输出晶体管在第一极耦接到固定的正电压源VDD的情况下同样实现了电压自举，从而在保证电路速度的前提下，避免了传统结构中输出晶体管与时钟信号直接相连而导致的严重的动态功耗和时钟馈通效应。因此，这种结构可以大大减小电路的总体功耗，增强电路的稳定性。
在本实施例所介绍的电路中，开关控制端SW所接收到的信号很重要，图2中的电路主要是用来阐述开关电容自举电路结构的特征，并不局限于用时钟来作为在SW节点来控制开关S3和S4的信号。也就是说只要采用了存储提取模块这种方式，而不是将输出晶体管直接与高电平相连，并且控制存储提取模块的工作是受时钟信号影响的自举电路或者移位寄存器单元电路结构都是本申请所要求保护的范畴。至于采用什么样的电路来产生开关控制信号，根据不同的应用和需求，是可以有不同的变化的。以下我们将详细介绍一些实例。
图3所示为根据本申请一个实施例的一种移位寄存器单元电路。该电路可以包括输入存储模块31，存储提取模块32，输出驱动模块33，下拉模块34，低电平维持模块35。
根据一个实施例，输入存储模块31可以包括存储电容C1和晶体管T311和T312，晶体管T311的第一极和第三极都耦接到输入端VI1，第二极耦接到电容C1的第一端和节点Q1；晶体管T312的第一端耦接到电容C1的第二端，T312的第二极耦接到低电平VSS，T312的第三极耦接到输入端VI1。
根据一个实施例，存储提取模块32可以包括用于传递存储电压的晶体管T321和T322，晶体管T321的第一极耦接到电容C1的第一端和节点Q1，T322的第一极耦接到电容C1的第二端。晶体管T321和T322的第三极都耦接到节点SW，控制信号输入端SW被配置为接收控制晶体管T321和T322工作的控制信号。
根据一个实施例，存储提取模块32还可以包括晶体管T323和T324，T323的第一极和第三极都耦接到第一时钟信号输入端CLK1，T323的第二极耦接至T321和T322的第三极SW节点；T324的第一极耦接至T323的第二极，T324的第二极耦接至低电平VSS，第三极耦接至放电控制信号输入端VI0。
根据一个实施例，输出驱动模块33可以包括输出晶体管T331和输出晶体管T332。 T331和T332的第一极都耦接到高电平VDD，第三极都耦接到T321的第二极和节点Q2。T331的第二极耦接到级联输出端COUT，T332的第二极耦接到信号输出端OUT。根据一个实施例，级联输出端COUT输出的信号不用于驱动负载，只用于输出给其他级的移位寄存器单元作为输入或控制之用。因此，根据一个实施例，输出晶体管T332的尺寸大于输出T331的尺寸。
根据一个实施例，下拉模块34可以包括Q2点的下拉管T341，COUT端的下拉管T342，和OUT端的下拉管T343，这三个晶体管的第二极都耦接到低电平VSS，第三极都耦接到下拉控制信号输入端VR1，区别在于T341的第一极耦接到Q2，T342的第一极耦接到COUT，T343的第一极耦接到OUT。
根据一个实施例，低电平维持模块35可以包括晶体管T351，T352和T353，它们的第二极都耦接到低电平VSS，第三极都耦接到第二时钟信号输入端CLK2，区别在于T351的第一极耦接到Q2节点，T352的第一极耦接到COUT，T353的第一极耦接到OUT。
图5所示为图3所示的根据本申请一个实施例的移位寄存器单元的示例性工作时序图。如图所示，可以将该移位寄存器单元的工作过程分为以下五个阶段：放电阶段P0，预充电阶段P1，上拉阶段P2，下拉阶段P3和低电平维持阶段P4，下面详细描述这五个阶段的工作过程。
(1)放电阶段P0
在这个阶段内，在输入信号端VI 1接收到的输入为低电平，放电控制信号输入端VI0接收到的信号为高电平，T324晶体管被开启，将SW节点电压放电至低电平。这是为了确保在对存储电容C1充电的时候，T321和T322是关断的，因此导致输出晶体管被提前打开而造成逻辑混乱。
当然，这步放电操作也可以放到P1阶段进行，但这样做可能会存在着同时对SW节点充电和放电的情形，会增加漏电功耗。
(2)预充电阶段P1
在这个阶段内，输入信号端VI1所接收到的输入信号变为高电平，T311管和T312管开启，电容C1充电。在这个过程中，第一时钟信号输入端CLK1所接收到的第一时钟信号处在低电平，SW点继续保持在低电平，T321管和T322管关断。没有高电平传输到输出晶体管T331和T332的第三极，T331和T332处于关断状态。并且，第二时钟信号输入端CLK2所接收到的时钟信号处在高电平，Q2节点、输出端OUT、级联输出端 COUT都被维持在低电平VSS。
(3)上拉阶段P2
在这个阶段内，输入信号端VI1接收到的输入信号变为低电平，晶体管T311和T312关断。第一时钟信号端CLK1接收到的时钟信号在这个阶段处在高电平，晶体管T323被开启，放电控制信号输入端VI0在这个阶段处在低电平，晶体管T324关断，从而SW节点电压从低电平变为高电平，开关晶体管T321和T322被开启，Q1节点上的电压被传输到Q2节点上。
随着Q2节点电压的升高，输出晶体管T331和T332被开启，对输出端OUT和级联输出端COUT进行充电。随着输出端OUT和级联输出端COUT电压的抬升至高电平，由于输出晶体管T331的寄生电容以及电容C1的存在，浮空的Q1节点和Q2节点的电压会因自举而抬升到高于高电平VDD的电压例如Vq。对于SW节点而言，晶体管T323导通将SW节点充电至高电平VDD，又由于Q1和Q2节点的电压抬升，使得SW节点的电压受电容耦合的影响被抬高至例如Vq。由图5可见，Q1节点、Q2节点和SW节点的电压都提高到高于VDD的例如电压Vq水平，这保证了开关晶体管T321和输出晶体管T331在这个阶段都是导通的，保证了输出晶体管T331的对输出端OUT充电速度。
根据一个实施例，由于晶体管T323的第一极和第三极都耦接至VDD，T323相当于一个二极管。因此，即便SW节点的电压达到高于VDD的水平，也不会发生倒灌的现象。
(4)下拉阶段P3
在这个阶段内，第一时钟信号输入端CLK1接收到的时钟信号下降到低电平，而下拉控制信号输入端VR1接收到的下拉控制信号处在高电平，晶体管T341，T342和T343被开启，将输出端OUT，级联输出端COUT，Q1节点和Q2节点进行放电至低电平。从图5可见，在这个实施示例中，SW节点的电压在这个阶段没有下拉至低电平而是下拉到一个低于高电平VDD而高于低电平VSS的电压水平例如Vx。这是由于SW节点的电压从低电平上升到高电平时，是晶体管T323对开关晶体管T321第三极充电和电容耦合的共同结果，而从高电平下降时，只有电容耦合的影响。
(5)低电平维持阶段P4
在这个阶段内和这个阶段后，第二时钟信号输入端CLK2接收到的第二时钟信号处在高电平，晶体管T351，T352和T353被开启。根据一个实施例，由于Q1点仍与Q2点相连，级联输出端COUT，输出端OUT，Q1节点和Q2节点都被维持在低电平VSS。
其中，第二时钟信号只要是一个与第一时钟信号不交叠的时钟信号即可。根据一个实施例，CLK1所接收到的第一时钟信号可以是三相的，因此第二时钟信号可以是图5中所示的彼此相差一个相位的CLK2或者CLK2’。
图3所示的实施例中的电路中控制开关晶体管T321和T322工作的SW节点处的电压可以被自举，可以让Q1点和Q2点更高效地连接在一起，保证自举的效果。相较于将输出晶体管的第一极直接连接至时钟信号的传统自举电路来说，本实施例中的电路避免了内部节点的时钟馈通效应和输出晶体管上因时钟信号引起的动态功耗。
图4所示为根据本申请一个实施例的一种移位寄存器单元电路。这种电路可以负载相对较小的应用场景。该电路可以包括输入存储模块41，存储提取模块42，输出驱动模块43，下拉模块44，低电平维持模块45。
根据一个实施例，输入存储模块41可以包括存储电容C1和晶体管T411和T412，晶体管T411的第一极和第三极都耦接到输入端VI1，第二极耦接到电容C1的第一端和节点Q1；晶体管T412的第一端耦接到电容C1的第二端，T412的第二极耦接到低电平VSS，T412的第三极耦接到输入端VI1。
根据一个实施例，存储提取模块42可以包括用于传递存储电压的晶体管T421和T422，晶体管T421的第一极耦接到电容C1的第一端和节点Q1，T422的第一极耦接到电容C1的第二端。晶体管T421和T422的第三极都耦接到节点SW，控制信号输入端SW被配置为接收控制晶体管T421和T422工作的控制信号。
根据一个实施例，存储提取模块42还可以包括晶体管T423和T424，T423的第一极和第三极都耦接到第一时钟信号输入端CLK1，T423的第二极耦接至T421和T422的第三极SW节点；T424的第一极耦接至T423的第二极，T424的第二极耦接至低电平VSS，第三极耦接至放电控制信号输入端VI0。
根据一个实施例，输出驱动模块43可以包括输出晶体管T431。T431的第一极耦接到高电平VDD，第三极耦接到T421的第二极和节点Q2。T431的第二极耦接到输出端OUT/COUT,这个输出信号既用于驱动负载又用于输出给其他级的移位寄存器单元作为输入或控制之用。
根据一个实施例，下拉模块44可以包括Q2点的下拉管T441和OUT/COUT端的下拉管T442，这两个晶体管的第二极都耦接到低电平VSS，第三极都耦接到下拉控制信号输入端VR1，区别在于T441的第一极耦接到Q2，而T442的第一极耦接到OUT/COUT。
根据一个实施例，低电平维持模块45可以包括晶体管T451和T452，它们的第二极都耦接到低电平VSS，第三极都耦接到第二时钟信号输入端CLK2，区别在于T451的第一极耦接到Q2节点，T452的第一极耦接到OUT/COUT。
图5所示为图4所示的根据本申请一个实施例的移位寄存器单元的示例性工作时序图。如图所示，可以将该移位寄存器单元的工作过程分为以下五个阶段：放电阶段P0，预充电阶段P1，上拉阶段P2，下拉阶段P3和低电平维持阶段P4，下面详细描述这五个阶段的工作过程。
(1)放电阶段P0
在这个阶段内，在输入信号端VI 1接收到的输入为低电平，放电控制信号输入端VI0接收到的信号为高电平，T424晶体管被开启，将SW节点电压放电至低电平。这是为了确保在对存储电容C1充电的时候，T421和T422是关断的，因此导致输出晶体管被提前打开而造成逻辑混乱。
当然，这步放电操作也可以放到P1阶段进行，但这样做可能会存在着同时对SW节点充电和放电的情形，会增加漏电功耗。
(2)预充电阶段P1
在这个阶段内，输入信号端VI1所接收到的输入信号变为高电平，T411管和T412管开启，电容C1充电。在这个过程中，第一时钟信号输入端CLK1所接收到的第一时钟信号处在低电平，SW点继续保持在低电平，T421管和T422管关断。没有高电平传输到输出晶体管T431和T432的第三极，T431和T432处于关断状态。并且，第二时钟信号输入端CLK2所接收到的时钟信号处在高电平，Q2节点和输出端OUT/COUT都被维持在低电平VSS。
(3)上拉阶段P2
在这个阶段内，输入信号端VI1接收到的输入信号变为低电平，晶体管T411和T412关断。第一时钟信号端CLK1接收到的时钟信号在这个阶段处在高电平，晶体管T423被开启，放电控制信号输入端VI0在这个阶段处在低电平，晶体管T424关断，从而SW节点电压从低电平变为高电平，开关晶体管T421和T422被开启，Q1节点上的电压被传输到Q2节点上。
随着Q2节点电压的升高，输出晶体管T431被开启，对输出端OUT/COUT进行充电。随着输出端OUT/COUT电压的抬升至高电平，由于输出晶体管T431的寄生电容以及电 容C1的存在，浮空的Q1节点和Q2节点的电压会因自举而抬升到高于高电平VDD的电压例如Vq。对于SW节点而言，晶体管T323导通将SW节点充电至高电平VDD，又由于Q1和Q2节点的电压抬升，使得SW节点的电压受电容耦合的影响被抬高至例如Vq。由图5可见，Q1节点、Q2节点和SW节点的电压都提高到高于VDD的例如电压Vq水平，这保证了开关晶体管T421和输出晶体管T431在这个阶段都是导通的，保证了输出晶体管T431对输出端OUT的充电速度。
根据一个实施例，由于晶体管T423的第一极和第三极都耦接至VDD，T423相当于一个二极管。因此，即便SW节点的电压达到高于VDD的水平，也不会发生倒灌的现象。
(4)下拉阶段P3
在这个阶段内，第一时钟信号输入端CLK1接收到的时钟信号下降到低电平，而下拉控制信号输入端VR1接收到的下拉控制信号处在高电平，晶体管T441和T442被开启，将输出端OUT/COUT、Q1节点和Q2节点进行放电至低电平。从图5可见，在这个实施示例中，SW节点的电压在这个阶段没有下拉至低电平而是下拉到了一个低于到电平VDD但高于低电平VSS的电压水平例如Vx。这是由于SW点的电压从低电平上升到高电平时，是晶体管T423对开关晶体管T421第三极充电和电容耦合的共同结果，而从高电平下降时，只有电容耦合的影响。
(5)低电平维持阶段P4
在这个阶段内和这个阶段后，第二时钟信号输入端CLK2接收到的第二时钟信号处在高电平，晶体管T451和T452被开启。根据一个实施例，由于Q1点仍与Q2点相连，输出端OUT/OUT，Q1节点和Q2节点都被维持在低电平VSS。
其中，第二时钟信号只要是一个与第一时钟信号不交叠的时钟信号即可。根据一个实施例，第一时钟信号输入端CLK1所接收到的第一时钟信号可以是三相的，因此第二时钟信号可以是图5中所示的彼此相差一个相位的CLK2或者CLK2’。
如图4所示的实施例提供了另一种移位寄存器单元电路方案，这个电路方案同样在SW节点产生稳定的控制信号，可以避免内部节点的时钟馈通效应和因与时钟信号相连而在输出晶体管上产生的动态功耗。相较于图3所示的电路，采用了更少的晶体管数量，电路结构更加简单，适合用于驱动负荷较小的情形。
图6所示为根据本申请一个实施例的显示器栅极驱动电路示意框图。该栅极驱动电路可以包括移位寄存器和多条信号线。其中，移位寄存器可以是由M个图3或图4 所示的移位寄存器单元组成的，M可以是大于等于4的正整数。
根据一个实施例，该栅极驱动电路可以包括五条输入信号线：第一时钟信号CK1，第二时钟信号CK2，第三时钟信号CK3，第一初始脉冲信号STV0和第二初始脉冲信号STV1。当然还要提供正电压源VDD和负电压源VSS。
根据一个实施例，对于第一级移位寄存器单元来说，放电控制信号输入端VI0可以被配置为接收第一初始脉冲信号STV0，输入端VI1可以被配置为接收第二初始脉冲信号STV1，第一时钟信号输入端CLK1可以被配置为接收第一时钟信号CK1，第二时钟信号输入端CLK2可以被配置为接收第二时钟信号CK2，下拉控制信号输入端VR1可以被耦接至第二级移位寄存器单元的级联输出端C<2>。
根据一个实施例，对第二级移位寄存器单元来说，放电控制信号输入端VI0可以被配置为接收第二初始脉冲信号STV1，输入端VI1可以被配置为耦接到第一级移位寄存器单元的级联输出端C<1>，第一时钟信号输入端CLK1可以被配置为接收第二时钟信号CK2，第二时钟信号输入端CLK2可以被配置为接收第三时钟信号CK3，下拉控制信号输入端VR1可以被耦接至第三级移位寄存器单元的级联输出端C<3>。
根据一个实施例，对于第二级之后的移位寄存器单元来说，以第N级移位寄存器单元为例(N为大于等于3小于M-1的正整数)，放电控制信号端VI0可以耦接至第N-2级移位寄存器单元的级联输出端C<N-2>，输入端VI1可以耦接至第N-1级移位寄存器单元的级联输出端C<N-1>，下拉控制信号输入端VR1可以被耦接至第N+1级移位寄存器的级联输出端C<N+1>。
根据一个实施例，对于第N-1级的移位寄存器单元来说，第一时钟信号输入端CLK1可以被配置为接收第一时钟信号CK1,第二时钟信号输入端CLK2可以配置为接收第二时钟信号CK2；对于第N级的移位寄存器单元来说，第一时钟信号输入端CLK1可以被配置为接收第二时钟信号CK2，第二时钟信号输入端CLK2可以被配置为接收第三时钟信号CK3。当然，其他的组合方式也是可以的，只要相邻两级的移位寄存器单元的第一时钟信号输入端CLK1接收到的时钟信号相差至少一个相位，相邻两级的单元的第二时钟信号输入端CLK2接收到的时钟信号也至少相差一个相位即可。
对于除最后一级外的每级移位寄存器单元来说，采用下一级的级联输出信号作为下拉控制信号，并不需要等到下一级的级联输出信号完全输出才能实现下拉，只需要下一级级联输出信号出现例如上升沿即可触发下拉操作，因此上述连接方式完全可以 满足各级的下拉操作需要。
根据一个实施例，最后一级移位寄存器单元例如第M级，可以不用于驱动负载，而只用于产生级联输出信号以提供给M-1级作为下拉控制信号。由于第M级的移位寄存器单元不需要驱动负载，因此可以不设置输出端OUT和驱动输出端OUT的电路，也可以不需要设置输出端OUT的下拉控制信号输出端VR和相应的下拉和维持晶体管。
图7所示为根据本申请另一个实施例的栅极驱动电路。与图6中所示的栅极驱动电路类似，该栅极驱动电路可以包括移位寄存器和多条信号线。其中，移位寄存器可以是由M个图3或图4所示的移位寄存器单元组成的，M可以是大于等于4的正整数。
与图6不同的是，根据一个实施例，对于第N-1级的移位寄存器单元来说，第一时钟信号输入端CLK1可以被配置为接收第一时钟信号CK1,第二时钟信号输入端CLK2可以配置为接收第三时钟信号CK3；对于第N级的移位寄存器单元来说，第一时钟信号输入端CLK1可以被配置为接收第二时钟信号CK2，第二时钟信号输入端CLK2可以被配置为接收第一时钟信号CK1。当然，其他的组合方式，只要相邻两级的移位寄存器单元的第一时钟信号输入端CLK1接收到的信号相差至少一个相位，相邻两级的移位寄存器单元的第二时钟信号输入端CLK2接收到的信号也至少相差一个相位即可。
图8所示为图6所示的栅极驱动电路的示例性时序波形图。可以看出，第一、第二和第三时钟CK1,CK2和CK3可以是一套三相时钟，彼此相差一个相位。
对于第一级的移位寄存器单元来说，在输入信号端的STV1到达高电平开始充电之前以及在CK1达到高电平之前，放电控制信号STV0先达到高电平，实现了对SW节点的放电操作，确保不会在充电阶段就开启开关晶体管T321和T322。
随后，STV1达到高电平，向C1充电，同时CK1处于低电平。
STV1变为低电平从而充电结束后，CK1到达高电平，存储电容C1中存储的输入信号被传输到输出晶体管T331和T332的第三极，并在输出端OUT产生第一级的栅极驱动信号O<1>。
类似的，对于第二级移位寄存器单元来说，第二时钟信号CK2达到高电平的时候，开关晶体管T321和T322被开启，在第二级的输出端得到输出信号O<2>。以此类推依次产生M-1个输出信号
这个实施例中，全局的布线只用到了一个正电压源和一个负电压源，减小了功耗和增强了电路的稳定性，在增强电路性能的同时，降低了版图布线耗费的面积。
图9所示为根据本申请一个实施例的一种显示器。该显示器可以包括栅极驱动电路91，数据驱动电路92，像素矩阵93，栅极驱动线94和数据驱动线95。这种显示器可以是液晶显示器，有机发光显示器，量子点发光显示器或电子纸显示器等。栅极驱动电路91产生扫描信号，并通过栅极驱动线94传递到像素矩阵93中，控制像素矩阵93逐行打开，以写入数据。而数据驱动电路92则产生每行所需的数据电压，通过数据驱动线95传递到像素矩阵内。本实施例中的栅极驱动电路可以包括本申请所提供的移位寄存器，如图6或图7所示。
图10所示为根据本申请一个实施例的产生栅极驱动信号方法的流程图。根据一个实施例，显示器的栅极驱动模块中的移位寄存器中包括多级移位寄存器单元，这个方法可以由除最后一级外的任一移位寄存器单元执行以下操作，其中每个移位寄存器单元包括输入存储模块、存储提取模块、输出驱动模块和下拉维持模块。
在步骤1002，输入存储模块接收并存储输入信号；
在步骤1004，存储提取模块至少在时钟信号的影响下将所存储的输入信号传输到输出驱动模块；
在步骤1006，输出驱动模块在所述存储提取模块的控制下将所述输入信号传输到输出端；
在步骤1008，下拉和维持模块在输出结束后将所述输出端的电压下拉到低电平并在所述输出驱动模块接收到下一个输入信号之前将所述输出端电压维持在低电平。
虽然已经通过例子对本申请的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上例子仅是为了进行说明，而不是为了限制本申请的范围。本领域的技术人员应该理解，可在不脱离本申请的范围和精神的情况下，对以上实施例进行修改。本申请的范围由所附权利要求来限定。

Claims (14)

  1. 一种移位寄存器单元电路，包括：
    输入存储模块，被配置为在输入端接收输入信号并存储所述输入信号；
    存储提取模块，被配置为至少在第一时钟信号的影响下从所述输入存储模块提取所述输入信号；
    输出驱动模块，被配置为在所述存储提取模块的控制下将所述输入信号传输到输出端；以及
    下拉和维持模块，被配置为在输出结束后将所述输出端的电压下拉到低电平并在所述输出驱动模块接收到下一个输入信号之前将所述输出端电压维持在低电平。
  2. 如权利要求1所述的电路，其中
    所述输入存储模块包括，存储电容被配置为存储所述输入信号，所述存储电容的第一端通过第一开关与所述输入端耦接，第二端通过第二开关与低电平耦接，所述第一开关和第二开关在所述输入信号的控制下开启或关闭；
    所述输出驱动模块包括，第一晶体管，所述第一晶体管包括与高电平耦接的第一极，以及与所述输出端和所述下拉和维持模块耦接的第二极，以及与所述存储提取模块耦接的第三极；
    所述存储提取模块包括，耦接在所述存储电容第一端以及所述第一晶体管第三极之间的第三开关，以及耦接在所述存储电容第二端以及所述输出端之间的第四开关，其中所述第一时钟信号影响所述第三和第四开关的开关状态。
  3. 如权利要求2所述的电路，其中所述输出驱动模块还包括第二晶体管，所述第二晶体管的第一极耦接到高电平，第二极耦接到第二输出端，第三极耦接到所述第一晶体管的第三极，其中所述第一晶体管的尺寸大于所述第二晶体管的尺寸。
  4. 如权利要求3所述的电路，其中所述第一开关是第三晶体管，包括耦接到所述输入端的第一极和第三极，以及耦接到所述存储电容第一端的第二极；所述第二开关是第四晶体管，包括耦接到所述存储电容第二端的第一极，耦接到低电平的第二极，和耦接到所述输入端的第三极，当所述输入信号为高电平时，所述第一和第二开关开启，所述存储电容充电。
  5. 如权利要求4所述的电路，其中所述第三开关是第五晶体管，包括耦接到所述存储电容第一端的第一极，耦接到所述第一晶体管第三极的第二极，和耦接到第一时钟信号输入端的第三极；所述第四开关是第六晶体管，包括耦接到所述存储电容第二端的第一极，耦接到所述输出端的第二极，和耦接到第一时钟信号输入端的第三极；所述第一时钟信号在所述存储电容充电结束后达到高电平，所述第三和第四开关开启。
  6. 如权利要求5所述的电路，其中所述存储提取模块还包括第七晶体管和第八晶体管，第七晶体管的第一极和第三极耦接到所述第一时钟信号输入端，第二极耦接到所述第五晶体管和第六晶体管的第三极，第八晶体管的第一极耦接到所述第七晶体管的第二极，第二极耦接到低电平，第三极耦接到放电控制信号输入端，使得在所述存储电容充电期间所述第三和第四开关处于关闭状态。
  7. 如权利要求2所述的电路，其中所述下拉和维持模块包括第九晶体管和第十晶体管，其中所述第九晶体管包括耦接到所述第一晶体管第三极的第一极，耦接到低电平的第二极，以及耦接到下拉和维持控制信号输入端的第三极，所述第十晶体管包括耦接到所述输出端的第一极，耦接到低电平的第二端，以及耦接到下拉和维持控制信号输入端的第三极。
  8. 如权利要求2所述的电路，其中所述下拉和维持模块包括下拉子模块和维持子模块，其中
    所述下拉子模块包括所述下拉子模块包括第十一和第十二晶体管，该两个晶体管的第二极都耦接到低电平，第三极都耦接到下拉控制信号输入端，其中第十一晶体管的第一极耦接到所述第一晶体管的第三极，第十二晶体管的第一极耦接到第一晶体管的第二极和所述输出端；
    所述维持子模块包括第十四和第十五晶体管，该两个晶体管的第二极都耦接到低电平，第三极都耦接到第二时钟信号输入端，其中第十四晶体管的第一极耦接到第一晶体管的第三极，第十五晶体管的第一极耦接到第一晶体管的第二极和所述输出端。
  9. 如权利要求3至7任一所述的电路，其中所述下拉和维持模块包括下拉子模块和维持子模块；
    所述下拉子模块包括第十一、第十二和第十三晶体管，该三个晶体管的第二极都耦接到低电平，第三极都耦接到一个下拉控制信号输入端，其中第十一晶体管的第一极耦接到 所述第一晶体管和第二晶体管的第三极，第十二晶体管的第一极耦接到第一晶体管的第二极和所述输出端，第十三晶体管的第一极耦接到第二晶体管的第二极和所述第二输出端；
    所述维持子模块包括第十四、第十五和第十六晶体管，该三个晶体管的第二极都耦接到低电平，第三极都耦接到第二时钟信号输入端，其中第十四晶体管的第一极耦接到第一晶体管和第二晶体管的第三极，第十五晶体管的第一极耦接到第一晶体管的第二极和所述输出端，第十六晶体管的第一极耦接到第二晶体管的第二极和所述第二输出端。
  10. 一种栅极驱动电路，包括移位寄存器，所述移位寄存器包括M个级连的单元，其中第1至M-1级所述单元包括如前述任一权利要求所述的电路，其中
    第N级的输入端耦接到第N-1级的第二输出端，第N级的下拉控制信号端耦接到第N+1级的第二输出端，第N级的放电控制信号输入端耦接到第N-2级的第二输出端，其中M为大于等于4的正整数，N为小于等于M-1但不小于3的正整数；
    其中第1级移位寄存器单元的输入端接收初始的输入信号，第1级的放电控制信号输入端接收初始的放电控制信号，第1级的下拉控制信号输入端耦接到第2级的第二输出端；以及第2级的放电控制信号输入端接收初始的输入信号，第2级的输入端耦接到第1级的第二输出端，第2级的下拉控制信号输入端耦接到第3级的第二输出端。
  11. 如权利要求10所述的栅极驱动电路，其中第M级移位寄存器单元具有如权利要求2所述的电路结构，其输出仅被配置向第M-1级单元提供下拉控制信号。
  12. 一种显示器，包括像素矩阵，与所述像素矩阵耦接的数据驱动电路，以及与所述像素矩阵耦接的如权利要求10或11所述的栅极驱动电路。
  13. 如权利要求12所述的显示器，其中所述显示器为TFT显示器，所述栅极驱动电路与所述像素矩阵形成在相同的基板上。
  14. 一种产生显示器栅极驱动信号的方法，包括显示器的栅极驱动中的移位寄存器中的每个单元执行以下操作，其中每个移位寄存器单元包括输入存储模块、存储提取模块、输出驱动模块和下拉维持模块，
    输入存储模块接收并存储输入信号；
    存储提取模块至少在时钟信号的影响下将所存储的输入信号传输到输出驱动模块；
    输出驱动模块在所述存储提取模块的控制下将所述输入信号传输到输出端；
    下拉和维持模块在输出结束后将所述输出端的电压下拉到低电平并在所述输出驱动模块接收到下一个输入信号之前将所述输出端电压维持在低电平。
PCT/CN2017/083983 2017-03-21 2017-05-11 栅极驱动电路 Ceased WO2018171015A1 (zh)

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