WO2018161400A1 - Tft基板中电极层的制作方法及柔性tft基板的制作方法 - Google Patents

Tft基板中电极层的制作方法及柔性tft基板的制作方法 Download PDF

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WO2018161400A1
WO2018161400A1 PCT/CN2017/080078 CN2017080078W WO2018161400A1 WO 2018161400 A1 WO2018161400 A1 WO 2018161400A1 CN 2017080078 W CN2017080078 W CN 2017080078W WO 2018161400 A1 WO2018161400 A1 WO 2018161400A1
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layer
tft substrate
electrode layer
fabricating
substrate
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王幸
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an electrode layer in a TFT substrate and a method for fabricating the same.
  • a flexible display is a display based on a flexible organic material as a substrate, which has the advantages of thinness, lightness, high contrast, fast response, wide viewing angle, high brightness, full color, etc., can be bent, folded, and even worn as a wearable body.
  • Part of the computer and therefore has a wide range of applications in special fields such as portable products and military applications, so flexible display technology has become the next generation of mainstream display technology.
  • An active matrix array (Array) substrate is used as a main structural part in current displays for providing a driving circuit to a display, and is usually provided with a plurality of gate scanning lines and a plurality of data lines, the plurality of gate scanning lines and a plurality of data lines.
  • the line defines a plurality of pixel units, each of which is provided with a thin film transistor (TFT) and a pixel electrode, and the gate of the thin film transistor is connected to the corresponding gate scan line, and the voltage on the gate scan line.
  • TFT thin film transistor
  • the gate of the thin film transistor is connected to the corresponding gate scan line, and the voltage on the gate scan line
  • the source and drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel electrode, thereby controlling the display of the corresponding pixel region.
  • the structure of the thin film transistor on the array substrate further includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, and an insulating protective layer which are stacked on the base substrate in this order from bottom to top.
  • Low Temperature Poly-Silicon (LTPS) thin film transistors have higher electron mobility and are displayed on liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs).
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the technology has received the attention of the industry and is regarded as an important material for realizing low-cost full-color flat panel display. Therefore, at present, flexible display devices mainly use array substrates of low temperature polysilicon thin film transistors.
  • the gate material of the low-temperature polysilicon thin film transistor mainly adopts a single-layer metal molybdenum. Due to the high hardness of the metal molybdenum itself, the transgranular fracture tends to increase in the bending process of the flexible display device, which eventually leads to slow current transmission and signal delay. The problem.
  • An object of the present invention is to provide a method for fabricating an electrode layer in a TFT substrate, which can realize fabrication of an electrode layer suitable for bending a flexible display device.
  • Another object of the present invention is to provide a method for fabricating a flexible TFT substrate, which can be used to form a gate electrode layer by using the above-described method for fabricating an electrode layer in a TFT substrate, which can effectively improve transgranularity during bending of the existing flexible display device.
  • the present invention first provides a method for fabricating an electrode layer in a TFT substrate, comprising the following steps:
  • Step 1 Providing a silicon substrate, forming a metal nickel layer on the silicon substrate;
  • Step 2 depositing a graphene layer on the metal nickel layer by chemical vapor deposition, and etching the graphene layer by plasma etching to form a patterned graphene layer;
  • Step 3 Dissolve the metallic nickel layer on the silicon substrate to separate the patterned graphene layer from the silicon substrate, and then transfer the patterned graphene layer to obtain an electrode layer of the TFT substrate.
  • the thickness of the metallic nickel layer formed in the step 1 is 10 to 50 nm.
  • the graphene layer formed by the deposition in the step 2 has a thickness of 5 to 10 nm.
  • the patterned graphene layer is positioned and transferred by means of alignment mark.
  • the TFT substrate is a flexible low temperature polysilicon TFT substrate.
  • the electrode layer formed in the step 3 is a gate electrode layer of the TFT substrate.
  • the present invention also provides a method for fabricating a flexible TFT substrate using the method for fabricating an electrode layer in the above TFT substrate, comprising the following steps:
  • Step 10 providing a glass substrate, forming a flexible substrate on the glass substrate;
  • Step 20 sequentially forming a buffer layer, an active layer, and a gate insulating layer on the flexible substrate;
  • Step 30 providing a silicon substrate, forming a metal nickel layer on the silicon substrate; depositing a graphene layer on the metal nickel layer by chemical vapor deposition, using a plasma etching method The graphene layer is etched to form a patterned graphene layer; the metallic nickel layer on the silicon substrate is dissolved, thereby separating the patterned graphene layer from the silicon substrate, and then patterning the graphene layer Transfer to the gate insulating layer to form a gate electrode layer;
  • Step 40 sequentially forming an interlayer insulating layer and a source/drain metal layer on the gate insulating layer and the gate electrode layer.
  • the flexible TFT substrate is a flexible low temperature polysilicon TFT substrate
  • the flexible substrate formed in the step 10 is a polyimide substrate, and has a thickness of 10 to 20 ⁇ m;
  • the thickness of the buffer layer, the active layer, and the gate insulating layer formed in the step 20 are respectively 200 to 300 nm, 40 to 50 nm, and 50 to 200 nm;
  • the thickness of the interlayer insulating layer and the source/drain metal layer formed in the step 40 is 500 to 700 nm and 400 to 600 nm, respectively.
  • the metal nickel layer formed in the step 30 has a thickness of 10 to 50 nm, and the deposited graphene layer has a thickness of 5 to 10 nm.
  • the patterned graphene layer is positioned and transferred onto the gate insulating layer by means of alignment marks.
  • the invention also provides a method for fabricating an electrode layer in a TFT substrate, comprising the following steps:
  • Step 1 Providing a silicon substrate, forming a metal nickel layer on the silicon substrate;
  • Step 2 depositing a graphene layer on the metal nickel layer by chemical vapor deposition, and etching the graphene layer by plasma etching to form a patterned graphene layer;
  • Step 3 dissolving the metal nickel layer on the silicon substrate, thereby separating the patterned graphene layer from the silicon substrate, and then transferring the patterned graphene layer to obtain an electrode layer of the TFT substrate;
  • the thickness of the metal nickel layer formed in the step 1 is 10 to 50 nm;
  • the thickness of the graphene layer deposited in the step 2 is 5-10 nm.
  • a metal nickel layer is first formed on a silicon substrate, and then a graphene layer is deposited on the metal nickel layer by chemical vapor deposition. And etching the graphene layer by plasma etching to form a patterned graphene layer, finally dissolving the metal nickel layer, separating the patterned graphene layer from the silicon substrate, and patterning the graphite
  • the electrode layer of the TFT substrate can be obtained by transferring the olefin layer, and the electrode layer using the graphene material has excellent electrical and mechanical properties, and has good thermal stability and chemical stability, and the manufacturing method is suitable for a flexible display device. Fabrication of a bent electrode layer.
  • the method for fabricating the flexible TFT substrate of the present invention adopts the above-mentioned method for fabricating the electrode layer in the TFT substrate to form the gate electrode layer, which can effectively improve the technique for increasing the resistance of the existing flexible display device during the bending process. problem.
  • FIG. 1 is a schematic flow chart of a method for fabricating an electrode layer in a TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step 1 of a method for fabricating an electrode layer in a TFT substrate of the present invention
  • 3-4 is a schematic view showing a step 2 of a method for fabricating an electrode layer in a TFT substrate of the present invention
  • FIG. 5 is a schematic view showing a step 3 of a method for fabricating an electrode layer in a TFT substrate of the present invention
  • FIG. 6 is a schematic flow chart of a method for fabricating a flexible TFT substrate of the present invention.
  • step 10 is a schematic diagram of step 10 of a method for fabricating a flexible TFT substrate of the present invention.
  • FIG. 8 is a schematic diagram of a step 20 of a method of fabricating a flexible TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 30 of a method of fabricating a flexible TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 40 of a method of fabricating a flexible TFT substrate of the present invention.
  • the present invention first provides a method for fabricating an electrode layer in a TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 2, a silicon substrate 200 is provided on which a metal nickel layer 300 is formed.
  • the thickness of the metallic nickel layer 300 formed in the step 1 is 10 to 50 nm.
  • Step 2 As shown in FIG. 3, a graphene layer 400 is deposited on the metal nickel layer 300 by chemical vapor deposition (CVD), as shown in FIG. The graphene layer 400 is etched to form a patterned graphene layer 405.
  • CVD chemical vapor deposition
  • the graphene layer 400 formed by the deposition in the step 2 has a thickness of 5 to 10 nm.
  • a graphene layer 400 is formed by plasma enhanced chemical vapor deposition (PECVD) deposition.
  • PECVD plasma enhanced chemical vapor deposition
  • Step 3 As shown in FIG. 5, the metallic nickel layer 300 on the silicon substrate 200 is dissolved, thereby separating the patterned graphene layer 405 from the silicon substrate 200, and then patterning the graphene layer 405. Transfer to obtain an electrode layer of the TFT substrate.
  • the patterned graphene layer 405 is positioned and transferred by means of alignment marks.
  • the metallic nickel layer 300 is dissolved using a dilute nitric acid solution.
  • the TFT substrate is a flexible low-temperature polysilicon TFT substrate.
  • the electrode layer formed in the step 3 is a gate electrode layer of the TFT substrate.
  • graphene has excellent electrical and mechanical properties, and has good thermal stability and chemical stability
  • graphene film material can be realized by chemical vapor deposition, and patterned by plasma etching.
  • a method of fabricating an electrode layer is formed by forming a metal nickel layer 300 on the silicon substrate 200, and then depositing a graphene layer 400 on the metal nickel layer 300 and etching it to form a patterned layer.
  • the graphene layer 405 finally dissolves the metallic nickel layer 300, and the electrode layer of the TFT substrate is obtained by transferring the patterned graphene layer 405, thereby realizing the fabrication of an electrode layer suitable for bending the flexible display device.
  • the present invention further provides a method for fabricating a flexible TFT substrate using the method, which specifically includes the following steps:
  • Step 10 as shown in FIG. 7, a glass substrate 100 is provided, and a flexible substrate 101 is formed on the glass substrate 100.
  • the flexible substrate 101 formed in the step 10 is a polyimide substrate and has a thickness of 10 to 20 ⁇ m.
  • Step 20 as shown in FIG. 8, a buffer layer 102, an active layer 103, and a gate insulating layer 104 are sequentially formed on the flexible substrate 101.
  • the buffer layer 102, the active layer 103, and the gate insulating layer 104 formed in the step 20 have thicknesses of 200 to 300 nm, 40 to 50 nm, and 50 to 200 nm, respectively.
  • the flexible TFT substrate is a flexible low-temperature polysilicon TFT substrate; the material of the active layer 103 is low-temperature polysilicon.
  • Step 30 as shown in FIG. 9, and in conjunction with FIG. 2 to FIG. 5, a silicon substrate 200 is formed on which a metal nickel layer 300 is formed; and the metal nickel is formed by chemical vapor deposition.
  • a layer of graphene 400 is deposited on layer 300, and the graphene layer 400 is etched by plasma etching to form a patterned graphene layer 405; the metal nickel layer 300 on the silicon substrate 200 is dissolved.
  • the patterned graphene layer 405 is separated from the silicon substrate 200, and then the patterned graphene layer 405 is transferred onto the gate insulating layer 104 to form the gate electrode layer 105.
  • the thickness of the metallic nickel layer 300 formed in the step 30 is 10 to 50 nm, and the thickness of the graphene layer 400 deposited is 5 to 10 nm.
  • the patterned graphene layer 405 is positioned and transferred onto the gate insulating layer 104 by means of alignment marks.
  • step 300 the metallic nickel layer 300 is dissolved using a dilute nitric acid solution.
  • Step 40 as shown in FIG. 10, an interlayer insulating layer 106 and a source/drain metal layer 107 are sequentially formed on the gate insulating layer 104 and the gate electrode layer 105.
  • the interlayer insulating layer 106 and the source/drain metal layer 107 formed in the step 40 have thicknesses of 500 to 700 nm and 400 to 600 nm, respectively.
  • the material of the gate electrode layer 105 formed in the step 30 is graphene, it has excellent electrical and mechanical properties, and has good thermal stability and chemical stability at the same time. Therefore, it is possible to effectively improve the technical problem that the prior art flexible display device using the metal molybdenum material as the gate electrode layer is prone to increase the resistance of the transgranular fracture during the bending process.
  • a metal nickel layer is first formed on a silicon substrate, and then a layer is deposited on the metal nickel layer by chemical vapor deposition. a graphene layer, and etching the graphene layer by a plasma etching method to form a patterned graphene layer, finally dissolving the metal nickel layer, separating the patterned graphene layer from the silicon substrate, and patterning
  • the electrode layer of the TFT substrate can be obtained by transferring the graphene layer, and the electrode layer using the graphene material has excellent electrical and mechanical properties, and has good thermal stability and chemical stability, and the manufacturing method is suitable for Fabrication of a bent electrode layer of a flexible display device.
  • the method for fabricating the flexible TFT substrate of the present invention adopts the above-mentioned method for fabricating the electrode layer in the TFT substrate to form the gate electrode layer, which can effectively improve the technique for increasing the resistance of the existing flexible display device during the bending process. problem.

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Abstract

本发明提供一种TFT基板中电极层的制作方法及柔性TFT基板的制作方法。本发明TFT基板中电极层的制作方法，首先在硅衬底上形成一层金属镍层，然后采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，并采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层，最后将金属镍层溶解掉，使图案化的石墨烯层与硅衬底分离，将图案化的石墨烯层转移即可得到TFT基板的电极层，采用石墨烯材料的电极层具有优秀的导电及机械性能，同时具有较好的热学稳定性及化学稳定性，该制作方法实现了适用于柔性显示装置弯折的电极层的制作。

Description

TFT基板中电极层的制作方法及柔性TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板中电极层的制作方法及柔性TFT基板的制作方法。
背景技术
在显示技术领域，柔性显示器是基于柔性有机材料作为基板的显示器，其具有薄而轻、高对比度、快速响应、宽视角、高亮度、全彩色等优点，可以被弯曲、折叠、甚至作为可穿戴计算机的一部分，因此在显示效果好的便携产品和军事等特殊领域有非常广泛的应用，因此柔性显示技术已然成为下一代主流显示技术。
有源矩阵阵列(Array)基板作为目前显示器中的主要结构部分，用于向显示器提供驱动电路，通常设置有数条栅极扫描线和数条数据线，该数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管(Thin Film Transistor，TFT)和像素电极，薄膜晶体管的栅极与相应的栅极扫描线相连，当栅极扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。通常阵列基板上薄膜晶体管的结构又包括自下而上依次层叠设置于衬底基板上的栅极、栅极绝缘层、有源层、源漏极、及绝缘保护层。
其中，低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管由于具有较高的电子迁移率，而在液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等显示技术中得到了业界的重视，被视为实现低成本全彩平板显示的重要材料。因此，目前柔性显示装置主要采用低温多晶硅薄膜晶体管的阵列基板。而低温多晶硅薄膜晶体管的栅极材料主要采用单层金属钼，由于金属钼本身硬度较大，在柔性显示装置弯折过程中易发生穿晶断裂致电阻增大，最终导致电流传输慢、信号延迟的问题。
针对上述问题，提出一种适用柔性显示弯折技术要求的电极层的制作方法是非常必要的。
发明内容
本发明的目的在于提供一种TFT基板中电极层的制作方法，能够实现适用于柔性显示装置弯折的电极层的制作。
本发明的另一目的在于提供一种柔性TFT基板的制作方法，采用上述的TFT基板中电极层的制作方法来形成栅电极层，能够有效改善现有柔性显示装置弯折过程中易发生穿晶断裂致电阻增大的技术问题。
为实现上述目的，本发明首先提供一种TFT基板中电极层的制作方法，包括如下步骤：
步骤1、提供一硅衬底，在所述硅衬底上形成一层金属镍层；
步骤2、采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层；
步骤3、将所述硅衬底上的金属镍层溶解掉，从而使图案化的石墨烯层与硅衬底分离，然后将图案化的石墨烯层转移，得到TFT基板的电极层。
所述步骤1中所形成的金属镍层的厚度为10～50nm。
所述步骤2中所沉积形成的石墨烯层的厚度为5～10nm。
所述步骤3中通过对位标记的方式将图案化的石墨烯层定位转移。
所述TFT基板为柔性的低温多晶硅TFT基板。
所述步骤3中形成的电极层为TFT基板的栅电极层。
本发明还提供一种使用上述TFT基板中电极层制作方法的柔性TFT基板的制作方法，包括如下步骤：
步骤10、提供玻璃基板，在所述玻璃基板上形成柔性基板；
步骤20、在柔性基板上依次形成缓冲层、有源层、栅极绝缘层；
步骤30、提供一硅衬底，在所述硅衬底上形成一层金属镍层；采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层；将所述硅衬底上的金属镍层溶解掉，从而使图案化的石墨烯层与硅衬底分离，然后将图案化的石墨烯层转移到栅极绝缘层上，形成栅电极层；
步骤40、在栅极绝缘层、及栅电极层上依次形成层间绝缘层、源漏金属层。
所述柔性TFT基板为柔性的低温多晶硅TFT基板；
所述步骤10中所形成的柔性基板为聚酰亚胺基板，厚度为10～20μm；
所述步骤20中所形成的缓冲层、有源层、及栅极绝缘层的厚度分别为200～300nm、40～50nm、50～200nm；
所述步骤40中所形成的层间绝缘层、及源漏金属层的厚度分别为500～700nm、400～600nm。
所述步骤30中所形成的金属镍层的厚度为10～50nm，所沉积形成的石墨烯层的厚度为5～10nm。
所述步骤30中，通过对位标记的方式，将所述图案化的石墨烯层定位转移到栅极绝缘层上。
本发明还提供一种TFT基板中电极层的制作方法，包括如下步骤：
步骤1、提供一硅衬底，在所述硅衬底上形成一层金属镍层；
步骤2、采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层；
步骤3、将所述硅衬底上的金属镍层溶解掉，从而使图案化的石墨烯层与硅衬底分离，然后将图案化的石墨烯层转移，得到TFT基板的电极层；
其中，所述步骤1中所形成的金属镍层的厚度为10～50nm；
其中，所述步骤2中所沉积形成的石墨烯层的厚度为5～10nm。
本发明的有益效果：本发明的TFT基板中电极层的制作方法，首先在硅衬底上形成一层金属镍层，然后采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，并采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层，最后将金属镍层溶解掉，使图案化的石墨烯层与硅衬底分离，将图案化的石墨烯层转移即可得到TFT基板的电极层，采用石墨烯材料的电极层具有优秀的导电及机械性能，同时具有较好的热学稳定性及化学稳定性，该制作方法实现了适用于柔性显示装置弯折的电极层的制作。本发明的柔性TFT基板的制作方法，采用上述的TFT基板中电极层的制作方法来形成栅电极层，能够有效改善现有柔性显示装置弯折过程中易发生穿晶断裂致电阻增大的技术问题。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的TFT基板中电极层的制作方法的流程示意图；
图2为本发明的TFT基板中电极层的制作方法的步骤1的示意图；
图3-4为本发明的TFT基板中电极层的制作方法的步骤2的示意图；
图5为本发明的TFT基板中电极层的制作方法的步骤3的示意图；
图6为本发明的柔性TFT基板的制作方法的流程示意图；
图7为本发明的柔性TFT基板的制作方法的步骤10的示意图；
图8为本发明的柔性TFT基板的制作方法的步骤20的示意图；
图9为本发明的柔性TFT基板的制作方法的步骤30的示意图；
图10为本发明的柔性TFT基板的制作方法的步骤40的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种TFT基板中电极层的制作方法，包括如下步骤：
步骤1、如图2所示，提供一硅衬底200，在所述硅衬底200上形成一层金属镍层300。
具体地，所述步骤1中所形成的金属镍层300的厚度为10～50nm。
步骤2、如图3所示，采用化学气相沉积法(Chemical Vapour Deposition，CVD)在所述金属镍层300上沉积一层石墨烯层400，如图4所示，采用等离子体蚀刻法对所述石墨烯层400进行蚀刻，形成图案化的石墨烯层405。
具体地，所述步骤2中所沉积形成的石墨烯层400的厚度为5～10nm。
具体地，所述步骤2中采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积形成石墨烯层400。
步骤3、如图5所示，将所述硅衬底200上的金属镍层300溶解掉，从而使图案化的石墨烯层405与硅衬底200分离，然后将图案化的石墨烯层405转移，得到TFT基板的电极层。
具体地，所述步骤3中通过对位标记的方式将图案化的石墨烯层405定位转移。
具体地，所述步骤3中采用稀硝酸溶液将金属镍层300溶解掉。
具体地，所述TFT基板为柔性的低温多晶硅TFT基板。
具体地，所述步骤3中形成的电极层为TFT基板的栅电极层。
由于石墨烯具有优秀的导电及机械性能，同时具有较好的热学稳定性及化学稳定性，且石墨烯的薄膜材料可通过化学气相沉积的方法实现，通过等离子体蚀刻法实现图案化，因此，本发明的TFT基板中电极层的制作方法，通过在硅衬底200上形成一层金属镍层300，然后再在金属镍层300上沉积一层石墨烯层400并进行蚀刻，形成图案化的石墨烯层405，最后将金属镍层300溶解掉，通过将图案化的石墨烯层405转移而得到TFT基板的电极层，实现了适用于柔性显示装置弯折的电极层的制作。
请参阅图6，在上述TFT基板中电极层的制作方法的基础上，本发明还提供一种使用该方法的柔性TFT基板的制作方法，具体包括如下步骤：
步骤10、如图7所示，提供玻璃基板100，在所述玻璃基板100上形成柔性基板101。
具体地，所述步骤10中所形成的柔性基板101为聚酰亚胺基板，厚度为10～20μm。
步骤20、如图8所示，在柔性基板101上依次形成缓冲层102、有源层103、栅极绝缘层104。
具体地，所述步骤20中所形成的缓冲层102、有源层103、及栅极绝缘层104的厚度分别为200～300nm、40～50nm、50～200nm。
具体地，所述柔性TFT基板为柔性的低温多晶硅TFT基板；所述有源层103的材料为低温多晶硅。
步骤30、如图9所示，并结合图2至图5，提供一硅衬底200，在所述硅衬底200上形成一层金属镍层300；采用化学气相沉积法在所述金属镍层300上沉积一层石墨烯层400，采用等离子体蚀刻法对所述石墨烯层400进行蚀刻，形成图案化的石墨烯层405；将所述硅衬底200上的金属镍层300溶解掉，从而使图案化的石墨烯层405与硅衬底200分离，然后将图案化的石墨烯层405转移到栅极绝缘层104上，形成栅电极层105。
具体地，所述步骤30中所形成的金属镍层300的厚度为10～50nm，所沉积形成的石墨烯层400的厚度为5～10nm。
具体地，所述步骤30中，通过对位标记的方式，将所述图案化的石墨烯层405定位转移到栅极绝缘层104上。
具体地，所述步骤300中采用稀硝酸溶液将金属镍层300溶解掉。
步骤40、如图10所示，在栅极绝缘层104、及栅电极层105上依次形成层间绝缘层106、源漏金属层107。
具体地，所述步骤40中所形成的层间绝缘层106、及源漏金属层107的厚度分别为500～700nm、400～600nm。
本发明的柔性TFT基板的制作方法，由于所述步骤30中形成的栅电极层105的材料为石墨烯，具有优秀的导电及机械性能，并同时具有较好的热学稳定性及化学稳定性，因此，能够有效改善现有采用金属钼材料作为栅电极层的柔性显示装置在弯折过程中易发生穿晶断裂致电阻增大的技术问题。
综上所述，本发明的TFT基板中电极层的制作方法，首先在硅衬底上形成一层金属镍层，然后采用化学气相沉积法在所述金属镍层上沉积一层 石墨烯层，并采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层，最后将金属镍层溶解掉，使图案化的石墨烯层与硅衬底分离，将图案化的石墨烯层转移即可得到TFT基板的电极层，采用石墨烯材料的电极层具有优秀的导电及机械性能，同时具有较好的热学稳定性及化学稳定性，该制作方法实现了适用于柔性显示装置弯折的电极层的制作。本发明的柔性TFT基板的制作方法，采用上述的TFT基板中电极层的制作方法来形成栅电极层，能够有效改善现有柔性显示装置弯折过程中易发生穿晶断裂致电阻增大的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种TFT基板中电极层的制作方法，包括如下步骤：
    步骤1、提供一硅衬底，在所述硅衬底上形成一层金属镍层；
    步骤2、采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层；
    步骤3、将所述硅衬底上的金属镍层溶解掉，从而使图案化的石墨烯层与硅衬底分离，然后将图案化的石墨烯层转移，得到TFT基板的电极层。
  2. 如权利要求1所述的TFT基板中电极层的制作方法，其中，所述步骤1中所形成的金属镍层的厚度为10～50nm。
  3. 如权利要求1所述的TFT基板中电极层的制作方法，其中，所述步骤2中所沉积形成的石墨烯层的厚度为5～10nm。
  4. 如权利要求1所述的TFT基板中电极层的制作方法，其中，所述步骤3中通过对位标记的方式将图案化的石墨烯层定位转移。
  5. 如权利要求1所述的TFT基板中电极层的制作方法，其中，所述TFT基板为柔性的低温多晶硅TFT基板。
  6. 如权利要求1所述的TFT基板中电极层的制作方法，其中，所述步骤3中形成的电极层为TFT基板的栅电极层。
  7. 一种柔性TFT基板的制作方法，包括如下步骤：
    步骤10、提供玻璃基板，在所述玻璃基板上形成柔性基板；
    步骤20、在柔性基板上依次形成缓冲层、有源层、栅极绝缘层；
    步骤30、提供一硅衬底，在所述硅衬底上形成一层金属镍层；采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层；将所述硅衬底上的金属镍层溶解掉，从而使图案化的石墨烯层与硅衬底分离，然后将图案化的石墨烯层转移到栅极绝缘层上，形成栅电极层；
    步骤40、在栅极绝缘层、及栅电极层上依次形成层间绝缘层、源漏金属层。
  8. 如权利要求7所述的柔性TFT基板的制作方法，其中，所述柔性TFT基板为柔性的低温多晶硅TFT基板；
    所述步骤10中所形成的柔性基板为聚酰亚胺基板，厚度为10～20μm；
    所述步骤20中所形成的缓冲层、有源层、及栅极绝缘层的厚度分别为200～300nm、40～50nm、50～200nm；
    所述步骤40中所形成的层间绝缘层、及源漏金属层的厚度分别为500～700nm、400～600nm。
  9. 如权利要求7所述的柔性TFT基板的制作方法，其中，所述步骤30中所形成的金属镍层的厚度为10～50nm，所沉积形成的石墨烯层的厚度为5～10nm。
  10. 如权利要求7所述的柔性TFT基板的制作方法，其中，所述步骤30中，通过对位标记的方式，将所述图案化的石墨烯层定位转移到栅极绝缘层上。
  11. 一种TFT基板中电极层的制作方法，包括如下步骤：
    步骤1、提供一硅衬底，在所述硅衬底上形成一层金属镍层；
    步骤2、采用化学气相沉积法在所述金属镍层上沉积一层石墨烯层，采用等离子体蚀刻法对所述石墨烯层进行蚀刻，形成图案化的石墨烯层；
    步骤3、将所述硅衬底上的金属镍层溶解掉，从而使图案化的石墨烯层与硅衬底分离，然后将图案化的石墨烯层转移，得到TFT基板的电极层；
    其中，所述步骤1中所形成的金属镍层的厚度为10～50nm；
    其中，所述步骤2中所沉积形成的石墨烯层的厚度为5～10nm。
  12. 如权利要求11所述的TFT基板中电极层的制作方法，其中，所述步骤3中通过对位标记的方式将图案化的石墨烯层定位转移。
  13. 如权利要求11所述的TFT基板中电极层的制作方法，其中，所述TFT基板为柔性的低温多晶硅TFT基板。
  14. 如权利要求11所述的TFT基板中电极层的制作方法，其中，所述步骤3中形成的电极层为TFT基板的栅电极层。
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