WO2018153077A1 - 移位寄存单元、移位寄存器、栅极驱动电路和显示面板 - Google Patents

移位寄存单元、移位寄存器、栅极驱动电路和显示面板 Download PDF

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Publication number
WO2018153077A1
WO2018153077A1 PCT/CN2017/102683 CN2017102683W WO2018153077A1 WO 2018153077 A1 WO2018153077 A1 WO 2018153077A1 CN 2017102683 W CN2017102683 W CN 2017102683W WO 2018153077 A1 WO2018153077 A1 WO 2018153077A1
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WIPO (PCT)
Prior art keywords
pull
module
frame
electrically connected
transistor
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PCT/CN2017/102683
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English (en)
French (fr)
Inventor
马明超
樊君
山岳
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/776,980 priority Critical patent/US10950324B2/en
Publication of WO2018153077A1 publication Critical patent/WO2018153077A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/04—Shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register including the shift register unit, a gate drive circuit including the shift register, and a gate including the same The display panel of the drive circuit.
  • the shift register of the gate drive circuit is usually integrated on the array substrate.
  • the shift register includes cascaded multi-stage shift register units, and typically, each shift register unit includes a plurality of transistors.
  • each shift register unit includes a plurality of transistors.
  • the present disclosure provides a shift register unit, a shift register including the shift register unit, a gate drive circuit including the shift register, and a display panel including the gate drive circuit.
  • the shift register unit has a long service life.
  • a shift register unit operating time including a plurality of multi-frame periods, each multi-frame period including a plurality of frame periods, Each frame period includes at least one duty cycle, and the shift register unit includes a trigger signal input end, an input module, a pull-up module, a pull-down control module, a plurality of pull-down modules, and a signal output end.
  • the trigger signal input end is electrically connected to the control end of the input module, and the trigger signal input end is configured to provide a valid signal to the control end of the input module at an input stage of the shift register unit;
  • An output end of the input module is electrically connected to a control end of the pull-up module, and the input module is configured to be configured to receive a valid signal when the control terminal of the input module receives the valid signal The control terminal of the pull module provides a valid signal;
  • An input end of the pull-up module is electrically connected to an initial signal end, an output end of the pull-up module is electrically connected to the signal output end, and the pull-up module is configured to receive an effective at a control end of the pull-up module When the signal is sent, the input end of the pull-up module is electrically connected to the output end of the pull-up module;
  • each of the pull-down modules is electrically connected to the second level signal end, and the first output end of each of the pull-down modules is electrically connected to the signal output end, and the second output of each of the pull-down modules
  • the output ends are electrically connected to the control end of the pull-up module.
  • the input end of the pull-down module and the first end of the pull-down module are The output end and the second output end of the pull-down module are electrically connected;
  • the pull-down control module includes a plurality of pull-down control signal outputs, and the plurality of pull-down control signal outputs are respectively electrically connected to control ends of the respective pull-down modules, and the pull-down control module is configured to be in the same multi-frame period
  • the pull-down phase of each frame period sequentially provides a valid signal to the control terminals of each of the pull-down modules, so that each of the pull-down modules is turned on in different frame periods.
  • each of the multi-frame periods includes an odd frame period and an even frame period that alternate with each other, and the pull-down module includes an odd frame pull-down module and an even-frame pull-down module.
  • the pull-down control module is configured to output a valid signal to a control end of the odd frame pull-down module during a pull-down phase of each odd frame period, and output an invalid signal to a control end of the even frame pull-down module,
  • the pull-down control module is configured to output a valid signal to a control end of the even-numbered frame pull-down module during a pull-down phase of each even frame period, and can output an invalid signal to a control end of the odd-numbered frame pull-down module.
  • the pull-down control module includes a pull-down control sub-module, an odd-frame trigger sub-module, and an even-frame trigger sub-module, where the odd-numbered frame triggers the first output end of the sub-module and the second output of the even-numbered frame pull-down module
  • the terminals are electrically connected to each other as a first output end of the pull-down control module, and the second output end of the odd-numbered frame pull-down module and the first output end of the even-numbered frame trigger sub-module are electrically connected to each other as the pull-down control module Second output;
  • the shift register unit further includes a first frame type signal input end and a second frame type signal input end,
  • the pull-down control sub-module is configured to output a valid signal in a pull-down phase of each frame
  • the control end of the odd frame triggering submodule is electrically connected to the first frame type signal input end, and the first input end of the odd frame triggering submodule is electrically connected to the output end of the pulldown control submodule,
  • the second input end of the odd frame triggering sub-module is electrically connected to the second level signal end, and the first output end of the odd frame triggering sub-module is electrically connected to the control end of the even-numbered frame pull-down module, the odd number
  • the second output end of the frame triggering submodule is electrically connected to the control end of the odd frame pulldown module, and the odd frame triggering submodule is configured to trigger the submodule of the odd frame when the control terminal receives the valid signal
  • the second input end is electrically connected to the first output end of the odd frame triggering submodule, and electrically connects the first input end of the odd frame triggering submodule to the second output end of the odd frame triggering submodule;
  • the control end of the even frame triggering submodule is electrically connected to the second frame type signal input end, and the first input end of the even frame triggering submodule is electrically connected to the output end of the pulldown control submodule,
  • the second input end of the even frame triggering submodule is electrically connected to the second level signal end, and the first output end of the even frame triggering submodule is electrically connected to the control end of the odd frame pulldown module, the even number
  • the second output end of the frame triggering sub-module is electrically connected to the control end of the even-numbered frame pull-down module, and the even-numbered frame triggering sub-module is configured to trigger the sub-module of the even-numbered frame when the control terminal receives the valid signal
  • the second input is electrically connected to the first output of the even frame triggering submodule, and electrically connects the first input of the even frame triggering submodule to the second output of the even frame triggering submodule.
  • the odd frame trigger submodule includes a first odd frame trigger transistor and a second odd frame trigger transistor,
  • the gate of the first odd frame trigger transistor is electrically connected to the first frame type signal input end, and the first pole of the first odd frame trigger transistor and the first input end of the odd frame trigger submodule are electrically Connected, the second pole of the first odd frame trigger transistor is electrically connected to the second output end of the odd frame trigger submodule,
  • a gate of the second odd frame trigger transistor is electrically connected to the first frame type signal input end, and a first pole of the second odd frame trigger transistor is electrically connected to the second level signal end, a second pole of the second odd frame trigger transistor and the odd frame trigger
  • the first output of the module is electrically connected.
  • the even frame trigger submodule includes a first even frame trigger transistor and a second even frame trigger transistor,
  • the gate of the first even frame trigger transistor is electrically connected to the second frame type signal input end, and the first pole of the first even frame trigger transistor and the first input end of the even frame trigger submodule are electrically Connecting, the second pole of the first even frame triggering transistor is electrically connected to the second output end of the even frame triggering submodule;
  • a gate of the second even frame trigger transistor is electrically connected to the second frame type signal input end, and a first pole of the second even frame trigger transistor is electrically connected to the second level signal end, A second pole of the second even frame trigger transistor is electrically coupled to the first output of the even frame trigger sub-module.
  • the odd frame pull-down module includes a first odd frame pull-down transistor, a second odd frame pull-down transistor, and a third odd frame pull-down transistor;
  • a gate of the first odd frame pull-down transistor is electrically connected to a control end of the odd frame pull-down module, and a first pole of the first odd frame pull-down transistor is electrically connected to the signal output end, the first odd number a second pole of the frame pull-down transistor is electrically connected to the second level signal terminal;
  • a first pole of the second odd frame pull-down transistor is electrically connected to a control end of the pull-up module, and a second pole of the second odd-frame pull-down transistor is electrically connected to the second level signal terminal, a gate of the second odd transistor is electrically connected to a control end of the odd frame pull-down module;
  • a gate of the third odd frame pull-down transistor is electrically connected to a control end of the pull-up module, and a first pole of the third odd-frame pull-down transistor is electrically connected to a control end of the odd frame pull-down module, A second pole of the third odd frame pull-down transistor is electrically coupled to the second level signal terminal.
  • the odd frame pull-down transistor further includes a first storage capacitor, a first end of the first storage capacitor is electrically connected to a control end of the odd frame pull-down module, and a second end of the first storage capacitor And electrically connected to the second level signal terminal.
  • the even frame pull-down module includes a first even frame pull-down transistor, a second even frame pull-down transistor, and a third even frame pull-down transistor.
  • a gate of the first even frame pull-down transistor is electrically connected to a control end of the even frame pull-down module, and a first pole of the first even frame pull-down transistor is electrically connected to the signal output end, the first even number
  • the second pole of the frame pull-down transistor is electrically connected to the second level signal terminal;
  • a gate of the second even frame pull-down transistor is electrically connected to a control end of the even frame pull-down module, and a first pole of the second even frame pull-down transistor is electrically connected to a control end of the pull-up module, a second pole of the second even frame pull-down transistor is electrically connected to the second level signal terminal;
  • a gate of the third even frame pull-down transistor is electrically connected to a control end of the pull-up module, and a first pole of the third even-frame pull-down transistor is electrically connected to the second level signal end, where the The second pole of the three even frame pull-down transistor is electrically coupled to the control terminal of the even frame pull-down module.
  • the even frame pull-down module further includes a second storage capacitor, a first end of the second storage capacitor is electrically connected to a control end of the even frame pull-down module, and a second end of the second storage capacitor is And electrically connected to the second level signal terminal.
  • the input module includes a forward input module and a reverse input module
  • the shift register unit includes a forward signal end and a reverse signal end
  • the trigger signal input end includes a forward trigger signal input end and a reverse trigger signal input terminal
  • the pull-down control sub-module includes a forward pull-down control sub-module and a reverse pull-down control sub-module
  • the control end of the forward input module is electrically connected to the forward trigger signal input end, and the input end of the forward input module is electrically connected to the forward signal end, and the output end of the forward input module is The output end of the input module is electrically connected;
  • the control end of the reverse input module is electrically connected to the reverse trigger signal input end, the input end of the reverse input module is electrically connected to the reverse signal end, and the output end of the reverse input module is The control end of the pull-up module is electrically connected;
  • the control end of the forward pull-down control sub-module is electrically connected to the forward signal end, and the input end of the forward pull-down control sub-module is electrically connected to the second clock signal end, and the forward pull-down control sub-module
  • the output end is electrically connected to the output end of the reverse pull-down control sub-module, and is electrically connected to the first input end of the odd frame trigger sub-module and the first input end of the even-numbered frame trigger sub-module;
  • the control end of the reverse pull-down control sub-module is electrically connected to the reverse signal end, and the input end of the reverse pull-down control sub-module is electrically connected to the fourth clock signal end, and the reverse pull-down control sub-module The output is electrically connected to the output of the forward pull-down control sub-module.
  • the forward input module is configured to electrically connect an input end of the forward input module to an output end of the forward input module when a control end thereof receives a valid signal;
  • the reverse input module is configured to electrically connect an input end of the reverse input module to an output end of the reverse input module when a control end thereof receives a valid signal;
  • the forward pull-down control sub-module is configured to output a valid signal provided by the forward signal terminal when the positive signal terminal provides a valid signal and the reverse signal terminal provides an invalid signal;
  • the reverse pull-down control sub-module is configured to output a valid signal provided by the reverse signal terminal when the forward signal terminal provides an invalid signal and the reverse signal terminal provides a valid signal.
  • the forward input module includes a forward input transistor, and a gate of the forward input transistor is electrically connected to a control end of the forward input module, and a first pole of the forward input transistor The input terminal of the forward input module is electrically connected, and the second pole of the forward input transistor is electrically connected to the output of the forward input module.
  • the reverse input module includes an inverting input transistor, a gate of the inverting input transistor is electrically connected to a control end of the inverting input module, and a first pole of the inverting input transistor is The input of the inverting input module is electrically connected, and the second pole of the inverting input transistor is electrically connected to the output of the inverting input module.
  • the forward pull-down control sub-module includes a first forward pull-down control transistor and a second forward pull-down control transistor,
  • a gate of the first forward pull-down control transistor is electrically connected to a control end of the forward pull-down control sub-module, and a first pole of the first forward pull-down control transistor is electrically connected to the second clock signal end The second pole of the first forward pull-down control transistor is electrically connected to the gate of the second pull-down control transistor;
  • the first forward pull-down control transistor has a first pole and the second clock signal end Electrically connected, a second pole of the second forward pull-down control transistor is electrically coupled to an output of the forward pull-down control sub-module.
  • the reverse pull-down control sub-module includes a first reverse pull-down control transistor and a second reverse pull-down control transistor,
  • a gate of the first reverse pull-down control transistor is electrically connected to the reverse signal terminal, and a first pole of the first reverse pull-down control transistor is electrically connected to the fourth clock signal terminal, the first a second pole of the reverse pull-down control transistor is electrically connected to a gate of the second reverse pull-down control transistor;
  • a first pole of the second reverse pull-down control transistor is electrically connected to the fourth clock signal end, and a second pole of the second reverse pull-down control transistor is electrically connected to an output end of the reverse pull-down control submodule connection.
  • the pull-up module includes a pull-up transistor and a third storage capacitor, and the initial signal end includes a first clock signal end.
  • a gate of the pull-up transistor is electrically connected to a control end of the pull-up module, a first pole of the pull-up transistor is electrically connected to the first clock signal end, and a second pole of the pull-up transistor is The signal output ends are electrically connected;
  • the first end of the third storage capacitor is electrically connected to the gate of the pull-up transistor, and the second end of the third storage capacitor is electrically connected to the signal output end.
  • a shift register including a plurality of cascaded shift register units, wherein each of the plurality of shift register units is an open space
  • the above shift register unit is provided.
  • a gate driving circuit including a shift register and a frame signal judging unit, and the shift register is the above shift register provided by the present disclosure
  • the frame signal determination unit is configured to output a frame trigger signal indicating the number of frames to the shift register unit.
  • a display panel including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present disclosure.
  • FIG. 1 is a block diagram of a shift register unit provided by the present disclosure
  • FIG. 2 is a schematic circuit diagram of a shift register unit provided by the present disclosure
  • 3 is a timing chart of one duty cycle of the shift register unit
  • FIG. 4 is a schematic diagram of a gate driving circuit provided by the present disclosure.
  • Figure 5 is a timing chart at the time of forward scanning
  • Fig. 6 is a timing chart at the time of reverse scanning.
  • a shift register unit wherein a working time of the shift register unit includes a plurality of multi-frame periods, each multi-frame period including a plurality of different frame periods, as shown in FIG.
  • the shift register unit includes a trigger signal input terminal INPUT, an input module 100, a pull-up module 200, a pull-down control module 300, and a plurality of pull-down modules and a signal output terminal OUTPUT.
  • the trigger signal input terminal INPUT is electrically connected to the control terminal of the input module 100, and the trigger signal input terminal INPUT is capable of providing a valid signal to the control terminal of the input module at the input stage of the shift register unit.
  • the output end of the input module 100 is electrically connected to the control terminal PU of the pull-up module 200.
  • the input module 100 can provide a valid signal to the control terminal PU of the pull-up module 200 when the control terminal of the input module 100 receives the valid signal.
  • the input end of the pull-up module 200 is electrically connected to the initial signal end, the output end of the pull-up module 200 is electrically connected to the signal output end OUTPUT, and the pull-up module 200 can receive a valid signal when the control terminal PU of the pull-up module 200 receives the valid signal.
  • the input end of the pull-up module 200 is electrically connected to the output end of the pull-up module 200.
  • each pull-down module is electrically connected to the second level signal terminal VGL
  • each The first output end of the pull-down module is electrically connected to the signal output terminal OUTPUT
  • the second output end of each pull-down module is electrically connected to the control terminal PU of the pull-up module 200.
  • the input terminal of the pull-down module is electrically connected to each output terminal.
  • the second level signal terminal VGL is electrically connected to the signal output terminal OUTPUT and the control terminal PU of the pull-up module 200, respectively, to utilize the second level signal terminal VGL pair.
  • the signal output terminal OUTPUT and the control terminal PU of the pull-up module 200 are discharged.
  • the pull-down control module 300 includes a plurality of pull-down control signal outputs, each of which is electrically connected to a control end of each of the pull-down modules, and the pull-down control module 300 can be in a pull-down phase of each frame period of the same multi-frame period.
  • a valid signal is sequentially provided to the control terminals of each of the pull-down modules such that each of the pull-down modules is turned on at different frame periods.
  • one multi-frame period of the shift register unit here is a display phase of the display device including the shift register unit.
  • a multi-frame image is displayed in each display phase, and accordingly, one of the multi-frame images is displayed in each of one multi-frame period of the shift register unit.
  • a scan signal is supplied to a plurality of gate lines of the display panel by using a shift register including the shift register unit, a plurality of pull-down modules operate in turn in one multi-frame period.
  • a pull-down module when a pull-down module is working (for example, turned on), the remaining pull-down modules are in a non-on state. For example, in one frame period, only one of the multiple pull-down modules works.
  • the pull-down time of each pull-down module is short, and therefore, each pull-down module has a long service life, thereby extending The service life of the shift register unit.
  • the pull-down time of each pull-down module is short, the pull-down module has better electrical performance (for example, each transistor is not easily aged, etc.), and can meet the requirements of high reliability products.
  • each signal output terminal OUTPUT is electrically connected to a corresponding one of the gate lines in the display panel, that is, the shift register unit supplies a scan signal to the corresponding gate line.
  • One frame period may include at least one duty cycle, and each duty cycle may include an output phase, an input phase, and a pulldown phase.
  • the number of duty cycles in one frame period may be the same as the number of gate lines in the display panel, but the present disclosure is not limited thereto.
  • the signal outputted by the signal output terminal OUTPUT is the signal provided by the initial signal end.
  • the initial signal end may be the first clock signal terminal CLK1 shown in FIG. 2.
  • the initial signal end may be a power signal output end (for example, a high level signal terminal VDD). The producer can select the type of the initial signal end according to the specific needs.
  • each of the multi-frame periods includes an odd frame period and an even frame period alternate with each other
  • the pull-down module includes an odd frame pull-down module 410 and an even-frame pull-down module 420.
  • the pull-down control module 300 outputs a valid signal to the control terminal PD1 of the odd-frame pull-down module 410 during the pull-down phase of the odd frame period, so that the input end of the odd-frame pull-down module is electrically connected to the output terminal, and the pull-down control module 300 pulls down the even-numbered frame.
  • the control terminal PD2 of the module 420 outputs an invalid signal to control the even frame pull-down module 420 not to operate.
  • the pull-down control module 300 outputs a valid signal to the control terminal PD2 of the even-numbered frame pull-down module 420 during the pull-down phase of the even frame period, so that the input end of the even-numbered frame pull-down module is electrically connected to the output terminal, and to the odd-numbered frame pull-down module 410
  • the control terminal PD1 outputs an invalid signal to control the odd frame pull-down module 410 to be inoperative.
  • Simultaneously setting the odd frame pull-down module 410 and the even frame pull-down module 420 in the shift register unit can extend the overall service life of the shift register unit and facilitate processing and manufacturing.
  • the specific structure of the pull-down control module 300 is not particularly limited.
  • the pull-down control module 300 includes a pull-down control sub-module 310, an odd-frame trigger sub-module 320, and an even-frame trigger sub-module 330, and correspondingly, the first output of the odd-frame trigger sub-module 320
  • the second outputs of the end and even frame triggering sub-modules 330 are electrically connected to each other as a first output of the pull-down control module 300, a second output of the odd-frame triggering sub-module 320, and a first output of the even-frame triggering sub-module 330
  • the terminals are electrically connected to each other as a second output of the pull-down control module 300.
  • the shift register unit further includes a first frame type signal input terminal GCH1 and a second frame class signal input terminal GCH2.
  • the pull-down control sub-module 310 is capable of outputting a valid signal during the pull-down phase of each frame.
  • the control end of the odd frame trigger sub-module 320 is electrically connected to the first frame type signal input terminal GCH1, and the first input end of the odd frame trigger sub-module 320 is electrically connected to the output end of the pull-down control sub-module 310, the odd frame trigger
  • the second input end of the module is electrically connected to the second level signal terminal VGL
  • the first output end of the odd frame triggering submodule is electrically connected to the control end PD2 of the even frame pulldown module 420
  • the odd frame triggering submodule 320 is The two outputs are electrically connected to the control terminal PD1 of the odd frame pull-down module 410.
  • the second input end of the odd frame triggering sub-module 320 is electrically connected to the first output end of the odd-numbered frame triggering sub-module 320, and the odd-numbered frame triggering sub-module A first input of 320 is electrically coupled to a second output of the odd frame trigger sub-module 320.
  • the control end of the even frame triggering sub-module 330 is electrically connected to the second frame type signal input terminal GCH2, the first input end of the even frame triggering sub-module 330 is electrically connected to the output end of the pull-down control sub-module 310, and the even-numbered frame triggering sub-module 330
  • the second input terminal is electrically connected to the second level signal terminal VGL
  • the first output terminal of the even frame triggering submodule 330 is electrically connected to the control terminal PD1 of the odd frame pulldown module 410
  • the second frame of the even frame triggering submodule 330 is connected.
  • the terminal is electrically connected to the control terminal PD2 of the even frame pull-down module 420.
  • the second input end of the even frame triggering submodule 330 is electrically connected to the first output end of the even frame triggering submodule 330, and the even frame is triggered.
  • the first input of the sub-module 330 is electrically coupled to the second output of the even frame trigger sub-module 330.
  • the control terminal PD1 of the odd frame pull-down module 410 receives the valid signal provided by the odd frame trigger sub-module 320, and the input of the odd-frame pull-down module 410 and the first output of the odd-frame pull-down module 410 respectively
  • the second output end of the odd frame pull-down module 410 is electrically connected to provide a second level signal from the second level signal terminal VGL to the signal output terminal OUTPUT and the control terminal PU of the pull-up module, respectively, so that the signal output can be
  • the terminal OUTPUT and the control terminal PU of the pull-up module 200 are discharged.
  • the control terminal PD2 of the even frame pull-down module 420 receives the valid signal provided by the even frame trigger sub-module 330, the input of the even-frame pull-down module 420 and the first output and the even-number of the even-frame pull-down module 420 Second of the frame pulldown module 420
  • the output terminals are electrically connected to provide a second level signal to the signal output terminal OUTPUT and the control terminal PU of the pull-up module, respectively, so that the signal output terminal OUTPUT and the control terminal PU of the pull-up module can be discharged.
  • the specific structure of the odd frame trigger sub-module is not particularly limited.
  • the odd frame trigger sub-module 320 includes a first odd frame trigger transistor M14 and a second odd frame. Trigger transistor M17.
  • the gate of the first odd frame trigger transistor M14 is electrically connected to the first frame type signal input terminal GCH1, and the first pole of the first odd frame trigger transistor M14 is electrically connected to the first input end of the odd frame trigger submodule 320.
  • the second pole of the first odd frame trigger transistor M14 is electrically coupled to the second output of the odd frame trigger sub-module 320.
  • the gate of the second odd frame trigger transistor M17 is electrically connected to the first frame type signal input terminal GCH1, the first pole of the second odd frame trigger transistor M17 is electrically connected to the second level signal terminal VGL, and the second odd frame trigger transistor The second pole of M17 is electrically coupled to the first output of the odd frame trigger sub-module 320.
  • first odd frame trigger transistor M14 is the same as that of the second odd frame trigger transistor M17. That is, the first odd frame trigger transistor M14 and the second odd frame trigger transistor M17 may both be N-type transistors or both may be P-type transistors. In the embodiment shown in Figure 2, both are N-type transistors.
  • the signal input through the first frame type signal input terminal GCH1 is a valid signal
  • the signal input through the second frame type signal input terminal GCH2 is an invalid signal. Therefore, the first odd frame trigger transistor M14 and the second odd frame trigger transistor M17 are turned on.
  • the valid signal output by the pull-down control sub-module 310 is passed to the control terminal PD1 of the odd-frame pull-down module 410 through the first odd-frame trigger transistor M14, thereby electrically connecting the input of the odd-frame pull-down module 410 to the output.
  • the signal input through the second frame type signal input terminal GCH2 is a valid signal
  • the signal input through the first frame type signal input terminal GCH1 is an invalid signal. Therefore, the first odd frame trigger transistor M14 and the second odd frame trigger transistor M17 are both turned off, and no signal is output to the odd frame pull-down module 410. That is to say, the odd frame pull-down module 410 at this time is in a state of not being turned on.
  • the even frame trigger sub-module 420 includes a first even The digital frame trigger transistor M12 and the second even frame trigger transistor M16.
  • the gate of the first even frame trigger transistor M12 is electrically connected to the second frame type signal input terminal GCH2, and the first input of the first even frame trigger transistor M12 and the first input of the even frame trigger submodule 330
  • the terminal is electrically connected
  • the second pole of the first even frame triggering transistor M12 is electrically connected to the second output of the even frame triggering submodule 330.
  • the gate of the second even frame trigger transistor M16 is electrically connected to the second frame type signal input terminal GCH2, the first pole of the second even frame trigger transistor M16 is electrically connected to the second level signal terminal VGL, and the second even frame trigger transistor The second pole of M16 is electrically coupled to the first output of the even frame trigger sub-module 330.
  • the signal input through the first frame type signal input terminal GCH1 is a valid signal
  • the signal input through the second frame type signal input terminal GCH2 is an invalid signal. Therefore, the first even frame trigger transistor M12 and the second even frame trigger transistor M16 are both in an off state. That is, in the odd frame period, the even frame trigger sub-module 330 does not output any signal to the even frame pull-down module 420, so that the even-frame pull-down module 420 is in a non-on state.
  • the signal input through the second frame type signal input terminal GCH2 is a valid signal
  • the signal input through the first frame type signal input terminal GCH1 is an invalid signal.
  • the first even frame trigger transistor M12 and the second even frame trigger transistor M16 are both turned on, so that the signal output by the pull-down control sub-module 310 is sent to the control terminal PD2 of the even-frame pull-down module 420, so that the even-frame pull-down module 420
  • the first output end and the second output end are electrically connected to the input end of the even frame pull-down module 420, respectively, to discharge the signal output terminal OUTPUT and the control terminal PU of the pull-up module.
  • first even frame trigger transistor M12 is the same as that of the second even frame trigger transistor M16. That is, the first even frame trigger transistor M12 and the second even frame trigger transistor M16 may both be N-type transistors or both may be P-type transistors. In the embodiment shown in Figure 2, both are N-type transistors.
  • the type of the first odd frame trigger transistor M14, the second odd frame trigger transistor M17, the type of the first even frame trigger transistor M12, and the second even frame trigger transistor M16 are all the same.
  • the specific structure of the odd frame pull-down module 410 is not special.
  • the odd frame pulldown module 410 includes a first odd frame pull down transistor M2, a second odd frame pull down transistor M7, and a third odd frame pull down transistor M15.
  • the gate of the first odd frame pull-down transistor M2 is electrically connected to the control terminal PD1 of the odd frame pull-down module 410, and the first pole of the first odd-frame pull-down transistor M2 is electrically connected to the signal output terminal OUTPUT, and the first odd frame is pulled down.
  • the second pole of the transistor M2 is electrically connected to the second level signal terminal VGL.
  • the first pole of the second odd frame pull-down transistor M7 is electrically connected to the control terminal PU of the pull-up module 200, the second pole of the second odd-numbered frame pull-down transistor M7 is electrically connected to the second level signal terminal VGL, and the second odd transistor M7
  • the gate is electrically connected to the control terminal PD1 of the odd frame pull-down module 410.
  • the gate of the third odd-numbered frame pull-down transistor M15 is electrically connected to the control terminal PU of the pull-up module 200, and the first pole of the third odd-numbered frame pull-down transistor M15 is electrically connected to the control terminal PD1 of the odd-frame pull-down module 410, and the third odd frame
  • the second electrode of the pull-down transistor M15 is electrically connected to the second level signal terminal VGL.
  • the odd frame pull-down module 410 functions to electrically connect the second level signal terminal VGL to the signal output terminal OUTPUT and the control terminal PU of the pull-up module 200 during the pull-down phase of the odd frame period.
  • the first odd-numbered frame pull-down transistor M2 When the control terminal PD1 of the odd frame pull-down module 410 receives the valid signal, the first odd-numbered frame pull-down transistor M2 is turned on, so that the second-level signal terminal VGL is electrically connected to the signal output terminal OUTPUT; meanwhile, the second odd-numbered frame pull-down transistor M7 is turned on, so that the second level signal terminal VGL is electrically connected to the control terminal PU of the pull-up module 200.
  • the third odd-numbered frame pull-down transistor M15 is turned on, and therefore, the second power is
  • the flat signal is passed through the first odd frame trigger transistor M14 to the control terminal PD1 of the odd frame pull-down module, and the first odd frame pull-down transistor M2 and the second odd frame pull-down transistor M7 are controlled to be turned off, so that a stable output signal can be ensured.
  • the odd frame pull-down module 410 further includes a first storage capacitor C1, the first storage capacitor C1 The first end is electrically connected to the control terminal PD1 of the odd frame pull-down module 410, and the second end of the first storage capacitor C1 is electrically connected to the low-level signal terminal VGL.
  • the first storage capacitor is beneficial to maintain the voltage of the control terminal PD1 of the odd frame pull-down module 410, preventing the leakage of the control terminal PD1 of the odd-frame pull-down module 410 when the shift register unit operates in an extreme environment (for example, a high-temperature environment, etc.) Make sure the shift register unit is working properly.
  • the specific structure of the even frame pull-down module 420 is also not particularly limited.
  • the even-frame pull-down module includes a first even-numbered frame pull-down transistor M3 and a second even number.
  • the gate of the first even frame pull-down transistor M3 is electrically connected to the control terminal PD2 of the even frame pull-down module 420, the first pole of the first even frame pull-down transistor M3 is electrically connected to the signal output terminal OUTPUT, and the first even frame pull-down transistor M3 The second pole is electrically connected to the second level signal terminal VGL.
  • the gate of the second even frame pull-down transistor M5 is electrically connected to the control terminal PD2 of the even frame pull-down module 420, and the first pole of the second even frame pull-down transistor M5 is electrically connected to the control terminal PU of the pull-up module 200, and the second even frame The second pole of the pull-down transistor M5 is electrically connected to the second level signal terminal VGL.
  • the gate of the third even frame pull-down transistor M13 is electrically connected to the control terminal PU of the pull-up module 200, and the first pole of the third even-frame pull-down transistor M13 and the second level signal terminal PU are electrically connected. Connected, the second pole of the third even frame pull-down transistor M13 is electrically coupled to the control terminal PD2 of the even frame pull-down module 420.
  • the second even frame pull-down transistor M3 After the gate of the first even frame pull-down transistor M3 receives the valid signal in the even frame period, the second even frame pull-down transistor M3 is turned on, thereby transmitting the second level signal provided by the second level signal terminal VGL to the signal.
  • the output terminal OUTPUT discharges the signal output terminal OUTPUT; at the same time, the gate of the second even frame pull-down transistor M5 receives the valid signal, and the second even frame pull-down transistor M5 is turned on, thereby turning the second level signal terminal VGL It is electrically connected to the control terminal PU of the pull-up module 200 to discharge the control terminal PU of the pull-up module 200.
  • the even frame pull-down module 420 further includes a second storage capacitor C2, and the first end of the second storage capacitor C2 and the control of the even frame pull-down module 420
  • the terminal PD2 is electrically connected, and the second end of the second storage capacitor C2 is electrically connected to the second level signal terminal VGL.
  • the second storage capacitor C2 is beneficial for maintaining the voltage of the control terminal PD2 of the even frame pull-down module, preventing the leakage of the control terminal PD2 of the even-frame pull-down module when the shift register unit operates in an extreme environment (for example, a high-temperature environment), thereby ensuring the shift The bit register unit can work normally.
  • the input module 100 is not particularly limited as long as it can charge the control terminal PU of the module 200 in the input phase.
  • the display panel may be forward-scanned and reverse-scanned.
  • the trigger signal input terminal INPUT of the shift register unit includes a forward trigger signal input terminal STVU and a reverse trigger signal input terminal STVD
  • the input module 100 includes a forward input module 110 and a reverse direction.
  • the shift register unit includes a forward signal terminal CN and a reverse signal terminal CNB.
  • the pull-down control sub-module 310 includes a forward pull-down control sub-module 311 and a reverse pull-down control sub-module 312.
  • the forward input module 110 is used as an input module
  • the reverse input module 120 is used as a reset module
  • the forward input module 110 acts as a reset module and the reverse input module 120 acts as an input module.
  • the control terminal of the forward input module 110 is electrically connected to the forward trigger signal input terminal STVU, and the input terminal of the forward input module 110 is electrically connected to the forward signal terminal CN, and the output terminal of the forward input module 110 and the pull-up module 200 are
  • the control terminal PU is electrically connected.
  • the control terminal of the forward input module 110 receives the valid signal, the input terminal of the forward input module 110 is electrically connected to the output terminal of the forward input module 110.
  • the control end of the inverting input module 120 is electrically connected to the reverse trigger signal input terminal STVD, and the input end of the inverting input module 120 is electrically connected to the reverse signal terminal CNB, and the output end of the inverting input module 120 and the pull-up module 200 are
  • the control terminal PU is electrically connected.
  • the control terminal of the reverse input module 120 receives the valid signal, the input terminal of the reverse input module 120 is electrically connected to the output terminal of the reverse input module 120.
  • the control terminal of the forward pull-down control sub-module 311 is electrically connected to the forward signal terminal CN, the input terminal of the forward pull-down control sub-module 311 is electrically connected to the second clock signal terminal CLK2, and the output terminal of the forward pull-down control sub-module 311 is
  • the output of the reverse pull-down control sub-module 312 is electrically coupled and electrically coupled to the first input of the odd frame trigger sub-module 320 and the first input of the even frame trigger sub-module 330.
  • the control terminal of the reverse pull-down control sub-module 312 is electrically connected to the reverse signal terminal CNB, and the input terminal of the reverse pull-down control sub-module 312 is electrically connected to the fourth clock signal terminal CLK4.
  • the forward signal terminal CN provides a valid signal
  • the reverse signal terminal CNB provides an invalid signal. Therefore, the valid signal provided by the forward signal terminal CN can be provided to the first input end of the odd frame trigger sub-module 320 and the even frame trigger sub-module 330 by the forward pull-down control sub-module 311.
  • the forward signal terminal CN provides an invalid signal
  • the reverse signal terminal CNB provides a valid signal. Accordingly, the valid signal provided by the reverse signal terminal CNB can be provided to the first input of the odd frame trigger sub-module 320 and the even frame trigger sub-module 330 by the reverse pull-down control sub-module 312.
  • the forward input module 110 includes a forward input transistor M9, and a forward input transistor M9.
  • the gate is electrically connected to the control terminal of the forward input module 110
  • the first pole of the forward input transistor M9 is electrically connected to the input terminal of the forward input module 110
  • the second pole and the forward input of the forward input transistor M9 The output of module 110 is electrically connected.
  • the active signal is input through the forward trigger signal input terminal STVU, and the first pole and the second pole of the forward input transistor M9 are controlled to be electrically connected to each other, thereby
  • the first level signal input by the signal terminal CN is transmitted to the control terminal PU of the pull-up module 200, and the control terminal PU of the pull-up module 200 is charged.
  • the inverting input module 120 includes an inverting input transistor M8 whose gate is electrically coupled to the control terminal of the inverting input module 120, and the inverting input transistor M8 The first pole is electrically connected to the inverting input terminal CNB, and the second pole of the inverting input transistor M8 and the output end of the inverting input module 120 Electrical connection.
  • the forward input transistor M9 and the reverse input transistor M8 may be transistors of the same type. In the embodiment shown in FIG. 2, the forward input transistor M9 and the reverse input transistor M8 are both N-type transistors.
  • the specific structure of the forward pull-down control sub-module 311 is not particularly limited.
  • the forward pull-down control sub-module 311 includes a first forward pull-down control.
  • the gate of the first forward pull-down control transistor M11 is electrically connected to the control terminal of the forward pull-down control sub-module 311, and the first pole of the first forward pull-down control transistor M11 is electrically connected to the second clock signal terminal CLK2, the first positive The second pole of the pull-down control transistor M11 is electrically connected to the gate of the second pull-down control transistor M4.
  • the first pole of the second forward pull-down control transistor M4 is electrically coupled to the second clock signal terminal CLK2, and the second pole of the second forward pull-down control transistor M4 is electrically coupled to the output of the forward pull-down control sub-module 311.
  • the type of the first forward pull-down control transistor M11 and the type of the second forward pull-down control transistor M4 are the same.
  • the first forward pull-down control transistor M11 and the second forward pull-down control transistor M4 are both N-type transistors.
  • the forward signal terminal CN receives the valid signal and transmits it to the gate of the first forward pull-down control transistor M11, and the first forward pull-down transistor M11 is turned on.
  • the second clock signal terminal CLK2 inputs an effective signal, so that the effective signal can be sent to the gate of the second pull-down control transistor M4 through the first forward pull-down transistor M11, so that the second pull-down control transistor M4 leads And pass the valid signal input through the second clock signal terminal CLK2 to the output terminal of the forward pull-down control sub-module 311.
  • the forward pull-down control sub-module 311 does not operate, thereby extending the service life of the forward pull-down control sub-module 311.
  • the specific structure of the reverse pull-down control sub-module 312 is also not particularly limited.
  • the reverse pull-down control sub-module 312 includes a first reverse pull-down control.
  • the gate of the first reverse pull-down control transistor M10 is electrically connected to the reverse signal terminal CNB, and the first pole of the first reverse pull-down control transistor M10 is electrically connected to the fourth clock signal terminal CLK4, and the first reverse pull-down control transistor M10 The second pole is electrically coupled to the gate of the second reverse pull-down control transistor M6.
  • the first pole of the second reverse pull-down control transistor M6 is electrically coupled to the fourth clock signal terminal CLK4, and the second pole of the second reverse pull-down control transistor M6 is electrically coupled to the output of the reverse pull-down control sub-module 312.
  • the active signal is provided through the reverse signal terminal CNB. Therefore, the first reverse pull-down control transistor M10 is turned on, and the fourth clock signal terminal CLK4 provides a valid signal in the pull-down phase of each frame of the reverse scan mode.
  • the first reverse pull-down control transistor M10 is transmitted to the gate of the second reverse pull-down control transistor M6, so that the second reverse pull-down control transistor M6 can be turned on, thereby providing the effective signal provided by the fourth clock signal terminal CLK4. It is transmitted to the output of the reverse pull-down control sub-module 312.
  • the specific structure of the pull-up module 200 is not particularly limited.
  • the pull-up module 200 includes a pull-up transistor M1 and a third storage capacitor C3.
  • the signal terminal includes a first clock signal terminal CLK1.
  • the gate of the pull-up transistor M1 is electrically connected to the control terminal PU of the pull-up module 200.
  • the first pole of the pull-up transistor M1 is electrically connected to the first clock signal terminal CLK1, and the second pole of the pull-up transistor M1 is connected to the signal output terminal OUTPUT. Electrical connection.
  • the first end of the third storage capacitor C3 is electrically connected to the gate of the pull-up transistor M1, and the second end of the third storage capacitor C3 is electrically connected to the signal output terminal OUTPUT.
  • the valid signal input through the input module 100 is stored in the third storage capacitor C3.
  • the control terminal PU of the pull-up module 200 is coupled to a higher potential by the bootstrap action of the third storage capacitor C3, so that the pull-up transistor M1 can be turned on.
  • the first clock signal terminal CLK1 outputs a valid signal, so that a valid signal can be output to the signal output terminal OUTPUT.
  • all of the transistors are N-type transistors.
  • the valid signal refers to a high level signal and the invalid signal refers to a low level signal.
  • the present disclosure is not limited thereto, and in the case where the transistor is a P-type transistor, the effective signal may refer to a low level signal, and the invalid signal may refer to a high level signal.
  • the second level signal provided by the second level signal terminal VGL may be a low level signal.
  • the input module 100 includes a forward input module 110 and a reverse input module 120.
  • the forward input module 110 includes a forward input transistor M9
  • the reverse input module 120 includes a reverse input transistor M8.
  • the pull-up module 200 includes a pull-up transistor M1 and a third storage capacitor C3.
  • the pull-down control module 300 includes a pull-down control sub-module 310, an odd-frame trigger sub-module 320, and an even-frame trigger sub-module 330.
  • the pull-down control sub-module 310 includes a forward pull-down control sub-module 311 and a reverse pull-down control sub-module 312.
  • the forward pull-down control sub-module 311 includes a first forward pull-down control transistor M11 and a second forward pull-down control transistor M4.
  • the reverse pull-down control sub-module 312 includes a first reverse pull-down control transistor M10 and a second reverse pull-down control transistor M6.
  • the odd frame trigger sub-module 320 includes a first odd frame trigger transistor M14 and a second odd frame trigger transistor M17.
  • the even frame trigger sub-module 330 includes a first even frame trigger transistor M12 and a second even-numbered trigger transistor M16.
  • the odd frame pull-down module includes a first odd-numbered frame pull-down transistor M2, a second odd-numbered frame pull-down transistor M7, a third odd-numbered frame pull-down transistor M15, and a first storage capacitor C1.
  • the even frame pull-down module includes a first even frame pull-down transistor M3, a second even frame pull-down transistor M5, a third even frame pull-down transistor M13, and a second storage capacitor C2.
  • the gate of the forward input transistor M9 is electrically connected to the forward trigger signal input terminal STVU, the first pole of the forward input transistor M9 is electrically connected to the forward signal terminal CN, and the second pole of the forward input transistor M9 is connected to the reverse input.
  • the second pole of transistor M8 is electrically connected.
  • the gate of the inverting input transistor M8 is electrically connected to the inverting trigger signal input terminal STVD, and the first pole of the inverting input transistor M8 is electrically connected to the inverting signal terminal CNB.
  • the gate of the first forward pull-down control transistor M11 is electrically connected to the control terminal of the forward pull-down control sub-module 311, and the first pole of the first forward pull-down control transistor M11 is electrically connected to the second clock signal CLK2, the first positive The second pole of the pull-down control transistor M11 is electrically coupled to the gate of the second forward pull-down control transistor M4.
  • the first pole of the second forward pull-down control transistor M4 is electrically coupled to the second clock signal terminal CLK2, and the second pole of the second forward pull-down control transistor M4 is electrically coupled to the first pole of the first odd frame trigger transistor M14.
  • the gate of the first reverse pull-down control transistor M10 is electrically connected to the reverse signal terminal CNB, and the first pole of the first reverse pull-down control transistor M10 is electrically connected to the fourth clock signal terminal CLK4, and the first reverse pull-down control transistor M10 The second pole is electrically coupled to the gate of the second reverse pull-down control transistor M6.
  • the first pole of the second reverse pull-down control transistor M6 is electrically coupled to the fourth clock signal terminal CLK4, and the second pole of the second reverse pull-down control transistor M6 is electrically coupled to the first pole of the first odd frame trigger transistor M14.
  • the gate of the first odd frame trigger transistor M14 is electrically connected to the first frame type signal input terminal GCH1, and the first pole of the first odd frame trigger transistor M14 is electrically connected to the first input end of the odd frame trigger submodule 320, first The second pole of the odd frame trigger transistor M14 is electrically coupled to the gates of the first odd frame pull-down transistor M2 and the second odd frame pull-down transistor M7.
  • the gate of the second odd frame trigger transistor M17 is electrically connected to the first frame type signal input terminal GCH1
  • the first pole of the second odd frame trigger transistor M17 is electrically connected to the second level signal terminal VGL
  • the second odd frame trigger transistor The second pole of M17 and the first even number
  • the gate of the frame pull-down transistor M3 and the gate of the second even-frame pull-down transistor M5 are electrically connected.
  • the gate of the first even frame triggering transistor M12 is electrically connected to the second frame type signal input terminal GCH2, and the first pole of the first even frame triggering transistor M12 is electrically connected to the first input end of the even frame triggering submodule 330, first The second pole of the even frame trigger transistor M12 is electrically coupled to the gates of the first even frame pull-down transistor M3 and the second even frame pull-down transistor M5.
  • the gate of the second even frame trigger transistor M16 is electrically connected to the second frame type signal input terminal GCH2, the first pole of the second even frame trigger transistor M16 is electrically connected to the second level signal terminal VGL, and the second even frame trigger transistor The second pole of M16 is electrically coupled to the gate of the first odd frame pull-down transistor M2 and the gate of the second odd frame pull-down transistor M7.
  • the first pole of the first odd frame pull-down transistor M2 is electrically connected to the signal output terminal OUTPUT, and the second pole of the first odd frame pull-down transistor M2 is electrically connected to the second level signal terminal VGL.
  • the first pole of the second odd frame pull-down transistor M7 is electrically connected to the first terminal of the third storage capacitor C3, and the second pole of the second odd frame pull-down transistor M7 is electrically connected to the second level signal terminal VGL.
  • the gate of the third odd-numbered frame pull-down transistor M15 is electrically connected to the first end of the third storage capacitor C3, and the first pole of the third odd-numbered frame pull-down transistor M15 is electrically connected to the gate of the first odd-numbered frame pull-down transistor M2, and the third The second pole of the odd frame pull-down transistor M15 is electrically connected to the second level signal terminal VGL.
  • the first end of the first storage capacitor C1 is electrically connected to the control terminal PD1 of the odd frame pull-down module 410, and the second end of the first storage capacitor C1 is electrically connected to the second level signal terminal VGL.
  • the gate of the first even frame pull-down transistor M3 is electrically connected to the control terminal PD2 of the even frame pull-down module 420, the first pole of the first even frame pull-down transistor M3 is electrically connected to the signal output terminal OUTPUT, and the first even frame pull-down transistor M3
  • the second pole is electrically connected to the second level signal terminal VGL.
  • the first pole of the second even frame pull-down transistor M5 is electrically connected to the control terminal PU of the pull-up module 200, and the second pole of the second even-frame pull-down transistor M5 is electrically connected to the second level signal terminal VGL.
  • a gate of the third even frame pull-down transistor M13 is electrically connected to a first end of the third storage capacitor C3, and a first pole of the third even frame pull-down transistor M13 is electrically connected to the second level signal terminal VGL , the third even frame
  • the second pole of the pull transistor M13 is electrically coupled to the control terminal PD2 of the even frame pull-down module 420.
  • the first end of the second storage capacitor C2 is electrically connected to the gates of the first even frame pull-down transistor M3 and the second even frame pull-down transistor M5, and the second end of the second storage capacitor C2 is electrically connected to the second level signal terminal VGL. .
  • one frame period includes a plurality of duty cycles, and each duty cycle includes three phases: an input phase T1, an output phase T2, and a pull-down phase T3.
  • FIG. 3 Shown in FIG. 3 is a timing chart when the shift register unit operates in the forward scan mode. Although not shown, it should be noted that in the forward mode, the forward signal terminal CN provides a valid signal and the reverse signal terminal CNB provides an invalid signal.
  • the operation of the even frame period in the forward scan mode will be described below with reference to FIG. It should be noted that in this case, the first frame type signal input terminal GCH1 provides a valid signal, and the second frame type signal input terminal GCH2 provides an invalid signal.
  • the positive trigger signal input terminal STVU provides a valid signal.
  • the first clock signal terminal CLK1 provides an invalid signal
  • the second clock signal terminal CLK2 provides an invalid signal.
  • the forward input transistor M9 is turned on, thereby charging the third storage capacitor C3 of the pull-up module 200, and maintaining the control terminal PU of the pull-up module 200 at a high level, causing the pull-up transistor M1 to be turned on.
  • the third odd frame pull-down transistor M15 and the third even frame pull-down transistor M13 are turned on, causing the control terminal PD1 of the odd frame pull-down module 410 and the control terminal PD2 of the even frame pull-down module 420 to be the second level signal terminal.
  • the second level signal provided by VGL (eg, low level). Therefore, the signal output from the signal output terminal OUTPUT is an invalid signal (for example, a low level signal) supplied from the first clock signal terminal CLK1.
  • the forward trigger signal input terminal STVU provides an invalid signal.
  • the first clock signal terminal CLK1 provides a valid signal.
  • the bootstrap action of the third storage capacitor C3 couples the gate of the pull-up transistor M1 to a higher potential, thereby causing the pull-up transistor M1 to conduct.
  • the third odd frame pull-down transistor M15 and the third even frame pull-down transistor M13 are turned on, causing the control terminal PD1 of the odd frame pull-down module 410 and the control terminal PD2 of the even frame pull-down module 420 to be the second level signal terminal.
  • the second level provided by VGL signal. Therefore, the signal outputted by the signal output terminal OUTPUT is a high level signal supplied from the first clock signal terminal CLK1.
  • the forward trigger signal input terminal STVU provides an invalid signal.
  • the first clock signal terminal CLK1 provides an invalid signal, and the second clock signal terminal CLK2 provides a valid signal.
  • the effective signal of the second clock signal terminal CLK2 is transmitted to the first pole of the first odd frame trigger transistor M14 through the second forward pull-down control transistor M4, and is transmitted to the control of the odd frame pull-down module 410 through the first odd frame trigger transistor M14. End PD1.
  • the control terminal PD1 of the odd frame pull-down module 410 is at a high level, which causes the first odd-numbered frame pull-down transistor M2 and the second odd-numbered frame pull-down transistor M7 to be turned on, thereby respectively respectively respectively respectively respectively the signal output terminal OUTPUT and the control terminal PU of the pull-up module 200 respectively Pull down to the second level (for example, low level).
  • the positive signal terminal CN provides a valid signal
  • the reverse signal terminal CNB provides an invalid signal
  • the first frame type signal input terminal GCH1 inputs an invalid signal
  • the second frame type signal input terminal GCH2 inputs a valid signal.
  • the positive trigger signal input terminal STVU provides a valid signal.
  • the first clock signal terminal CLK1 provides an invalid signal
  • the second clock signal terminal CLK2 provides an invalid signal.
  • the forward input transistor M9 is turned on, thereby charging the third storage capacitor C3 of the pull-up module 200, and maintaining the control terminal PU of the pull-up module 200 at a high level, causing the pull-up transistor M1 to be turned on.
  • the third odd frame pull-down transistor M15 and the third even frame pull-down transistor M13 are turned on, causing the control terminal PD1 of the odd frame pull-down module 410 and the control terminal PD2 of the even frame pull-down module 420 to be the second level signal terminal.
  • the second level signal provided by VGL (eg, low level). Therefore, the signal output from the signal output terminal OUTPUT is an invalid signal (for example, a low level signal) supplied from the first clock signal terminal CLK1.
  • the forward trigger signal input terminal STVU provides an invalid signal.
  • the first clock signal terminal CLK1 provides a valid signal.
  • the bootstrap action of the third storage capacitor C3 couples the gate of the pull-up transistor M1 to a higher potential, thereby causing the pull-up transistor M1 to conduct.
  • the third odd frame pull-down transistor M15 and the third even frame pull-down transistor M13 are turned on, causing the control terminal PD1 of the odd frame pull-down module 410 and the control terminal PD2 of the even frame pull-down module 420 to be the second level signal terminal.
  • the second level provided by VGL signal. Therefore, the signal outputted by the signal output terminal OUTPUT is a high level signal supplied from the first clock signal terminal CLK1.
  • the forward trigger signal input terminal STVU provides an invalid signal.
  • the first clock signal terminal CLK1 provides an invalid signal, and the second clock signal terminal CLK2 provides a valid signal.
  • the effective signal of the second clock signal terminal CLK2 is transmitted to the first pole of the first even frame trigger transistor M12 through the second forward pull-down control transistor M4, and is transmitted to the control of the even frame pull-down module 420 through the first even frame trigger transistor M12. End PD2.
  • the control terminal PD2 of the even frame pull-down module is at a high level, causing the first even frame pull-down transistor M3 and the second even frame pull-down transistor M5 to be turned on, thereby respectively pulling down the signal output terminal OUTPUT and the control terminal PU of the pull-up module 200 respectively.
  • the second level eg, low level
  • a shift register including a plurality of cascaded shift register units, wherein each of the shift register units is the shift described above provided by the present disclosure Registration unit.
  • the shift register unit includes a plurality of pull-down modules, different use of different pull-down modules in different frames can extend the service life of the entire shift register unit, thereby prolonging the service life of the shift register.
  • FIG. 4 is a schematic diagram of a shift register capable of implementing forward scan and reverse scan in accordance with the present disclosure.
  • the signal output terminal OUTPUT of the previous stage shift register unit is electrically connected to the forward trigger signal input terminal STVU of the subsequent stage shift register unit.
  • the reverse trigger signal input terminal STVD of the previous stage shift register unit is electrically connected to the signal output terminal OUTPUT of the subsequent stage shift register unit.
  • the shift register further includes a first clock signal line CLK1', a second clock signal line CLK2', a third clock signal line CLK3', in addition to the cascaded multi-stage shift register unit.
  • the first level signal line VDD and the shift register unit of each stage are respectively The first level signal terminals VDD are connected, and the second level signal lines VGL' are respectively connected to the second level signal terminals VGL of the shift register units of the respective stages.
  • the first clock signal terminal CLK1 of the first stage shift register unit is connected to the first clock signal line CLK1', and the first stage shift
  • the second clock signal terminal CLK2 of the register unit is connected to the second clock signal line CLK2'
  • the fourth clock signal terminal CLK4 of the first stage shift register unit is connected to the fourth clock signal line CLK4'
  • the second stage shift register unit The first clock signal terminal CLK1 is connected to the second clock signal line CLK2'
  • the second clock signal terminal CLK2 of the second-stage shift register unit is connected to the third clock signal line CLK3'
  • the four clock signal terminal CLK4 is connected to the first clock signal line CLK1'
  • the first clock signal terminal CLK1 of the third stage shift register unit is connected to the third clock signal line CLK3'
  • the second clock of the third stage shift register unit The signal terminal CLK2 is connected to the fourth clock signal line CLK4', and the fourth clock signal terminal
  • the forward trigger signal input terminal STUV of the first stage shift register unit is connected to the forward trigger signal line STVU', and the reverse trigger signal input terminal of the last stage shift register unit is connected to the reverse trigger signal line STVD'.
  • the output of the first stage shift register unit is OUTPUT1
  • the output of the second stage shift register unit is OUTPUT2
  • the output of the third stage shift register unit is OUTPUT3
  • the fourth stage shift register The output of the unit is OUTPUT4, and the output of the Nth stage shift register unit is OUTPUTN.
  • the configuration of the shift register unit capable of realizing forward scan and reverse scan can further improve the use of the shift register. life.
  • Fig. 5 shows the signals outputted from the signal output terminals of the first four shift register units in the forward scan mode and the timing of the respective signal terminals.
  • Fig. 6 shows the signals outputted from the signal output terminals of the first four shift register units in the reverse scan mode and the timing of the respective signal terminals.
  • a gate driving circuit including a shift register and a frame signal judging unit, and the shift register is the above shift register provided by the present disclosure
  • the frame signal determination unit is capable of outputting a frame trigger signal indicating the number of frames to the shift register unit.
  • the so-called frame trigger signal characterizing the number of frames refers to the number of frames characterizing the frame in one frame period.
  • the frame trigger signal representing the number of frames may be a signal representing an odd frame and a signal representing an even frame (eg, by the first frame type signal input end and the second frame, respectively).
  • a display panel including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present disclosure.
  • the display panel Since the above-described gate driving circuit provided by the present disclosure has a long service life, the display panel also has a long service life.

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Abstract

提供一种移位寄存单元，该移位寄存单元的工作阶段包括多个帧周期，每个帧周期包括多个不同的帧，该移位寄存单元包括触发信号输入端INPUT、输入模块（100）、上拉模块（200）、下拉控制模块（300）、多个下拉模块和信号输出端OUTPUT，下拉控制模块（300）能够在同一个帧周期的各个帧的下拉阶段依次向各个下拉模块的控制端提供有效信号。还提供一种移位寄存器、一种栅极驱动电路和一种显示面板。该移位寄存单元具有较长的使用寿命，并且，该移位寄存单元具有较好的电性能，能够满足高信赖性产品的要求。

Description

移位寄存单元、移位寄存器、栅极驱动电路和显示面板 技术领域
本公开涉及显示技术领域，具体地，涉及一种移位寄存单元、一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动电路和一种包括该栅极驱动电路的显示面板。
背景技术
为了减小显示装置的边框，通常将栅极驱动电路的移位寄存器集成在阵列基板上。移位寄存器包括级联的多级移位寄存单元，通常，每个移位寄存单元包括多个晶体管。随着显示装置的功能越来越强大，人们使用显示装置的时间也越来越长，因此，如何提高移位寄存单元中晶体管的使用寿命成为本领域亟待解决的技术问题。
发明内容
本公开提供一种移位寄存单元、一种包括该移位寄存单元的移位寄存器、一种包括该移位寄存器的栅极驱动电路和一种包括该栅极驱动电路的显示面板。所述移位寄存单元具有较长的使用寿命。
为了至少部分地实现上述目的，作为本公开的一个方面，提供一种移位寄存单元，所述移位寄存单元的工作时间包括多个多帧周期，每个多帧周期包括多个帧周期，每个帧周期包括至少一个工作周期，所述移位寄存单元包括触发信号输入端、输入模块、上拉模块、下拉控制模块、多个下拉模块和信号输出端，
其中，所述触发信号输入端与所述输入模块的控制端电连接，且所述触发信号输入端构造为在所述移位寄存单元的输入阶段向所述输入模块的控制端提供有效信号；
所述输入模块的输出端与所述上拉模块的控制端电连接，所述输入模块构造为在该输入模块的控制端接收到有效信号时，向所述上 拉模块的控制端提供有效信号；
所述上拉模块的输入端与初始信号端电连接，所述上拉模块的输出端与所述信号输出端电连接，所述上拉模块构造为在该上拉模块的控制端接收到有效信号时，使得该上拉模块的输入端与该上拉模块的输出端电连接；
每个所述下拉模块的输入端均与第二电平信号端电连接，每个所述下拉模块的第一输出端均与所述信号输出端电连接，每个所述下拉模块的第二输出端均与所述上拉模块的控制端电连接，对于每个下拉模块而言，当该下拉模块的控制端接收到有效信号时，使得该下拉模块的输入端和该下拉模块的第一输出端、该下拉模块的第二输出端电连接；
所述下拉控制模块包括多个下拉控制信号输出端，所述多个下拉控制信号输出端分别与各个所述下拉模块的控制端电连接，所述下拉控制模块构造为在同一个多帧周期的各个帧周期的下拉阶段依次向各个所述下拉模块的控制端提供有效信号，以使得各个所述下拉模块分别在不同的帧周期开启。
可选地，每个所述多帧周期包括彼此交替的奇数帧周期和偶数帧周期，所述下拉模块包括奇数帧下拉模块和偶数帧下拉模块，
所述下拉控制模块构造为在每个奇数帧周期的下拉阶段向所述奇数帧下拉模块的控制端输出有效信号，并向所述偶数帧下拉模块的控制端输出无效信号，
所述下拉控制模块构造为在每个偶数帧周期的下拉阶段向所述偶数帧下拉模块的控制端输出有效信号，并能够向所述奇数帧下拉模块的控制端输出无效信号。
可选地，所述下拉控制模块包括下拉控制子模块、奇数帧触发子模块和偶数帧触发子模块，所述奇数帧触发子模块的第一输出端和所述偶数帧下拉模块的第二输出端彼此电连接作为所述下拉控制模块的第一输出端，所述奇数帧下拉模块的第二输出端和所述偶数帧触发子模块的第一输出端彼此电连接作为所述下拉控制模块的第二输出端；
所述移位寄存单元还包括第一帧类别信号输入端和第二帧类别信号输入端，
所述下拉控制子模块构造为在各帧的下拉阶段输出有效信号；
所述奇数帧触发子模块的控制端与所述第一帧类别信号输入端电连接，所述奇数帧触发子模块的第一输入端与所述下拉控制子模块的输出端电连接，所述奇数帧触发子模块的第二输入端与所述第二电平信号端电连接，所述奇数帧触发子模块的第一输出端与所述偶数帧下拉模块的控制端电连接，所述奇数帧触发子模块的第二输出端与所述奇数帧下拉模块的控制端电连接，所述奇数帧触发子模块构造为在其控制端接收到有效信号时，将所述奇数帧触发子模块的第二输入端与所述奇数帧触发子模块的第一输出端电连接，并将所述奇数帧触发子模块的第一输入端与所述奇数帧触发子模块的第二输出端电连接；
所述偶数帧触发子模块的控制端与所述第二帧类别信号输入端电连接，所述偶数帧触发子模块的第一输入端与所述下拉控制子模块的输出端电连接，所述偶数帧触发子模块的第二输入端与所述第二电平信号端电连接，所述偶数帧触发子模块的第一输出端与所述奇数帧下拉模块的控制端电连接，所述偶数帧触发子模块的第二输出端与所述偶数帧下拉模块的控制端电连接，所述偶数帧触发子模块构造为在其控制端接收到有效信号时，将所述偶数帧触发子模块的第二输入端与所述偶数帧触发子模块的第一输出端电连接，并将所述偶数帧触发子模块的第一输入端与所述偶数帧触发子模块的第二输出端电连接。
可选地，所述奇数帧触发子模块包括第一奇数帧触发晶体管和第二奇数帧触发晶体管，
所述第一奇数帧触发晶体管的栅极与所述第一帧类别信号输入端电连接，所述第一奇数帧触发晶体管的第一极与所述奇数帧触发子模块的第一输入端电连接，所述第一奇数帧触发晶体管的第二极与所述奇数帧触发子模块的第二输出端电连接，
所述第二奇数帧触发晶体管的栅极与所述第一帧类别信号输入端电连接，所述第二奇数帧触发晶体管的第一极与所述第二电平信号端电连接，所述第二奇数帧触发晶体管的第二极与所述奇数帧触发子 模块的第一输出端电连接。
可选地，所述偶数帧触发子模块包括第一偶数帧触发晶体管和第二偶数帧触发晶体管，
所述第一偶数帧触发晶体管的栅极与所述第二帧类别信号输入端电连接，所述第一偶数帧触发晶体管的第一极与所述偶数帧触发子模块的第一输入端电连接，所述第一偶数帧触发晶体管的第二极与所述偶数帧触发子模块的第二输出端电连接；
所述第二偶数帧触发晶体管的栅极与所述第二帧类别信号输入端电连接，所述第二偶数帧触发晶体管的第一极与所述第二电平信号端电连接，所述第二偶数帧触发晶体管的第二极与所述偶数帧触发子模块的第一输出端电连接。
可选地，所述奇数帧下拉模块包括第一奇数帧下拉晶体管、第二奇数帧下拉晶体管和第三奇数帧下拉晶体管；
所述第一奇数帧下拉晶体管的栅极与所述奇数帧下拉模块的控制端电连接，所述第一奇数帧下拉晶体管的第一极与所述信号输出端电连接，所述第一奇数帧下拉晶体管的第二极与所述第二电平信号端电连接；
所述第二奇数帧下拉晶体管的第一极与所述上拉模块的控制端电连接，所述第二奇数帧下拉晶体管的第二极与所述第二电平信号端电连接，所述第二奇数晶体管的栅极与所述奇数帧下拉模块的控制端电连接；
所述第三奇数帧下拉晶体管的栅极与所述上拉模块的控制端电连接，所述第三奇数帧下拉晶体管的第一极与所述奇数帧下拉模块的控制端电连接，所述第三奇数帧下拉晶体管的第二极与所述第二电平信号端电连接。
可选地，所述奇数帧下拉晶体管还包括第一存储电容，所述第一存储电容的第一端与所述奇数帧下拉模块的控制端电连接，所述第一存储电容的第二端与所述第二电平信号端电连接。
可选地，所述偶数帧下拉模块包括第一偶数帧下拉晶体管、第二偶数帧下拉晶体管、第三偶数帧下拉晶体管，
所述第一偶数帧下拉晶体管的栅极与所述偶数帧下拉模块的控制端电连接，所述第一偶数帧下拉晶体管的第一极与所述信号输出端电连接，所述第一偶数帧下拉晶体管的第二极与第二电平信号端电连接；
所述第二偶数帧下拉晶体管的栅极与所述偶数帧下拉模块的控制端电连接，所述第二偶数帧下拉晶体管的第一极与所述上拉模块的控制端电连接，所述第二偶数帧下拉晶体管的第二极与所述第二电平信号端电连接；
所述第三偶数帧下拉晶体管的栅极与所述上拉模块的控制端电连接，所述第三偶数帧下拉晶体管的第一极与所述第二电平信号端电连接，所述第三偶数帧下拉晶体管的第二极与所述偶数帧下拉模块的控制端电连接。
可选地，所述偶数帧下拉模块还包括第二存储电容，所述第二存储电容的第一端与所述偶数帧下拉模块的控制端电连接，所述第二存储电容的第二端与所述第二电平信号端电连接。
可选地，所述输入模块包括正向输入模块和反向输入模块，所述移位寄存单元包括正向信号端、反向信号端，所述触发信号输入端包括正向触发信号输入端和反向触发信号输入端，所述下拉控制子模块包括正向下拉控制子模块和反向下拉控制子模块，
所述正向输入模块的控制端与所述正向触发信号输入端电连接，所述正向输入模块的输入端与所述正向信号端电连接，所述正向输入模块的输出端与所述输入模块的输出端电连接；
所述反向输入模块的控制端与所述反向触发信号输入端电连接，所述反向输入模块的输入端与所述反向信号端电连接，所述反向输入模块的输出端与所述上拉模块的控制端电连接；
所述正向下拉控制子模块的控制端与所述正向信号端电连接，所述正向下拉控制子模块的输入端与第二时钟信号端电连接，所述正向下拉控制子模块的输出端与所述反向下拉控制子模块的输出端电连接，且与所述奇数帧触发子模块的第一输入端以及所述偶数帧触发子模块的第一输入端电连接；
所述反向下拉控制子模块的控制端与所述反向信号端电连接，所述反向下拉控制子模块的输入端与第四时钟信号端电连接，所述反向下拉控制子模块的输出端与所述正向下拉控制子模块的输出端电连接。
可选地，所述正向输入模块构造为当其控制端接收到有效信号时，将所述正向输入模块的输入端与所述正向输入模块的输出端电连接；
所述反向输入模块构造为当其控制端接收到有效信号时，将所述反向输入模块的输入端与所述反向输入模块的输出端电连接；
所述正向下拉控制子模块构造为在所述正向信号端提供有效信号且所述反向信号端提供无效信号时输出由所述正向信号端提供的有效信号；
所述反向下拉控制子模块构造为在所述正向信号端提供无效信号且所述反向信号端提供有效信号时输出由所述反向信号端提供的有效信号。
可选地，所述正向输入模块包括正向输入晶体管，所述正向输入晶体管的栅极与所述正向输入模块的控制端电连接，所述正向输入晶体管的第一极与所述正向输入模块的输入端电连接，所述正向输入晶体管的第二极与所述正向输入模块的输出端电连接。
可选地，所述反向输入模块包括反向输入晶体管，所述反向输入晶体管的栅极与所述反向输入模块的控制端电连接，所述反向输入晶体管的第一极与所述反向输入模块的输入端电连接，所述反向输入晶体管的第二极与所述反向输入模块的输出端电连接。
可选地，所述正向下拉控制子模块包括第一正向下拉控制晶体管和第二正向下拉控制晶体管，
所述第一正向下拉控制晶体管的栅极与所述正向下拉控制子模块的控制端电连接，所述第一正向下拉控制晶体管的第一极与所述第二时钟信号端电连接，所述第一正向下拉控制晶体管的第二极与所述第二下拉控制晶体管的栅极电连接；
所述第二正向下拉控制晶体管的第一极与所述第二时钟信号端 电连接，所述第二正向下拉控制晶体管的第二极与所述正向下拉控制子模块的输出端电连接。
可选地，所述反向下拉控制子模块包括第一反向下拉控制晶体管和第二反向下拉控制晶体管，
所述第一反向下拉控制晶体管的栅极与所述反向信号端电连接，所述第一反向下拉控制晶体管的第一极与所述第四时钟信号端电连接，所述第一反向下拉控制晶体管的第二极与所述第二反向下拉控制晶体管的栅极电连接；
所述第二反向下拉控制晶体管的第一极与所述第四时钟信号端电连接，所述第二反向下拉控制晶体管的第二极与所述反向下拉控制子模块的输出端电连接。
可选地，所述上拉模块包括上拉晶体管和第三存储电容，所述初始信号端包括第一时钟信号端，
所述上拉晶体管的栅极与所述上拉模块的控制端电连接，所述上拉晶体管的第一极与所述第一时钟信号端电连接，所述上拉晶体管的第二极与所述信号输出端电连接；
所述第三存储电容的第一端与所述上拉晶体管的栅极电连接，所述第三存储电容的第二端与所述信号输出端电连接。
作为本公开的第二个方面，提供一种移位寄存器，所述移位寄存器包括级联的多个移位寄存单元，其中，所述多个移位寄存单元中的每一个为本公开所提供的上述移位寄存单元。
作为本公开的第三个方面，提供一种栅极驱动电路，其中，所述栅极驱动电路包括移位寄存器和帧信号判断单元，所述移位寄存器为本公开所提供的上述移位寄存器，所述帧信号判断单元构造为向所述移位寄存单元输出表征帧数的帧触发信号。
作为本公开的第四个方面，提供一种显示面板，所述显示面板包括栅极驱动电路，其中，所述栅极驱动电路为本公开所提供的上述栅极驱动电路。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是本公开所提供的移位寄存单元的模块示意图；
图2是本公开所提供的移位寄存单元的电路结构示意图；
图3是移位寄存单元的一个工作周期的时序图；
图4是本公开所提供的栅极驱动电路的示意图；
图5是正向扫描时的时序图；
图6是反向扫描时的时序图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
作为本公开的一个方面，提供一种移位寄存单元，其中，所述移位寄存单元的工作时间包括多个多帧周期，每个多帧周期包括多个不同的帧周期，如图1所示，所述移位寄存单元包括触发信号输入端INPUT、输入模块100、上拉模块200、下拉控制模块300和多个下拉模块和信号输出端OUTPUT。
触发信号输入端INPUT与输入模块100的控制端电连接，且触发信号输入端INPUT能够在所述移位寄存单元的输入阶段向所述输入模块的控制端提供有效信号。
输入模块100的输出端与上拉模块200的控制端PU电连接，输入模块100能够在该输入模块100的控制端接收到有效信号时，向上拉模块200的控制端PU提供有效信号。
上拉模块200的输入端与初始信号端电连接，上拉模块200的输出端与信号输出端OUTPUT电连接，上拉模块200能够在该上拉模块200的控制端PU接收到有效信号时，使得该上拉模块200的输入端与该上拉模块200的输出端电连接。
每个下拉模块的输入端均与第二电平信号端VGL电连接，每个 下拉模块的第一输出端均与信号输出端OUTPUT电连接，每个下拉模块的第二输出端均与上拉模块200的控制端PU电连接，对于任意一个下拉模块而言，当该下拉模块的控制端接收到有效信号时，该下拉模块的输入端和每个输出端电连接。当下拉模块的输入端与每个输出端电连接时，第二电平信号端VGL分别与信号输出端OUTPUT和上拉模块200的控制端PU电连接，以利用第二电平信号端VGL对信号输出端OUTPUT和上拉模块200的控制端PU放电。
下拉控制模块300包括多个下拉控制信号输出端，各个下拉控制信号输出端分别与各个所述下拉模块的控制端电连接，下拉控制模块300能够在同一个多帧周期的各个帧周期的下拉阶段依次向各个所述下拉模块的控制端提供有效信号，以使得各个所述下拉模块分别在不同的帧周期开启。
需要指出的是，此处移位寄存单元的一个多帧周期即为包括所述移位寄存单元的显示装置的一个显示阶段。每个显示阶段中都显示多帧图像，相应地，在移位寄存单元的一个多帧周期中的每个帧周期中显示所述多帧图像之一。在利用包括所述移位寄存单元的移位寄存器向显示面板的多条栅线提供扫描信号时，一个多帧周期中，多个下拉模块轮流工作。换言之，在一个多帧周期中，当一个下拉模块工作(例如，开启)时，其余下拉模块均处于非开启的状态。例如，在一个帧周期中，只有多个下拉模块之一工作。与只包括一个下拉模块的移位寄存单元相比，本公开所提供的移位寄存单元中，各个下拉模块的开启时间较短，因此，每个下拉模块都具有较长的使用寿命，从而延长了所述移位寄存单元的使用寿命。此外，由于各个下拉模块的开启时间较短，从而使得所述下拉模块具有较好的电性能(例如，各个晶体管不容易老化等)，可以满足高可靠性产品的要求。
在本公开中，每个信号输出端OUTPUT与显示面板中相应的一条栅线电连接，即，移位寄存单元为相应的栅线提供扫描信号。一个帧周期可包括至少一个工作周期，每个工作周期可包括输出阶段、输入阶段和下拉阶段。在一个示例中，一个帧周期中的工作周期的数量可与显示面板中的栅线的数量相同，但是本公开不限于此。
由于所述上拉模块的输入端与初始信号端电连接，因此，在输出阶段，信号输出端OUTPUT输出的信号即为初始信号端所提供的信号。在本公开中，对初始信号端的具体类型以及结构并没有特殊的限制。作为一种实施方式，初始信号端可以为图2中所示的第一时钟信号端CLK1。作为另一种实施方式，初始信号端可以为电源信号输出端(例如，高电平信号端VDD)。生产者可以根据具体的需求选择初始信号端的类型。
为了简化显示装置的具体结构，在一个示例中，每个所述多帧周期包括彼此交替的奇数帧周期和偶数帧周期，下拉模块包括奇数帧下拉模块410和偶数帧下拉模块420。
下拉控制模块300在奇数帧周期的下拉阶段向奇数帧下拉模块410的控制端PD1输出有效信号，以使得奇数帧下拉模块的输入端与输出端电连接，同时，下拉控制模块300向偶数帧下拉模块420的控制端PD2输出无效信号，以控制偶数帧下拉模块420不工作。
所述下拉控制模块300在偶数帧周期的下拉阶段向偶数帧下拉模块420的控制端PD2输出有效信号，以使得偶数帧下拉模块的输入端与输出端电连接，并向奇数帧下拉模块410的控制端PD1输出无效信号，以控制奇数帧下拉模块410不工作。
在移位寄存单元中同时设置奇数帧下拉模块410和偶数帧下拉模块420，可以延长所述移位寄存单元的整体使用寿命，便于加工制造。
在本公开中，对下拉控制模块300的具体结构并不做特殊的限定。在图2中所示的具体实施方式中，下拉控制模块300包括下拉控制子模块310、奇数帧触发子模块320和偶数帧触发子模块330，相应地，奇数帧触发子模块320的第一输出端和偶数帧触发子模块330的第二输出端彼此电连接，作为下拉控制模块300的第一输出端，奇数帧触发子模块320的第二输出端和偶数帧触发子模块330的第一输出端彼此电连接，作为下拉控制模块300的第二输出端。
所述移位寄存单元还包括第一帧类别信号输入端GCH1和第二帧类别信号输入端GCH2。
下拉控制子模块310能够在各帧的下拉阶段输出有效信号。
奇数帧触发子模块320的控制端与第一帧类别信号输入端GCH1电连接，奇数帧触发子模块320的第一输入端与下拉控制子模块310的输出端电连接，所述奇数帧触发子模块的第二输入端与第二电平信号端VGL电连接，所述奇数帧触发子模块的第一输出端与偶数帧下拉模块420的控制端PD2电连接，奇数帧触发子模块320的第二输出端与奇数帧下拉模块410的控制端PD1电连接。奇数帧触发子模块320的控制端接收到有效信号时，将奇数帧触发子模块320的第二输入端与该奇数帧触发子模块320的第一输出端电连接，并将奇数帧触发子模块320的第一输入端与该奇数帧触发子模块320的第二输出端电连接。
偶数帧触发子模块330的控制端与第二帧类别信号输入端GCH2电连接，偶数帧触发子模块330的第一输入端与下拉控制子模块310的输出端电连接，偶数帧触发子模块330的第二输入端与第二电平信号端VGL电连接，偶数帧触发子模块330的第一输出端与奇数帧下拉模块410的控制端PD1电连接，偶数帧触发子模块330的第二输出端与偶数帧下拉模块420的控制端PD2电连接。当偶数帧触发子模块330的控制端接收到有效信号时，将该偶数帧触发子模块330的第二输入端与偶数帧触发子模块330的第一输出端电连接，并将该偶数帧触发子模块330的第一输入端与该偶数帧触发子模块330的第二输出端电连接。
在奇数帧周期，奇数帧下拉模块410的控制端PD1接收到由奇数帧触发子模块320提供的有效信号，奇数帧下拉模块410的输入端分别与该奇数帧下拉模块410的第一输出端和该奇数帧下拉模块410的第二输出端电连接，以分别向信号输出端OUTPUT和上拉模块的控制端PU提供来自第二电平信号端VGL的第二电平信号，从而可以对信号输出端OUTPUT和上拉模块200的控制端PU进行放电。
在偶数帧周期，偶数帧下拉模块420的控制端PD2接收到由偶数帧触发子模块330提供的有效信号，偶数帧下拉模块420的输入端与该偶数帧下拉模块420的第一输出端和偶数帧下拉模块420的第二 输出端电连接，以分别向信号输出端OUTPUT和上拉模块的控制端PU提供第二电平信号，从而可以对信号输出端OUTPUT和上拉模块的控制端PU进行放电。
在本公开中，对奇数帧触发子模块的具体结构并没有特殊的限制，在图2所示的具体实施方式中，奇数帧触发子模块320包括第一奇数帧触发晶体管M14和第二奇数帧触发晶体管M17。
具体地，第一奇数帧触发晶体管M14的栅极与第一帧类别信号输入端GCH1电连接，第一奇数帧触发晶体管M14的第一极与奇数帧触发子模块320的第一输入端电连接，第一奇数帧触发晶体管M14的第二极与奇数帧触发子模块320的第二输出端电连接。
第二奇数帧触发晶体管M17的栅极与第一帧类别信号输入端GCH1电连接，第二奇数帧触发晶体管M17的第一极与第二电平信号端VGL电连接，第二奇数帧触发晶体管M17的第二极与奇数帧触发子模块320的第一输出端电连接。
需要指出的是，第一奇数帧触发晶体管M14的类型与第二奇数帧触发晶体管M17的类型相同。即，第一奇数帧触发晶体管M14和第二奇数帧触发晶体管M17可以都为N型晶体管，也可以都为P型晶体管。在图2中所示的具体实施方式中，二者均为N型晶体管。
在奇数帧周期，通过第一帧类别信号输入端GCH1输入的信号为有效信号，通过第二帧类别信号输入端GCH2输入的信号为无效信号。因此，第一奇数帧触发晶体管M14与第二奇数帧触发晶体管M17导通。下拉控制子模块310输出的有效信号通过第一奇数帧触发晶体管M14传递至奇数帧下拉模块410的控制端PD1，从而将奇数帧下拉模块410的输入端与输出端电连接。
在偶数帧周期，通过第二帧类别信号输入端GCH2输入的信号为有效信号，通过第一帧类别信号输入端GCH1输入的信号为无效信号。因此，第一奇数帧触发晶体管M14和第二奇数帧触发晶体管M17均截止，不向奇数帧下拉模块410输出任何信号。也就是说，此时的奇数帧下拉模块410处于不开启的状态。
同样地，在本公开中，所述偶数帧触发子模块420包括第一偶 数帧触发晶体管M12和第二偶数帧触发晶体管M16。
如图2所示，第一偶数帧触发晶体管M12的栅极与第二帧类别信号输入端GCH2电连接，第一偶数帧触发晶体管M12的第一极与偶数帧触发子模块330的第一输入端电连接，第一偶数帧触发晶体管M12的第二极与偶数帧触发子模块330的第二输出端电连接。
第二偶数帧触发晶体管M16的栅极与第二帧类别信号输入端GCH2电连接，第二偶数帧触发晶体管M16的第一极与第二电平信号端VGL电连接，第二偶数帧触发晶体管M16的第二极与偶数帧触发子模块330的第一输出端电连接。
在奇数帧周期，通过第一帧类别信号输入端GCH1输入的信号为有效信号，通过第二帧类别信号输入端GCH2输入的信号为无效信号。因此，第一偶数帧触发晶体管M12和第二偶数帧触发晶体管M16都处于截止状态。即，在奇数帧周期，偶数帧触发子模块330不向偶数帧下拉模块420输出任何信号，使得偶数帧下拉模块420处于不开启的状态。
在偶数帧周期，通过第二帧类别信号输入端GCH2输入的信号为有效信号，通过第一帧类别信号输入端GCH1输入的信号为无效信号。此时，第一偶数帧触发晶体管M12和第二偶数帧触发晶体管M16均导通，从而将下拉控制子模块310输出的信号输送至偶数帧下拉模块420的控制端PD2，使得偶数帧下拉模块420的第一输出端和第二输出端分别与偶数帧下拉模块420的输入端电连接，从而对信号输出端OUTPUT和上拉模块的控制端PU进行放电。
需要指出的是，第一偶数帧触发晶体管M12的类型与第二偶数帧触发晶体管M16的类型相同。即，第一偶数帧触发晶体管M12和第二偶数帧触发晶体管M16可以都为N型晶体管，也可以都为P型晶体管。在图2中所示的具体实施方式中，二者均为N型晶体管。
并且，第一奇数帧触发晶体管M14的类型、第二奇数帧触发晶体管M17、第一偶数帧触发晶体管M12的类型、第二偶数帧触发晶体管M16的类型均相同。
在本公开中，对奇数帧下拉模块410的具体结构并不做特殊的 限定，在图2中所示的具体实施方式中，奇数帧下拉模块410包括第一奇数帧下拉晶体管M2、第二奇数帧下拉晶体管M7和第三奇数帧下拉晶体管M15。
具体地，第一奇数帧下拉晶体管M2的栅极与奇数帧下拉模块410的控制端PD1电连接，第一奇数帧下拉晶体管M2的第一极与信号输出端OUTPUT电连接，第一奇数帧下拉晶体管M2的第二极与所述第二电平信号端VGL电连接。
第二奇数帧下拉晶体管M7的第一极与上拉模块200的控制端PU电连接，第二奇数帧下拉晶体管M7的第二极与第二电平信号端VGL电连接，第二奇数晶体管M7的栅极与奇数帧下拉模块410的控制端PD1电连接。
第三奇数帧下拉晶体管M15的栅极与上拉模块200的控制端PU电连接，第三奇数帧下拉晶体管M15的第一极与奇数帧下拉模块410的控制端PD1电连接，第三奇数帧下拉晶体管M15的第二极与第二电平信号端VGL电连接。
如上文中所述，奇数帧下拉模块410的作用在于，在奇数帧周期的下拉阶段，将第二电平信号端VGL与信号输出端OUTPUT、以及上拉模块200的控制端PU电连接。
当奇数帧下拉模块410的控制端PD1接收到有效信号时，第一奇数帧下拉晶体管M2导通，使得第二电平信号端VGL与信号输出端OUTPUT电连接；同时，第二奇数帧下拉晶体管M7导通，使得第二电平信号端VGL与上拉模块200的控制端PU电连接。
在奇数帧周期的输入阶段以及奇数帧周期的输出阶段，由于上拉模块200的控制端PU为有效电平信号，因此，第三奇数帧下拉晶体管M15是导通的，因此，将第二电平信号通过第一奇数帧触发晶体管M14传递至奇数帧下拉模块的控制端PD1，控制第一奇数帧下拉晶体管M2和第二奇数帧下拉晶体管M7截止，从而可以确保稳定的输出信号。
为了确保奇数帧下拉模块的稳定工作，在一个示例中，所述奇数帧下拉模块410还包括第一存储电容C1，该第一存储电容C1的 第一端与奇数帧下拉模块410的控制端PD1电连接，第一存储电容C1的第二端与低电平信号端VGL电连接。第一存储电容有利于保持奇数帧下拉模块410的控制端PD1的电压，防止移位寄存单元工作在极端环境(例如，高温环境等)中时奇数帧下拉模块410的控制端PD1发生漏电，从而确保移位寄存单元能够正常工作。
在本公开中，对偶数帧下拉模块420的具体结构也没有特殊的限制，在图2中所示的具体实施方式中，所述偶数帧下拉模块包括第一偶数帧下拉晶体管M3、第二偶数帧下拉晶体管M5、第三偶数帧下拉晶体管M13。
第一偶数帧下拉晶体管M3的栅极与偶数帧下拉模块420的控制端PD2电连接，第一偶数帧下拉晶体管M3的第一极与信号输出端OUTPUT电连接，第一偶数帧下拉晶体管M3的第二极与第二电平信号端VGL电连接。
第二偶数帧下拉晶体管M5的栅极与偶数帧下拉模块420的控制端PD2电连接，第二偶数帧下拉晶体管M5的第一极与上拉模块200的控制端PU电连接，第二偶数帧下拉晶体管M5的第二极与第二电平信号端VGL电连接。
所述第三偶数帧下拉晶体管M13的栅极与所述上拉模块200的控制端PU电连接，所述第三偶数帧下拉晶体管M13的第一极与所述第二电平信号端PU电连接，第三偶数帧下拉晶体管M13的第二极与偶数帧下拉模块420的控制端PD2电连接。
在偶数帧周期，第一偶数帧下拉晶体管M3的栅极接收到有效信号后，第二偶数帧下拉晶体管M3导通，从而将第二电平信号端VGL提供的第二电平信号传输至信号输出端OUTPUT，以对信号输出端OUTPUT进行放电；同时，第二偶数帧下拉晶体管M5的栅极接收到有效信号，该第二偶数帧下拉晶体管M5导通，从而将第二电平信号端VGL与上拉模块200的控制端PU电连接，以对上拉模块200的控制端PU进行放电。
在一个示例中，所述偶数帧下拉模块420还包括第二存储电容C2，该第二存储电容C2的第一端与所述偶数帧下拉模块420的控制 端PD2电连接，第二存储电容C2的第二端与第二电平信号端VGL电连接。第二存储电容C2有利于保持偶数帧下拉模块的控制端PD2的电压，防止移位寄存单元工作在极端环境(例如，高温环境)中时偶数帧下拉模块的控制端PD2发生漏电，从而确保移位寄存单元能够正常工作。
在本公开中，对输入模块100并没有特殊的限制，只要能够在输入阶段向上拉模块200的控制端PU充电即可。
在一个示例中，当包括所述移位寄存单元的移位寄存器用于显示面板中时，可以对显示面板进行正向扫描和反向扫描。此时，如图2所示，移位寄存单元的所述触发信号输入端INPUT包括正向触发信号输入端STVU和反向触发信号输入端STVD，输入模块100包括正向输入模块110和反向输入模块120。所述移位寄存单元包括正向信号端CN、反向信号端CNB，下拉控制子模块310包括正向下拉控制子模块311和反向下拉控制子模块312。
在正向扫描模式，通过正向信号端CN提供有效信号，通过反向信号端CNB提供无效信号；在反向扫描模式，通过正向信号端CN提供无效信号，通过反向信号端CNB提供有效信号。由此可知，在正向扫描模式，正向输入模块110用作输入模块，反向输入模块120用作复位模块。在反向扫描模式，正向输入模块110用作复位模块，反向输入模块120用作输入模块。
正向输入模块110的控制端与正向触发信号输入端STVU电连接，正向输入模块110的输入端与正向信号端CN电连接，正向输入模块110的输出端与上拉模块200的控制端PU电连接，当正向输入模块110的控制端接收到有效信号时，正向输入模块110的输入端与该正向输入模块110的输出端电连接。
反向输入模块120的控制端与反向触发信号输入端STVD电连接，反向输入模块120的输入端与反向信号端CNB电连接，反向输入模块120的输出端与上拉模块200的控制端PU电连接，当反向输入模块120的控制端接收到有效信号时，反向输入模块120的输入端与该反向输入模块120的输出端电连接。
正向下拉控制子模块311的控制端与正向信号端CN电连接，正向下拉控制子模块311的输入端与第二时钟信号端CLK2电连接，正向下拉控制子模块311的输出端与反向下拉控制子模块312的输出端电连接，且与奇数帧触发子模块320的第一输入端以及偶数帧触发子模块330的第一输入端电连接。
反向下拉控制子模块312的控制端与反向信号端CNB电连接，反向下拉控制子模块312的输入端与第四时钟信号端CLK4电连接。
如上文中所述，在正向扫描模式，正向信号端CN提供有效信号，反向信号端CNB提供无效信号。因此，可以通过正向下拉控制子模块311向奇数帧触发子模块320和偶数帧触发子模块330的第一输入端提供由正向信号端CN提供的有效信号。在反向扫描模式，正向信号端CN提供无效信号，反向信号端CNB提供有效信号。因此，可以通过反向下拉控制子模块312向奇数帧触发子模块320和偶数帧触发子模块330的第一输入端提供由反向信号端CNB提供的有效信号。
在本公开中，对正向输入模块的具体结构没有特殊的限制，例如，在图2中所示的具体实施方式中，正向输入模块110包括正向输入晶体管M9，正向输入晶体管M9的栅极与该正向输入模块110的控制端电连接，正向输入晶体管M9的第一极与该正向输入模块110的输入端电连接，正向输入晶体管M9的第二极与正向输入模块110的输出端电连接。
在正向扫描模式，在每个帧周期的输入阶段中，通过正向触发信号输入端STVU输入有效信号，控制正向输入晶体管M9的第一极和第二极彼此电连接，从而将正向信号端CN输入的第一电平信号传输至上拉模块200的控制端PU，并为上拉模块200的控制端PU充电。
在图2中所示的具体实施方式中，反向输入模块120包括反向输入晶体管M8，该反向输入晶体管M8的栅极与反向输入模块120的控制端电连接，反向输入晶体管M8的第一极与反向输入端CNB电连接，反向输入晶体管M8的第二极与反向输入模块120的输出端 电连接。
正向输入晶体管M9和反向输入晶体管M8可以是同类型的晶体管。在图2所示的具体实施方式中，正向输入晶体管M9和反向输入晶体管M8均为N型晶体管。
在本公开中，对正向下拉控制子模块311的具体结构并没有特殊的限制，例如，在图2中所示的具体实施方式中，正向下拉控制子模块311包括第一正向下拉控制晶体管M11和第二正向下拉控制晶体管M4。
第一正向下拉控制晶体管M11的栅极与正向下拉控制子模块311的控制端电连接，第一正向下拉控制晶体管M11的第一极与第二时钟信号端CLK2电连接，第一正向下拉控制晶体管M11的第二极与第二下拉控制晶体管M4的栅极电连接。
第二正向下拉控制晶体管M4的第一极与第二时钟信号端CLK2电连接，第二正向下拉控制晶体管M4的第二极与正向下拉控制子模块311的输出端电连接。
容易理解的是，在本实施方式中，第一正向下拉控制晶体管M11的类型和第二正向下拉控制晶体管M4的类型相同。在图2中所示的实施方式中，第一正向下拉控制晶体管M11和第二正向下拉控制晶体管M4均为N型晶体管。
在正向扫描模式，正向信号端CN接收到有效信号，并传输至第一正向下拉控制晶体管M11的栅极，第一正向下拉晶体管M11导通。在各帧的下拉阶段，第二时钟信号端CLK2输入有效信号，从而可以通过第一正向下拉晶体管M11将有效信号输送至第二下拉控制晶体管M4的栅极，使得第二下拉控制晶体管M4导通，并将通过第二时钟信号端CLK2输入的有效信号发送至正向下拉控制子模块311的输出端。
在反向扫描模式，由于正向信号端CN接收到无效信号，因此，第一正向下拉控制晶体管M11截止，从而导致第二下拉控制晶体管M4也截止。也就是说，在反向扫描时，正向下拉控制子模块311不工作，从而延长了正向下拉控制子模块311的使用寿命。
在本公开中，对反向下拉控制子模块312的具体结构也不做特殊的限制，例如，在图2中所示的实施方式中，反向下拉控制子模块312包括第一反向下拉控制晶体管M10和第二反向下拉控制晶体管M6。
第一反向下拉控制晶体管M10的栅极与反向信号端CNB电连接，第一反向下拉控制晶体管M10的第一极与第四时钟信号端CLK4电连接，第一反向下拉控制晶体管M10的第二极与第二反向下拉控制晶体管M6的栅极电连接。
第二反向下拉控制晶体管M6的第一极与第四时钟信号端CLK4电连接，第二反向下拉控制晶体管M6的第二极与反向下拉控制子模块312的输出端电连接。
在正向扫描模式，通过反向信号端CNB提供的是无效信号，因此，第一反向下拉控制晶体管M10是截止的，从而导致第二反向下拉控制晶体管M6也是截止的。因此，在正向扫描模式，反向下拉控制子模块312不工作，从而提高了反向下拉控制子模块312的使用寿命。
在反向扫描模式，通过反向信号端CNB提供有效信号，因此，第一反向下拉控制晶体管M10导通，在反向扫描模式的每帧的下拉阶段，第四时钟信号端CLK4提供有效信号，通过第一反向下拉控制晶体管M10传输至第二反向下拉控制晶体管M6的栅极，从而可以将第二反向下拉控制晶体管M6导通，进而将第四时钟信号端CLK4提供的有效信号传输至反向下拉控制子模块312的输出端。
在本公开中，对上拉模块200的具体结构并没有特殊的限制，例如，在图2中所示的具体实施方式中，上拉模块200包括上拉晶体管M1和第三存储电容C3，初始信号端包括第一时钟信号端CLK1。
上拉晶体管M1的栅极与上拉模块200的控制端PU电连接，上拉晶体管M1的第一极与第一时钟信号端CLK1电连接，上拉晶体管M1的第二极与信号输出端OUTPUT电连接。
第三存储电容C3的第一端与上拉晶体管M1的栅极电连接，第三存储电容C3的第二端与信号输出端OUTPUT电连接。
在输入阶段，通过输入模块100输入的有效信号存储在第三存储电容C3内。在输出阶段，通过第三存储电容C3的自举作用将上拉模块200的控制端PU耦合至更高的电位，从而可以使得上拉晶体管M1导通。并且，在输出阶段，第一时钟信号端CLK1输出的是有效信号，从而可以向信号输出端OUTPUT输出有效信号。
下面介绍图2介绍本公开所提供的移位寄存单元的可选实施方式的工作原理。
在图2中所示的具体实施方式中，所有的晶体管均为N型晶体管，这种情况下，有效信号是指高电平信号，无效信号是指低电平信号。需要注意的是，本公开不限于此，并且在晶体管为P型晶体管的情况下，有效信号可指低电平信号，无效信号可指高电平信号。
在一个示例中，第二电平信号端VGL提供的第二电平信号可为低电平信号。
输入模块100包括正向输入模块110和反向输入模块120。其中，正向输入模块110包括正向输入晶体管M9，反向输入模块120包括反向输入晶体管M8。
上拉模块200包括上拉晶体管M1和第三存储电容C3。
下拉控制模块300包括下拉控制子模块310、奇数帧触发子模块320和偶数帧触发子模块330。
下拉控制子模块310包括正向下拉控制子模块311和反向下拉控制子模块312。其中，正向下拉控制子模块311包括第一正向下拉控制晶体管M11和第二正向下拉控制晶体管M4。反向下拉控制子模块312包括第一反向下拉控制晶体管M10和第二反向下拉控制晶体管M6。
奇数帧触发子模块320包括第一奇数帧触发晶体管M14和第二奇数帧触发晶体管M17。
偶数帧触发子模块330包括第一偶数帧触发晶体管M12和第二偶数很触发晶体管M16。
奇数帧下拉模块包括第一奇数帧下拉晶体管M2、第二奇数帧下拉晶体管M7、第三奇数帧下拉晶体管M15和第一存储电容C1。
偶数帧下拉模块包括第一偶数帧下拉晶体管M3、第二偶数帧下拉晶体管M5、第三偶数帧下拉晶体管M13和第二存储电容C2。
下面具体介绍各个晶体管之间的连接关系。
正向输入晶体管M9的栅极与正向触发信号输入端STVU电连接，正向输入晶体管M9的第一极与正向信号端CN电连接，正向输入晶体管M9的第二极与反向输入晶体管M8的第二极电连接。反向输入晶体管M8的栅极与反向触发信号输入端STVD电连接，反向输入晶体管M8的第一极与反向信号端CNB电连接。
第一正向下拉控制晶体管M11的栅极与正向下拉控制子模块311的控制端电连接，第一正向下拉控制晶体管M11的第一极与第二时钟信号CLK2端电连接，第一正向下拉控制晶体管M11的第二极与第二正向下拉控制晶体管M4的栅极电连接。
第二正向下拉控制晶体管M4的第一极与第二时钟信号端CLK2电连接，第二正向下拉控制晶体管M4的第二极与第一奇数帧触发晶体管M14的第一极电连接。
第一反向下拉控制晶体管M10的栅极与反向信号端CNB电连接，第一反向下拉控制晶体管M10的第一极与第四时钟信号端CLK4电连接，第一反向下拉控制晶体管M10的第二极与第二反向下拉控制晶体管M6的栅极电连接。
第二反向下拉控制晶体管M6的第一极与第四时钟信号端CLK4电连接，第二反向下拉控制晶体管M6的第二极与第一奇数帧触发晶体管M14的第一极电连接。
第一奇数帧触发晶体管M14的栅极与第一帧类别信号输入端GCH1电连接，第一奇数帧触发晶体管M14的第一极与奇数帧触发子模块320的第一输入端电连接，第一奇数帧触发晶体管M14的第二极与第一奇数帧下拉晶体管M2以及第二奇数帧下拉晶体管M7的栅极电连接。
第二奇数帧触发晶体管M17的栅极与第一帧类别信号输入端GCH1电连接，第二奇数帧触发晶体管M17的第一极与第二电平信号端VGL电连接，第二奇数帧触发晶体管M17的第二极与第一偶数 帧下拉晶体管M3的栅极以及第二偶数帧下拉晶体管M5的栅极电连接。
第一偶数帧触发晶体管M12的栅极与第二帧类别信号输入端GCH2电连接，第一偶数帧触发晶体管M12的第一极与偶数帧触发子模块330的第一输入端电连接，第一偶数帧触发晶体管M12的第二极与第一偶数帧下拉晶体管M3和第二偶数帧下拉晶体管M5的栅极电连接。
第二偶数帧触发晶体管M16的栅极与第二帧类别信号输入端GCH2电连接，第二偶数帧触发晶体管M16的第一极与第二电平信号端VGL电连接，第二偶数帧触发晶体管M16的第二极与第一奇数帧下拉晶体管M2的栅极以及第二奇数帧下拉晶体管M7的栅极电连接。
第一奇数帧下拉晶体管M2的第一极与信号输出端OUTPUT电连接，第一奇数帧下拉晶体管M2的第二极与所述第二电平信号端VGL电连接。第二奇数帧下拉晶体管M7的第一极与第三存储电容C3的第一端电连接，第二奇数帧下拉晶体管M7的第二极与第二电平信号端VGL电连接。第三奇数帧下拉晶体管M15的栅极与第三存储电容C3的第一端电连接，第三奇数帧下拉晶体管M15的第一极与第一奇数帧下拉晶体管M2的栅极电连接，第三奇数帧下拉晶体管M15的第二极与第二电平信号端VGL电连接。第一存储电容C1的第一端与奇数帧下拉模块410的控制端PD1电连接，第一存储电容C1的第二端与第二电平信号端VGL电连接。
第一偶数帧下拉晶体管M3的栅极与偶数帧下拉模块420的控制端PD2电连接，第一偶数帧下拉晶体管M3的第一极与信号输出端OUTPUT电连接，第一偶数帧下拉晶体管M3的第二极与第二电平信号端VGL电连接。第二偶数帧下拉晶体管M5的第一极与上拉模块200的控制端PU电连接，第二偶数帧下拉晶体管M5的第二极与第二电平信号端VGL电连接。所述第三偶数帧下拉晶体管M13的栅极与第三存储电容C3的第一端电连接，所述第三偶数帧下拉晶体管M13的第一极与所述第二电平信号端VGL电连接，第三偶数帧下 拉晶体管M13的第二极与偶数帧下拉模块420的控制端PD2电连接。第二存储电容C2的第一端与第一偶数帧下拉晶体管M3以及第二偶数帧下拉晶体管M5的栅极电连接，第二存储电容C2的第二端与第二电平信号端VGL电连接。
下面结合图3的时序图介绍图2中所示的移位寄存单元的工作原理。
本领域技术人员容易理解的是，一个帧周期包括多个工作周期，每个工作周期包括三个阶段：输入阶段T1、输出阶段T2和下拉阶段T3。
图3中所示的是移位寄存单元在正向扫描模式下工作时的时序图。虽然未示出，但是需要指出的是，在该正向模式下，正向信号端CN提供有效信号，反向信号端CNB提供无效信号。
下面结合图3对正向扫描模式下偶数帧周期的工作过程进行说明。需要指出的是，这种情况下，第一帧类别信号输入端GCH1提供有效信号，第二帧类别信号输入端GCH2提供无效信号。
在输入阶段T1，正向触发信号输入端STVU提供有效信号。第一时钟信号端CLK1提供无效信号，第二时钟信号端CLK2提供无效信号。正向输入晶体管M9导通，从而向上拉模块200的第三存储电容C3充电，将上拉模块200的控制端PU维持在高电平，导致上拉晶体管M1导通。在此阶段，第三奇数帧下拉晶体管M15和第三偶数帧下拉晶体管M13导通，导致奇数帧下拉模块410的控制端PD1、偶数帧下拉模块420的控制端PD2均为第二电平信号端VGL提供的第二电平信号(例如，低电平)。因此，信号输出端OUTPUT输出的信号为第一时钟信号端CLK1提供的无效信号(例如，低电平信号)。
在输出阶段T2，正向触发信号输入端STVU提供无效信号。第一时钟信号端CLK1提供有效信号。第三存储电容C3的自举作用将上拉晶体管M1的栅极耦合至更高的电位，从而导致上拉晶体管M1导通。在此阶段，第三奇数帧下拉晶体管M15和第三偶数帧下拉晶体管M13导通，导致奇数帧下拉模块410的控制端PD1、偶数帧下拉模块420的控制端PD2均为第二电平信号端VGL提供的第二电平 信号。因此，信号输出端OUTPUT输出的信号为第一时钟信号端CLK1提供的高电平信号。
在下拉阶段T3，正向触发信号输入端STVU提供无效信号。第一时钟信号端CLK1提供无效信号，第二时钟信号端CLK2提供有效信号。第二时钟信号端CLK2的有效信号通过第二正向下拉控制晶体管M4传递至第一奇数帧触发晶体管M14的第一极，并通过第一奇数帧触发晶体管M14传递至奇数帧下拉模块410的控制端PD1。奇数帧下拉模块410的控制端PD1为高电平，导致第一奇数帧下拉晶体管M2、第二奇数帧下拉晶体管M7导通，从而分别将信号输出端OUTPUT和上拉模块200的控制端PU分别下拉至第二电平(例如，低电平)。
下面结合图3介绍在正向扫描模式下偶数帧的工作过程。需要指出的是，正向信号端CN提供有效信号，反向信号端CNB提供无效信号，第一帧类别信号输入端GCH1输入无效信号，第二帧类别信号输入端GCH2输入有效信号。
在输入阶段T1，正向触发信号输入端STVU提供有效信号。第一时钟信号端CLK1提供无效信号，第二时钟信号端CLK2提供无效信号。正向输入晶体管M9导通，从而向上拉模块200的第三存储电容C3充电，将上拉模块200的控制端PU维持在高电平，导致上拉晶体管M1导通。在此阶段，第三奇数帧下拉晶体管M15和第三偶数帧下拉晶体管M13导通，导致奇数帧下拉模块410的控制端PD1、偶数帧下拉模块420的控制端PD2均为第二电平信号端VGL提供的第二电平信号(例如，低电平)。因此，信号输出端OUTPUT输出的信号为第一时钟信号端CLK1提供的无效信号(例如，低电平信号)。
在输出阶段T2，正向触发信号输入端STVU提供无效信号。第一时钟信号端CLK1提供有效信号。第三存储电容C3的自举作用将上拉晶体管M1的栅极耦合至更高的电位，从而导致上拉晶体管M1导通。在此阶段，第三奇数帧下拉晶体管M15和第三偶数帧下拉晶体管M13导通，导致奇数帧下拉模块410的控制端PD1、偶数帧下拉模块420的控制端PD2均为第二电平信号端VGL提供的第二电平 信号。因此，信号输出端OUTPUT输出的信号为第一时钟信号端CLK1提供的高电平信号。
在下拉阶段T3，正向触发信号输入端STVU提供无效信号。第一时钟信号端CLK1提供无效信号，第二时钟信号端CLK2提供有效信号。第二时钟信号端CLK2的有效信号通过第二正向下拉控制晶体管M4传递至第一偶数帧触发晶体管M12的第一极，并通过第一偶数帧触发晶体管M12传递至偶数帧下拉模块420的控制端PD2。偶数帧下拉模块的控制端PD2为高电平，导致第一偶数帧下拉晶体管M3、第二偶数帧下拉晶体管M5导通，从而分别将信号输出端OUTPUT和上拉模块200的控制端PU分别下拉至第二电平(例如，低电平)。
作为本公开的另一个方面，提供一种移位寄存器，所述移位寄存器包括级联的多个移位寄存单元，其中，每个所述移位寄存单元为本公开所提供的上述移位寄存单元。
如上文中所述，由于移位寄存单元包括多个下拉模块，因此，在不同帧交替使用不同的下拉模块，可以延长整个移位寄存单元的使用寿命，进而延长移位寄存器的使用寿命。
图4是根据本公开的一种能够实现正向扫描和反向扫描的移位寄存器的示意图。通过图4可以看出，在相邻两级移位寄存单元中，前一级移位寄存单元的信号输出端OUTPUT与后一级移位寄存单元的正向触发信号输入端STVU电连接。前一级移位寄存单元的反向触发信号输入端STVD与后一级移位寄存单元的信号输出端OUTPUT电连接。
如图4中所示，除了包括级联的多级移位寄存单元，所述移位寄存器还包括第一时钟信号线CLK1’、第二时钟信号线CLK2’、第三时钟信号线CLK3’、第四时钟信号线CLK4’、正向触发信号线STVU’、反向触发信号线STVD’、第一帧类别信号线GCH1’、第二帧类别信号线GCH2’、正向信号线CN’、反向信号线CNB’、第一电平信号线VDD’和第二电平信号线VGL’。
如图4中所示，第一电平信号线VDD分别与各级移位寄存单元 的第一电平信号端VDD相连，第二电平信号线VGL’分别与各级移位寄存单元的第二电平信号端VGL相连。
从第一级移位寄存单元开始，每连续的四级移位寄存单元中：第一级移位寄存单元的第一时钟信号端CLK1与第一时钟信号线CLK1’相连，第一级移位寄存单元的第二时钟信号端CLK2与第二时钟信号线CLK2’相连，第一级移位寄存单元的第四时钟信号端CLK4与第四时钟信号线CLK4’相连；第二级移位寄存单元的第一时钟信号端CLK1与第二时钟信号线CLK2’相连，第二级移位寄存单元的第二时钟信号端CLK2与第三时钟信号线CLK3’相连，第二级移位寄存单元的第四时钟信号端CLK4与第一时钟信号线CLK1’相连；第三级移位寄存单元的第一时钟信号端CLK1与第三时钟信号线CLK3’相连，第三级移位寄存单元的第二时钟信号端CLK2与第四时钟信号线CLK4’相连，第三级移位寄存单元的第四时钟信号端CLK4与第二时钟信号线CLK2’相连；第四级移位寄存单元的第一时钟信号端CLK1与第四时钟信号线CLK4’相连，第四级移位寄存单元的第二时钟信号端CLK2与第一时钟信号线CLK1’相连，第四级移位寄存单元的第四时钟信号端CLK4与第三时钟信号线CLK3’相连。
第一级移位寄存单元的正向触发信号输入端STUV与正向触发信号线STVU’相连，最后一级移位寄存单元的反向触发信号输入端与反向触发信号线STVD’相连。
在图4中，第一级移位寄存单元的输出端为OUTPUT1，第二级移位寄存单元的输出端为OUTPUT2，第三级移位寄存单元的输出端为OUTPUT3，第四级移位寄存单元的输出端为OUTPUT4，第N级移位寄存单元的输出端为OUTPUTN。
由于可以在正向扫描和反向扫描时分别使用正向输入模块和反向输入模块，因此，具有能够实现正向扫描和反向扫描的移位寄存单元的构造可以进一步提高移位寄存器的使用寿命。
图5示出了正向扫描模式下前四级移位寄存单元的信号输出端输出的信号以及各个信号端的时序。
图6示出了反向扫描模式下前四级移位寄存单元的信号输出端输出的信号以及各个信号端的时序。
作为本公开的第三个方面，提供一种栅极驱动电路，其中，所述栅极驱动电路包括移位寄存器和帧信号判断单元，所述移位寄存器为本公开所提供的上述移位寄存器，所述帧信号判断单元能够向所述移位寄存单元输出表征帧数的帧触发信号。
在本公开中，所谓的表征帧数的帧触发信号是指，表征该帧在一个帧周期中的帧数。例如，当帧周期包括奇数帧和偶数帧时，表征帧数的帧触发信号则可以是表征奇数帧的信号和表示偶数帧的信号(例如，分别由第一帧类别信号输入端和第二帧类别信号输入端提供的信号)。
作为本公开的第四个方面，提供一种显示面板，所述显示面板包括栅极驱动电路，其中，所述栅极驱动电路为本公开所提供的上述栅极驱动电路。
由于本公开所提供的上述栅极驱动电路具有较长的使用寿命，因此，所述显示面板也具有较长的使用寿命。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种移位寄存单元，所述移位寄存单元包括触发信号输入端、输入模块、上拉模块、下拉控制模块、多个下拉模块和信号输出端，
    其中，所述触发信号输入端与所述输入模块的控制端电连接，且所述触发信号输入端构造为在所述移位寄存单元的输入阶段向所述输入模块的控制端提供有效信号；
    所述输入模块的输出端与所述上拉模块的控制端电连接，所述输入模块构造为在该输入模块的控制端接收到有效信号时，向所述上拉模块的控制端提供有效信号；
    所述上拉模块的输入端与初始信号端电连接，所述上拉模块的输出端与所述信号输出端电连接，所述上拉模块构造为在该上拉模块的控制端接收到有效信号时，使得该上拉模块的输入端与该上拉模块的输出端电连接；
    每个所述下拉模块的输入端均与第二电平信号端电连接，每个所述下拉模块的第一输出端均与所述信号输出端电连接，每个所述下拉模块的第二输出端均与所述上拉模块的控制端电连接，对于每个下拉模块而言，当该下拉模块的控制端接收到有效信号时，使得该下拉模块的输入端和该下拉模块的第一输出端、该下拉模块的第二输出端电连接；
    所述下拉控制模块包括多个下拉控制信号输出端，所述多个下拉控制信号输出端分别与各个所述下拉模块的控制端电连接，所述下拉控制模块构造为在下拉阶段依次向各个所述下拉模块的控制端提供有效信号，以使得各个所述下拉模块分别在不同的帧周期开启，每个所述帧周期是用于显示一帧图像的时间段。
  2. 根据权利要求1所述的移位寄存单元，其中，所述不同的帧周期包括彼此交替的奇数帧周期和偶数帧周期，所述下拉模块包括奇数帧下拉模块和偶数帧下拉模块，
    所述下拉控制模块构造为在每个奇数帧周期的下拉阶段向所述 奇数帧下拉模块的控制端输出有效信号，并向所述偶数帧下拉模块的控制端输出无效信号，
    所述下拉控制模块构造为在每个偶数帧周期的下拉阶段向所述偶数帧下拉模块的控制端输出有效信号，并能够向所述奇数帧下拉模块的控制端输出无效信号。
  3. 根据权利要求2所述的移位寄存单元，其中，所述下拉控制模块包括下拉控制子模块、奇数帧触发子模块和偶数帧触发子模块，所述奇数帧触发子模块的第一输出端和所述偶数帧下拉模块的第二输出端彼此电连接作为所述下拉控制模块的第一输出端，所述奇数帧下拉模块的第二输出端和所述偶数帧触发子模块的第一输出端彼此电连接作为所述下拉控制模块的第二输出端；
    所述移位寄存单元还包括第一帧类别信号输入端和第二帧类别信号输入端，
    所述下拉控制子模块构造为在各帧的下拉阶段输出有效信号；
    所述奇数帧触发子模块的控制端与所述第一帧类别信号输入端电连接，所述奇数帧触发子模块的第一输入端与所述下拉控制子模块的输出端电连接，所述奇数帧触发子模块的第二输入端与所述第二电平信号端电连接，所述奇数帧触发子模块的第一输出端与所述偶数帧下拉模块的控制端电连接，所述奇数帧触发子模块的第二输出端与所述奇数帧下拉模块的控制端电连接，所述奇数帧触发子模块构造为在其控制端接收到有效信号时，将所述奇数帧触发子模块的第二输入端与所述奇数帧触发子模块的第一输出端电连接，并将所述奇数帧触发子模块的第一输入端与所述奇数帧触发子模块的第二输出端电连接；
    所述偶数帧触发子模块的控制端与所述第二帧类别信号输入端电连接，所述偶数帧触发子模块的第一输入端与所述下拉控制子模块的输出端电连接，所述偶数帧触发子模块的第二输入端与所述第二电平信号端电连接，所述偶数帧触发子模块的第一输出端与所述奇数帧下拉模块的控制端电连接，所述偶数帧触发子模块的第二输出端与所述偶数帧下拉模块的控制端电连接，所述偶数帧触发子模块构造为在 其控制端接收到有效信号时，将所述偶数帧触发子模块的第二输入端与所述偶数帧触发子模块的第一输出端电连接，并将所述偶数帧触发子模块的第一输入端与所述偶数帧触发子模块的第二输出端电连接。
  4. 根据权利要求3所述的移位寄存单元，其中，所述奇数帧触发子模块包括第一奇数帧触发晶体管和第二奇数帧触发晶体管，
    所述第一奇数帧触发晶体管的栅极与所述第一帧类别信号输入端电连接，所述第一奇数帧触发晶体管的第一极与所述奇数帧触发子模块的第一输入端电连接，所述第一奇数帧触发晶体管的第二极与所述奇数帧触发子模块的第二输出端电连接，
    所述第二奇数帧触发晶体管的栅极与所述第一帧类别信号输入端电连接，所述第二奇数帧触发晶体管的第一极与所述第二电平信号端电连接，所述第二奇数帧触发晶体管的第二极与所述奇数帧触发子模块的第一输出端电连接。
  5. 根据权利要求3所述的移位寄存单元，其中，所述偶数帧触发子模块包括第一偶数帧触发晶体管和第二偶数帧触发晶体管，
    所述第一偶数帧触发晶体管的栅极与所述第二帧类别信号输入端电连接，所述第一偶数帧触发晶体管的第一极与所述偶数帧触发子模块的第一输入端电连接，所述第一偶数帧触发晶体管的第二极与所述偶数帧触发子模块的第二输出端电连接；
    所述第二偶数帧触发晶体管的栅极与所述第二帧类别信号输入端电连接，所述第二偶数帧触发晶体管的第一极与所述第二电平信号端电连接，所述第二偶数帧触发晶体管的第二极与所述偶数帧触发子模块的第一输出端电连接。
  6. 根据权利要求2至5中任意一项所述的移位寄存单元，其中，所述奇数帧下拉模块包括第一奇数帧下拉晶体管、第二奇数帧下拉晶体管和第三奇数帧下拉晶体管；
    所述第一奇数帧下拉晶体管的栅极与所述奇数帧下拉模块的控 制端电连接，所述第一奇数帧下拉晶体管的第一极与所述信号输出端电连接，所述第一奇数帧下拉晶体管的第二极与所述第二电平信号端电连接；
    所述第二奇数帧下拉晶体管的第一极与所述上拉模块的控制端电连接，所述第二奇数帧下拉晶体管的第二极与所述第二电平信号端电连接，所述第二奇数晶体管的栅极与所述奇数帧下拉模块的控制端电连接；
    所述第三奇数帧下拉晶体管的栅极与所述上拉模块的控制端电连接，所述第三奇数帧下拉晶体管的第一极与所述奇数帧下拉模块的控制端电连接，所述第三奇数帧下拉晶体管的第二极与所述第二电平信号端电连接。
  7. 根据权利要求6所述的移位寄存单元，其中，所述奇数帧下拉晶体管还包括第一存储电容，所述第一存储电容的第一端与所述奇数帧下拉模块的控制端电连接，所述第一存储电容的第二端与所述第二电平信号端电连接。
  8. 根据权利要求2至5中任意一项所述的移位寄存单元，其中，所述偶数帧下拉模块包括第一偶数帧下拉晶体管、第二偶数帧下拉晶体管、第三偶数帧下拉晶体管，
    所述第一偶数帧下拉晶体管的栅极与所述偶数帧下拉模块的控制端电连接，所述第一偶数帧下拉晶体管的第一极与所述信号输出端电连接，所述第一偶数帧下拉晶体管的第二极与第二电平信号端电连接；
    所述第二偶数帧下拉晶体管的栅极与所述偶数帧下拉模块的控制端电连接，所述第二偶数帧下拉晶体管的第一极与所述上拉模块的控制端电连接，所述第二偶数帧下拉晶体管的第二极与所述第二电平信号端电连接；
    所述第三偶数帧下拉晶体管的栅极与所述上拉模块的控制端电连接，所述第三偶数帧下拉晶体管的第一极与所述第二电平信号端电 连接，所述第三偶数帧下拉晶体管的第二极与所述偶数帧下拉模块的控制端电连接。
  9. 根据权利要求8所述的移位寄存单元，其中，所述偶数帧下拉模块还包括第二存储电容，所述第二存储电容的第一端与所述偶数帧下拉模块的控制端电连接，所述第二存储电容的第二端与所述第二电平信号端电连接。
  10. 根据权利要求1至5中任意一项所述的移位寄存单元，其中，所述输入模块包括正向输入模块和反向输入模块，所述移位寄存单元包括正向信号端、反向信号端，所述触发信号输入端包括正向触发信号输入端和反向触发信号输入端，所述下拉控制子模块包括正向下拉控制子模块和反向下拉控制子模块，
    所述正向输入模块的控制端与所述正向触发信号输入端电连接，所述正向输入模块的输入端与所述正向信号端电连接，所述正向输入模块的输出端与所述输入模块的输出端电连接；
    所述反向输入模块的控制端与所述反向触发信号输入端电连接，所述反向输入模块的输入端与所述反向信号端电连接，所述反向输入模块的输出端与所述上拉模块的控制端电连接；
    所述正向下拉控制子模块的控制端与所述正向信号端电连接，所述正向下拉控制子模块的输入端与第二时钟信号端电连接，所述正向下拉控制子模块的输出端与所述反向下拉控制子模块的输出端电连接，且与所述奇数帧触发子模块的第一输入端以及所述偶数帧触发子模块的第一输入端电连接；
    所述反向下拉控制子模块的控制端与所述反向信号端电连接，所述反向下拉控制子模块的输入端与第四时钟信号端电连接，所述反向下拉控制子模块的输出端与所述正向下拉控制子模块的输出端电连接。
  11. 根据权利要求10所述的移位寄存单元，其中，所述正向输 入模块构造为当其控制端接收到有效信号时，将所述正向输入模块的输入端与所述正向输入模块的输出端电连接；
    所述反向输入模块构造为当其控制端接收到有效信号时，将所述反向输入模块的输入端与所述反向输入模块的输出端电连接；
    所述正向下拉控制子模块构造为在所述正向信号端提供有效信号且所述反向信号端提供无效信号时输出由所述正向信号端提供的有效信号；
    所述反向下拉控制子模块构造为在所述正向信号端提供无效信号且所述反向信号端提供有效信号时输出由所述反向信号端提供的有效信号。
  12. 根据权利要求11所述的移位寄存单元，其中，所述正向输入模块包括正向输入晶体管，所述正向输入晶体管的栅极与所述正向输入模块的控制端电连接，所述正向输入晶体管的第一极与所述正向输入模块的输入端电连接，所述正向输入晶体管的第二极与所述正向输入模块的输出端电连接。
  13. 根据权利要求11所述的移位寄存单元，其中，所述反向输入模块包括反向输入晶体管，所述反向输入晶体管的栅极与所述反向输入模块的控制端电连接，所述反向输入晶体管的第一极与所述反向输入模块的输入端电连接，所述反向输入晶体管的第二极与所述反向输入模块的输出端电连接。
  14. 根据权利要求11所述的移位寄存单元，其中，所述正向下拉控制子模块包括第一正向下拉控制晶体管和第二正向下拉控制晶体管，
    所述第一正向下拉控制晶体管的栅极与所述正向下拉控制子模块的控制端电连接，所述第一正向下拉控制晶体管的第一极与所述第二时钟信号端电连接，所述第一正向下拉控制晶体管的第二极与所述第二下拉控制晶体管的栅极电连接；
    所述第二正向下拉控制晶体管的第一极与所述第二时钟信号端电连接，所述第二正向下拉控制晶体管的第二极与所述正向下拉控制子模块的输出端电连接。
  15. 根据权利要求11所述的移位寄存单元，其中，所述反向下拉控制子模块包括第一反向下拉控制晶体管和第二反向下拉控制晶体管，
    所述第一反向下拉控制晶体管的栅极与所述反向信号端电连接，所述第一反向下拉控制晶体管的第一极与所述第四时钟信号端电连接，所述第一反向下拉控制晶体管的第二极与所述第二反向下拉控制晶体管的栅极电连接；
    所述第二反向下拉控制晶体管的第一极与所述第四时钟信号端电连接，所述第二反向下拉控制晶体管的第二极与所述反向下拉控制子模块的输出端电连接。
  16. 根据权利要求1至5中任意一项所述的移位寄存单元，其中，所述上拉模块包括上拉晶体管和第三存储电容，所述初始信号端包括第一时钟信号端，
    所述上拉晶体管的栅极与所述上拉模块的控制端电连接，所述上拉晶体管的第一极与所述第一时钟信号端电连接，所述上拉晶体管的第二极与所述信号输出端电连接；
    所述第三存储电容的第一端与所述上拉晶体管的栅极电连接，所述第三存储电容的第二端与所述信号输出端电连接。
  17. 一种移位寄存器，所述移位寄存器包括级联的多个移位寄存单元，其中，所述多个移位寄存单元中的每一个为权利要求1至16中任意一项所述的移位寄存单元。
  18. 一种栅极驱动电路，其中，所述栅极驱动电路包括移位寄存器和帧信号判断单元，所述移位寄存器为权利要求17所述的移位 寄存器，所述帧信号判断单元构造为向所述移位寄存单元输出表征帧数的帧触发信号。
  19. 一种显示面板，所述显示面板包括栅极驱动电路，其中，所述栅极驱动电路为权利要求18所述的栅极驱动电路。
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