WO2018149100A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2018149100A1
WO2018149100A1 PCT/CN2017/096598 CN2017096598W WO2018149100A1 WO 2018149100 A1 WO2018149100 A1 WO 2018149100A1 CN 2017096598 W CN2017096598 W CN 2017096598W WO 2018149100 A1 WO2018149100 A1 WO 2018149100A1
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WIPO (PCT)
Prior art keywords
signal line
substrate
conductive member
conductive
array substrate
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PCT/CN2017/096598
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English (en)
French (fr)
Inventor
董向丹
高永益
朴进山
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/751,410 priority Critical patent/US11011551B2/en
Priority to EP17835995.6A priority patent/EP3584840A4/en
Publication of WO2018149100A1 publication Critical patent/WO2018149100A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • Embodiments of the present invention relate to an array substrate and a display device.
  • an organic light emitting unit and a pixel circuit for supplying a driving current to the organic light emitting unit are disposed in each pixel unit.
  • the pixel circuit is provided with a high-level signal end and a low-level signal end to respectively receive a high-level signal and a low-level signal, and the high-level signal and the low-level signal are respectively composed of a high-level signal line and a low-level signal. Line available. At present, the resistance of the high-level signal line and the low-level signal line is relatively large, which results in different signals received by the pixel circuits in different regions, thereby causing different brightness of the organic light-emitting units in different regions, thereby affecting display uniformity. .
  • An embodiment of the present invention provides an array substrate including a substrate and a signal line disposed on the substrate, and the substrate is further provided with at least one conductive member corresponding to the signal line, the signal line and The corresponding conductive members are connected in parallel, and the conductive members corresponding to the different signal lines are insulated.
  • an organic light emitting unit is further disposed on the substrate, and the signal line includes a high level signal line and/or a low level signal line.
  • the signal line and the conductive member are respectively disposed on both sides of the substrate along the thickness direction thereof, and the region corresponding to each signal line on the substrate is formed with at least two via holes, the lining A connecting member corresponding to each of the through holes is further disposed on the bottom, and each of the connecting members passes through the through hole to connect the signal line with the corresponding conductive member.
  • the substrate is a flexible substrate.
  • the connector comprises a conductive silver paste.
  • the conductive member and the signal line are disposed on the same side of the substrate along the thickness direction thereof, and an insulating spacer layer is disposed between the conductive member and the signal line, and the insulating spacer layer and each
  • Each of the signal lines corresponds to at least two via holes
  • the substrate is further provided Connecting members respectively corresponding to the respective via holes are provided, and each of the connecting members connects the signal lines in parallel with the corresponding conductive members through the via holes.
  • the material forming the conductive member includes a two-layer structure conductive material of copper and graphite.
  • another embodiment of the present invention further provides a display device comprising the above array substrate provided by the present invention.
  • a further embodiment of the present invention further provides a display device comprising the above array substrate provided by the present invention, wherein the signal line and the conductive member are respectively disposed on two sides of the substrate along a thickness direction thereof.
  • the display device further includes a flexible circuit board including a connection line corresponding to the signal line, and one end of the signal line is connected to the conductive member through a corresponding connection line on the flexible circuit board; The other end of the signal line is connected to the conductive member through at least one via.
  • a portion of the flexible circuit board is disposed on a side of the substrate on which the signal line is formed and is electrically connected to the signal line, and another portion of the flexible wiring board is folded over to the substrate to be formed
  • One side of the conductive member is electrically connected to the conductive member.
  • the flexible circuit board includes a flexible substrate, the connecting line is disposed on a side of the flexible substrate facing the array substrate, and the flexible substrate is further provided with an insulating layer, the insulating layer covers the connecting line And exposing a first predetermined connection area and a second predetermined connection area, wherein the first predetermined connection area is an area connected to the signal line, and the second predetermined connection area is an area connected to the conductive member, The second predetermined connection region is connected to the conductive member through a connector.
  • the at least one via hole is formed on the substrate and corresponds to the signal line, and the substrate is further provided with connecting members respectively corresponding to the respective via holes, and each of the connecting members passes through the corresponding A via hole connects a portion of the signal line that is not connected to the connection line to a corresponding conductive member.
  • the connector comprises a conductive silver paste.
  • the substrate of the array substrate is a flexible substrate.
  • 1a is a schematic front view of an array substrate according to a first embodiment of the present invention
  • Figure 1b is a schematic view of the back structure corresponding to Figure 1a;
  • Figure 1c is a schematic view of the array substrate of Figure 1a;
  • Figure 2a is a cross-sectional view taken along line A-A' of Figure 1a;
  • FIG. 2b is a schematic structural view of the first via after forming the structure of FIG. 1a;
  • 3a is a schematic front view of an array substrate according to a second embodiment of the present invention.
  • Figure 3b is a schematic view of the back structure corresponding to Figure 3a;
  • FIG. 4a is a schematic front view of a display device according to a third embodiment
  • Figure 4b is a schematic view of the back structure corresponding to Figure 4a;
  • Figure 5a is a cross-sectional view taken along line B-B' of Figure 4a;
  • Figure 5b is a cross-sectional view taken along line C-C' of Figure 4b.
  • One embodiment of the present invention provides an array substrate for a display device, such as an OLED display device. 1a to 3b, the array substrate includes a substrate 10 and a signal line disposed on the substrate 10 (such as a high-level signal line VDD and a low level in FIG. 1a).
  • the signal line VSS is further provided with a conductive member 12 corresponding to the signal line, and the signal line is connected in parallel with the corresponding conductive member 12, and the conductive members 12 corresponding to the different signal lines are insulated and spaced apart.
  • the parallel connection of the signal line with the corresponding conductive member 12 means that at least two different positions on the signal line are respectively connected to two different positions on the conductive member, so that the resistance after the signal line is connected in parallel with the conductive member 12 is smaller than the signal line. Its own resistance.
  • the signal line is used to provide an electrical signal to the pixel unit.
  • the resistance of the signal line is large, the voltage division on the signal line is large. Therefore, even when the same brightness is displayed, the display of the array substrate is used.
  • the electrical signals received by the pixel units in different regions of the device are not the same, resulting in different actual brightness of different regions, and the display uniformity is lowered.
  • the resistor is connected in parallel on the signal line, so that the resistance of the signal line can be reduced, and the voltage division on the signal line can be reduced, thereby making the pixel of the array substrate different positions.
  • the electrical signals received by the unit have a small difference, thereby improving the uniformity of the display.
  • the array substrate is suitable for use in an organic light emitting diode (OLED) display device, that is, the substrate 10 is further provided with an organic light emitting unit 101.
  • the signal line includes a high level signal line VDD and/or a low level signal line VSS.
  • the organic electroluminescent display device includes a plurality of pixel units 100.
  • Each of the pixel units 100 includes an organic light emitting unit 101 and a pixel driving circuit 102 for supplying a driving current to the organic light emitting unit 101 to drive the organic light emitting unit 101 to emit light.
  • the signal line is electrically coupled to the pixel drive circuit or, as part of the pixel circuit, provides an electrical signal to the pixel circuit to drive the organic light emitting unit to emit light.
  • the divided voltage on the high-level signal line VDD and/or the low-level signal line VSS decreases, and the pixel driving circuit of different regions
  • the signal difference received by the high-level signal end and the low-level signal end is reduced, so that the difference in driving current supplied to the corresponding organic light-emitting unit by the pixel driving circuit in different regions is reduced, thereby improving display uniformity and improving display effect.
  • the same signal line can be connected in parallel with the same conductive member 12, or a plurality of conductive members 12 can be connected in parallel at the same time.
  • the two parts of the high-level signal line VDD are respectively and two.
  • the two portions of the conductive member 12 in parallel and the low-level signal line VSS are also respectively connected in parallel with the two conductive members 12.
  • the high level signal line VDD is taken as an example, when the high level signal line
  • the shapes and sizes of the corresponding two conductive members 12 are also set to be the same (as shown in Figure 1b, the two conductive members 12 on the left and right sides have the same size and shape; the middle two The conductive members 12 are the same in size and shape, so that the resistance of the different portions of the high-level signal line VDD after the parallel connection of the conductive members 12 is also the same.
  • the conductive members 12 and the signal lines may be disposed in different layers of the insulating spacer.
  • the signal lines and the conductive members 12 are respectively disposed on both sides of the substrate 10 along the thickness direction thereof, and at least two regions corresponding to each of the signal lines are formed on the substrate 10.
  • the first via hole v1 is further provided with a first connecting member 11 corresponding to each of the first via holes v1, and each of the first connecting members 11 passes the signal line and the corresponding conductive through the first via hole v1.
  • Pieces 12 are connected in parallel.
  • the material forming the conductive member 12 may be a transparent conductive material or a non-transparent conductive material.
  • the array substrate is particularly suitable for use in an organic electroluminescence display device, and in this case, even if the conductive member 12 is made of a non-transparent material, the display is not affected.
  • the material forming the conductive member 12 may include a metal material having good electrical conductivity, such as copper or copper alloy, aluminum or aluminum alloy, or the like, or a non-metallic conductive material such as a transparent conductive material of ITO, or other conductive material, Double-layer conductive materials such as copper and graphite.
  • the substrate 10 is a flexible substrate, and the material thereof may include, for example, polyimide (PI), and when the first via hole v1 is formed, laser drilling may be employed. This embodiment does not limit the laser used.
  • PI polyimide
  • the signal line may be connected in parallel with the conductive member 12 in the non-display area of the array substrate, that is, the first via hole v1 and the first connection member 11 for connecting the signal line and the conductive member 12 in parallel in the non-display area.
  • a signal line, a thin film transistor array, and an organic electroluminescent organic light-emitting unit are formed on the substrate 10 to obtain an array substrate.
  • the signal line and the substrate 10 are simultaneously formed by laser drilling.
  • a first via hole v1 (as shown in FIG.
  • the conductive member 12 is formed on the other side of the substrate 10 by attaching a metal layer; finally, at a position corresponding to each of the first via holes v1 Forming the first connecting member 11 such that the first connecting member 11 electrically connects the signal line and the corresponding conductive member 12 through the first via hole v1 Connection (as shown in Figure 2a).
  • the first connector 11 may comprise a conductive silver paste.
  • the first via hole v1 penetrating the signal line and the substrate can be directly dripped, and patterning is not required, thereby simplifying the manufacturing process.
  • the first via hole v1 may also pass through the substrate 10 and be disposed beside the signal line.
  • the first connecting member 11 may adopt a structure of a conductive film layer, and one end is disposed on the signal line and connected to the signal line; The other end is deposited in the first via hole v1 and connected to the conductive member 12.
  • the signal line may further include a signal transmission portion VSS1 and a connection portion VSS2 (as shown in FIGS. 1a and 4a), the signal transmission portion VSS1 and the connection portion VSS2 are electrically connected, and the first via hole v1 may be disposed corresponding to the signal transmission portion
  • the position of VSS1 is such that the first connecting member 11 connects the signal transmitting portion VSS1 with the conductive member 12 through the first via hole v1; it may also be disposed at a position corresponding to the connecting portion VSS2 such that the first connecting member 11 passes the first
  • the via hole v1 connects the connection portion VSS2 to the conductive member 12.
  • the conductive member 12 when the signal line includes only the high-level signal line VDD, the conductive member 12 may be formed as a whole film layer on the substrate 10, thereby reducing the resistance of the signal line to a greater extent; A plurality of first via holes v1 are uniformly disposed at positions corresponding to the signal lines on the 10th.
  • the high-level signal can be obtained under the premise that the high-level signal line VDD and the low-level signal line VSS respectively correspond to the insulation interval of the conductive member 12
  • the area covered by the line VDD and the low-level signal line VSS on the substrate 10 is as large as possible to minimize the resistance thereof, thereby minimizing the resistance and low-voltage of the high-level signal line VDD in parallel with the conductive member 12.
  • the conductive member 12 and the signal line may be disposed on the same side of the substrate 10 along the thickness direction thereof, and the conductive member 12
  • the signal lines are arranged in different layers (the corresponding diagrams are not given).
  • An insulating spacer layer is disposed between the conductive member 12 and the signal line, and at least two second via holes are disposed in the region corresponding to the insulating spacer layer and each signal line, and the substrate 10 is further provided with a second The holes respectively correspond to the second connecting members, and each of the second connecting members connects the signal lines with the corresponding conductive members 12 through the second through holes.
  • the second via may also penetrate the insulating spacer and the signal line at the same time, and the second connector may also be a conductive silver paste implanted in the second via.
  • Another embodiment of the present invention provides a display device including the above array substrate.
  • a signal line and a corresponding conductive member 12 are disposed on the substrate 10 of the array substrate, and the signal lines are connected in parallel with the corresponding conductive members 12.
  • the array substrate may include an organic light emitting unit.
  • the signal line includes a high level signal line VDD and a low level signal line VSS
  • the display device may further include a package for encapsulating the display area of the array substrate. Encapsulation layer.
  • the first exemplary structure of the display device may be as follows. As described above, in the array substrate, the signal lines and the conductive members 12 are respectively disposed on both sides of the substrate 10, and the positions of the corresponding signal lines on the substrate 10 form at least two first via holes v1, and the substrate 10 is further The first connecting member 11 is disposed, and each of the first connecting members 11 connects the signal line and the conductive member 12 in parallel through the first via hole v1. Alternatively, the signal line and the conductive member 12 are disposed on the same side of the substrate 10, and an insulating spacer layer is disposed between the signal line and the conductive member 12. The insulating spacer layer is provided with a plurality of second via holes, the signal line and the conductive member 12. Connected by respective second connectors that pass through the second via.
  • a second exemplary structure of the display device may be as follows. As shown in FIG. 4a to FIG. 5b, it includes an array substrate and a flexible wiring board 20, and signal lines (such as a high-level signal line VDD and a low-level signal line VSS in FIG. 4a) and a conductive member 12 are respectively disposed in the array substrate. On both sides of the substrate 10 in the thickness direction thereof.
  • the flexible wiring board 20 is connected to an array substrate, a driving circuit board (not shown) such that the driving circuit board supplies driving signals to the array substrate through the flexible wiring board 20.
  • the flexible wiring board 20 includes a connecting line 21 corresponding to the signal line, and one end of the signal line is connected to the conductive member 12 through a corresponding connecting line 21 on the flexible wiring board.
  • a portion of the flexible circuit board 20 is disposed on a side of the substrate 10 on which the signal line is formed and electrically connected to the signal line, and another portion of the flexible wiring board 20 is folded over to the substrate 10 in which the conductive member 12 is formed. One side is electrically connected to the conductive member 12.
  • the other end of the signal line is connected to the conductive member 12 through at least one first via.
  • the first via hole v1 is formed on the substrate 10 and corresponds to the signal line, the first via hole v1 penetrates through the substrate 10, and the substrate 10 is further provided with a first corresponding to each of the first via holes v1.
  • the connecting member 11, each of the first connecting members 11 connects the position of the signal line not connected to the connecting line 21 to the corresponding conductive member 12 through the first via hole v1.
  • first via hole v1 corresponding to the signal line may include various situations, for example, the first via hole v1 penetrates the position where the signal line is not connected to the connection line 21 and the substrate 10; or The first via v1 is placed beside the signal line.
  • the signal line is connected in parallel with the conductive member 12 through the first connecting member 11 in the two or more first via holes v1; the second structure in the display device The signal line is connected in parallel with the conductive member 12 through the first connecting member 11 in the first via hole v1 on the substrate and the connecting line 21 on the flexible wiring board 20.
  • the substrate 10 also employs a flexible substrate to facilitate puncturing.
  • the flexible wiring board 20 includes a flexible substrate 22, and a connecting line 21 is disposed on a side of the flexible substrate 22 facing the array substrate.
  • An insulating layer 24 is further disposed on the flexible substrate 22.
  • the insulating layer 24 covers the connecting line 21 and exposes a first predetermined connecting area and a second predetermined connecting area.
  • the first predetermined connecting area is an area connected to the signal line.
  • the second predetermined connection region is a region connected to the conductive member 12, and the second predetermined connection region is connected to the conductive member 12 through the third connecting member 23.
  • the first connecting member 11 and the third connecting member 23 may each comprise a conductive silver paste.
  • the signal line is connected in parallel with the conductive member, the resistance is connected in parallel on the signal line, so that the resistance of the signal line can be reduced.
  • the signal line can be a high-level signal line and a low-level signal line, and the reduction of the signal line resistance can reduce the voltage division on the signal line, thereby causing the pixel substrate to be in different positions in the pixel unit.
  • the driving current of the organic light emitting unit has a small difference in phase, thereby improving display uniformity.
  • the signal lines and the conductive members may be respectively disposed on both sides of the substrate, so that the substrates simultaneously function as load and insulation intervals, thereby reducing the thickness of the signal line while making the thickness of the display device small.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Electroluminescent Light Sources (AREA)
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Abstract

一种阵列基板及显示装置，阵列基板包括衬底（10）和设置在衬底上的信号线（VDD，VSS），衬底上还设置有与信号线对应的至少一个导电件（12），信号线与相应的导电件并联，不同信号线对应的导电件绝缘间隔，由此能够减小信号线的电阻，从而改善显示效果。

Description

阵列基板和显示装置 技术领域
本发明的实施例涉及一种阵列基板和显示装置。
背景技术
在有机电致发光(Organic Light-Emitting Diode，OLED)显示器件中，每个像素单元内均设置有有机发光单元和用于为该有机发光单元提供驱动电流的像素电路。像素电路设置有高电平信号端和低电平信号端，以分别接收高电平信号和低电平信号，高电平信号和低电平信号分别由高电平信号线和低电平信号线提供。目前，高电平信号线和低电平信号线的电阻较大，这就导致不同区域的像素电路接收到的信号不同，从而使得不同区域的有机发光单元的亮度不同，进而影响显示的均一性。
发明内容
本发明的实施例提供一种阵列基板，包括衬底和设置在衬底上的信号线，所述衬底上还设置有与所述信号线对应的至少一个导电件，所述信号线和与之相应的导电件并联，不同信号线对应的导电件绝缘间隔。
例如，所述衬底上还设置有有机发光单元，所述信号线包括高电平信号线和/或低电平信号线。
例如，所述信号线和导电件分别设置在所述衬底的沿其厚度方向的两侧，所述衬底上与每条信号线对应的区域均形成有至少两个过孔，所述衬底上还设置有与各过孔分别对应的连接件，各个所述连接件穿过所述过孔将所述信号线与相应的导电件并联。
例如，所述衬底为柔性衬底。
例如，所述连接件包括导电银胶。
例如，所述导电件与所述信号线设置在所述衬底的沿其厚度方向的同一侧，所述导电件与所述信号线之间设置有绝缘间隔层，所述绝缘间隔层与每个信号线对应的区域均设置有至少两个过孔，所述衬底上还设 置有与各过孔分别对应的连接件，各个所述连接件通过所述过孔将所述信号线与相应的导电件并联。
例如，形成所述导电件的材料包括铜和石墨的双层结构导电材料。
相应地，本发明的另一个实施例还提供一种显示装置，包括本发明提供的上述的阵列基板。
相应地，本发明的再一个实施例还提供一种显示装置，包括本发明提供的上述阵列基板，所述信号线和导电件分别设置在所述衬底的沿其厚度方向的两侧，所述显示装置还包括柔性线路板，所述柔性线路板包括与所述信号线对应的连接线，所述信号线的一端通过所述柔性线路板上相应的连接线与所述导电件相连；所述信号线的另一端通过至少一个过孔与所述导电件相连。
例如，所述柔性电路板的一部分设置在所述衬底形成有所述信号线的一侧并与所述信号线电连接，所述柔性线路板的另一部分翻折至所述衬底形成有所述导电件的一侧并与所述导电件电连接。
例如，所述柔性线路板包括柔性基底，所述连接线设置在所述柔性基底朝向所述阵列基板的一侧，所述柔性基底上还设置有绝缘层，所述绝缘层覆盖所述连接线并露出第一预定连接区和第二预定连接区，所述第一预定连接区为与所述信号线相连的区域，所述第二预定连接区为与所述导电件相连的区域，所述第二预定连接区域与所述导电件通过连接件相连。
例如，所述至少一个过孔形成在所述衬底上并与所述信号线对应，所述衬底上还设置有与各过孔分别对应的连接件，各个所述连接件穿过所对应的过孔将所述信号线的未与所述连接线连接的部分与相应的导电件相连。
例如，所述连接件包括导电银胶。
例如，所述阵列基板的衬底为柔性衬底。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一 些实施例，而非对本发明的限制。
图1a是本发明第一实施例提供的一种阵列基板的正面结构示意图；
图1b是与图1a相对应的背面结构示意图；
图1c是图1a中阵列基板的示意图；
图2a是图1a中沿A-A’线的剖视图；
图2b是在制作图1a的结构时形成第一过孔后的结构示意图；
图3a是本发明第二实施例提供的一种阵列基板的正面结构示意图；
图3b是与图3a相对应的背面结构示意图；
图4a是第三实施例提供的一种显示装置的正面结构示意图；
图4b是与图4a对应的背面结构示意图；
图5a是图4a中沿B-B’线的剖视图；
图5b是图4b中沿C-C’线的剖视图。
其中，附图标记为：
10、衬底；11、第一连接件；12、导电件；VDD、高电平信号线；VSS、低电平信号线；VSS1、信号传输部；VSS2、连接部；v1、第一过孔；v3、第三过孔；20、柔性线路板；21、连接线；22、柔性基底；23、第三连接件；24、绝缘层；100、像素单元；101、有机发光单元；102、像素驱动电路。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。本发明的一个实施例提供了一种阵列基板，该阵列基板用于显示装置，例如OLED显示装置。结合图1a至图3b所示，该阵列基板包括衬底10和设置在衬底10上的信号线(如图1a中的高电平信号线VDD和低电平 信号线VSS)，衬底10上还设置有与所述信号线对应的导电件12，所述信号线与相应的导电件12并联，不同信号线对应的导电件12绝缘间隔。所述信号线与相应的导电件12并联是指，信号线上至少两个不同位置分别与导电件上的两个不同位置对应相连，从而使得信号线与导电件12并联后的电阻小于信号线本身的电阻。
所述信号线用于向像素单元提供电信号，当信号线的电阻较大时，信号线上的分压也就较大，因此，即使在显示同一亮度的情况下，采用该阵列基板的显示装置的不同区域的像素单元接收到的电信号并不相同，导致不同区域的实际亮度并不相同，显示均一性降低。而本实施例中，由于信号线与导电件12并联，相当于在信号线上并联了电阻，因而可以降低信号线的电阻，减小信号线上的分压，从而使得阵列基板不同位置的像素单元接收到的电信号相差较小，进而提高显示的均一性。
所述阵列基板适用于有机电致发光(Organic Light Emitting Diode，OLED)显示装置中，即，衬底10上还设置有有机发光单元101。所述信号线包括高电平信号线VDD和/或低电平信号线VSS。请参阅图1c，所述有机电致发光显示装置包括多个像素单元100。每一像素单元100包括有机发光单元101与像素驱动电路102，像素驱动电路102用于为有机发光单元101提供驱动电流，以驱动有机发光单元101发光。所述信号线与所述像素驱动电路电连接，或作为所述像素电路的一部分，为所述像素电路提供电信号，从而驱动所述有机发光单元发光。当高电平信号线VDD和/或低电平信号VSS的电阻降低时，高电平信号线VDD和/或低电平信号线VSS上的分压减小，不同区域的像素驱动电路上的高电平信号端和低电平信号端接收到的信号差异减小，从而使得不同区域的像素驱动电路提供给相应的有机发光单元的驱动电流差异减小，进而提高显示均一性，改善显示效果。
可以理解的是，同一信号线可以与同一个导电件12并联，也可以同时并联多个的导电件12，结合图1a和图1b所示，高电平信号线VDD的两部分分别与两个导电件12并联、低电平信号线VSS的两部分也分别与两个导电件12并联。这种情况下，为了使得高、低电平信号线并连后的电阻分布更均匀，以高电平信号线VDD为例，当高电平信号线 VDD的两部分原本的电阻相同时，将其对应的两个导电件12的形状、大小也设置为相同(如图1b中左右两侧的两个导电件12大小、形状相同；中间的两个导电件12的大小、形状相同)，从而使得高电平信号线VDD的不同部分在分别并联导电件12之后的电阻也是相同的。
由于阵列基板上的走线较多，因此，为了防止导电件12的设置影响其他信号线或导电结构，可以将导电件12与信号线设置在绝缘间隔的不同层中。例如，结合图1a至图3b，所述信号线和导电件12分别设置在衬底10的沿其厚度方向的两侧，衬底10上与每条信号线对应的区域均形成有至少两个第一过孔v1，衬底10上还设置有与各第一过孔v1分别对应的第一连接件11，各个第一连接件11通过第一过孔v1将所述信号线与相应的导电件12并联。将信号线和导电件12分别设置在衬底10的两侧时，衬底10可以同时起到承载和绝缘间隔的作用，从而可以在减小信号线电阻的同时，使得阵列基板达到较小的厚度。
形成导电件12的材料可以为透明导电材料，也可以为非透明导电材料。如上文所述，所述阵列基板尤其适用于有机电致发光显示装置中，这时，即使使用非透明材料制作导电件12，也不会影响显示。例如，形成导电件12的材料可以包括导电性能较好的金属材料，例如铜或铜合金、铝或铝合金等，或者例如非金属导电材料，例如ITO的透明导电材料，又或者其它导电材料，如铜和石墨的双层结构导电材料等。
为了便于在衬底10上形成过孔，例如，衬底10为柔性衬底，其材料例如可以包括聚酰亚胺(PI)，在制作第一过孔v1时，可以采用激光打孔的方式，本实施例对于所使用的激光不做限制。
例如，信号线可以在阵列基板的非显示区与导电件12并联，即，用于将信号线和导电件12并联的第一过孔v1和第一连接件11设置在非显示区。制作过程中，可以先在衬底10上形成信号线、薄膜晶体管阵列以及有机电致有机发光单元等结构，得到阵列基板；然后，再通过激光打孔的方式形成同时贯穿信号线和衬底10的第一过孔v1(如图2b所示)；之后，通过贴附金属层的方式在衬底10的另一侧形成导电件12；最后，在对应每个第一过孔v1的位置均形成第一连接件11，从而使所述第一连接件11通过第一过孔v1将信号线与相应的导电件12电 连接(如图2a所示)。
第一连接件11可以包括导电银胶。在上述制作过程中，直接向贯穿信号线和衬底的第一过孔v1中滴注即可，不需要进行构图，从而简化制作工艺。当然，第一过孔v1也可以只贯穿衬底10，并设置在信号线旁边，这时，第一连接件11可以采用导电膜层的结构，一端设置在信号线上而与信号线连接；另一端沉积在第一过孔v1中，与导电件12相连。
例如，信号线还可以包括信号传输部VSS1和连接部VSS2(如图1a和图4a所示)，信号传输部VSS1和连接部VSS2电连接，第一过孔v1可以设置在对应于信号传输部VSS1的位置，以使得第一连接件11通过第一过孔v1将信号传输部VSS1与导电件12相连；也可以设置在对应于连接部VSS2的位置，以使得第一连接件11通过第一过孔v1将连接部VSS2与导电件12相连。
如图3a所示，当所述信号线仅包括高电平信号线VDD时，导电件12可以为形成衬底10上的整层膜层，从而更大程度地降低信号线的电阻；衬底10上对应信号线的位置均匀设置多个第一过孔v1。当信号线包括高电平信号线VDD和低电平信号VSS时，在保证高电平信号线VDD和低电平信号线VSS分别对应的导电件12绝缘间隔的前提下，可以高电平信号线VDD和低电平信号线VSS在衬底10上覆盖的面积尽量大，以尽量减小其电阻，从而尽可能地减小高电平信号线VDD与导电件12并联后的电阻以及低电平信号线VSS与导电件12并联后的电阻。
当然，除了上述将导电件12和信号线分别设置在衬底10两侧的结构以外，还可以将导电件12和信号线设置在衬底10的沿其厚度方向的同一侧，且导电件12与所述信号线设置在不同层中(未给出相应的示图)。导电件12与所述信号线之间设置有绝缘间隔层，绝缘间隔层与每个信号线对应的区域均设置有至少两个第二过孔，衬底10上还设置有与各第二过孔分别对应的第二连接件，各个所述第二连接件通过所述第二过孔将所述信号线与相应的导电件12并联。和第一过孔类似地，第二过孔也可以同时贯穿绝缘间隔层和信号线，且第二连接件也可以为注入在第二过孔内的导电银胶。
本发明的另一个实施例提供了一种显示装置，包括上述阵列基板。阵列基板的衬底10上设置有信号线和相应的导电件12，信号线与相应的导电件12并联。并且，所述阵列基板可以包括有机发光单元，这时，信号线包括高电平信号线VDD和低电平信号线VSS，所述显示装置还可以包括用于对阵列基板的显示区进行封装的封装层。
所述显示装置的第一种示例性结构可以为如下所述。如上文所述，在阵列基板中，信号线和导电件12分别设置在衬底10的两侧，衬底10上对应信号线的位置形成至少两个第一过孔v1，衬底10上还设置第一连接件11，各个第一连接件11通过第一过孔v1将信号线和导电件12并联。或者，信号线和导电件12均设置在衬底10的同一侧，信号线与导电件12之间设置绝缘间隔层，绝缘间隔层上设置有多个第二过孔，信号线和导电件12通过各个穿过第二过孔的第二连接件相连。
所述显示装置的第二种示例性结构可以为如下所述。如图4a至图5b所示，其包括阵列基板和柔性线路板20，阵列基板中信号线(如图4a中的高电平信号线VDD和低电平信号线VSS)和导电件12分别设置在衬底10的沿其厚度方向的两侧。柔性线路板20与阵列基板、驱动电路板(未示出)相连，以使得驱动电路板通过柔性线路板20为阵列基板提供驱动信号。柔性线路板20包括与信号线对应的连接线21，所述信号线的一端通过所述柔性线路板上相应的连接线21与导电件12相连。例如，柔性电路板20的一部分设置在衬底10形成有所述信号线的一侧并与所述信号线电连接，柔性线路板20的另一部分翻折至衬底10形成有导电件12的一侧并与导电件12电连接。
所述信号线的另一端通过至少一个第一过孔与导电件12相连。例如，第一过孔v1形成在衬底10上并与所述信号线对应，第一过孔v1贯穿衬底10，衬底10上还设置有与各第一过孔v1分别对应的第一连接件11，各个第一连接件11通过第一过孔v1将所述信号线的未与连接线21连接的位置与相应的导电件12相连。
需要说明的是，所述“与信号线对应的第一过孔v1”可以包括多种情形，例如第一过孔v1同时贯穿信号线未与连接线21连接的位置和衬底10；或者，第一过孔v1设置在信号线的旁边。
可见，在显示装置的第一种结构中，信号线是通过两个或两个以上第一过孔v1内的第一连接件11实现与导电件12的并联；在显示装置的第二种结构中，所述信号线通过衬底上第一过孔v1内的第一连接件11和柔性线路板20上的连接线21实现与导电件12的并联。在第二种结构中，衬底10同样采用柔性衬底，以便于打孔。
例如，在显示装置的第二种结构中，如图5b所示，柔性线路板20包括柔性基底22，连接线21设置在所述柔性基底22朝向所述阵列基板的一侧。柔性基底22上还设置有绝缘层24，绝缘层24覆盖所述连接线21并露出第一预定连接区和第二预定连接区，所述第一预定连接区为与信号线相连的区域，所述第二预定连接区为与导电件12相连的区域，所述第二预定连接区域与所述导电件12通过第三连接件23相连。其中，第一连接件11和第三连接件23均可以包括导电银胶。
以上为对本发明实施例提供的阵列基板和显示装置的描述，可以看出，由于信号线与导电件并联，相当于在信号线上并联了电阻，因而可以降低信号线的电阻。在有机电致发光显示装置中，信号线可以为高电平信号线和低电平信号线，信号线电阻的降低可以减小信号线上的分压，从而使得阵列基板不同位置的像素单元中的有机发光单元的驱动电流相差较小，进而提高显示的均一性。并且，信号线和导电件可以分别设在衬底的两侧，从而使得衬底同时起到承载和绝缘间隔的作用，从而在降低信号线电阻的同时，使得显示装置的厚度较小。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2017年2月17日递交的中国专利申请第201710087430.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板，包括衬底和设置在所述衬底上的信号线，其中，所述衬底上还设置有与所述信号线对应的至少一个导电件，所述信号线和与之相应的导电件并联，不同信号线对应的导电件绝缘间隔。
  2. 根据权利要求1所述的阵列基板，其中，所述衬底上还设置有有机发光单元，所述信号线包括高电平信号线和/或低电平信号线。
  3. 根据权利要求1或2所述的阵列基板，其中，所述信号线和所述导电件分别设置在所述衬底的沿其厚度方向的两侧，所述衬底上与每条信号线对应的区域均形成有至少两个过孔，所述衬底上还设置有与各过孔分别对应的连接件，各个所述连接件穿过所述过孔将所述信号线与相应的导电件并联。
  4. 根据权利要求1-3任一所述的阵列基板，其中，所述衬底为柔性衬底。
  5. 根据权利要求1-4任一所述的阵列基板，其中，所述第一连接件包括导电银胶。
  6. 根据权利要求1所述的阵列基板，其中，所述导电件与所述信号线设置在所述衬底的沿其厚度方向的同一侧，所述导电件与所述信号线之间设置有绝缘间隔层，所述绝缘间隔层与每个信号线对应的区域均设置有至少两个过孔，所述衬底上还设置有与各过孔分别对应的连接件，各个所述连接件穿过所述过孔将所述信号线与相应的导电件并联。
  7. 根据权利要求1-6任一所述的阵列基板，其中，形成所述导电件的材料包括铜和石墨的双层结构导电材料。
  8. 一种显示装置，包括权利要求1-7任一所述的阵列基板。
  9. 一种显示装置，包括权利要求1或2所述的阵列基板，其中，
    所述信号线和导电件分别设置在所述衬底的沿其厚度方向的两侧，所述显示装置还包括柔性线路板，所述柔性线路板包括与所述信号线对应的连接线，所述信号线的一端通过所述柔性线路板上相应的连接线与所述导电件相连；所述信号线的另一端通过至少一个过孔与所述导电件相连。
  10. 根据权利要求9所述的显示装置，其中，所述柔性电路板的一部分设置在所述衬底形成有所述信号线的一侧并与所述信号线电连接，所述柔性线路板的另一部分翻折至所述衬底形成有所述导电件的一侧并与所述导电件电连接。
  11. 根据权利要求10所述的显示装置，其中，所述柔性线路板包括柔性基底，所述连接线设置在所述柔性基底朝向所述阵列基板的一侧，所述柔性基底上还设置有绝缘层，所述绝缘层覆盖所述连接线并露出第一预定连接区和第二预定连接区，所述第一预定连接区为与所述信号线相连的区域，所述第二预定连接区为与所述导电件相连的区域，所述第二预定连接区域与所述导电件通过连接件相连。
  12. 根据权利要求10所述的显示装置，其中，所述至少一个过孔形成在所述衬底上并与所述信号线对应，所述衬底上还设置有与各过孔分别对应的连接件，所述连接件穿过所对应的过孔将所述信号线的未与所述连接线连接的部分与相应的导电件相连。
  13. 根据权利要求11或12所述的显示装置，其中，所述连接件包括导电银胶。
  14. 根据权利要求9-13任一所述的显示装置，其中，所述阵列基板的衬底为柔性衬底。
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