WO2018133092A1 - Système et procédé de traitement de signal - Google Patents

Système et procédé de traitement de signal Download PDF

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Publication number
WO2018133092A1
WO2018133092A1 PCT/CN2017/072181 CN2017072181W WO2018133092A1 WO 2018133092 A1 WO2018133092 A1 WO 2018133092A1 CN 2017072181 W CN2017072181 W CN 2017072181W WO 2018133092 A1 WO2018133092 A1 WO 2018133092A1
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Prior art keywords
signal
positive
negative
output
comparator
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PCT/CN2017/072181
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English (en)
Chinese (zh)
Inventor
张孟文
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深圳市汇顶科技股份有限公司
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Priority to CN201780000083.6A priority Critical patent/CN107078723B/zh
Priority to PCT/CN2017/072181 priority patent/WO2018133092A1/fr
Publication of WO2018133092A1 publication Critical patent/WO2018133092A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Definitions

  • the present application relates to the field of electronic devices and, more particularly, to signal processing systems and methods of signal processing.
  • the current active pen-inductive pressure detecting sensor uses a square wave signal to detect time and power consumption in the control circuit or control chip of the touch screen.
  • the current square wave signal is generated by shaping the waveform of the fully differential oscillator through a comparator and finally outputting a square wave signal with a duty cycle of 50%.
  • the comparator has a problem of inconsistent positive and negative high and low delays (for example, high to low delay or low to high delay), resulting in an actual square wave duty cycle deviation of 50%.
  • the duty cycle of some of the other waves is sensitive (such as a dual-edge counter)
  • the deviation of the duty cycle will reduce the accuracy of the calculation, which in turn affects the accuracy of the detected time and power consumption.
  • the embodiment of the present application provides a signal processing system and a signal processing method, which can obtain a signal with an accurate duty ratio, thereby improving calculation accuracy.
  • a signal processing system includes: an output device including a first positive output terminal and a first negative output terminal, the first positive output terminal outputting the first positive signal and the first negative output terminal outputting the first negative signal
  • the phase difference is a fixed value
  • the first comparator includes a second positive input terminal and a second negative input terminal, the second positive input terminal is coupled to the first positive output terminal, the second negative input terminal
  • the first comparator is connected to the first negative output terminal, and the first comparator is configured to perform shaping processing on the first positive signal and the first negative signal to generate a second signal, the second signal is a square wave signal
  • the second comparator includes a third positive input terminal and a third negative input terminal, the third positive input terminal is coupled to the first negative output terminal, and the third negative input terminal is coupled to the first positive output terminal, and
  • the second comparator is configured to perform shaping processing on the first positive signal and the first negative signal to generate a third signal, the third signal is a square wave signal, and a multiplexer
  • the embodiment of the present application can generate a fourth signal with an accurate rising edge by selecting the second signal or the third signal, and the fifth signal can switch between the rising edge and the falling edge according to the accurate rising edge, that is, the generating duty ratio is relatively accurate.
  • the signal can improve the computational accuracy of applications that are sensitive to duty cycle.
  • the edge trigger further includes a second output, the edge trigger further configured to output a sixth signal through the second output, the sixth signal being a signal opposite to the fifth signal
  • the multiplexer is specifically configured to: according to the edge transition of the high and low levels of the sixth signal, select the second signal or the third signal to generate the fourth signal in turn.
  • the multiplexer jumps on the edge of the high and low levels of the sixth signal, and switches the selected second signal or the third signal as the fourth signal, so that there is no error on the rising edge of the fourth signal, and finally the generated duty ratio is relatively accurate.
  • the signal which improves the computational accuracy of applications that are sensitive to duty cycle.
  • the first positive signal and the first negative signal have a phase difference of 180°, and the fifth signal has a duty ratio of 50%.
  • the fifth signal generated by the signal processing system is a signal with an accurate high-level duty ratio of 50%, thereby being able to improve sensitivity to duty ratio The accuracy of the application's calculations.
  • the phase difference between the first positive signal and the first negative signal is a fixed value that is not equal to 180°
  • the duty ratio of the fifth signal is the first positive signal and the first negative
  • the phase difference of the signal is proportional.
  • the duty ratio of the generated fifth signal is proportional to the phase difference.
  • the phase difference between the first positive signal and the second negative signal is a fixed value not equal to 180°
  • a high-level duty ratio with a duty ratio of 50% is still generated, which improves the signal processing.
  • the range of applications of the system and can get a more accurate high-level duty cycle signal.
  • the edge flip-flop is an edge flip-flop capable of two-way.
  • the edge flip-flop is an edge flip-flop capable of dividing by two, such that the fifth signal output by the edge trigger is an edge jump at the rising edge of each accurate fourth signal, and a relatively accurate high level can be obtained.
  • the signal of the duty cycle is an edge flip-flop capable of dividing by two, such that the fifth signal output by the edge trigger is an edge jump at the rising edge of each accurate fourth signal, and a relatively accurate high level can be obtained.
  • the edge trigger capable of dividing by two further includes a first input end and a second input end, wherein the first input end is configured to receive the fourth signal, and the second input end is The second output is connected.
  • An edge-trigger that can be divided by two can be implemented by one of the output-side inputs, resulting in a more accurate high-level duty cycle signal.
  • the multiplexer includes a first NAND gate, a second NAND gate, and a third NAND gate, the first NAND gate including a third input terminal, a fourth input terminal, and a third input terminal a third output terminal, the second NAND gate includes a fifth input terminal, a sixth input terminal, and a fourth output terminal, wherein the third NAND gate includes a seventh input terminal, an eighth input terminal, and a fifth output terminal, and the a third output terminal is coupled to the seventh input terminal, the fourth output terminal is coupled to the eighth input terminal, the third input terminal is configured to receive the second signal, and the fourth input terminal is configured to receive the sixth signal
  • the fifth output is configured to output the fourth signal, the fifth input is configured to receive the third signal, and the sixth input is configured to receive a seventh signal, where the seventh signal is opposite to the sixth signal signal of.
  • the multiplexer of the structure can realize the selection of the second signal or the third signal as the fourth signal, so that the fifth signal which is hopped according to the rising edge of the fourth signal can be generated, thereby being able to improve the sensitivity to the duty ratio The accuracy of the application's calculations.
  • the signal processing system further includes an inverter for converting the sixth signal to the seventh signal.
  • the multiplexer can select the second signal or the third signal as the fourth signal according to the sixth signal and the seventh signal.
  • the multiplexer can select the second signal or the third signal as the fourth signal according to the sixth signal and the seventh signal.
  • the output device is an LC LC oscillator.
  • the first comparator and the second comparator are self-biased comparators.
  • a method of signal processing is provided, the method being performed by a module of the signal processing system of the first aspect or any of the possible implementations of the first aspect.
  • the first positive output terminal outputs the first positive signal and the first negative output terminal outputs the first negative signal
  • the phase difference between the first positive signal and the first negative signal is a fixed value.
  • the first comparator performs shaping processing on the first positive signal and the first negative signal to generate a second signal of the square wave signal
  • the second comparator performs shaping processing on the first positive signal and the first negative signal to generate a square wave a third signal of the signal
  • the multiplexer selects the second signal or the third signal to generate a fourth signal having an accurate rising edge
  • the edge trigger generates an edge jump according to the rising edge of the fourth signal
  • the fifth signal such that by selecting a signal that is processed by two comparators that are completely symmetric, to generate a square wave signal with a relatively accurate duty cycle, can improve the calculation accuracy of a duty-sensitive application.
  • FIG. 1 is an architectural diagram of a prior art signal processing system
  • FIG. 2 is a schematic diagram of duty cycle deviation of an output signal of a signal processing system in the prior art
  • FIG. 3 is a schematic diagram of a signal processing system of an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an inductor-capacitor (LC) oscillator according to an embodiment of the present application
  • 5(a) and 5(b) are schematic structural diagrams of a comparator according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an edge trigger of an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a multiplexer according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of signal changes of signal processing according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of signal changes of signal processing according to still another embodiment of the present application.
  • FIG. 10 is a schematic diagram showing signal changes of signal processing according to still another embodiment of the present application.
  • FIG. 11 is a schematic flowchart of a method for signal processing according to an embodiment of the present application.
  • the oscillator is an energy conversion device capable of converting DC power into AC power having a certain frequency, and the circuit formed is called an oscillation circuit.
  • the comparator is an electronic component that outputs different voltage results at the output by comparing the magnitude of the current or voltage at the two inputs.
  • the comparator is often used in an analog-to-digital conversion circuit.
  • the multiplexer is a circuit that can select any one of them as needed during the multiplexed data transfer process.
  • the edge trigger receives input data when a certain transition (positive or negative transition) of a clock pulse (CP) arrives.
  • CP clock pulse
  • the duty ratio refers to the ratio of the time that the high level takes up within one cycle. For example, the duty ratio of the square wave is 50%, indicating that the high level takes 0.5 cycles.
  • the signal processing system includes an oscillator 110 and a comparator 120.
  • the positive terminal of the oscillator 110 outputs V 1p
  • the negative terminal outputs V 1n
  • the V 5 signal is output through the processing of the comparator 120. Since a single comparator is equivalent to first making V 1p and V 1n poor and then comparing with 0 voltage, the phases of V 1p and V 1n are different, and the effect is only the amplitude after the difference, so V 1p and V 1n
  • the output V 5 signal is a square wave signal with a duty ratio of about 50%. For example, if the phase difference between V 1p and V 1n is 90° or 125°, the V 5 signal remains. For a square wave signal with a duty cycle of approximately 50%, the signal processing system has a smaller application range and lower calculation accuracy.
  • the V5 signal is theoretically a signal having a duty ratio of 50%, but since the comparator 120 has a problem of high and low delay inconsistency, the output is made.
  • the duty cycle of the V 5 signal deviates by 50%, and the duty cycle offset of 50% includes a large duty cycle (V 5 signal as shown in Figure 2) and a small duty cycle (V 5 as shown in Figure 2). '). In this way, for applications that are sensitive to duty cycle, the accuracy of the calculation will be seriously affected.
  • FIG. 3 illustrates a signal processing system 300 in accordance with an embodiment of the present application.
  • the signal processing system 300 includes an output device 301, a first comparator 302, a second comparator 303, a multiplexer 304, and an edge trigger 305.
  • the output device 301 includes a first positive output terminal and a first negative output terminal, and the first positive output terminal outputs a first positive signal and the first negative output terminal outputs a first negative signal with a phase difference of a fixed value;
  • the first comparator 302 includes a second positive input terminal and a second negative input terminal, the second positive input terminal is coupled to the first positive output terminal, and the second negative input terminal is coupled to the first negative output terminal.
  • the first comparator 302 is configured to perform shaping processing on the first positive signal and the first negative signal to generate a second signal V 2p , where the second signal V 2p is a square wave signal;
  • the second comparator 303 includes a third positive input terminal and a third negative input terminal, the third positive input terminal is coupled to the first negative output terminal, and the third negative input terminal is coupled to the first positive output terminal.
  • the second comparator 303 is configured to perform shaping processing on the first positive signal and the first negative signal to generate a third signal V 2n , where the third signal V 2n is a square wave signal;
  • the multiplexer 304 is configured to select the second signal V 2p or the third signal V 2n to generate a fourth signal V 4 , the fourth signal V 4 having an accurate rising edge;
  • the edge trigger 305 is configured to generate a fifth signal V 5 according to a rising edge of the rising edge of the fourth signal, the edge trigger comprising a first output end, the first output end is configured to output a fifth signal.
  • the first comparator 302 and the second comparator 303 are completely symmetrical with the output of the output device 301 such that the phase of the output waveform of the first comparator 302 and the second comparator 303 is strictly 180° out of phase.
  • the V 5 signal duty ratio is greater than 50%, but the rising edge is accurate. Therefore, the embodiment of the present application can select the second signal generated by the two symmetric comparators or the second signal.
  • the third signal obtains a fourth signal with an accurate rising edge, and the fifth signal can switch between the rising edge and the falling edge according to the accurate rising edge, that is, generate a signal with a relatively accurate duty cycle.
  • first positive signal and the first negative signal may both be analog signals, so the shaping process by the first comparator and the second comparator may specifically be performing analog-to-digital conversion, that is, converting the analog signal into a digital signal ( That is, the square wave signal).
  • first positive signal the signal outputted by the first positive output terminal
  • first negative output terminal the signal outputted by the first negative output terminal
  • the embodiment of the present application may be applied to a scenario where the duty ratio of the signal is too large, and may also be applied to a scenario where the duty ratio of the signal is small, but for the convenience of description, the signal of the embodiment of the present application is occupied.
  • the empty ratio is large as an example, but the application is not limited thereto.
  • the signal processing system of the embodiment of the present application outputs a first positive signal through a first positive output terminal of the output device, and a first negative output terminal outputs a first negative signal, and the first positive signal and the first negative signal
  • the phase difference is a fixed value
  • the first comparator shapes the first positive signal and the first negative signal to generate a second signal of the square wave signal
  • the second comparator performs the first positive signal and the first negative signal together
  • the shaping process generates a third signal of a square wave signal
  • the multiplexer selects the second signal or the third signal to generate a fourth signal having an accurate rising edge
  • the edge trigger generates an edge jump according to the rising edge of the fourth signal.
  • the fifth signal such that by selecting a signal that is processed by two comparators that are completely symmetric, to generate a square wave signal with a relatively accurate duty cycle, can improve the calculation accuracy of a duty-sensitive application.
  • the fifth signal generated according to the signal processing system is a signal with an accurate high-level duty ratio of 50%.
  • the duty ratio of the generated fifth signal is proportional to the phase difference.
  • the phase difference between the first positive signal and the first negative signal is 90°
  • the high level duty ratio of the fifth signal is 25%.
  • the present application can generate a high-level duty ratio whose duty ratio is proportional to the phase difference. The application range of the signal processing system is improved, and a relatively accurate high-level duty ratio can be obtained.
  • the output device 301 of the embodiment of the present application may be an oscillator, specifically an oscillator. It can be an LC LC oscillator (as shown in FIG. 4 ), or it can be a resistor-capacitor (RC) oscillator or a crystal oscillator, which is not limited in this application.
  • an oscillator specifically an oscillator. It can be an LC LC oscillator (as shown in FIG. 4 ), or it can be a resistor-capacitor (RC) oscillator or a crystal oscillator, which is not limited in this application.
  • RC resistor-capacitor
  • the first comparator 302 may be a self-bias comparator as shown in FIG. 5(a), and the second comparator 303 may be a self-bias comparator as shown in FIG. 5(b).
  • the first comparator 302 receives the first positive signal V 1p and the first negative signal V 1n to generate a second signal V 2p
  • the second comparator 303 receives the first positive signal V 1p and the first negative signal V 1n to generate a third signal V 2n .
  • first comparator 302 and the second comparator 303 may also be comparators of other configurations, which are not limited in the present application.
  • the multiplexer 304 can be as shown in FIG. 6, that is, the multiplexer is composed of three NAND gates, and the three NAND gates are respectively referred to as the first NAND gate 1, the second The non-gate 2 and the third NAND gate 3 are distinguished, and the first NAND gate includes a third input terminal V 2p input terminal, a fourth input terminal V 3n and a third output terminal, and the second NAND gate includes a fifth The input terminal V 2n , the sixth input terminal V 3p and the fourth output terminal, the third NAND gate includes a seventh input terminal, an eighth input terminal and a fifth output terminal V 4 , and the third output terminal and the third The seven input terminals are connected, and the fourth output terminal is connected to the eighth input terminal, that is, the output of the first NAND gate and the output of the second NAND gate are used as the third NAND input.
  • V 3n is a digital signal "0" and V 3p is a digital signal "1”
  • V 2p and "0" are ANDed to obtain "0”
  • non-operation is performed to obtain "1”.
  • V 1 and V 2n perform the AND operation to obtain V 2n , and then perform non-operation Will be 1 and Then proceed with the operation
  • the non-operation is again performed to obtain V 2n , that is, the output V 4 is equal to V 2n .
  • V 3n is the digital signal "1”
  • V 3p is the digital signal "0”.
  • the output V 4 V 2p is obtained by the multiplexer 304 shown in FIG.
  • the fourth input terminal receives the sixth signal V 3n
  • the fifth input terminal receives the third signal V 2n
  • the sixth input terminal receives the seventh signal
  • the signal V 3p because the V 3p signal is a signal opposite to the positive and negative of the V 3n signal, the fifth output terminal can output the fourth signal V 4 . That is to say, the multiplexer performs NAND processing by inputting a signal having a high and low level change and opposite, respectively, and performing NAND processing with the second signal and the third signal, and then performing non-processing on the result to finally select the second.
  • the signal or the third signal results in a fourth signal with an accurate rising edge.
  • multiplexer 304 may also be a multiplexer of other configurations, which is not limited in the present application.
  • the edge flip-flop is an edge flip-flop capable of dividing by two, such that the fifth signal output by the edge trigger is an edge jump on a rising edge of each fourth signal, that is, The frequency of the fourth signal is twice the frequency of the fifth signal, and the frequency of the fifth signal is divided by the frequency of the fourth signal.
  • the edge flip-flop capable of dividing the input signal by two may be an edge flip-flop as shown in FIG. 7, and the edge flip-flop 305 includes two input terminals and two output terminals, and the signals of the two output terminals are opposite.
  • the signal, for example, V 5 and V 3n in FIG. 7 are opposite signals, that is, V 5 is a digital signal "1", and V 3n is a digital signal "0".
  • the output terminal QB is connected to the input terminal D, so as to realize half of the frequency signal V 4, i.e., 4 V frequency signal into a frequency signal V5 twice.
  • the first output of the edge flip-flop 305 is used to output a fifth signal
  • the second output is used to output the sixth signal V 3p
  • the multiplexer 304 can jump according to the edge of the sixth signal.
  • the second signal or the third signal is selected as the fourth signal.
  • the multiplexer 304 may select the second signal or the third signal as the fourth signal according to the edge transition of the high and low levels of the seventh signal, and the seventh signal is the signal obtained by inverting the sixth signal. This application does not limit this.
  • the signal processing system may be a in FIG. 7 V 3n input to fourth input terminal in FIG. 6, and V 3n to be obtained after the seventh inverted signal input terminal of the sixth input, a second selection signal to achieve Or the third signal is used as the fourth signal, so that an accurate signal with a duty ratio of 50% can be obtained.
  • the signal processing system of the embodiment of the present application may set an inverter between the second output end and the sixth input end to implement the inverse conversion of the sixth signal into the sixth signal input sixth input end.
  • the seventh signal and the fifth signal are both inverted signals of the sixth signal, the seventh signal and the fifth signal are the same signal.
  • the inverter may be disposed in the multiplexer or may be disposed after the second output of the edge flip flop to obtain two opposite signals required by the multiplexer. Limited.
  • the edge trigger outputs V 3n
  • the inverter reverses V 3n to generate a seventh signal, which is input to the sixth input of the multiplexer, and the reverser is set at the fourth input of the multiplexer.
  • the seventh signal is converted to the opposite signal and input to the fourth input.
  • the edge flip-flop can also return V 5 to the fourth input of the multiplexer while outputting V 5 , and set an inverter at the sixth input of the multiplexer to set V 5 is converted to the opposite signal and input to the sixth input. That is, regardless of the output of V 3n , V 5 is directly used as the input of the multiplexer.
  • the phase difference of the signal outputted by the output device 301 is 180°.
  • V 5 is assumed to be high.
  • V 2n is selected to determine V 4 , that is, V 4 is a low level consistent with V 2n .
  • V 4 is also the rising edge.
  • the edge trigger detects the rising edge of V 4 , the edge of V 5 jumps (ie, changes from high level to low level).
  • the multiplexer 304 selects V 2p as V 4 (as in the period T 1 to T 2 in FIG. 8 ), that is, V 4 is from the high level to the low level consistent with V 2n . Flat change.
  • the duty cycle of the V 5 signal thus generated is exactly 50%.
  • the phase difference of the signal outputted by the output device 301 is 180°.
  • the multiplexer 304 shown in FIG. 6 can be used to select V. 2p determining V 4, V 4 to be consistent with i.e. V 2p is V 5 is also kept low until a rising edge of V 2p at time T 2, at time T 2 V 4 is also rising, the edge-triggered After detecting the rising edge of V 4 , the edge transition of V 5 (ie, from low level to high level) is performed.
  • V 5 is high, multiplexer 304 selects V 2n to generate V 4 (as in the period T 2 to T 3 in FIG. 9 ), that is, V 4 is from high level to low level consistent with V 2n . Flat change.
  • the duty cycle of the V 5 signal thus generated is exactly 50%.
  • phase difference of the signal outputted by the output device 301 is 180° as an example. If V 2p and V 3p in FIG. 6 are input together, the first NAND gate is input, and V 3n and V 2n are input together to the second NAND gate. Then, the signal changes as shown in Fig. 10, and finally the V 5 signal with an accurate duty ratio of 50% can still be output.
  • the signal processing system of the embodiment of the present application outputs a first positive signal through a first positive output terminal of the output device, and a first negative output terminal outputs a first negative signal, and the first positive signal and the first negative signal
  • the phase difference is a fixed value
  • the first comparator shapes the first positive signal and the first negative signal to generate a second signal of the square wave signal
  • the second comparator performs the first positive signal and the first negative signal together
  • the shaping process generates a third signal of a square wave signal
  • the multiplexer selects the second signal or the third signal to generate a fourth signal having an accurate rising edge
  • the edge trigger generates an edge jump according to the rising edge of the fourth signal.
  • the fifth signal such that by selecting a signal that is processed by two comparators that are completely symmetric, to generate a square wave signal with a relatively accurate duty cycle, can improve the calculation accuracy of a duty-sensitive application.
  • FIG. 3 to FIG. 10 describe a signal processing system, and the following details describe the embodiment of the present application. Number processing method.
  • FIG. 11 shows a schematic flow chart of a method 1100 of signal processing in accordance with an embodiment of the present application.
  • the signal processing method is applied to a signal processing system including an output device, a first comparator, a second comparator, a multiplexer, and an edge trigger, the output device including the first a positive output terminal and a first negative output terminal, the first comparator includes a second positive input terminal and a second negative input terminal, the second positive input terminal is coupled to the first positive output terminal, and the second negative input terminal is coupled to The first negative output terminal is connected, the second comparator comprises a third positive input terminal and a third negative input terminal, the third positive input terminal is connected to the first negative output terminal, and the third negative input terminal and the third A positive output connection, the method 1100 includes:
  • the output device outputs a first positive signal through the first positive output terminal and a first negative signal through the first negative output terminal, and a phase difference between the first positive signal and the first negative signal is a fixed value;
  • the first comparator performs shaping processing on the first positive signal and the first negative signal to generate a second signal, where the second signal is a square wave signal;
  • the second comparator performs shaping processing on the first positive signal and the first negative signal to generate a third signal, where the third signal is a square wave signal;
  • the multiplexer selects the second signal or the third signal to generate a fourth signal, where the fourth signal has an accurate rising edge
  • the edge trigger receives the fourth signal, and performs a high-low level edge transition according to a rising edge of the fourth signal to generate a fifth signal.
  • the method further includes: the edge trigger outputting a sixth signal, the sixth signal is a signal opposite to the fifth signal, or the sixth signal is the same as the fifth signal a signal, wherein the multiplexer alternately selects the second signal or the third signal generates a fourth signal, including: selecting the second signal or the first according to the edge transition of the high and low levels of the sixth signal The third signal generates the fourth signal.
  • the first positive signal and the first negative signal have a phase difference of 180°, and the fifth signal has a duty ratio of 50%.
  • the phase difference between the first positive signal and the first negative signal is a fixed value that is not equal to 180°
  • the duty ratio of the fifth signal is the first positive signal and the first The phase difference of the negative signal is proportional.
  • the edge trigger is edge triggered by two-way Device.
  • the output device is an LC filter.
  • the first comparator and the second comparator are self-bias comparators.
  • the first positive output terminal outputs a first positive signal and the first negative output terminal outputs a first negative signal
  • the first positive signal and the first negative signal are output.
  • the phase difference is a fixed value
  • the first comparator shapes the first positive signal and the first negative signal to generate a second signal of the square wave signal
  • the second comparator pairs the first positive signal and the first negative signal
  • a shaping process to generate a third signal of a square wave signal
  • the multiplexer selecting the second signal or the third signal to generate a fourth signal having an accurate rising edge
  • a fifth signal is generated, so that by selecting a signal processed by two comparators that are completely symmetric, a square wave signal with a relatively accurate duty ratio can be generated, which can improve the calculation accuracy of a duty-sensitive application.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and The method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

La présente invention concerne un système et un procédé de traitement de signal. Le système de traitement de signal comprend : un dispositif de sortie (301) comprenant des premières extrémités de sortie positive et négative; un premier comparateur (302) comprenant des deuxièmes extrémités d'entrée positive et négative, la deuxième extrémité d'entrée positive étant connectée à la première extrémité de sortie positive, la deuxième extrémité d'entrée négative étant connectée à la première extrémité de sortie négative, et servant à effectuer une mise en forme sur un premier signal positif (V1p) et sur un premier signal négatif (V1n) dans le but de générer un deuxième signal (V2p); un second comparateur (303) comprenant des troisième extrémités d'entrée positive et négative, la troisième extrémité d'entrée positive étant connectée à la première extrémité de sortie négative, la troisième extrémité d'entrée négative étant connectée à la première extrémité de sortie positive, et servant à effectuer une mise en forme sur le premier signal positif (V1p) et sur le premier signal négatif (V1n) dans le but de générer un troisième signal (V2n); un multiplexeur (304) servant à sélectionner le deuxième signal (V2p) ou le troisième signal (V2n) dans le but de générer un quatrième signal (V4), le quatrième signal (V4) ayant un front montant précis; et un déclencheur de front (305) servant à effectuer une transition de front selon le front montant du quatrième signal (V4) dans le but de générer un cinquième signal (V5).
PCT/CN2017/072181 2017-01-23 2017-01-23 Système et procédé de traitement de signal WO2018133092A1 (fr)

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PCT/CN2017/072181 WO2018133092A1 (fr) 2017-01-23 2017-01-23 Système et procédé de traitement de signal

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CN110333598B (zh) * 2019-04-29 2021-04-23 西安知微传感技术有限公司 获取电容反馈式微扭转镜电容反馈信号的方法及电路

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CN101340422A (zh) * 2007-07-02 2009-01-07 聚积科技股份有限公司 信号编码器与信号译码器
CN101546995A (zh) * 2008-03-25 2009-09-30 索尼株式会社 信号处理设备
CN103095622A (zh) * 2011-11-01 2013-05-08 上海华虹集成电路有限责任公司 一种适用于iso14443协议的bpsk信号恢复电路
US8829953B1 (en) * 2014-01-09 2014-09-09 Freescale Semiconductor, Inc. Programmable clock divider

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CN101340422A (zh) * 2007-07-02 2009-01-07 聚积科技股份有限公司 信号编码器与信号译码器
CN101546995A (zh) * 2008-03-25 2009-09-30 索尼株式会社 信号处理设备
CN103095622A (zh) * 2011-11-01 2013-05-08 上海华虹集成电路有限责任公司 一种适用于iso14443协议的bpsk信号恢复电路
US8829953B1 (en) * 2014-01-09 2014-09-09 Freescale Semiconductor, Inc. Programmable clock divider

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