WO2018133092A1

WO2018133092A1 - Signal processing system and signal processing method

Info

Publication number: WO2018133092A1
Application number: PCT/CN2017/072181
Authority: WO
Inventors: 张孟文
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2017-01-23
Filing date: 2017-01-23
Publication date: 2018-07-26
Also published as: CN107078723B; CN107078723A

Abstract

A signal processing system and a signal processing method. The signal processing system comprises: an output device (301) comprising a first positive output end and a first negative output end; a first comparator (302) comprising a second positive input end and a second negative input end, the second positive input end being connected to the first positive output end, the second negative input end being connected to the first negative output end, and used for shaping on a first positive signal (V_1p) and a first negative signal (V_1n) to generate a second signal (V_2p); a second comparator (303) comprising a third positive input end and a third negative input end, the third positive input end being connected to the first negative output end, the third negative input end being connected to the first positive output end, and the second comparator (303) being used for performing shaping on the first positive signal (V_1p) and the first negative signal (V_1n) to generate a third signal (V_2n); a multiplexer (304) used for selecting the second signal (V_2p) or the third signal (V_2n) to generate a fourth signal (V₄), the fourth signal (V₄) having an accurate rising edge; and an edge trigger (305) used for performing edge transition according to the rising edge of the fourth signal (V₄) to generate a fifth signal (V₅).

Description

Signal processing system and signal processing method

Technical field

The present application relates to the field of electronic devices and, more particularly, to signal processing systems and methods of signal processing.

Background technique

The current active pen-inductive pressure detecting sensor uses a square wave signal to detect time and power consumption in the control circuit or control chip of the touch screen. The current square wave signal is generated by shaping the waveform of the fully differential oscillator through a comparator and finally outputting a square wave signal with a duty cycle of 50%. However, in general, the comparator has a problem of inconsistent positive and negative high and low delays (for example, high to low delay or low to high delay), resulting in an actual square wave duty cycle deviation of 50%. For applications where the duty cycle of some of the other waves is sensitive (such as a dual-edge counter), the deviation of the duty cycle will reduce the accuracy of the calculation, which in turn affects the accuracy of the detected time and power consumption.

Summary of the invention

The embodiment of the present application provides a signal processing system and a signal processing method, which can obtain a signal with an accurate duty ratio, thereby improving calculation accuracy.

In a first aspect, a signal processing system is provided. The signal processing system includes: an output device including a first positive output terminal and a first negative output terminal, the first positive output terminal outputting the first positive signal and the first negative output terminal outputting the first negative signal The phase difference is a fixed value; the first comparator includes a second positive input terminal and a second negative input terminal, the second positive input terminal is coupled to the first positive output terminal, the second negative input terminal The first comparator is connected to the first negative output terminal, and the first comparator is configured to perform shaping processing on the first positive signal and the first negative signal to generate a second signal, the second signal is a square wave signal; the second comparator The second comparator includes a third positive input terminal and a third negative input terminal, the third positive input terminal is coupled to the first negative output terminal, and the third negative input terminal is coupled to the first positive output terminal, and The second comparator is configured to perform shaping processing on the first positive signal and the first negative signal to generate a third signal, the third signal is a square wave signal, and a multiplexer for selecting the second signal or the first The third signal generates a fourth signal, the fourth signal having Rising correct; edge flip-flop, for rising edge of the fourth signal to generate a fifth signal edge transition, the rim comprises a first flip-flop output terminal, a first output terminal for outputting the fifth signal.

The embodiment of the present application can generate a fourth signal with an accurate rising edge by selecting the second signal or the third signal, and the fifth signal can switch between the rising edge and the falling edge according to the accurate rising edge, that is, the generating duty ratio is relatively accurate. The signal can improve the computational accuracy of applications that are sensitive to duty cycle.

In some possible implementations, the edge trigger further includes a second output, the edge trigger further configured to output a sixth signal through the second output, the sixth signal being a signal opposite to the fifth signal The multiplexer is specifically configured to: according to the edge transition of the high and low levels of the sixth signal, select the second signal or the third signal to generate the fourth signal in turn.

The multiplexer jumps on the edge of the high and low levels of the sixth signal, and switches the selected second signal or the third signal as the fourth signal, so that there is no error on the rising edge of the fourth signal, and finally the generated duty ratio is relatively accurate. The signal, which improves the computational accuracy of applications that are sensitive to duty cycle.

In some possible implementations, the first positive signal and the first negative signal have a phase difference of 180°, and the fifth signal has a duty ratio of 50%.

If the phase of the first positive signal and the first negative signal are different by 180°, the fifth signal generated by the signal processing system according to the above is a signal with an accurate high-level duty ratio of 50%, thereby being able to improve sensitivity to duty ratio The accuracy of the application's calculations.

In some possible implementations, the phase difference between the first positive signal and the first negative signal is a fixed value that is not equal to 180°, and the duty ratio of the fifth signal is the first positive signal and the first negative The phase difference of the signal is proportional.

If the phase difference between the first positive signal and the second negative signal is a fixed value not equal to 180°, the duty ratio of the generated fifth signal is proportional to the phase difference. Compared with the prior art, when the phase difference between the first positive signal and the second negative signal is a fixed value not equal to 180°, a high-level duty ratio with a duty ratio of 50% is still generated, which improves the signal processing. The range of applications of the system, and can get a more accurate high-level duty cycle signal.

In some possible implementations, the edge flip-flop is an edge flip-flop capable of two-way.

The edge flip-flop is an edge flip-flop capable of dividing by two, such that the fifth signal output by the edge trigger is an edge jump at the rising edge of each accurate fourth signal, and a relatively accurate high level can be obtained. The signal of the duty cycle.

In some possible implementations, the edge trigger capable of dividing by two further includes a first input end and a second input end, wherein the first input end is configured to receive the fourth signal, and the second input end is The second output is connected.

An edge-trigger that can be divided by two can be implemented by one of the output-side inputs, resulting in a more accurate high-level duty cycle signal.

In some possible implementations, the multiplexer includes a first NAND gate, a second NAND gate, and a third NAND gate, the first NAND gate including a third input terminal, a fourth input terminal, and a third input terminal a third output terminal, the second NAND gate includes a fifth input terminal, a sixth input terminal, and a fourth output terminal, wherein the third NAND gate includes a seventh input terminal, an eighth input terminal, and a fifth output terminal, and the a third output terminal is coupled to the seventh input terminal, the fourth output terminal is coupled to the eighth input terminal, the third input terminal is configured to receive the second signal, and the fourth input terminal is configured to receive the sixth signal The fifth output is configured to output the fourth signal, the fifth input is configured to receive the third signal, and the sixth input is configured to receive a seventh signal, where the seventh signal is opposite to the sixth signal signal of.

The multiplexer of the structure can realize the selection of the second signal or the third signal as the fourth signal, so that the fifth signal which is hopped according to the rising edge of the fourth signal can be generated, thereby being able to improve the sensitivity to the duty ratio The accuracy of the application's calculations.

In some possible implementations, the signal processing system further includes an inverter for converting the sixth signal to the seventh signal.

By inverting the signal in the inverter, and converting the sixth signal into the seventh signal, the multiplexer can select the second signal or the third signal as the fourth signal according to the sixth signal and the seventh signal. Thus, it is possible to generate a fifth signal that is hopped according to the rising edge of the fourth signal, so that the calculation accuracy of the application that is relatively sensitive to the duty ratio can be improved.

In some possible implementations, the output device is an LC LC oscillator.

In some possible implementations, the first comparator and the second comparator are self-biased comparators.

In a second aspect, a method of signal processing is provided, the method being performed by a module of the signal processing system of the first aspect or any of the possible implementations of the first aspect.

According to the above technical solution, the first positive output terminal outputs the first positive signal and the first negative output terminal outputs the first negative signal, and the phase difference between the first positive signal and the first negative signal is a fixed value. The first comparator performs shaping processing on the first positive signal and the first negative signal to generate a second signal of the square wave signal, and the second comparator performs shaping processing on the first positive signal and the first negative signal to generate a square wave a third signal of the signal, the multiplexer selects the second signal or the third signal to generate a fourth signal having an accurate rising edge, and the edge trigger generates an edge jump according to the rising edge of the fourth signal The fifth signal, such that by selecting a signal that is processed by two comparators that are completely symmetric, to generate a square wave signal with a relatively accurate duty cycle, can improve the calculation accuracy of a duty-sensitive application.

DRAWINGS

1 is an architectural diagram of a prior art signal processing system;

2 is a schematic diagram of duty cycle deviation of an output signal of a signal processing system in the prior art;

3 is a schematic diagram of a signal processing system of an embodiment of the present application;

4 is a schematic structural diagram of an inductor-capacitor (LC) oscillator according to an embodiment of the present application;

5(a) and 5(b) are schematic structural diagrams of a comparator according to an embodiment of the present application;

6 is a schematic structural diagram of an edge trigger of an embodiment of the present application;

7 is a schematic structural diagram of a multiplexer according to an embodiment of the present application;

FIG. 8 is a schematic diagram of signal changes of signal processing according to an embodiment of the present application; FIG.

9 is a schematic diagram of signal changes of signal processing according to still another embodiment of the present application;

FIG. 10 is a schematic diagram showing signal changes of signal processing according to still another embodiment of the present application; FIG.

FIG. 11 is a schematic flowchart of a method for signal processing according to an embodiment of the present application.

detailed description

In order to facilitate the understanding of the embodiments of the present application, the following elements are first introduced before introducing the embodiments of the present application.

The oscillator is an energy conversion device capable of converting DC power into AC power having a certain frequency, and the circuit formed is called an oscillation circuit.

The comparator is an electronic component that outputs different voltage results at the output by comparing the magnitude of the current or voltage at the two inputs. The comparator is often used in an analog-to-digital conversion circuit.

The multiplexer is a circuit that can select any one of them as needed during the multiplexed data transfer process.

The edge trigger receives input data when a certain transition (positive or negative transition) of a clock pulse (CP) arrives.

The duty ratio refers to the ratio of the time that the high level takes up within one cycle. For example, the duty ratio of the square wave is 50%, indicating that the high level takes 0.5 cycles.

An architectural diagram of a prior art signal processing system is shown in FIG. As shown in FIG. 1, the signal processing system includes an oscillator 110 and a comparator 120. The positive terminal of the oscillator 110 outputs V _1p , the negative terminal outputs V _1n , and the V ₅ signal is output through the processing of the comparator 120. Since a single comparator is equivalent to first making V _1p and V _1n poor and then comparing with 0 voltage, the phases of V _1p and V _1n are different, and the effect is only the amplitude after the difference, so V _1p and V _1n When the phase is any fixed value, the output V ₅ signal is a square wave signal with a duty ratio of about 50%. For example, if the phase difference between V _1p and V _1n is 90° or 125°, the V ₅ signal remains. For a square wave signal with a duty cycle of approximately 50%, the signal processing system has a smaller application range and lower calculation accuracy.

Further, when the phase difference between V _1p and V _1n is 180°, the V5 signal is theoretically a signal having a duty ratio of 50%, but since the comparator 120 has a problem of high and low delay inconsistency, the output is made. The duty cycle of the V ₅ signal deviates by 50%, and the duty cycle offset of 50% includes a large duty cycle (V ₅ signal as shown in Figure 2) and a small duty cycle (V ₅ as shown in Figure 2). '). In this way, for applications that are sensitive to duty cycle, the accuracy of the calculation will be seriously affected.

FIG. 3 illustrates a signal processing system 300 in accordance with an embodiment of the present application. The signal processing system 300 includes an output device 301, a first comparator 302, a second comparator 303, a multiplexer 304, and an edge trigger 305.

The output device 301 includes a first positive output terminal and a first negative output terminal, and the first positive output terminal outputs a first positive signal and the first negative output terminal outputs a first negative signal with a phase difference of a fixed value;

The first comparator 302 includes a second positive input terminal and a second negative input terminal, the second positive input terminal is coupled to the first positive output terminal, and the second negative input terminal is coupled to the first negative output terminal. The first comparator 302 is configured to perform shaping processing on the first positive signal and the first negative signal to generate a second signal V _2p , where the second signal V _2p is a square wave signal;

The second comparator 303 includes a third positive input terminal and a third negative input terminal, the third positive input terminal is coupled to the first negative output terminal, and the third negative input terminal is coupled to the first positive output terminal. The second comparator 303 is configured to perform shaping processing on the first positive signal and the first negative signal to generate a third signal V _2n , where the third signal V _2n is a square wave signal;

The multiplexer 304 is configured to select the second signal V _2p or the third signal V _{2n to} generate a fourth signal V ₄ , the fourth signal V ₄ having an accurate rising edge;

The edge trigger 305 is configured to generate a fifth signal V ₅ according to a rising edge of the rising edge of the fourth signal, the edge trigger comprising a first output end, the first output end is configured to output a fifth signal.

The first comparator 302 and the second comparator 303 are completely symmetrical with the output of the output device 301 such that the phase of the output waveform of the first comparator 302 and the second comparator 303 is strictly 180° out of phase. In addition, as can be seen from FIG. 2, the V ₅ signal duty ratio is greater than 50%, but the rising edge is accurate. Therefore, the embodiment of the present application can select the second signal generated by the two symmetric comparators or the second signal. The third signal obtains a fourth signal with an accurate rising edge, and the fifth signal can switch between the rising edge and the falling edge according to the accurate rising edge, that is, generate a signal with a relatively accurate duty cycle.

It should be noted that the first positive signal and the first negative signal may both be analog signals, so the shaping process by the first comparator and the second comparator may specifically be performing analog-to-digital conversion, that is, converting the analog signal into a digital signal ( That is, the square wave signal).

It should be understood that the first positive output terminal and the first negative output terminal continuously output signals, and the signal outputted by the first positive output terminal is referred to as “first positive signal”, and the signal outputted by the first negative output terminal is referred to as “first The negative signal", such that the phase difference between the first positive signal and the first negative signal continuously outputted remains at a constant value.

It should also be understood that the embodiment of the present application may be applied to a scenario where the duty ratio of the signal is too large, and may also be applied to a scenario where the duty ratio of the signal is small, but for the convenience of description, the signal of the embodiment of the present application is occupied. The empty ratio is large as an example, but the application is not limited thereto.

Therefore, the signal processing system of the embodiment of the present application outputs a first positive signal through a first positive output terminal of the output device, and a first negative output terminal outputs a first negative signal, and the first positive signal and the first negative signal The phase difference is a fixed value, the first comparator shapes the first positive signal and the first negative signal to generate a second signal of the square wave signal, and the second comparator performs the first positive signal and the first negative signal together The shaping process generates a third signal of a square wave signal, and the multiplexer selects the second signal or the third signal to generate a fourth signal having an accurate rising edge, and the edge trigger generates an edge jump according to the rising edge of the fourth signal. The fifth signal, such that by selecting a signal that is processed by two comparators that are completely symmetric, to generate a square wave signal with a relatively accurate duty cycle, can improve the calculation accuracy of a duty-sensitive application.

Optionally, if the phases of the first positive signal and the first negative signal are different by 180°, the fifth signal generated according to the signal processing system is a signal with an accurate high-level duty ratio of 50%.

Optionally, if the phase difference between the first positive signal and the second negative signal is a fixed value not equal to 180°, the duty ratio of the generated fifth signal is proportional to the phase difference. For example, if the phase difference between the first positive signal and the first negative signal is 90°, the high level duty ratio of the fifth signal is 25%. Compared with the prior art, when the phase difference between the first positive signal and the second negative signal is a fixed value not equal to 180°, the present application can generate a high-level duty ratio whose duty ratio is proportional to the phase difference. The application range of the signal processing system is improved, and a relatively accurate high-level duty ratio can be obtained.

Optionally, the output device 301 of the embodiment of the present application may be an oscillator, specifically an oscillator. It can be an LC LC oscillator (as shown in FIG. 4 ), or it can be a resistor-capacitor (RC) oscillator or a crystal oscillator, which is not limited in this application.

Alternatively, the first comparator 302 may be a self-bias comparator as shown in FIG. 5(a), and the second comparator 303 may be a self-bias comparator as shown in FIG. 5(b). The first comparator 302 receives the first positive signal V _1p and the first negative signal V _{1n to} generate a second signal V _2p , and the second comparator 303 receives the first positive signal V _1p and the first negative signal V _{1n to} generate a third signal V _2n .

It should be understood that the first comparator 302 and the second comparator 303 may also be comparators of other configurations, which are not limited in the present application.

Optionally, the multiplexer 304 can be as shown in FIG. 6, that is, the multiplexer is composed of three NAND gates, and the three NAND gates are respectively referred to as the first NAND gate 1, the second The non-gate 2 and the third NAND gate 3 are distinguished, and the first NAND gate includes a third input terminal V _2p input terminal, a fourth input terminal V _3n and a third output terminal, and the second NAND gate includes a fifth The input terminal V _2n , the sixth input terminal V _3p and the fourth output terminal, the third NAND gate includes a seventh input terminal, an eighth input terminal and a fifth output terminal V ₄ , and the third output terminal and the third The seven input terminals are connected, and the fourth output terminal is connected to the eighth input terminal, that is, the output of the first NAND gate and the output of the second NAND gate are used as the third NAND input.

For example, as shown in FIG. 6, assuming that V _3n is a digital signal "0" and V _3p is a digital signal "1", V _2p and "0" are _ANDed to obtain "0", and then non-operation is performed to obtain "1". And "1" and V _2n perform the AND operation to obtain V _2n , and then perform non-operation

Will be 1 and

Then proceed with the operation

The non-operation is again performed to obtain V _2n , that is, the output V ₄ is equal to V _2n .

Similarly, V _3n is the digital signal "1", and V _3p is the digital signal "0". The output V ₄ = V _{2p is} obtained by the multiplexer 304 shown in FIG.

Receiving the second signal V _2p at the third input terminal, the fourth input terminal receives the sixth signal V _3n , the fifth input terminal receives the third signal V _2n , and the sixth input terminal receives the seventh signal The signal V _3p , because the V _3p signal is a signal opposite to the positive and negative of the V _3n signal, the fifth output terminal can output the fourth signal V ₄ . That is to say, the multiplexer performs NAND processing by inputting a signal having a high and low level change and opposite, respectively, and performing NAND processing with the second signal and the third signal, and then performing non-processing on the result to finally select the second. The signal or the third signal results in a fourth signal with an accurate rising edge.

It should be understood that the multiplexer 304 may also be a multiplexer of other configurations, which is not limited in the present application.

Optionally, the edge flip-flop is an edge flip-flop capable of dividing by two, such that the fifth signal output by the edge trigger is an edge jump on a rising edge of each fourth signal, that is, The frequency of the fourth signal is twice the frequency of the fifth signal, and the frequency of the fifth signal is divided by the frequency of the fourth signal.

Alternatively, the edge flip-flop capable of dividing the input signal by two may be an edge flip-flop as shown in FIG. 7, and the edge flip-flop 305 includes two input terminals and two output terminals, and the signals of the two output terminals are opposite. The signal, for example, V ₅ and V _{3n in} FIG. 7 are opposite signals, that is, V ₅ is a digital signal "1", and V _3n is a digital signal "0". The present application embodiment, the output terminal QB is connected to the input terminal D, so as to realize half of the frequency signal V _4, i.e., ₄ V frequency signal into a frequency signal V5 twice.

Optionally, the first output of the edge flip-flop 305 is used to output a fifth signal, the second output is used to output the sixth signal V _3p , and the multiplexer 304 can jump according to the edge of the sixth signal. The second signal or the third signal is selected as the fourth signal.

Optionally, the multiplexer 304 may select the second signal or the third signal as the fourth signal according to the edge transition of the high and low levels of the seventh signal, and the seventh signal is the signal obtained by inverting the sixth signal. This application does not limit this.

Alternatively, the signal processing system may be a in FIG. 7 V _3n input to fourth input terminal in FIG. 6, and V _3n to be obtained after the seventh inverted signal input terminal of the sixth input, a second selection signal to achieve Or the third signal is used as the fourth signal, so that an accurate signal with a duty ratio of 50% can be obtained.

Optionally, the signal processing system of the embodiment of the present application may set an inverter between the second output end and the sixth input end to implement the inverse conversion of the sixth signal into the sixth signal input sixth input end.

It should be understood that when the seventh signal and the fifth signal are both inverted signals of the sixth signal, the seventh signal and the fifth signal are the same signal.

It should also be understood that the inverter may be disposed in the multiplexer or may be disposed after the second output of the edge flip flop to obtain two opposite signals required by the multiplexer. Limited.

For example, the edge trigger outputs V _3n , and the inverter reverses V _3n to generate a seventh signal, which is input to the sixth input of the multiplexer, and the reverser is set at the fourth input of the multiplexer. The seventh signal is converted to the opposite signal and input to the fourth input.

Optionally, the edge flip-flop can also return V ₅ to the fourth input of the multiplexer while outputting V ₅ , and set an inverter at the sixth input of the multiplexer to set V _{5 is} converted to the opposite signal and input to the sixth input. That is, regardless of the output of V _3n , V _{5 is} directly used as the input of the multiplexer.

A specific embodiment of the present application is described below. As shown in FIG. 8, the phase difference of the signal outputted by the output device 301 is 180°. For example, in the time period T ₀ to T ₁ , V ₅ is assumed to be high. In normal times, it is known from the multiplexer 304 shown in FIG. 6 that V _{2n is} selected to determine V ₄ , that is, V ₄ is a low level consistent with V _2n . Until V _2n is the rising edge at time T ₁ , V ₄ is also the rising edge. After the edge trigger detects the rising edge of V ₄ , the edge of V ₅ jumps (ie, changes from high level to low level). When V ₅ is low, the multiplexer 304 selects V _2p as V ₄ (as in the period T ₁ to T ₂ in FIG. 8 ), that is, V ₄ is from the high level to the low level consistent with V _2n . Flat change. Thus, the duty cycle of the V ₅ signal thus generated is exactly 50%.

Similarly, the phase difference of the signal outputted by the output device 301 is 180°. As shown in FIG. 9, if V ₅ is assumed to be low level, the multiplexer 304 shown in FIG. 6 can be used to select V. _2p determining V _4, V ₄ to be consistent with i.e. V _2p is V ₅ is also kept low until a rising edge of V _2p at time T _2, at time T ₂ V ₄ is also rising, the edge-triggered After detecting the rising edge of V ₄ , the edge transition of V ₅ (ie, from low level to high level) is performed. When V ₅ is high, multiplexer 304 selects V _{2n to} generate V ₄ (as in the period T ₂ to T ₃ in FIG. 9 ), that is, V ₄ is from high level to low level consistent with V _2n . Flat change. Thus, the duty cycle of the V ₅ signal thus generated is exactly 50%.

In addition, the phase difference of the signal outputted by the output device 301 is 180° as an example. If V _2p and V _{3p in} FIG. 6 are input together, the first NAND gate is input, and V _3n and V _2n are input together to the second NAND gate. Then, the signal changes as shown in Fig. 10, and finally the V ₅ signal with an accurate duty ratio of 50% can still be output.

The above described FIG. 3 to FIG. 10 describe a signal processing system, and the following details describe the embodiment of the present application. Number processing method.

FIG. 11 shows a schematic flow chart of a method 1100 of signal processing in accordance with an embodiment of the present application. As shown in FIG. 11, the signal processing method is applied to a signal processing system including an output device, a first comparator, a second comparator, a multiplexer, and an edge trigger, the output device including the first a positive output terminal and a first negative output terminal, the first comparator includes a second positive input terminal and a second negative input terminal, the second positive input terminal is coupled to the first positive output terminal, and the second negative input terminal is coupled to The first negative output terminal is connected, the second comparator comprises a third positive input terminal and a third negative input terminal, the third positive input terminal is connected to the first negative output terminal, and the third negative input terminal and the third A positive output connection, the method 1100 includes:

S1110, the output device outputs a first positive signal through the first positive output terminal and a first negative signal through the first negative output terminal, and a phase difference between the first positive signal and the first negative signal is a fixed value;

S1120, the first comparator performs shaping processing on the first positive signal and the first negative signal to generate a second signal, where the second signal is a square wave signal;

S1130, the second comparator performs shaping processing on the first positive signal and the first negative signal to generate a third signal, where the third signal is a square wave signal;

S1140, the multiplexer selects the second signal or the third signal to generate a fourth signal, where the fourth signal has an accurate rising edge;

S1150. The edge trigger receives the fourth signal, and performs a high-low level edge transition according to a rising edge of the fourth signal to generate a fifth signal.

Optionally, as an embodiment, the method further includes: the edge trigger outputting a sixth signal, the sixth signal is a signal opposite to the fifth signal, or the sixth signal is the same as the fifth signal a signal, wherein the multiplexer alternately selects the second signal or the third signal generates a fourth signal, including: selecting the second signal or the first according to the edge transition of the high and low levels of the sixth signal The third signal generates the fourth signal.

Optionally, as an embodiment, the first positive signal and the first negative signal have a phase difference of 180°, and the fifth signal has a duty ratio of 50%.

Optionally, as an embodiment, the phase difference between the first positive signal and the first negative signal is a fixed value that is not equal to 180°, and the duty ratio of the fifth signal is the first positive signal and the first The phase difference of the negative signal is proportional.

Optionally, as an embodiment, the edge trigger is edge triggered by two-way Device.

Optionally, as an embodiment, the output device is an LC filter.

Optionally, as an embodiment, the first comparator and the second comparator are self-bias comparators.

It should be understood that the meanings of the various terms in the embodiments of the present application are the same as those in the foregoing embodiments. To avoid repetition, details are not described herein again.

Therefore, in the signal processing method of the embodiment of the present application, the first positive output terminal outputs a first positive signal and the first negative output terminal outputs a first negative signal, and the first positive signal and the first negative signal are output. The phase difference is a fixed value, the first comparator shapes the first positive signal and the first negative signal to generate a second signal of the square wave signal, and the second comparator pairs the first positive signal and the first negative signal Performing a shaping process to generate a third signal of a square wave signal, the multiplexer selecting the second signal or the third signal to generate a fourth signal having an accurate rising edge, and the edge trigger performing edge jump according to the rising edge of the fourth signal A fifth signal is generated, so that by selecting a signal processed by two comparators that are completely symmetric, a square wave signal with a relatively accurate duty ratio can be generated, which can improve the calculation accuracy of a duty-sensitive application.

It should be understood that the term "and/or" herein is merely an association relationship describing an associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, and A and B exist simultaneously. There are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.

It should be understood that, in the various embodiments of the present application, the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application. The implementation process constitutes any limitation.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and The method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of this application is subject to the scope of protection of the claims.

Claims

A signal processing system, comprising:

The output device includes a first positive output end and a first negative output end, and a phase difference between the first positive signal output by the first positive output terminal and the first negative signal output by the first negative output terminal is a fixed value;

a first comparator comprising a second positive input terminal and a second negative input terminal, the second positive input terminal being coupled to the first positive output terminal, the second negative input terminal and the first negative output terminal Connecting, and the first comparator is configured to perform shaping processing on the first positive signal and the first negative signal to generate a second signal, where the second signal is a square wave signal;

a second comparator comprising a third positive input terminal and a third negative input terminal, the third positive input terminal being coupled to the first negative output terminal, the third negative input terminal and the first positive output terminal Connecting, and the second comparator is configured to perform shaping processing on the first positive signal and the first negative signal to generate a third signal, where the third signal is a square wave signal;

a multiplexer for selecting the second signal or the third signal to generate a fourth signal, the fourth signal having an accurate rising edge;

An edge trigger is configured to generate a fifth signal according to the edge transition of the fourth signal, the edge trigger comprising a first output, and the first output is configured to output a fifth signal.
The signal processing system of claim 1 wherein said edge trigger further comprises a second output, said edge trigger further for outputting a sixth signal through said second output, said The sixth signal is a signal opposite to the fifth signal, or the sixth signal is the same signal as the fifth signal;

The multiplexer is used to:

And selecting the second signal or the third signal to generate the fourth signal according to the edge transition of the high and low levels of the sixth signal.
The signal processing system according to claim 1 or 2, wherein a phase difference between said first positive signal and said first negative signal is 180°, and a duty ratio of said fifth signal is 50%.
The signal processing system according to claim 1 or 2, wherein a phase difference between said first positive signal and said first negative signal is a fixed value not equal to 180°, and a duty of said fifth signal The ratio is proportional to the phase difference between the first positive signal and the first negative signal.
The signal processing system according to any one of claims 1 to 4, wherein the edge flip-flop is an edge flip-flop capable of dividing by two.
A signal processing system according to claim 5, wherein said capable of performing The two-way edge flip-flop further includes a first input for receiving the fourth signal, the second input and a second output of the edge flip-flop End connection.
The signal processing system according to any one of claims 1 to 6, wherein the multiplexer comprises a first NAND gate, a second NAND gate, and a third NAND gate, the first The NAND gate includes a third input terminal, a fourth input terminal, and a third output terminal, wherein the second NAND gate includes a fifth input terminal, a sixth input terminal, and a fourth output terminal, and the third NAND gate includes a seventh input end, an eighth input end, and a fifth output end, wherein the third output end is connected to the seventh input end, and the fourth output end is connected to the eighth input end, the third The input end is configured to receive the second signal, the fourth input end is configured to receive the sixth signal, the fifth output end is used to output the fourth signal, and the fifth input end is configured to receive The third signal is used to receive a seventh signal, and the seventh signal is a signal opposite to the sixth signal.
The signal processing system of claim 7 wherein said signal processing system further comprises an inverter for converting said sixth signal to said seventh signal.
The signal processing system according to any one of claims 1 to 8, wherein the output device is an inductor-capacitor LC oscillator.
A signal processing system according to any one of claims 1 to 9, wherein said first comparator and said second comparator are self-biased comparators.
A method of signal processing, the method being applied to a signal processing system, the signal processing system comprising an output device, a first comparator, a second comparator, a multiplexer, and an edge trigger, The output device includes a first positive output and a first negative output, the first comparator includes a second positive input and a second negative input, and the second positive input is coupled to the first positive output The second negative input terminal is coupled to the first negative output terminal, the second comparator includes a third positive input terminal and a third negative input terminal, the third positive input terminal and the first negative input terminal The output terminal is connected, and the third negative input terminal is connected to the first positive output terminal, and the method includes:

The output device outputs a first positive signal through the first positive output terminal and a first negative signal through the first negative output terminal, and a phase difference between the first positive signal and the first negative signal is Fixed value;

The first comparator performs shaping processing on the first positive signal and the first negative signal to generate a second signal, where the second signal is a square wave signal;

The second comparator performs shaping processing on the first positive signal and the first negative signal to generate a third signal, where the third signal is a square wave signal;

The multiplexer selects the second signal or the third signal to generate a fourth signal, the fourth signal having an accurate rising edge;

The edge flip-flop performs a high-low level edge jump according to a rising edge of the fourth signal to generate a fifth signal.
The method of claim 11 wherein the method further comprises:

The edge trigger outputs a sixth signal, the sixth signal is a signal opposite to the fifth signal, or the sixth signal is the same signal as the fifth signal;

The multiplexer in turn selects the second signal or the third signal to generate a fourth signal, including:

And selecting the second signal or the third signal to generate the fourth signal according to the edge transition of the high and low levels of the sixth signal.
The method according to claim 11 or 12, wherein the first positive signal and the first negative signal have a phase difference of 180° and the fifth signal has a duty ratio of 50%.
The method according to claim 11 or 12, wherein the phase difference between the first positive signal and the first negative signal is a fixed value not equal to 180°, and the duty ratio of the fifth signal is The phase difference between the first positive signal and the first negative signal is proportional.
The method according to any one of claims 11 to 14, wherein the edge flip-flop is an edge flip-flop capable of dividing by two.
The method according to any one of claims 11 to 15, wherein the output device is an LC LC oscillator.
The method according to any one of claims 11 to 16, wherein the first comparator and the second comparator are self-biased comparators.