WO2018120730A1 - 显示基板及其制备方法 - Google Patents

显示基板及其制备方法 Download PDF

Info

Publication number
WO2018120730A1
WO2018120730A1 PCT/CN2017/091417 CN2017091417W WO2018120730A1 WO 2018120730 A1 WO2018120730 A1 WO 2018120730A1 CN 2017091417 W CN2017091417 W CN 2017091417W WO 2018120730 A1 WO2018120730 A1 WO 2018120730A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
display substrate
planarization layer
forming
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/091417
Other languages
English (en)
French (fr)
Inventor
杜生平
苏同上
黄正峰
杨玉
马云
郭稳
刘丽华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/063,924 priority Critical patent/US11309358B2/en
Publication of WO2018120730A1 publication Critical patent/WO2018120730A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning

Definitions

  • Embodiments of the present invention relate to a display substrate and a method of fabricating the same.
  • COA Color Filter On Array
  • the advantage is that the aperture ratio can be improved, the contrast of the product can be improved, and the color film substrate and the array substrate are not present.
  • the alignment problem also reduces the difficulty of making the liquid crystal cell.
  • the COA display substrate includes a base substrate 1 , a thin film transistor 2 (TFT) formed on the base substrate 1 , a passivation layer covering the thin film transistor 2 and the base substrate 1 . 4.
  • TFT thin film transistor
  • a color resist 12/13/14 over the passivation layer 4 a planarization layer 5 covering the color resist 12/13/14 and the passivation layer 4, and a corresponding over the planarization layer 5
  • the display electrode 7 of the pixel region 10 wherein the display electrode 7 is connected to the corresponding thin film transistor 2 through a via.
  • the height of the portion of the planarization layer 5 located in the pixel region 10 is significantly higher than the height of the portion located in the non-pixel region 9, and the flattening effect is not
  • the preparation of the other structures is affected; in addition, when the display electrode 7 is prepared, since the film thickness of the planarization layer 5 over the color color resist 12/13/14 is thick, there is a gap between the display electrode 7 and the drain A large height difference H (the height difference is approximately equal to the difference between the sum of the passivation layer film thickness, the color resist film thickness, the flattening layer film thickness above the color resist layer and the drain film thickness), when displayed
  • the electrode 7 is connected to the drain through the via hole, the portion of the display electrode 7 located in the via hole is liable to be broken, resulting in poor connection between the display electrode 7 and the drain electrode.
  • the embodiment provides a display substrate and a method of fabricating the same that can improve the flatness of the planarization layer and avoid breakage of the display electrode.
  • a method of preparing a display substrate the display substrate is divided into a non-pixel area and a color pixel area, and the method for preparing the display substrate includes:
  • Thinning a thickness of the planarization layer in the color pixel region such that a thickness of a portion of the planarization layer located in the color pixel region is smaller than a thickness of a portion located in the non-pixel region;
  • a display electrode is formed over the planarization layer, and the display electrode and the drain are connected through a via.
  • the step of forming a planarization layer over the passivation layer and the color resist is performed in synchronization with the step of thinning the thickness of the planarization layer in the color pixel region,
  • the steps of forming the planarization layer include:
  • planarization material film comprising: a fully-retained region, a partially-retained region, and a non-retained region, the semi-reserved region and the color pixel Corresponding to the region, the non-reserved region corresponding to the region where the drain is located;
  • the flattening material film after the exposure treatment is subjected to development processing to constitute the planarization layer.
  • the manufacturing method further includes: forming a first via hole on a region corresponding to the drain on the planarization layer; wherein
  • Forming a passivation layer over the thin film transistor includes:
  • Forming the display electrode over the planarization layer includes:
  • the display electrode is connected to the drain through the first via hole and the second via hole.
  • the manufacturing method further includes: forming a first via hole on a region corresponding to the drain on the planarization layer, where
  • Forming a passivation layer over the thin film transistor includes:
  • Forming the display electrode over the planarization layer includes:
  • the display electrode is connected to the drain through the first via hole and the second via hole.
  • the display substrate is an OLED substrate, and the display electrode is an anode, and the method for preparing the display substrate further includes:
  • a pixel defining layer above the planarization layer, a plurality of receiving holes are formed in the pixel defining layer, and the receiving holes are disposed corresponding to the display electrodes;
  • a protective substrate is disposed above the cathode.
  • the display substrate is a liquid crystal display substrate
  • the display electrode is a pixel electrode
  • the method for preparing the display substrate further includes:
  • An alignment layer is formed over the protective layer.
  • the display substrate is further divided into white pixel regions.
  • a thickness of a portion of the planarization layer located in the non-pixel region is The difference in thickness of the portion of the planarization layer located in the color pixel region is 2 ⁇ m to 3 ⁇ m.
  • a portion of the planarization layer located in the non-pixel region has a thickness of 3 ⁇ m to 3.5 ⁇ m;
  • the portion of the planarization layer located in the color pixel region has a thickness of 0 to 1.5 ⁇ m.
  • an embodiment of the present invention further provides a display substrate, the display substrate is divided into a non-pixel region and a color pixel region, and the display substrate includes: a substrate substrate, a thin film transistor, formed on Above the substrate substrate and in the non-pixel region; a passivation layer formed over the thin film transistor; a color color resist formed over the passivation layer and located in the color pixel region; planarization a layer formed over the passivation layer and the color resist, a thickness of a portion of the planarization layer in the color pixel region being smaller than a thickness of a portion of the planarization layer in the non-pixel region And a display electrode formed over the planarization layer, the display electrode being connected to a drain of the thin film transistor through a via.
  • the display substrate is an OLED substrate, and the display electrode is an anode; the display substrate further includes: a pixel defining layer formed on the planarization layer, and the pixel defining layer is formed with a plurality of accommodations a hole, the receiving hole is disposed corresponding to the display electrode, an organic light emitting layer is formed in the receiving hole, a cathode is formed above the organic light emitting layer, and a protective substrate is formed above the cathode.
  • the display substrate is a liquid crystal display substrate
  • the display electrode is a pixel electrode
  • the display substrate further includes: a protective layer formed over the pixel electrode; and an alignment layer formed over the protective layer .
  • the display substrate is further divided into white pixel regions.
  • a difference between a thickness of a portion of the planarization layer in the non-pixel region and a thickness of a portion of the planarization layer in the color pixel region is: 2 ⁇ m to 3 ⁇ m.
  • a portion of the planarization layer located in the non-pixel region has a thickness of 3 ⁇ m to 3.5 ⁇ m;
  • the portion of the planarization layer located in the color pixel region has a thickness of 0 to 1.5 ⁇ m.
  • the technical solution of the embodiment of the present invention reduces the film thickness of the portion of the planarization layer above the color color resist by thinning the planarization layer located in the color pixel region, It can effectively improve the flatness of the planarization layer.
  • the film thickness of the portion of the planarization layer above the color resist is reduced, the height difference between the display electrode and the drain can be reduced, thereby effectively reducing the position of the display electrode when it is connected to the drain through the via.
  • the part of the via has a risk of breaking.
  • 1 is a schematic structural view of a known COA display substrate
  • FIG. 2 is a flowchart of a method for preparing a display substrate according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic structural view of a display substrate prepared by the preparation method shown in FIG. 2;
  • FIG. 4a to 4g are schematic views showing the intermediate structure of the display substrate shown in FIG. 3;
  • FIG. 5 is a flow chart showing a first via hole formed by using a halftone mask and a thinning process for a planarization layer located in a color pixel region;
  • FIG. 6 is a schematic view showing a patterning process of a planarization material film by using a halftone mask
  • FIG. 7 is a flowchart of a method for preparing a display substrate according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic structural view of a display substrate prepared by the preparation method shown in FIG. 7;
  • FIG. 9 is a flowchart of a method for preparing a display substrate according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural view of a display substrate prepared by the preparation method shown in FIG. 9.
  • FIG. 10 is a schematic structural view of a display substrate prepared by the preparation method shown in FIG. 9.
  • FIG. 2 is a flow chart of a method for preparing a display substrate according to a first embodiment of the present invention
  • FIG. 3 is a schematic structural view of a display substrate prepared by using the preparation method shown in FIG. 1
  • FIG. 4 a to FIG. The schematic diagram of the intermediate structure of the display substrate is shown.
  • the display substrate is divided into a non-pixel area 9 and a color pixel area 10, wherein the non-pixel area 9 refers to an area where pixel display is not performed, and the color pixel area 10 refers to a color pixel capable of being performed.
  • the method of preparing the display substrate includes the following steps S1-S6.
  • step S1 a thin film transistor is formed in a region above the substrate and corresponding to the non-display region.
  • a thin film transistor 2 is formed in a region above the base substrate 1 and corresponding to the non-pixel region 9.
  • the base substrate 1 may be a glass substrate or a resin material substrate, and the thin film transistor 2 may be prepared by any known method of preparing the thin film transistor 2.
  • the thin film transistor 2 may include a gate, an active layer, a source, and a drain, wherein a gate insulating layer 3 is disposed between the gate and the active layer.
  • gate lines and data lines are simultaneously prepared during the fabrication of the thin film transistor 2.
  • Step S2 forming a passivation layer over the thin film transistor.
  • a thin film 41 of a passivation material can be formed over the thin film transistor 2 and the gate insulating layer 3.
  • the passivation material is at least one of silicon oxide (chemical formula SiOx), silicon nitride (chemical formula SiNx), silicon oxynitride (SiOxNy).
  • the thin film may be formed by deposition, coating, sputtering, or the like.
  • a plasma enhanced chemical vapor deposition PECVD
  • PECVD plasma enhanced chemical vapor deposition
  • Step S3 forming a color color resistance in a region above the passivation layer and corresponding to the color pixel region.
  • the color pixel region 10 may include: a red pixel region, a green pixel region, and a blue pixel region.
  • the color resist 12/13/14 (also referred to as a color filter) may include, for example, a red color resist pattern 12, a green color resist pattern 13, and a blue color resist pattern 14.
  • a red color resist pattern 12 can be prepared in a red pixel region by using a preparation method of any known red color resist pattern, and a green color resist pattern 13 can be prepared in the green pixel region.
  • a blue color resist pattern 14 is prepared in the blue color pixel region.
  • Step S4 forming a planarization layer over the passivation layer and the color resist.
  • a planarization material film 51 may be formed over the passivation layer 4 and the color resist 12/13/14, and the planarization material film 51 is patterned to form a first via. 8.
  • the first via 8 is located directly above the drain of the thin film transistor 2, and the remaining planarizing material constitutes the planarization layer 5.
  • the film thickness of the planarizing material film 51 may be from 3 ⁇ m to 3.5 ⁇ m.
  • planarizing material is an organic resin material.
  • the planarization material film 51 can be masked and exposed using a predetermined mask, and the exposed planarization material film 51 is developed to remove the planarization material directly above the drain to form a planarization material.
  • the display substrate includes a white pixel region 11 in addition to the non-pixel region 9 and the color pixel region 10.
  • the setting of the white pixel area 11 can effectively increase the brightness of the display panel and reduce the overall power consumption.
  • the planarization layer 5 filled in the blank region can be utilized as a white color resist, so that the setting of the white color resistance does not require an additional patterning process.
  • the height of the upper surface of the portion of the planarization layer 5 located in the pixel region is significantly higher than the height of the upper surface of the portion located in the non-pixel region 9 and the white pixel region 11, and the planarization effect is not good.
  • Step S5 thinning the thickness of the portion of the planarization layer located in the color pixel region.
  • step S5 the portion of the planarization layer 5 located in the color pixel region 10 is thinned to reduce the height of the upper surface of the portion of the planarization layer 5 located in the pixel region, so that the planarization layer
  • the thickness of the portion located in the color pixel region 10 is smaller than the thickness of the portion in the non-pixel region 9, and the flatness of the planarization layer 5 can be effectively improved at this time.
  • the difference between the thickness of the portion of the planarization layer 5 located in the non-pixel region 9 and the thickness of the portion in the color pixel region 10 is 2 ⁇ m to 3 ⁇ m.
  • the thickness of the planarization layer in the non-pixel region 9 may be 3 ⁇ m to 3.5 ⁇ m, and the thickness of the planarization layer in the color pixel region 10 may be 0 to 1.5 ⁇ m.
  • Step S6 forming a display electrode over the planarization layer, and connecting the display electrode and the drain of the thin film transistor through the via.
  • a patterning process is performed on the passivation material film 41 to form a second via hole 6 under the first via hole 8, and the remaining passivation material constitutes the passivation layer 4; Forming a transparent conductive material film over the planarization layer 5 and the first via hole 8 and the second via hole 6; then, performing a patterning process on the transparent conductive material film to form a pattern of the display electrode 7, And the display electrode 7 is connected to the drain through the first via 8 and the second via 6.
  • the one-time patterning process in the embodiment of the present invention may specifically include steps of photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • step S6 Since the portion of the planarization layer 5 located in the color pixel region 10 is thinned in step S5, that is, the film thickness of the portion of the planarization layer 5 above the color color resist is reduced, so that step S6 can be made The height difference between the formed display electrode 7 and the drain is reduced, which in turn can effectively reduce the risk of breakage of the portion of the display electrode 7 that is located in the via hole when the via is connected to the drain.
  • the technical solution of the present invention can effectively improve the flatness of the planarization layer 5 and reduce the risk of breakage of the display electrode 7.
  • the embodiment of the present invention is not limited to forming the first via 8 on the planarization material film 51 and then forming the second via 6 on the passivation material film 41.
  • the second via hole 6 may be formed on the passivation material film 41
  • the first via hole 8 may be formed on the planarization material film 51.
  • a passivation material film 41 may be formed over the thin film transistor 2 and the gate insulating layer 3, and then the passivation material film 41 is subjected to a patterning process to form a second via hole 6 so that the second pass The hole 6 is disposed corresponding to the drain and communicates with the first via 8 formed in the subsequent order, and the remaining passivation material constitutes the passivation layer 4.
  • the passivation material film 41 is not required to be processed, and the transparent conductive material film can be directly formed and the transparent conductive material film can be subjected to a patterning process.
  • the embodiment of the present invention can also complete the thinning process of the planarization layer 5 in the color pixel region 10 while forming the first via hole 8 by one patterning process, that is, steps S4 and S5 can be performed simultaneously.
  • . 5 is a flow chart of forming a first via hole using a halftone mask and thinning a planarization layer in a color pixel region
  • FIG. 6 is a patterning of a planarization material film using a halftone mask. Schematic diagram of processing, as shown in FIGS. 5 and 6, the process of forming the planarization layer 5 may include the following steps S401-S403.
  • Step S401 forming a thin film of the planarizing material over the passivation layer and the color resist.
  • the planarization material is exemplified as an organic resin material which can be used as a negative photoresist
  • the planarization material film 51 includes: a fully-retained area, a partially-retained area, and a non-retained area, and is semi-reserved.
  • the area corresponds to the color pixel area 10
  • the non-retention area corresponds to the area where the first via 8 is to be formed.
  • Step S402 masking and exposing the film of the planarizing material with a halftone mask.
  • the halftone mask 15 includes a completely transparent region 15a, a partially transparent region 15c, and a partially transparent region 15b.
  • the fully transparent region 15a is disposed corresponding to the fully-retained region.
  • the divided light-transmitting region 15c is disposed corresponding to the partially-retained region, and the opaque region 15b is disposed corresponding to the non-reserved region.
  • Step S403 developing a film of the planarization material after the exposure processing.
  • the remaining planarizing material constitutes a planarization layer 5 in which all of the planarization material in the fully-retained region remains, and the planarization material of the non-retained region is entirely removed to form the first via 8, and the planarization material in the color pixel region 10 Partially reserved for thinning.
  • a single patterning process is employed to complete the thinning treatment of the planarization layer 5 in the color pixel region 10 while forming the first via hole 8, which can effectively reduce the processing steps and shorten the preparation of the display substrate. cycle.
  • planarization material in this embodiment may also be an organic resin material that can be used as a positive photoresist, which can also complete the pair of color pixel regions 10 by forming a first via hole 8 by a single patterning process.
  • the thinning treatment of the planarization layer 5 in the middle The specific process will not be described here.
  • an embodiment of the present invention further provides a display substrate prepared by the above-described preparation method.
  • the display substrate is divided into a non-pixel region 9 and a color pixel region 10, and includes: a lining
  • the base substrate 1 and the non-pixel region 9 above the base substrate 1 and the non-pixel region 9 have a thin film transistor 2, a passivation layer 4 formed over the thin film transistor 2, and a color color formed over the passivation layer 4 and located in the color pixel region 10.
  • a photoresist layer 12/13/14 a planarization layer 5 formed over the passivation layer 4 and the color resists 12/13/14, and a display electrode 7 formed over the planarization layer 5, wherein the planarization layer 5 is located at the color pixel
  • the thickness of the portion in the region 10 is smaller than the thickness of the portion in the non-pixel region 9, and the display electrode 7 is connected to the drain in the thin film transistor 5 through the via.
  • the difference between the thickness of the portion of the planarization layer 5 located in the non-pixel region 9 and the thickness of the portion located in the color pixel region 10 is 2 ⁇ m to 3 ⁇ m.
  • the thickness of the portion of the planarization layer in the non-pixel region 9 may be: 3 ⁇ m to 3.5 ⁇ m, and the thickness of the portion located in the color pixel region 10 may be 0 to 1.5 ⁇ m.
  • the technical solution of the embodiment of the present invention thins the portion of the planarization layer 5 located in the color pixel region 10 such that the thickness of the portion of the color pixel region 10 is smaller than that of the non-pixel region 9.
  • the thickness is such that the flatness of the planarization layer 5 can be effectively improved.
  • the film thickness of the portion of the planarization layer 5 located above the color resist 12/13/14 is reduced, the height difference H between the display electrode 7 and the drain can be reduced, so that the display electrode 7 can be effectively reduced.
  • the via is connected to the drain, the portion of the via that is located in the via is at risk of breaking.
  • the material of the planarization layer 5 comprises: an organic resin material.
  • the display substrate is further divided into white pixel regions 11.
  • FIG. 7 is a flow chart of a method for preparing a display substrate according to Embodiment 2 of the present invention
  • FIG. 8 is a schematic structural view of a display substrate prepared by using the preparation method shown in FIG. 7, as shown in FIG. 7 and FIG.
  • the display substrate is an Organic Light-Emitting Diode (OELD) substrate
  • the display electrode 7 is an anode.
  • the method for preparing the display substrate of the present embodiment further includes steps S7a to S10a in addition to the steps S1 to S6 in the first embodiment.
  • steps S1 to S6 refer to the content in the first embodiment. Only steps S7a to S10a will be exemplarily described below.
  • Step S7a forming a pixel defining layer above the planarization layer.
  • a film of a pixel defining material is formed on the planarization layer 5, wherein the pixel defining material may be a transparent organic resin material; then, the film of the pixel defining material is patterned to form a plurality of receiving holes, the receiving hole and the display
  • the electrodes 7 are correspondingly disposed, and the remaining pixel defining materials constitute the pixel defining layer 16.
  • step S8a an organic light-emitting layer is formed in the receiving hole.
  • step S8a for example, an organic light-emitting solution may be formed in the receiving hole by an inkjet process, and the organic light-emitting solution may be dried to form the organic light-emitting layer 17.
  • the organic light-emitting layer 17 emits white light under the action of a voltage.
  • the entire receiving hole and the pixel are made during the inkjet process.
  • An organic luminescent solution is present on the upper surface of the defining layer 16, and is further dried so that each of the accommodating holes is filled with the organic luminescent material and a thin organic luminescent material is present on the upper surface of the pixel defining layer 16.
  • step S9a a cathode is formed above the organic light-emitting layer.
  • a thin film of a transparent conductive material is formed over the organic light-emitting layer 17, and the thin film of the transparent conductive material constitutes the cathode 18.
  • step S10a a protective substrate is placed above the cathode.
  • the protective substrate 19 may be a glass substrate or a resin material substrate for protecting the cathode 18.
  • an embodiment of the present invention provides a display substrate prepared by the above preparation method. As shown in FIG. 8, the display substrate is an OLED substrate, and the display substrate includes not only the substrate substrate 1, the thin film transistor 2, and the passivation.
  • the layer 4, the planarization layer 5, the color resists 12/13/14 and the display electrode 7, further include a pixel defining layer 16, an organic light emitting layer 17, and a cathode 18.
  • the pixel defining layer 16 is located above the planarization layer 5.
  • the pixel defining layer 16 is formed with a plurality of receiving holes.
  • the receiving holes are disposed corresponding to the display electrodes 7.
  • the organic light emitting layer 17 is located in the receiving hole, and the cathode 18 is located in the organic light emitting layer 17. Above.
  • FIG. 9 is a flow chart of a method for preparing a display substrate according to a third embodiment of the present invention
  • FIG. 10 is a schematic structural view of a display substrate prepared by using the preparation method shown in FIG.
  • the display substrate is a liquid crystal display substrate (array substrate in a liquid crystal display panel)
  • the display electrode 7 is a pixel electrode.
  • the method for preparing the display substrate includes the steps S1 to S8 and the step S8b in addition to the steps S1 to S6 in the first embodiment.
  • the steps S1 to S6 refer to the content in the first embodiment. Only step S7b and step S8b will be described in detail.
  • step S7b a protective layer is formed over the pixel electrode.
  • a thin film of the protective material is formed on the planarization layer 5, wherein the protective material may be a transparent organic resin material, and the protective material film constitutes the protective layer 20.
  • step S8b an alignment layer is formed over the protective layer.
  • a film of an alignment material is formed on the protective layer 20; then, a film orientation or photo-alignment treatment is performed on the film of the alignment material to form a pretilt angle on the surface of the film of the alignment material, and the remaining alignment material constitutes the alignment layer 21.
  • an embodiment of the present invention further provides a display substrate prepared by the above preparation method.
  • the display substrate is a liquid crystal display substrate, and the display substrate includes not only the base substrate 1, the thin film transistor 2, the passivation layer 4, the planarization layer 5, the color color resistance 12/13/14, and the display electrode 7. Also included are: a protective layer 20 and an alignment layer 21.
  • the protective layer 20 is located above the planarization layer 5, and the alignment layer 21 is located above the protective layer 20.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板及其制备方法。显示基板被划分为非像素区域(9)和彩色像素区域(10)。制备方法包括：在衬底基板(1)的上方且在非像素区域(9)内形成薄膜晶体管(2)；在薄膜晶体管(2)的上方形成钝化层(4)；在钝化层(4)的上方且在彩色像素区域(10)内形成彩色色阻(12、13、14)；在钝化层(4)和彩色色阻(12、13、14)的上方形成平坦化层(5)；减薄平坦化层(5)位于彩色像素区域(10)中的部分的厚度；在平坦化层(5)的上方形成显示电极(7)，显示电极(7)与薄膜晶体管(2)中的漏极通过过孔(8、6)连接。通过对平坦化层位于彩色像素区域中的部分进行减薄处理，使得位于彩色色阻上方的部分膜厚减小，有效改善了平坦化层的平坦性；同时由于显示电极与漏极之间的高度差减小，有效降低了显示电极出现断裂的风险。

Description

显示基板及其制备方法 技术领域
本发明的实施例涉及一种显示基板及其制备方法。
背景技术
COA(Color Filter On Array)是一种将彩色光阻(Color Filter)直接制备在阵列基板上的技术，其优点是可以提高开口率、改善产品的对比度，且不存在彩膜基板与阵列基板的对位问题，也降低了液晶盒制成的难度。
图1是一种已知的COA显示基板的结构示意图。如图1所示，该COA显示基板包括：衬底基板1、形成在衬底基板1上方的薄膜晶体管2(Thin Film Transistor，简称TFT)、覆盖薄膜晶体管2和衬底基板1的钝化层4、位于钝化层4上方的彩色色阻12/13/14、覆盖所述彩色色阻12/13/14和所述钝化层4的平坦化层5以及位于平坦化层5上方且对应于像素区域10的显示电极7，其中，显示电极7通过过孔与对应的薄膜晶体管2连接。
由图1可见，由于在像素区域10内存在彩色色阻12/13/14，平坦化层5位于像素区域10的部分的高度明显高于位于非像素区域9的部分的高度，平坦化效果不佳，影响后序其他结构的制备；此外，在制备显示电极7时，由于位于彩色色阻12/13/14上方的平坦化层5膜厚很厚，使得显示电极7与漏极之间有较大的高度差H(高度差近似等于钝化层膜厚、彩色色阻膜厚、位于彩色色阻上方的平坦化层膜厚的三者之和与漏极膜厚的差)，当显示电极7通过过孔与漏极连接时，显示电极7位于过孔中的部分容易出现断裂，从而导致显示电极7与漏极连接不良。
由此可见，如何改善平坦化层的平坦性以及避免显示电极与漏极连接不良，是本领域技术人员亟需解决的技术问题。
发明内容
为了解决已知技术中存在的上述至少一个问题，本发明的至少一个 实施例提供了一种显示基板及其制备方法，其可以改善平坦化层的平坦性并且避免显示电极断裂。
为实现上述目的，本发明的实施例采取以下技术方案。
一方面，一种显示基板的制备方法，所述显示基板被划分为非像素区域和彩色像素区域，所述显示基板的制备方法包括：
在衬底基板的上方且对应于所述非像素区域的区域内形成薄膜晶体管；
在所述薄膜晶体管的上方形成钝化层；
在所述钝化层的上方且对应于所述彩色像素区域的区域内形成彩色色阻；
在所述钝化层和所述彩色色阻的上方形成平坦化层；
减薄所述彩色像素区域中的所述平坦化层的厚度，以使得所述平坦化层的位于所述彩色像素区域中的部分的厚度小于位于所述非像素区域中的部分的的厚度；
在所述平坦化层的上方形成显示电极，并使所述显示电极与所述漏极通过过孔连接。
可选地，所述在所述钝化层和所述彩色色阻的上方形成平坦化层的步骤与所述减薄所述彩色像素区域中的所述平坦化层的厚度的步骤同步进行，形成平坦化层的步骤包括：
在所述钝化层和所述彩色色阻的上方形成平坦化材料薄膜，所述平坦化材料薄膜包括：完全保留区域、部分保留区域和不保留区域，所述半保留区域与所述彩色像素区域对应，所述不保留区域与所述漏极所处区域对应；
采用半色调掩膜版对所述平坦化材料薄膜进行掩膜、曝光处理；
对曝光处理后的所述平坦化材料薄膜进行显影处理以构成所述平坦化层。
可选地，所述制备方法还包括：在所述平坦化层上对应所述漏极的区域形成第一过孔；其中，
在所述薄膜晶体管的上方形成钝化层包括：
在所述薄膜晶体管的上方形成钝化材料薄膜；
在所述平坦化层的上方形成显示电极包括：
对所述钝化材料薄膜进行一次构图工艺，以在所述第一过孔的下方 形成第二过孔，剩余的钝化材料构成所述钝化层；
在所述平坦化层的上方以及所述第一过孔和所述第二过孔内形成透明导电材料薄膜；以及
对所述透明导电材料薄膜进行一次构图工艺，以形成所述显示电极的图形，所述显示电极通过所述第一过孔和所述第二过孔与所述漏极连接。
可选地，所述制备方法还包括：在所述平坦化层上对应所述漏极的区域形成第一过孔，其中，
在所述薄膜晶体管的上方形成钝化层包括：
在所述薄膜晶体管的上方形成钝化材料薄膜；
对所述钝化材料薄膜进行一次构图工艺，以形成第二过孔，所述第二过孔与所述漏极对应设置且与后序形成的所述第一过孔连通，剩余的钝化材料构成所述钝化层；
在所述平坦化层的上方形成显示电极包括：
在所述平坦化层的上方以及所述第一过孔和所述第二过孔内形成透明导电材料薄膜；
对所述透明导电材料薄膜进行一次构图工艺，以形成所述显示电极的图形，所述显示电极通过所述第一过孔和所述第二过孔与所述漏极连接。
可选地，所述显示基板为OLED基板，所述显示电极为阳极，所述显示基板的制备方法还包括：
在所述平坦化层的上方形成像素界定层，所述像素界定层中形成有若干个容纳孔，并且所述容纳孔与所述显示电极对应设置；
在所述容纳孔内形成有机发光层；
在所述有机发光层的上方形成阴极；以及
在所述阴极的上方设置保护基板。
可选地，所述显示基板为液晶显示基板，所述显示电极为像素电极，所述显示基板的制备方法还包括：
在所述像素电极的上方形成保护层；以及
在所述保护层的上方形成取向层。
可选地，所述显示基板还划分有白色像素区域。
可选地，所述平坦化层位于所述非像素区域中的部分的厚度与所述 平坦化层位于所述彩色像素区域中的部分的厚度的差为：2μm～3μm。
可选地，所述平坦化层位于所述非像素区域中的部分的厚度为3μm～3.5μm；
所述平坦化层位于所述彩色像素区域中的部分的厚度为0～1.5μm。
基于相同的发明构思，本发明的实施例还提供了一种显示基板，所述显示基板被划分为非像素区域和彩色像素区域，并且所述显示基板包括：衬底基板，薄膜晶体管，形成在所述衬底基板上方且位于所述非像素区域内；钝化层，形成在所述薄膜晶体管上方；彩色色阻，形成在所述钝化层上方且位于所述彩色像素区域内；平坦化层，形成在所述钝化层和所述彩色色阻上方，所述平坦化层位于所述彩色像素区域中的部分的厚度小于所述平坦化层位于所述非像素区域中的部分的厚度；以及显示电极，形成在所述平坦化层上方，所述显示电极与所述薄膜晶体管中的漏极通过过孔连接。
可选地，所述显示基板为OLED基板，所述显示电极为阳极；所述显示基板还包括：像素界定层，形成在所述平坦化层上方，所述像素界定层上形成有若干个容纳孔，所述容纳孔与所述显示电极对应设置，所述容纳孔内形成有机发光层，所述有机发光层的上方形成有阴极；以及保护基板，形成在所述阴极上方。
可选地，所述显示基板为液晶显示基板，所述显示电极为像素电极，所述显示基板还包括：保护层，形成在所述像素电极上方；以及取向层，形成在所述保护层上方。
可选地，所述显示基板还划分有白色像素区域。
可选地，所述平坦化层位于所述非像素区域中的部分的厚度与所述平坦化层位于所述彩色像素区域中的部分的厚度的差为：2μm～3μm。
可选地，所述平坦化层位于所述非像素区域中的部分的厚度为3μm～3.5μm；
所述平坦化层位于所述彩色像素区域中的部分的厚度为0～1.5μm。
本发明的实施例具有以下有益效果：
本发明实施例的技术方案通过对位于彩色像素区域中的平坦化层进行减薄处理，使得平坦化层位于彩色色阻上方的部分的膜厚减小，从 而能有效改善平坦化层的平坦性。此外，由于平坦化层位于彩色色阻上方的部分的膜厚减小，可使得显示电极与漏极之间的高度差减小，从而可有效降低显示电极通过过孔与漏极连接时其位于过孔中的部分出现断裂的风险。
附图说明
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：
图1是一种已知的COA显示基板的结构示意图；
图2为本发明实施例一提供的一种显示基板的制备方法的流程图；
图3为采用图2所示制备方法制备出的显示基板的结构示意图；
图4a至图4g为制备图3所示的显示基板的中间结构示意图；
图5为采用半色调掩膜版形成第一过孔和对位于彩色像素区域中的平坦化层进行减薄处理的流程图；
图6为采用半色调掩膜版对平坦化材料薄膜进行图案化处理时的示意图；
图7为本发明实施例二提供的一种显示基板的制备方法的流程图；
图8为采用图7所示制备方法制备出的显示基板的结构示意图；
图9为本发明实施例三提供的一种显示基板的制备方法的流程图；
图10为采用图9所示制备方法制备出的显示基板的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位 置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的显示基板及其制备方法进行详细描述。
图2为本发明实施例一提供的一种显示基板的制备方法的流程图，图3为采用图1所示制备方法制备出的显示基板的结构示意图，图4a至图4g为制备图3所示的显示基板的中间结构示意图。如图2至图4g所示，该显示基板被划分为非像素区域9和彩色像素区域10，其中，非像素区域9是指不进行像素显示的区域，彩色像素区域10是指能够进行彩色像素显示的区域。该显示基板的制备方法包括以下步骤S1-S6。
步骤S1、在衬底基板的上方且对应于非显示区域的区域内形成薄膜晶体管。
如图4a所示，在衬底基板1的上方且对应于非像素区域9的区域内形成薄膜晶体管2。该衬底基板1可以为玻璃基板或树脂材料基板，该薄膜晶体管2可采用已知的任意一种薄膜晶体管2的制备方法制备而成。例如，薄膜晶体管2可包括：栅极、有源层、源极和漏极，其中，栅极和有源层之间设置有栅极绝缘层3。
本领域技术人员应该知晓的是，虽然未示出，但在制备薄膜晶体管2的过程中同时制备出栅线和数据线。
步骤S2、在薄膜晶体管的上方形成钝化层。
如图4b所示，可在薄膜晶体管2和栅极绝缘层3的上方形成钝化材料薄膜41。可选地，钝化材料为氧化硅(化学式SiOx)、氮化硅(化学式SiNx)、氮氧化硅(SiOxNy)中的至少一种。
需要说明的是，在本发明实施例中，可通过沉积、涂敷、溅射等方式来形成薄膜。例如，在步骤S2中，可采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition,简称PECVD)来形成钝化材料薄膜41。
步骤S3、在钝化层的上方且对应于彩色像素区域的区域内形成彩色色阻。
如图4c所示，本实施例中，可选地，彩色像素区域10可包括：红色像素区域、绿色像素区域和蓝色像素区域。彩色色阻12/13/14(又称为彩色滤光片)例如可包括：红色色阻图形12、绿色色阻图形13和蓝色色阻图形14。在步骤S3中，可采用已知任意一种红色色阻图形的制备方法在红色像素区域制备出红色色阻图形12、在绿色像素区域制备出绿色色阻图形13并且在 蓝色色像素区域制备出蓝色色阻图形14。
步骤S4、在钝化层和彩色色阻的上方形成平坦化层。
如图4d和4e所示，例如，可在钝化层4和彩色色阻12/13/14的上方形成平坦化材料薄膜51，并对平坦化材料薄膜51进行图案化以形成第一过孔8。第一过孔8位于薄膜晶体管2的漏极的正上方，剩余的平坦化材料构成平坦化层5。可选地，平坦化材料薄膜51的膜厚可为：3μm～3.5μm。
可选地，平坦化材料为有机树脂材料。可使用预设的掩膜版对平坦化材料薄膜51进行掩膜、曝光处理，再对曝光处理后的平坦化材料薄膜51进行显影处理，以将位于漏极正上方的平坦化材料去除，形成第一过孔8。
本实施例中，可选地，该显示基板除了包括非像素区域9和彩色像素区域10之外，还包括白色像素区域11。白色像素区域11的设置可有效提升显示面板的亮度，降低整体功耗。在本实施例中，可利用填充于空白区域内的平坦化层5作为白色色阻，这样白色色阻的设置不需要增加一次图案化工艺。
在经过步骤S4之后，平坦化层5位于像素区域的部分的上表面高度明显高于位于非像素区域9和位于白色像素区域11的部分的上表面高度，平坦化效果不佳。
步骤S5、减薄平坦化层位于彩色像素区域中的部分的厚度。
如图4f所示，在步骤S5中，通过对平坦化层5位于彩色像素区域10中的部分进行减薄处理以降低平坦化层5的位于像素区域的部分的上表面高度，使得平坦化层5位于彩色像素区域10中的部分的厚度小于非像素区域9中的部分的厚度，此时可有效改善平坦化层5的平坦性。
可选地，经过步骤S5处理后，平坦化层5位于非像素区域9中的部分的厚度与彩色像素区域10中的部分的厚度的差为2μm～3μm。
例如，经过步骤S5处理后，非像素区域9中的平坦化层的厚度可为：3μm～3.5μm，彩色像素区域10中的平坦化层的厚度可为：0～1.5μm。
步骤S6、在平坦化层的上方形成显示电极，并且使显示电极与薄膜晶体管中的漏极通过过孔连接。
如图3和图4g所示，首先，对钝化材料薄膜41进行一次构图工艺，以在第一过孔8的下方形成第二过孔6，剩余的钝化材料构成钝化层4；然后，在平坦化层5的上方以及第一过孔8、第二过孔6内形成透明导电材料薄膜；接着，对透明导电材料薄膜进行一次构图工艺，以形成显示电极7的图形， 并且使显示电极7通过第一过孔8、第二过孔6与漏极连接。需要说明的是，本发明实施例中的一次构图工艺具体可包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等步骤。
由于在步骤S5中对平坦化层5位于彩色像素区域10中的部分进行了减薄处理，即：减小了平坦化层5位于彩色色阻上方的部分的膜厚，从而可使得步骤S6中所形成的显示电极7与漏极之间的高度差减小，进而可有效降低显示电极7通过过孔与漏极连接时其位于过孔中的部分出现断裂的风险。
由上述内容可见，本发明的技术方案可有效改善平坦化层5的平坦性并且降低显示电极7断裂的风险。
需要说明的是，本发明的实施例不限于先在平坦化材料薄膜51上形成第一过孔8、再在钝化材料薄膜41上形成第二过孔6。例如，在其他一些实施例中，也可先在钝化材料薄膜41上形成第二过孔6，再在平坦化材料薄膜51上形成第一过孔8。
例如，在步骤S2中，可先在薄膜晶体管2和栅绝缘层3的上方形成钝化材料薄膜41，然后对钝化材料薄膜41进行一次构图工艺以形成第二过孔6，使得第二过孔6与漏极对应设置且与后序形成的第一过孔8连通，剩余的钝化材料构成钝化层4。此时，在步骤S6中，无需再对钝化材料薄膜41进行处理，可直接形成透明导电材料薄膜并对透明导电材料薄膜进行一次构图工艺即可。此外，本发明的实施例也可通过一次图案化工艺在形成第一过孔8的同时完成对彩色像素区域10中的平坦化层5的减薄处理，即：步骤S4和步骤S5可同步进行。图5为采用半色调掩膜版形成第一过孔和对位于彩色像素区域中的平坦化层进行减薄处理的流程图，图6为采用半色调掩膜版对平坦化材料薄膜进行图案化处理时的示意图，如图5和图6所示，形成平坦化层5的过程可包括以下步骤S401-S403。
步骤S401、在钝化层和彩色色阻的上方形成平坦化材料薄膜。
如图6所示，以平坦化材料为可作为负性光刻胶的有机树脂材料为例子进行示例性说明，平坦化材料薄膜51包括：全保留区域、部分保留区域和不保留区域，半保留区域与彩色像素区域10对应，不保留区域(与漏极对应)与待形成第一过孔8的区域对应。
步骤S402、采用半色调掩膜版对平坦化材料薄膜进行掩膜、曝光处理。
仍如图6所示，半色调掩膜版15包括：完全透光区域15a、部分透光区域15c和不全透光区域15b，完全透光区域15a与全保留区域对应设置，部 分透光区域15c与部分保留区域对应设置，不透光区域15b与不保留区域对应设置。
步骤S403、对曝光处理后的平坦化材料薄膜进行显影处理。
剩余的平坦化材料构成平坦化层5，其中，全保留区域中的平坦化材料全部保留，不保留区域的平坦化材料全部去除以形成第一过孔8，彩色像素区域10中的平坦化材料部分保留以实现减薄。
在本实施例中，采用一次图案化工艺以在形成第一过孔8的同时完成对彩色像素区域10中的平坦化层5的减薄处理，可有效减少工艺处理步骤，缩短显示基板的制备周期。
需要说明的是，本实施例中的平坦化材料也可以是可作为正性光刻胶的有机树脂材料，其也可通过一次图案化工艺形成第一过孔8的同时完成对彩色像素区域10中的平坦化层5的减薄处理。具体过程此处不再赘述。
基于相同的发明构思，本发明的实施例还提供了一种通过上述制备方法制备的显示基板，如图3所示，显示基板被划分为非像素区域9和彩色像素区域10，并且包括：衬底基板1、衬底基板1上方且位于非像素区域9的有薄膜晶体管2、形成在薄膜晶体管2上方的钝化层4、形成在钝化层4上方且位于彩色像素区域10内的彩色色阻12/13/14、形成在钝化层4和彩色色阻12/13/14上方的平坦化层5、形成在平坦化层5上方的显示电极7，其中，平坦化层5位于彩色像素区域10中的部分的厚度小于非像素区域9中的部分的厚度，并且显示电极7与薄膜晶体管5中的漏极通过过孔连接。
可选地，平坦化层5位于非像素区域9中的部分的厚度与位于彩色像素区域10中的部分的厚度的差为2μm～3μm。
可选地，平坦化层位于非像素区域9中的部分的厚度可为：3μm～3.5μm，位于彩色像素区域10中的部分的厚度可为：0～1.5μm。
与已知技术相比，本发明实施例的技术方案通过对平坦化层5位于彩色像素区域10中的部分进行减薄处理，使得彩色像素区域10中部分的厚度小于非像素区域9中的部分的厚度，从而能有效改善平坦化层5的平坦性。此外，由于平坦化层5位于彩色色阻12/13/14上方的部分的膜厚减小，可使得显示电极7与漏极之间的高度差H减小，从而可有效降低显示电极7通过过孔与漏极连接时其位于过孔中的部分出现断裂的风险。
可选地，平坦化层5的材料包括：有机树脂材料。
可选地，显示基板还划分有白色像素区域11。
图7为本发明实施例二提供的一种显示基板的制备方法的流程图，图8为采用图7所示制备方法制备出的显示基板的结构示意图，如图7和图8所示，该显示基板为有机发光二极管(Organic Light-Emitting Diode，简称OELD)基板，显示电极7为阳极。本实施例的该显示基板的制备方法除了包括上述实施例一中的步骤S1～S6之外，还额外包括步骤S7a～S10a，对于步骤S1～S6的描述可参见上述实施例一中的内容，下面仅对步骤S7a～S10a进行示例性描述。
步骤S7a、在平坦化层的上方形成像素界定层。
例如，首先，在平坦化层5上形成像素界定材料薄膜，其中像素界定材料可为透明的有机树脂材料；然后，对像素界定材料薄膜进行图案化处理以形成若干个容纳孔，容纳孔与显示电极7对应设置，剩余的像素界定材料构成像素界定层16。
步骤S8a、在容纳孔内形成有机发光层。
在步骤S8a中，例如可采用喷墨工艺在容纳孔内形成有机发光溶液，并对有机发光溶液进行干燥处理，以形成有机发光层17。在本实施例中，有机发光层17在电压作用下发出白光。
需要说明的是，在实际制备过程中，为保证各容纳孔内有机发光溶液的量的一致性以及后序形成的阴极18的平整度，在进行喷墨工艺时，使整个容纳孔内以及像素界定层16的上表面均存在机发光溶液，再经过干燥处理以使得各容纳孔中均填充满有机发光材料且使像素界定层16的上表面存在一层很薄的有机发光材料。
步骤S9a、在有机发光层的上方形成阴极。
例如，在有机发光层17的上方形成透明导电材料薄膜，该透明导电材料薄膜构成阴极18。
步骤S10a、在阴极的上方设置保护基板。
在步骤S10a中，例如，该保护基板19可以为玻璃基板或树脂材料基板，用于对阴极18进行保护。
需要说明的是，在本实施例中，为提升OLED的发光性能，还可在阳极7和有机发光层17之间形成空穴传输层和电子阻挡层，在阴极18和有机发光层17之间形成电子传输层和空穴阻挡层。基于相同的发明构思，本发明实施例提供了一种通过上述制备方法制备的显示基板。如图8所示，该显示基板为OLED基板，该显示基板不但包括衬底基板1、薄膜晶体管2、钝化 层4、平坦化层5、彩色色阻12/13/14和显示电极7，还包括像素界定层16、有机发光层17和阴极18。
像素界定层16位于平坦化层5的上方，像素界定层16上形成有若干个容纳孔，容纳孔与显示电极7对应设置，有机发光层17位于容纳孔内，阴极18位于有机发光层17的上方。
图9为本发明实施例三提供的一种显示基板的制备方法的流程图，图10为采用图9所示制备方法制备出的显示基板的结构示意图。如图9和图10所示，该显示基板为液晶显示基板(液晶显示面板中的阵列基板)，显示电极7为像素电极。该显示基板的制备方法除了包括上述实施例一中的步骤S1～步骤S6之外，还额外包括步骤S7b和步骤S8b，对于步骤S1～步骤S6的描述可参见上述实施例一中的内容，下面仅对步骤S7b和步骤S8b进行详细描述。
步骤S7b、在像素电极的上方形成保护层。
在平坦化层5上形成保护材料薄膜，其中保护材料可为透明的有机树脂材料，该保护材料薄膜构成保护层20。
步骤S8b、在保护层的上方形成取向层。
首先，在保护层20上形成取向材料薄膜；然后，对取向材料薄膜进行薄膜取向或光控取向处理，以在取向材料薄膜的表面形成预倾角，剩余的取向材料构成取向层21。
基于相同的发明构思，本发明实施例还提供了一种通过上述制备方法制备的显示基板。参见图10所示，该显示基板为液晶显示基板，该显示基板不但包括衬底基板1、薄膜晶体管2、钝化层4、平坦化层5、彩色色阻12/13/14和显示电极7，还包括：保护层20和取向层21。
保护层20位于平坦化层5的上方，取向层21位于保护层20的上方。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。
本申请要求于2016年12月27日提交的名称为“显示面板及其制备方法”的中国专利申请No.201611228190.8的优先权，该申请全文以引用方式合并于本文。

Claims (15)

  1. 一种显示基板的制备方法，所述显示基板划分为非像素区域和彩色像素区域，所述显示基板的制备方法包括：
    在衬底基板的上方且在所述非像素区域内形成薄膜晶体管；
    在所述薄膜晶体管的上方形成钝化层；
    在所述钝化层的上方且在所述彩色像素区域内形成彩色色阻；
    在所述钝化层和所述彩色色阻的上方形成平坦化层；
    减薄所述平坦化层位于所述彩色像素区域中的部分的厚度，以使得所述平坦化层位于所述彩色像素区域中的部分的厚度小于所述平坦化层位于所述非像素区域中的部分的厚度；
    在所述平坦化层的上方形成显示电极，并使所述显示电极与所述薄膜晶体管的漏极通过过孔连接。
  2. 根据权利要求1所述的显示基板的制备方法，其中，在所述钝化层和所述彩色色阻的上方形成平坦化层与所述减薄所述平坦化层位于所述彩色像素区域中的部分的厚度同步进行，
    其中，形成平坦化层包括：
    在所述钝化层和所述彩色色阻的上方形成平坦化材料薄膜，所述平坦化材料薄膜包括：完全保留区域、部分保留区域和不保留区域，所述半保留区域与所述彩色像素区域对应，所述不保留区域与所述漏极的区域对应；
    采用半色调掩膜版对所述平坦化材料薄膜进行掩膜、曝光处理；
    对曝光处理后的所述平坦化材料薄膜进行显影处理以构成所述平坦化层。
  3. 根据权利要求1所述的显示基板的制备方法，还包括：在所述平坦化层上对应所述漏极的区域形成第一过孔其中，
    在所述薄膜晶体管的上方形成钝化层包括：
    在所述薄膜晶体管的上方形成钝化材料薄膜；
    在所述平坦化层的上方形成显示电极包括：
    对所述钝化材料薄膜进行一次构图工艺，以在所述第一过孔的下方形成第二过孔，剩余的钝化材料构成所述钝化层；
    在所述平坦化层的上方以及所述第一过孔和所述第二过孔内形成透明导电材料薄膜；以及
    对所述透明导电材料薄膜进行一次构图工艺，以形成所述显示电极的图形，所述显示电极通过所述第一过孔和所述第二过孔与所述漏极连接。
  4. 根据权利要求1所述的显示基板的制备方法，还包括：在所述平坦化层上对应所述漏极的区域形成第一过孔；
    在所述薄膜晶体管的上方形成钝化层包括：
    在所述薄膜晶体管的上方形成钝化材料薄膜；
    对所述钝化材料薄膜进行一次构图工艺，以形成第二过孔，所述第二过孔与所述漏极对应设置且与后序形成的所述第一过孔连通，剩余的钝化材料构成所述钝化层；
    在所述平坦化层的上方形成显示电极包括：
    在所述平坦化层的上方以及所述第一过孔和所述第二过孔内形成透明导电材料薄膜；以及
    对所述透明导电材料薄膜进行一次构图工艺，以形成所述显示电极的图形，所述显示电极通过所述第一过孔和所述第二过孔与所述漏极连接。
  5. 根据权利要求1所述的显示基板的制备方法，其中所述显示基板为OLED基板，所述显示电极为阳极，所述显示基板的制备方法还包括：
    在所述平坦化层的上方形成像素界定层，所述像素界定层中形成有若干个容纳孔，并且所述容纳孔与所述显示电极对应设置；
    在所述容纳孔内形成有机发光层；
    在所述有机发光层的上方形成阴极；以及
    在所述阴极的上方设置保护基板。
  6. 根据权利要求1所述的显示基板的制备方法，其中所述显示基板为液晶显示基板，所述显示电极为像素电极，所述显示基板的制备方法还包括：
    在所述像素电极的上方形成保护层；以及
    在所述保护层的上方形成取向层。
  7. 根据权利要求1所述的显示基板的制备方法，其中，所述显示基板还划分有白色像素区域。
  8. 根据权利要求1-7中任一所述的显示基板的制备方法，其中，所述平坦化层位于所述非像素区域中的部分的厚度与所述平坦化层位于所述彩色像素区域中的部分的厚度的差为：2μm～3μm。
  9. 根据权利要求1-7中任一所述的显示基板的制备方法，其中，所述平坦化层位于所述非像素区域中的部分的厚度为3μm～3.5μm；
    所述平坦化层位于所述彩色像素区域中的部分的厚度为0～1.5μm。
  10. 一种显示基板，划分有非像素区域和彩色像素区域，
    所述显示基板包括：
    衬底基板，
    薄膜晶体管，形成在所述衬底基板上方且位于所述非像素区域内；
    钝化层，形成在所述薄膜晶体管上方；
    彩色色阻，形成在所述钝化层上方且位于所述彩色像素区域内；
    平坦化层，形成在所述钝化层和所述彩色色阻上方，所述平坦化层位于所述彩色像素区域中的部分的厚度小于所述平坦化层位于所述非像素区域中的部分的厚度；以及
    显示电极，形成在所述平坦化层上方，所述显示电极与所述薄膜晶体管中的漏极通过过孔连接。
  11. 根据权利要求10所述的显示基板，其中所述显示基板为OLED基板，所述显示电极为阳极，
    所述显示基板还包括：
    像素界定层，形成在所述平坦化层上方，所述像素界定层上形成有若干个容纳孔，所述容纳孔与所述显示电极对应设置，所述容纳孔内形成有机发光层，所述有机发光层的上方形成有阴极；以及
    保护基板，形成在所述阴极上方。
  12. 根据权利要求10所述的显示基板，其中所述显示基板为液晶显示基板，所述显示电极为像素电极，
    所述显示基板还包括：
    保护层，形成在所述像素电极上方；以及
    取向层，形成在所述保护层上方。
  13. 根据权利要求10所述的显示基板，其中，所述显示基板还划分有白色像素区域。
  14. 根据权利要求10-13中任一所述的显示基板，其中，所述平坦化层位于所述非像素区域中的部分的厚度与所述平坦化层位于所述彩色像素区域中的部分的厚度的差为：2μm～3μm。
  15. 根据权利要求10-13中任一所述的显示基板，其中，所述平坦化层位于所述非像素区域中的部分的厚度为3μm～3.5μm；
    所述平坦化层位于所述彩色像素区域中的部分的厚度为0～1.5μm。
PCT/CN2017/091417 2016-12-27 2017-07-03 显示基板及其制备方法 Ceased WO2018120730A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/063,924 US11309358B2 (en) 2016-12-27 2017-07-03 Display substrate and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611228190.8A CN106783883B (zh) 2016-12-27 2016-12-27 显示基板及其制备方法
CN201611228190.8 2016-12-27

Publications (1)

Publication Number Publication Date
WO2018120730A1 true WO2018120730A1 (zh) 2018-07-05

Family

ID=58922755

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/091417 Ceased WO2018120730A1 (zh) 2016-12-27 2017-07-03 显示基板及其制备方法

Country Status (3)

Country Link
US (1) US11309358B2 (zh)
CN (1) CN106783883B (zh)
WO (1) WO2018120730A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783883B (zh) * 2016-12-27 2023-11-10 京东方科技集团股份有限公司 显示基板及其制备方法
CN107359188A (zh) * 2017-08-28 2017-11-17 惠科股份有限公司 显示面板及其制造方法
CN207265054U (zh) * 2017-10-24 2018-04-20 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
US11476451B2 (en) * 2019-03-27 2022-10-18 Chengdu Boe Optoelectronics Technology Co., Ltd. Display device and manufacturing method thereof for reducing color cast between view angles
CN110164873B (zh) * 2019-05-30 2021-03-23 京东方科技集团股份有限公司 阵列基板的制作方法、阵列基板、显示面板及显示装置
CN110890409B (zh) * 2019-11-29 2022-11-04 京东方科技集团股份有限公司 显示装置及其oled面板、oled面板的制作方法
CN111045262B (zh) * 2019-12-09 2021-07-06 深圳市华星光电半导体显示技术有限公司 Coa基板及显示面板
CN111740035B (zh) * 2020-07-03 2023-08-22 京东方科技集团股份有限公司 阵列基板、显示面板及制造方法
CN111682057B (zh) * 2020-07-07 2021-09-24 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制备方法
CN111987136B (zh) * 2020-09-09 2022-12-23 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制备方法
CN113054149B (zh) * 2021-03-17 2022-08-09 昆山国显光电有限公司 显示面板的制作方法和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921142A (zh) * 2006-09-11 2007-02-28 友达光电股份有限公司 有机发光显示装置及其制造方法
CN103258793A (zh) * 2013-03-29 2013-08-21 京东方科技集团股份有限公司 一种coa阵列基板的制备方法、阵列基板及显示装置
CN103887440A (zh) * 2012-12-21 2014-06-25 乐金显示有限公司 有机发光二极管显示器及其制造方法
CN105448954A (zh) * 2014-09-23 2016-03-30 三星显示有限公司 包括灰色滤色器的显示装置
US20160178945A1 (en) * 2014-12-17 2016-06-23 Samsung Display Co., Ltd. Thin film display panel and liquid crystal display device including the same
CN106783883A (zh) * 2016-12-27 2017-05-31 京东方科技集团股份有限公司 显示基板及其制备方法
CN206293440U (zh) * 2016-12-27 2017-06-30 京东方科技集团股份有限公司 显示基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484109B1 (ko) * 2002-12-14 2005-04-18 삼성에스디아이 주식회사 기판 제조방법, 이 기판제조방법을 이용한 유기 전계발광표시장치의 제조방법 및 유기 전계 발광 표시장치
CN101783395A (zh) * 2009-01-20 2010-07-21 京东方科技集团股份有限公司 有机电致发光器件及其制造方法
TWI587734B (zh) * 2009-03-26 2017-06-11 精工愛普生股份有限公司 有機ｅｌ裝置、有機ｅｌ裝置之製造方法、及電子機器
CN101887897B (zh) * 2009-05-13 2013-02-13 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
KR101097317B1 (ko) * 2009-11-18 2011-12-21 삼성모바일디스플레이주식회사 유기 발광 디스플레이 장치
KR20120077470A (ko) * 2010-12-30 2012-07-10 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조 방법
US8937307B2 (en) * 2012-08-10 2015-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921142A (zh) * 2006-09-11 2007-02-28 友达光电股份有限公司 有机发光显示装置及其制造方法
CN103887440A (zh) * 2012-12-21 2014-06-25 乐金显示有限公司 有机发光二极管显示器及其制造方法
CN103258793A (zh) * 2013-03-29 2013-08-21 京东方科技集团股份有限公司 一种coa阵列基板的制备方法、阵列基板及显示装置
CN105448954A (zh) * 2014-09-23 2016-03-30 三星显示有限公司 包括灰色滤色器的显示装置
US20160178945A1 (en) * 2014-12-17 2016-06-23 Samsung Display Co., Ltd. Thin film display panel and liquid crystal display device including the same
CN106783883A (zh) * 2016-12-27 2017-05-31 京东方科技集团股份有限公司 显示基板及其制备方法
CN206293440U (zh) * 2016-12-27 2017-06-30 京东方科技集团股份有限公司 显示基板

Also Published As

Publication number Publication date
US20210202583A1 (en) 2021-07-01
CN106783883B (zh) 2023-11-10
US11309358B2 (en) 2022-04-19
CN106783883A (zh) 2017-05-31

Similar Documents

Publication Publication Date Title
WO2018120730A1 (zh) 显示基板及其制备方法
US9722005B2 (en) Light-emitting device, array substrate, display device and manufacturing method of light-emitting device
CN104360557B (zh) 阵列基板及其制造方法，以及显示装置
CN103353683B (zh) 一种阵列基板以及包括该阵列基板的显示装置
CN104576700B (zh) Coa型woled结构及制作方法
US9709864B2 (en) Array substrate and its manufacturing method and display device
US10268082B2 (en) Display panel and method of manufacturing the same, and display device
CN104282729B (zh) 一种有机发光显示面板及其制备方法、显示装置
CN103325732B (zh) 一种coa基板及其制造方法、显示装置
CN108538890A (zh) 一种有机发光显示装置
CN104538428B (zh) Coa型woled结构及制作方法
WO2018227958A1 (zh) 掩膜板模组、膜层的制作方法及有机电致发光显示面板的制作方法
WO2015192517A1 (zh) 彩膜基板及其制备方法、有机发光显示面板和显示装置
WO2018209977A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
US20170170245A1 (en) Organic light emitting diode display and method for manufacturing the same
WO2015180381A1 (zh) 一种有机电致发光显示面板及显示装置
WO2018120691A1 (zh) 阵列基板及其制造方法、显示装置
CN105093667A (zh) 一种阵列基板及其制作方法、显示装置
WO2016150286A1 (zh) 阵列基板及其制备方法、显示装置
KR20160078608A (ko) 유기발광 표시장치 및 이를 제조하는 방법
WO2020228425A1 (zh) 阵列基板及其制造方法、显示面板、显示装置
WO2014015617A1 (zh) 阵列基板及显示装置
US11569307B2 (en) Array substrate, manufacturing method thereof, display panel and display device
WO2020177666A1 (zh) 像素单元及其制造方法、显示基板
US9799683B2 (en) Array substrate, preparation method thereof and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17888532

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17888532

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09.12.2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17888532

Country of ref document: EP

Kind code of ref document: A1