WO2018112952A1 - Procédé de fabrication de substrat de réseau - Google Patents

Procédé de fabrication de substrat de réseau Download PDF

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Publication number
WO2018112952A1
WO2018112952A1 PCT/CN2016/111870 CN2016111870W WO2018112952A1 WO 2018112952 A1 WO2018112952 A1 WO 2018112952A1 CN 2016111870 W CN2016111870 W CN 2016111870W WO 2018112952 A1 WO2018112952 A1 WO 2018112952A1
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WO
WIPO (PCT)
Prior art keywords
area
region
defining
photoresist layer
hole
Prior art date
Application number
PCT/CN2016/111870
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English (en)
Chinese (zh)
Inventor
何家伟
Original Assignee
深圳市柔宇科技有限公司
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Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2016/111870 priority Critical patent/WO2018112952A1/fr
Priority to CN201680049260.5A priority patent/CN108140646A/zh
Publication of WO2018112952A1 publication Critical patent/WO2018112952A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.
  • the electrode layer of the array substrate needs to be connected to the source/drain of the display region and the metal trace layer of the peripheral region, and the circuit is turned on by connecting the metal, so the insulating layer in the display region needs to be dried.
  • the hole can be connected by etching.
  • the existing dry etching method can use the physical vertical bombardment method and the photoresist back-off method; since the source/drain opening has one less active layer than the hole where the gate is located, the display area is completed when the hole of the wiring area is completed.
  • the source/drain metal layer has been bombarded excessively causing damage.
  • the present application provides a method for fabricating an array substrate, which reduces damage to the source and drain of the display region due to etching.
  • the present invention provides a method for fabricating an array substrate, comprising: providing a substrate having a display region and a trace region; wherein the display region forms a source and a drain, and the trace region is formed with a peripheral bridge metal line;
  • Patterning the photoresist layer by a halftone mask forming a first via defining region in the display region and a second hole defining region in the routing region on the photoresist layer; a thickness of the via defining region to the insulating layer is greater than a thickness of the second via defining region to the insulating layer;
  • the step of patterning the photoresist layer by a halftone mask, forming a first via defining region in the display region and a second hole definition in the trace region on the photoresist layer District including:
  • the halftone mask including a light shielding area, a full transmission area, and a semi-permeable area
  • the halftone mask is removed and the first via defining region and the second via defining region are formed on the photoresist layer by development.
  • the second hole defining region exposes the insulating layer.
  • the step of etching the first via defining area and the second hole defining area is performed by physical vertical bombardment to simultaneously dry the first via defining area and the second hole defining area.
  • the display region is formed with a gate and a semiconductor layer connected to the source and the drain, and the peripheral bridge metal line of the trace region is formed in the same layer as the gate and simultaneously formed.
  • the method includes forming a pixel electrode layer on the insulating layer formed with the first via and the second via, the pixel electrode layer being connected to the source or the drain through the first via, passing A second via is connected to the peripheral bridge metal line.
  • the step etches the first via defining region and the second hole defining region, and the etching time is the same.
  • the thickness of the photoresist layer is 2.0 ⁇ m.
  • a first via region and a second via region are first defined by using a halftone mask, and thicknesses of the first via region and the second via region to the insulating layer are different.
  • the first via and the second via are simultaneously etched, so that the source or the drain is not damaged by the etching process.
  • 1 is a flow chart of a method of manufacturing an array substrate of the present application.
  • FIG. 2 to FIG. 6 are schematic cross-sectional views of a substrate of each step of the method for fabricating an array substrate of the present application.
  • the present application provides an array substrate manufacturing method for manufacturing an OLED. (Organic Light-Emitting Diode) array substrate of the display, comprising:
  • Step S1 providing a substrate 10 having a display area A and a wiring area P; wherein the display area A forms a source electrode 15 and a drain electrode 16, and the wiring line area P is formed with a peripheral bridge metal line 20.
  • the substrate 10 is a glass substrate.
  • a semiconductor layer 17 is formed on the substrate 10 in the display area A, and a semiconductor layer 17 is connected to the source 15 and the drain 16.
  • the peripheral bridge metal line 20 of the routing area P is located on the same layer as the gate 14. And formed at the same time.
  • the gate electrode 14 and the peripheral bridge metal line 20 are covered with a gate insulating layer 141, and the semiconductor layer 17 is formed on the gate insulating layer 141 at a position opposite to the gate electrode 14.
  • the gate electrode 14 , the source electrode 15 , the drain electrode 16 , the semiconductor layer 17 , and the peripheral bridge metal line 20 are formed by a patterning process such as photomask development etching, and are not described herein.
  • an insulating layer 12 and a layer of the insulating layer 12 are formed on the peripheral 15 and the drain 16 of the display area A and the P-shaped peripheral bridge metal line 20.
  • Photoresist layer 13 is 2.0 ⁇ m, which is moderate in thickness, and is convenient for performing a halftone mask mask pattern process.
  • step S3 the photoresist layer 13 is patterned by a halftone mask 30, and a first via defining region 131 located in the display area A is formed on the photoresist layer 13 and located at the The second hole defining region 132 of the routing region P; wherein the thickness of the first via defining region 131 to the insulating layer is greater than the thickness of the second via defining region 132 to the insulating layer 12.
  • a first via defining region 131 located in the display area A is formed on the photoresist layer 13 and located at the The second hole defining region 132 of the routing region P; wherein the thickness of the first via defining region 131 to the insulating layer is greater than the thickness of the second via defining region 132 to the insulating layer 12.
  • the halftone mask 30 including the light shielding area 31, the full transmission area 32, and the semi-permeable area 33 is provided.
  • the halftone mask 30 is illuminated, and the first via defining region pattern is formed on the photoresist layer 13 at a position corresponding to the semipermeable region 33, and the position corresponding to the full transparent region 32 forms the first Two-hole definition area pattern;
  • the first via defining region 131 and the second via defining region 132 are formed on the photoresist layer 13 by removing the halftone mask. Thus, the photoresist layer of the first via defining region is not completely removed and the portion covering the source or the drain is left.
  • the second hole defining region 132 exposes the insulating layer 12.
  • the second hole defining region 132 and the insulating layer 12 may also protect the photoresist layer portion as long as the photoresist layer of the first via region can protect the source and the drain during etching. Extremely.
  • step S4 the first via defining region 131 and the second via defining region 132 are etched to form a first via 133 connected to the source 15 or the drain 16 and the periphery.
  • the second via 134 connected to the metal line 20 is bridged.
  • etching mainly refers to dry etching, and specifically adopts a pass.
  • the first via defining region 131 and the second via defining region 132 are simultaneously dry-etched by the vertical bombardment method, and the first via 133 penetrating the insulating layer 12 is formed and penetrates through the insulating layer at the same time. 12 and a second via 134 of the gate insulating layer 141.
  • the physical vertical bombardment method the voltage between the upper and lower electrodes is increased, so that the particles are subjected to a large force in the electric field to obtain a large kinetic energy to vertically bombard the substrate.
  • the physical bombardment method may have a gate insulating layer at the source or the drain opening than the peripheral bridge metal line, so that when the second via hole of the trace P is played, the display area is A via position has caused damage to the metal layer of the source or the drain, and the photoresist back-off method of the prior art etches the photoresist so that the size of the connected pixel electrode and the source/drain are relatively large, in order to To ensure contact with the source and drain, the area of the source and drain will also increase the area, thus affecting the transmittance.
  • a first via and a second via region are first defined by using a halftone mask, and the first via region does not penetrate the photoresist layer, so during the etching process. a portion of the first via hole that does not penetrate the photoresist layer serves as a blocking portion.
  • the second via hole 134 penetrates the insulating layer 12 and the gate insulating layer 141, the first via hole 133 just penetrates the first via hole. The remaining occlusion portion of the region and the insulating layer expose the source or the drain, so that the source or the drain is not damaged by the etching process. At the same time, the reduction of the aperture ratio by the photoresist back-off method is avoided.
  • step S5 the photoresist layer 13 is removed.
  • Step S6 forming a pixel electrode layer 18 on the insulating layer 13 formed with the first via hole 133 and the second via hole 134, the pixel electrode layer 18 passing through the first via hole 133 and the source 15 or the drain
  • the pole 16 is connected to the peripheral bridge wire 20 via a second via 134.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un procédé de fabrication de substrat de réseau, comprenant les étapes consistant à : fournir un substrat sur lequel une zone d'affichage et une zone de fil sont formées, une source et un drain étant formés dans la zone d'affichage et un fil métallique de pontage périphérique étant formé dans la zone de fil ; former, sur la source et le drain de la zone d'affichage et le fil métallique de pontage périphérique de la zone de fil, une couche isolante et une couche de résine photosensible empilée sur la couche isolante ; former des motifs sur la couche de résine photosensible au moyen d'un masque de demi-tons et former, sur la couche de résine photosensible, une première zone de définition de trou d'interconnexion située dans la zone d'affichage et une deuxième zone de définition de trou d'interconnexion située dans la zone de fil, l'épaisseur entre la première zone de définition de trou d'interconnexion et la couche isolante étant supérieure à l'épaisseur entre la deuxième zone de définition de trou d'interconnexion et la couche isolante ; graver la première zone de définition de trou d'interconnexion et la deuxième zone de définition de trou d'interconnexion afin de former un premier trou d'interconnexion relié à la source ou au drain et un deuxième trou d'interconnexion relié au fil métallique de pontage périphérique ; et éliminer la couche de résine photosensible.
PCT/CN2016/111870 2016-12-24 2016-12-24 Procédé de fabrication de substrat de réseau WO2018112952A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2016/111870 WO2018112952A1 (fr) 2016-12-24 2016-12-24 Procédé de fabrication de substrat de réseau
CN201680049260.5A CN108140646A (zh) 2016-12-24 2016-12-24 阵列基板制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/111870 WO2018112952A1 (fr) 2016-12-24 2016-12-24 Procédé de fabrication de substrat de réseau

Publications (1)

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WO2018112952A1 true WO2018112952A1 (fr) 2018-06-28

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Cited By (1)

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CN113192426A (zh) * 2021-04-27 2021-07-30 Oppo广东移动通信有限公司 显示面板、显示模组及电子设备

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CN109166868B (zh) * 2018-09-03 2020-08-11 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN111769044A (zh) * 2020-05-27 2020-10-13 英诺赛科（珠海）科技有限公司 高电子迁移率晶体管及其制造方法

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CN101330062A (zh) * 2008-07-25 2008-12-24 友达光电股份有限公司 薄膜晶体管阵列基板的制作方法
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WO2015043268A1 (fr) * 2013-09-26 2015-04-02 京东方科技集团股份有限公司 Substrat de matrice, son procédé de fabrication et appareil d'affichage
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192426A (zh) * 2021-04-27 2021-07-30 Oppo广东移动通信有限公司 显示面板、显示模组及电子设备
CN113192426B (zh) * 2021-04-27 2023-08-25 Oppo广东移动通信有限公司 显示面板、显示模组及电子设备

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