WO2018109862A1 - Circuit d'amplification de puissance - Google Patents

Circuit d'amplification de puissance Download PDF

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Publication number
WO2018109862A1
WO2018109862A1 PCT/JP2016/087201 JP2016087201W WO2018109862A1 WO 2018109862 A1 WO2018109862 A1 WO 2018109862A1 JP 2016087201 W JP2016087201 W JP 2016087201W WO 2018109862 A1 WO2018109862 A1 WO 2018109862A1
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WO
WIPO (PCT)
Prior art keywords
signal
digital
distortion compensation
power amplifier
power
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PCT/JP2016/087201
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English (en)
Japanese (ja)
Inventor
安藤　暢彦
田島　賢一
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三菱電機株式会社
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Priority to PCT/JP2016/087201 priority Critical patent/WO2018109862A1/fr
Priority to JP2018538910A priority patent/JPWO2018109862A1/ja
Publication of WO2018109862A1 publication Critical patent/WO2018109862A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • the present invention relates to a circuit that compensates for nonlinear input / output characteristics (hereinafter referred to as “nonlinear characteristics” or “distortion characteristics”) of a power amplifier, and more particularly, a circuit that compensates for nonlinear characteristics of a power amplifier used in a radio communication technology. It is about.
  • a power amplifier which is a component of a wireless communication device, has a function of amplifying the power of a transmission signal and outputting it to an antenna element.
  • this type of power amplifier operates in a region exhibiting nonlinear characteristics, its power efficiency (hereinafter also simply referred to as “efficiency”) increases, but distortion components are added to the transmission signal due to the nonlinear characteristics of the power amplifier. Therefore, there is a problem that the signal quality deteriorates. Therefore, a distortion compensation technique for compensating for the distortion component generated in the power amplifier is widely adopted.
  • a power amplifier circuit having a Cartesian feedback loop includes an analog adder that adds an in-phase component (I component) and a quadrature component (Q component) of an input baseband signal to an in-phase component and a quadrature component of an analog feedback signal, respectively.
  • I component in-phase component
  • Q component quadrature component
  • a quadrature modulator that quadrature modulates the output of the analog adder to generate a modulation signal, a power amplifier that amplifies the power of the modulation signal, and a part of the signal extracted from the output signal of the power amplifier in analog feedback
  • a feedback path for negative feedback as a signal and a quadrature demodulator for quadrature demodulating the analog feedback signal to generate an in-phase component and a quadrature component of the analog feedback signal are provided.
  • an analog adder, a quadrature modulator, a power amplifier, a feedback path, and a quadrature demodulator constitute a loop circuit.
  • the analog adder adds the in-phase component and the quadrature component of the analog feedback signal to the in-phase component and the quadrature component of the input baseband signal, respectively. It is possible to compensate for the non-linear characteristics.
  • a power amplifier circuit having such a Cartesian feedback loop is disclosed in, for example, Patent Document 1 (International Publication No. 2014/112382).
  • DPD Digital Pre-Distorter
  • LUT Look Up Table
  • polynomials to prepare or calculate in advance a compensation characteristic that approximately represents the inverse characteristic that compensates for the nonlinear characteristic of the power amplifier. This is a circuit for correcting an input signal to be applied.
  • Patent Document 2 Japanese Patent Laid-Open No. 2010-28766.
  • the loop circuit is configured to cancel the distortion component generated in the power amplifier, and a high distortion compensation effect can be obtained.
  • the high distortion compensation effect is limited to a case where the frequency band is narrow. That is, if the signal delay time in the loop circuit becomes longer due to factors such as group delay generated in the power amplifier, unstable operation such as oscillation occurs in a high frequency region. In order to avoid such unstable operation, the frequency band (hereinafter also referred to as “distortion compensation band”) that can compensate for the nonlinear characteristics of the power amplifier must be narrowed. It is difficult to apply a feedback loop to a wideband signal.
  • the approximation accuracy of the compensation characteristic realized using the LUT or the polynomial may not be sufficient. In this case, a high distortion compensation effect cannot be obtained.
  • an object of the present invention is to provide a power amplifier circuit capable of widening a distortion compensation band while ensuring a high distortion compensation effect.
  • a power amplifier circuit includes a distortion compensation circuit that performs digital signal processing for distortion compensation on a digital input signal, and a DA conversion that converts a digital output of the distortion compensation circuit into an analog transmission signal in a specific frequency band.
  • a frequency converter that converts the analog transmission signal into a high-frequency transmission signal, and a power amplifier that amplifies the power of the high-frequency transmission signal, wherein the distortion compensation circuit receives a distortion compensation signal as an input, and the digital input
  • a digital subtractor that subtracts the distortion compensation signal from the signal to generate a digital transmission signal; and a digital input / output characteristic that models the input / output characteristic of the power amplifier, and the digital input / output characteristic is based on the digital input / output characteristic.
  • An estimation amplifier that amplifies the transmission signal and an output of the estimation amplifier are attenuated to generate an attenuation signal. Characterized in that it comprises a damping device which gives a signal to the digital subtractor as said distortion compensation signal.
  • the distortion compensation circuit can compensate the nonlinear characteristic of the power amplifier by performing digital signal processing on the digital input signal. If the operation speed of the distortion compensation circuit is increased, a low-delay loop circuit unit that has been difficult to realize with conventional analog signal processing can be configured. Therefore, a distortion compensation band is ensured while ensuring a high distortion compensation effect. Can be realized.
  • FIG. 6 is a diagram illustrating a first configuration example of a set of an estimation amplifier and a loop control unit according to Embodiment 1.
  • FIG. 6 It is a figure which shows an example of the content of the lookup table shown by FIG. 6 is a diagram illustrating a second configuration example of a set of an estimation amplifier and a loop control unit in Embodiment 1.
  • FIG. It is a figure which shows schematically the structure of the power amplifier circuit of Embodiment 2 which concerns on this invention.
  • FIG. 1 is a diagram schematically showing a configuration of a power amplifier circuit 1 according to a first embodiment of the present invention.
  • the power amplifier circuit 1 includes a digital processing unit 2 that operates in synchronization with an operation clock group supplied from a clock generator (not shown), and an output from the digital processing unit 2. It has been digitally converts the digital transmission signal X into an analog transmission signal Xa in a specific frequency band Omega b - analog (DA) converter 4A (.
  • DA Omega b - analog
  • DAC4A digital signal processing unit 3
  • ADC4D analog signal processing unit 4D
  • the digital processing unit 2 outputs a data signal S as an original signal, and the digital transmission signal X by using the data signal S as a digital input signal and subjecting the data signal S to digital signal processing for distortion compensation. And a distortion compensation circuit 11 for generating.
  • the digital transmission signal X is output to the DAC 4A.
  • Each of the data signal S and the digital transmission signal X is a digital signal having an in-phase component (I component) and a quadrature component (Q component).
  • the DAC 4A converts the digital transmission signal X having an I component and a Q component into an analog transmission signal Xa composed of an in-phase signal (I signal) and a quadrature signal (Q signal).
  • the signal generation unit 10 and the distortion compensation circuit 11 may be configured by a semiconductor integrated circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).
  • the analog processing unit 3 a frequency converter 51 for converting an analog transmission signal Xa to the high frequency transmission signal Xr radio frequency Omega r of millimeter-wave band, a power amplifier 52 for amplifying the electric power of the high frequency transmission signal Xr , a portion of the output of the power amplifier 52 is branched high-frequency feedback signal to the branch section 53 for generating a Yr, high-frequency feedback signal frequency inverse conversion unit 54 which converts Yr to analog feedback signal Ya of the particular frequency band Omega b And an output terminal 55 for outputting the high-frequency transmission signal amplified by the power amplifier 52 to the outside.
  • the branching unit 53 can be configured by, for example, a known directional coupler.
  • the frequency conversion unit 51 uses a local oscillation signal supplied from a local oscillation source (not shown) to orthogonally modulate an analog transmission signal Xa composed of two systems of I and Q signals to produce one system. What is necessary is just to be comprised by the analog modulator which produces
  • the frequency inverse converter 54 orthogonally demodulates one system of high-frequency feedback signal Yr using a local oscillation signal supplied from a local oscillation source (not shown), and performs two systems of I signal and Q signal. What is necessary is just to be comprised by the analog demodulator which produces
  • the ADC 4D can convert an analog feedback signal Ya composed of an I signal and a Q signal into a digital feedback signal Y having an I component and a Q component.
  • the distortion compensation circuit 11 has a function of compensating for nonlinear characteristics (distortion characteristics) of the power amplifier 52. That is, the distortion compensation circuit 11 can compensate each distortion of the AM-AM characteristic and the AM-PM characteristic of the power amplifier 52.
  • the AM-AM characteristic is an input / output characteristic indicating the correspondence between the input power (input amplitude) and the output power (output amplitude) of the power amplifier 52
  • the AM-PM characteristic is the input power ( This is an input / output characteristic indicating a correspondence relationship between (input amplitude) and output phase.
  • the AM-AM characteristic is linear, but if the input power is large, the AM-AM characteristic tends to be nonlinear.
  • the phase of the output waveform is constant without depending on the input power.
  • the phase of the output waveform changes and distortion occurs in the AM-PM characteristics.
  • the distortion compensation circuit 11 includes a loop circuit unit 13 and a loop control unit 15, and the loop circuit unit 13 includes a digital subtracter 21, an estimation amplifier 22, and an attenuator 23. .
  • the digital subtractor 21 generates a digital transmission signal X by subtracting the distortion compensation signal supplied from the attenuator 23 from the original signal S.
  • the digital transmission signal X is supplied to the estimation amplifier 22, the loop control unit 15, and the DAC 4A.
  • the estimation amplifier 22 has a digital input / output characteristic that models the input / output characteristic of the power amplifier 52, and a digital transmission signal X is generated by amplifying the digital transmission signal X based on the digital input / output characteristic.
  • the attenuator 23 attenuates the power of the digital amplified signal Z to generate an attenuated signal, and outputs this attenuated signal to the digital subtractor 21 as a distortion compensation signal.
  • Each of the original signal S, the digital transmission signal X, the digital amplification signal Z, and the attenuation signal is a digital signal having an I component and a Q component which are orthogonal (cartesian) components. Therefore, the loop circuit unit 13 constitutes a Cartesian loop circuit.
  • the digital amplification signal Z is expressed by the following equation (1).
  • N is a distortion signal component generated in the estimation amplifier 22.
  • the digital amplification signal Z is approximately expressed by the following equation (2).
  • the operation speed of the loop circuit unit 13 depends on an operation clock group given to the digital processing unit 2. For this reason, the delay time of the signal in the loop circuit unit 13 is shortened by setting the frequency of the operation clock group to a high frequency. If the delay time is shortened, an unstable operation such as oscillation is prevented from occurring in a high frequency region, so that the bandwidth of the loop circuit unit 13 can be increased. As a result, the loop circuit unit Thus, it is possible to realize the widening of the distortion compensation band by 13.
  • the loop control unit 15 has a function of variably controlling the digital input / output characteristics of the estimation amplifier 22 in accordance with changes in the input / output characteristics of the power amplifier 52 based on the digital transmission signal X and the digital feedback signal Y.
  • FIG. 2 is a diagram illustrating a first configuration example of a set of the estimation amplifier 22 and the loop control unit 15 according to the first embodiment.
  • the estimation amplifier 22 includes a characteristic acquisition unit 31, a lookup table (LUT) 32, and a digital multiplier 33.
  • the LUT 32 is a storage area of a memory that stores a plurality of combinations of a value indicating the instantaneous power of the digital transmission signal X and a characteristic value indicating the digital input / output characteristic of the estimation amplifier 22.
  • the characteristic acquisition unit 31 calculates the instantaneous power of the digital transmission signal X, acquires a characteristic value G corresponding to the calculated instantaneous power, and gives this characteristic value G to the digital multiplier 33.
  • the digital multiplier 33 can generate the digital amplified signal Z by multiplying the digital transmission signal X by the characteristic value G.
  • the characteristic acquisition unit 31 and the digital multiplier 33 constitute the multiplication processing unit of the present embodiment.
  • the loop control unit 15 shown in FIG. 2 includes a table update unit 15U that updates the combinations stored in the LUT 32 based on the digital transmission signal X and the digital feedback signal Y.
  • n is an integer
  • time t n by the complex signal value of the digital transmission signal X in the x (n)
  • digital at time t n When the instantaneous power of the transmission signal X is p (n), the digital input / output characteristics of the estimation amplifier 22 can be expressed by the following equation (3) using the function f ⁇ .
  • the table updating unit 15U includes the latest N complex signal values x (1) to x (N) (N is a positive integer greater than or equal to 2) and N complex signal values y (1) corresponding thereto.
  • N is a positive integer greater than or equal to 2
  • N complex signal values y (1) corresponding thereto.
  • To y (N) to calculate characteristic values x (1) / y (1),..., X (N) / y (N), and these characteristic values x (1) / y (1 ,..., X (N) / y (N) are rearranged in the order of the magnitude of the instantaneous powers p (1) to p (N), so that the stored contents of the LUT 32 can be generated.
  • FIG. 3 is a diagram showing an example of the stored contents of the LUT 32 shown in FIG.
  • the table update unit 15U can update the stored contents of the LUT 32 at predetermined time intervals.
  • instantaneous power is used, but the present invention is not limited to this.
  • the instantaneous amplitude of the digital transmission signal X may be used instead of the instantaneous power.
  • FIG. 4 is a diagram illustrating a second configuration example of the set of the estimation amplifier 22 and the loop control unit 15 according to the first embodiment.
  • the estimation amplifier 22 includes a polynomial calculation unit 35 and a coefficient storage unit 36.
  • the polynomial calculator 35 has a function of calculating a polynomial value that determines the digital input / output characteristics of the estimation amplifier 22.
  • a known memory polynomial can be used as this kind of polynomial.
  • the memory polynomial is given by the following equations (4) and (5), for example.
  • m is an integer in the range of 0 to M ⁇ 1 (M is an integer of 2 or more), and M represents the depth of the memory.
  • k is an integer in the range of 0 to K-1 (K is an integer of 2 or more), and represents the order of the memory polynomial.
  • w m, k are coefficients for uniquely determining the digital input / output characteristics modeling the input / output characteristics of the power amplifier 52.
  • the coefficient storage unit 36 is a storage area of a memory that stores the values of the coefficient group ⁇ w m, k ⁇ .
  • the above equation (4) can be expressed using a matrix and a vector. That is, the following equation (6) can be derived from the above equations (4) and (5).
  • ⁇ and W are vectors, respectively, and ⁇ is a matrix.
  • the vectors ⁇ and W and the matrix ⁇ are determined by the following equations (7), (8), and (9).
  • the symbol T in the equations (7) and (9) represents transposition. Therefore, the vector ⁇ is a vector of N + 1 rows obtained by transposing a vector of N + 1 columns.
  • the vector W having the coefficients w m, k can be calculated according to the following equation (10).
  • ⁇ H represents an adjoint matrix (adjoint matrix) for the matrix ⁇ .
  • the loop control unit 15 includes a coefficient estimation unit 15M that estimates the coefficient group ⁇ w m, k ⁇ by executing the calculation according to the above equation (10) based on the digital transmission signal X and the digital feedback signal Y. Since the loop control unit 15 performs distortion compensation using the memory polynomial, it is possible to compensate not only the distortion characteristics of the power amplifier 52 but also the memory effect of the power amplifier 52.
  • the distortion compensation circuit 11 can compensate the nonlinear characteristic of the power amplifier 52 by performing digital signal processing on the data signal S. If the operation speed of the distortion compensation circuit 11 is increased, a low-delay loop circuit unit 13 that is difficult to realize by conventional analog signal processing can be configured. Therefore, distortion can be achieved while ensuring a high distortion compensation effect. A wider compensation band can be realized.
  • the estimation amplifier 22 has digital input / output characteristics that model the input / output characteristics of the power amplifier 52.
  • the loop control unit 15 can variably control the digital input / output characteristics of the estimation amplifier 22 based on the digital transmission signal X and the digital feedback signal Y. For this reason, even when the input / output characteristics of the power amplifier 52 change due to factors such as temperature or aging, the loop control unit 15 changes the digital input / output characteristics of the estimation amplifier 22 in accordance with the change of the input / output characteristics. Thus, a high distortion compensation effect can be obtained.
  • FIG. 5 is a diagram schematically showing a configuration of a power amplifier circuit 1A according to the second embodiment of the present invention.
  • the power amplifier circuit 1A includes a digital processing unit 2A that operates in synchronization with an operation clock group supplied from a clock generator (not shown), and an output from the digital processing unit 2A. and DAC4A converting a digital transmission signal X, which is an analog transmission signal Xa in a specific frequency band Omega b, an analog processing unit 3 for performing analog signal processing on the analog transmission signal Xa, amplified supplied from the analog processing unit 3 An output terminal 55 that outputs a signal to the outside and an ADC 4D that converts the analog feedback signal Ya fed back from the analog processing unit 3 into a digital feedback signal Y are provided.
  • the digital processing unit 2A has a signal generation unit 10 that outputs the data signal S as an original signal, and uses the data signal S as a digital input signal.
  • the configuration of the power amplifying circuit 1A of the present embodiment is the same as that of the power amplifying circuit 1 of the first embodiment except that the distortion compensating circuit 11A of FIG. 5 is provided instead of the distortion compensating circuit 11 of the first embodiment. Is the same.
  • the distortion compensation circuit 11 ⁇ / b> A of this embodiment includes an up sampler 12, a loop circuit unit 13, a down sampler 14, and a loop control unit 15.
  • the configuration of the distortion compensation circuit 11A is the same as the configuration of the distortion compensation circuit 11 of the first embodiment except that the up-sampler 12 and the down-sampler 14 are provided to shorten the delay time of the loop circuit unit 13. .
  • the up-sampler 12 applies a digital signal having a sampling rate f h higher than the sampling rate f s by performing an up-sampling process (first sampling rate conversion) on the data signal S having a predetermined sampling rate f s. It has a function of generating a signal and outputting this digital input signal to the loop circuit unit 13.
  • the upsampling process can be realized by, for example, an interpolation that inserts a zero value between data values of the data signal S and a low-pass filter.
  • the downsampler 14 performs a downsampling process (second sampling rate conversion) on the output of the digital subtractor 21 to generate a digital transmission signal X having a sampling rate f s , and this digital transmission signal X is It has a function of outputting to the DAC 4A.
  • a downsampling process for example, decimation that thins out the data values of the output of the digital subtractor 21 every L (L is an integer of 2 or more) may be executed.
  • the distortion compensation circuit 11A can increase the operation speed of the loop circuit unit 13 and shorten the delay time of the loop circuit unit 13.
  • the width can be widened, and a high compensation effect can be obtained even for a wideband transmission signal.
  • the power amplifier circuit according to the present invention can improve the non-linear characteristics of the power amplifier, and thus can be suitably used, for example, in wireless communication technology.
  • 1,1A power amplification circuit 1,2A digital processing unit, 3 analog processing unit, 4A DA converter (DAC), 4D AD converter (ADC), 10 signal generation unit, 11, 11A distortion compensation circuit, 12 upsampler , 13 loop circuit section, 14 downsampler, 15 loop control section, 15U table update section, 15M coefficient estimation section, 21 digital subtractor, 22 estimation amplifier, 23 attenuator, 31 characteristic acquisition section, 32 lookup table (LUT) 33, digital multiplier, 35 polynomial arithmetic unit, 36 coefficient storage unit, 51 frequency conversion unit, 52 power amplifier, 53 branching unit, 54 frequency inverse conversion unit, 55 output terminal.
  • DAC DA converter
  • ADC 4D AD converter

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un circuit d'amplification de puissance (1) comprenant : un circuit de compensation de distorsion (11) pour exécuter un traitement de signal numérique sur un signal d'entrée numérique (S); une unité de conversion de fréquence (51) pour convertir un signal de transmission analogique (Xa) en un signal de transmission haute fréquence (Xr); et un amplificateur de puissance (52) pour amplifier la puissance du signal de transmission haute fréquence (Xr). Le circuit de compensation de distorsion (11) comprend : un soustracteur numérique (21) qui soustrait un signal de compensation de distorsion du signal d'entrée numérique (S) et génère un signal de transmission numérique (X); un amplificateur d'estimation (22) qui amplifie le signal de transmission numérique (X); et un atténuateur (23) qui atténue une sortie (Z) de l'amplificateur d'estimation et génère un signal d'atténuation, et fournit ce signal d'atténuation au soustracteur numérique (21) en tant que signal de compensation de distorsion.
PCT/JP2016/087201 2016-12-14 2016-12-14 Circuit d'amplification de puissance WO2018109862A1 (fr)

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PCT/JP2016/087201 WO2018109862A1 (fr) 2016-12-14 2016-12-14 Circuit d'amplification de puissance
JP2018538910A JPWO2018109862A1 (ja) 2016-12-14 2016-12-14 電力増幅回路

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270306A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd カルテシアン帰還型非線形歪補償器
JP2004320329A (ja) * 2003-04-15 2004-11-11 Nec Corp デジタルフィードバック方式の歪み補償回路
JP2013106330A (ja) * 2011-11-16 2013-05-30 Fujitsu Ltd 狭帯域のフィードバック経路を有する適応的リニアライザ
JP2014158230A (ja) * 2013-02-18 2014-08-28 Ntt Docomo Inc ディジタルプリディストータとその制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5004823B2 (ja) * 2008-02-21 2012-08-22 三菱電機株式会社 送信装置
US9484962B1 (en) * 2015-06-05 2016-11-01 Infineon Technologies Ag Device and method for adaptive digital pre-distortion

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270306A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd カルテシアン帰還型非線形歪補償器
JP2004320329A (ja) * 2003-04-15 2004-11-11 Nec Corp デジタルフィードバック方式の歪み補償回路
JP2013106330A (ja) * 2011-11-16 2013-05-30 Fujitsu Ltd 狭帯域のフィードバック経路を有する適応的リニアライザ
JP2014158230A (ja) * 2013-02-18 2014-08-28 Ntt Docomo Inc ディジタルプリディストータとその制御方法

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