WO2018103330A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2018103330A1
WO2018103330A1 PCT/CN2017/092174 CN2017092174W WO2018103330A1 WO 2018103330 A1 WO2018103330 A1 WO 2018103330A1 CN 2017092174 W CN2017092174 W CN 2017092174W WO 2018103330 A1 WO2018103330 A1 WO 2018103330A1
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Prior art keywords
pixel
disposed
array substrate
adjacent
sub
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PCT/CN2017/092174
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English (en)
French (fr)
Inventor
龙春平
李盼
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/746,687 priority Critical patent/US10510780B2/en
Priority to EP17828829.6A priority patent/EP3553598A4/en
Publication of WO2018103330A1 publication Critical patent/WO2018103330A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to the field of liquid crystal display, and in particular to an array substrate and a display device.
  • Embodiments of the present disclosure provide an array substrate and a display device thereof, which can improve the display performance degradation caused by the electric field disorder at the edge of the pixel of the display device of the conventional planar conversion type.
  • an array substrate comprising a plurality of sub-pixel regions arranged in a row and a column, the sub-pixel regions comprising pixel opening regions; wherein conductive patterns are provided between two sub-pixel regions adjacent in a row direction At least a portion of the conductive pattern is located between pixel open regions in two sub-pixel regions adjacent in the row direction; the conductive pattern is connected to a common voltage.
  • a common electrode is disposed in the sub-pixel region; the common electrode is connected to a common voltage by connecting a common voltage line, and the common voltage line is disposed between pixel open regions of two adjacent rows.
  • the array substrate includes a first conductive layer, and the conductive pattern and the common electrode are both disposed in the first conductive layer.
  • the common electrode is coupled to at least one adjacent conductive pattern, the adjacent conductive pattern being a conductive pattern disposed between a sub-pixel region in which the common electrode is located and an adjacent sub-pixel region.
  • two of the conductive patterns disposed on both sides of the same sub-pixel region in the row direction are connected.
  • two of the conductive patterns disposed on the same side of two sub-pixel regions adjacent in the column direction are connected.
  • a first connection pattern is disposed between two of the conductive patterns disposed on the same side of two sub-pixel regions adjacent in the column direction of the first conductive layer, and the pixels of two adjacent columns are disposed.
  • Data lines are disposed between the open areas, and at least a portion of the first connection pattern is separated from the data lines.
  • a second connection pattern is disposed between two conductive patterns disposed on two sides of the same sub-pixel region in a row direction of the first conductive layer; and between the pixel opening regions of two adjacent columns There is a data line, at least a portion of the set area of the second connection pattern being separated from the set area of the data line.
  • the conductive pattern is between adjacent two common voltage lines; the first connection pattern is also connected to the common voltage line at an intersection with the common voltage line, the conductive The graphic is connected to the common voltage line by the first connection pattern.
  • the projected length of the first connected pattern in the row direction is less than the projected length of the conductive pattern in the row direction.
  • the material of the first conductive layer is a metal material.
  • a pixel electrode is disposed in the sub-pixel region, and the pixel electrode includes an extension extending in a row direction; the extension portion and the common voltage line overlap each other.
  • gate lines are disposed between the pixel open areas of two adjacent rows; data lines are disposed between the pixel open areas of two adjacent columns;
  • a line width of the gate line at an intersection with the data line is smaller than a line width between adjacent two of the data lines, and/or the common voltage line meets with the data line
  • the line width at the point is smaller than the line width between the two adjacent data lines.
  • gate lines are provided between the pixel open regions of two adjacent rows, and the conductive pattern is located between two adjacent gate lines.
  • a pixel electrode is disposed in the sub-pixel region; a gate line is disposed between the pixel opening regions of two adjacent rows; and a data line is disposed between the pixel opening regions of two adjacent columns; a switching transistor is further disposed in the sub-pixel region, and a gate of the switching transistor is connected to the gate line.
  • a first pole other than the gate is connected to the data line, and a second pole is connected to the pixel electrode; wherein the data line is connected to the first pole of the switching transistor by an extended pattern of the data line, The extended pattern is provided with an opening at an intersection with the gate line.
  • gate lines are disposed between the pixel opening regions of two adjacent rows; data lines are disposed between the pixel opening regions of two adjacent columns; and a switching transistor is further disposed in the sub-pixel region.
  • a gate of the switching transistor is connected to the gate line, a first pole other than the gate is connected to the data line, and a second pole is connected to the pixel electrode; wherein the data line is first connected to the switching transistor
  • the poles are connected by an extended pattern of the data lines, the extended pattern comprising more than one linear portion extending in the row direction.
  • a display device comprising any of the above array substrates.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic view showing a manner of setting a gate conductive layer in the array substrate shown in FIG. 2;
  • FIG. 4 is a schematic view showing the arrangement of a gate conductive layer and an active layer in the array substrate shown in FIG. 2;
  • FIG. 5 is a schematic view showing the arrangement of a gate conductive layer, an active layer, and a source/drain conductive layer in the array substrate shown in FIG. 2;
  • FIG. 6 is a schematic view showing the arrangement of the first conductive layer in the array substrate shown in FIG. 2;
  • FIG. 7 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic view showing the arrangement of a gate conductive layer and an active layer in the array substrate shown in FIG. 7;
  • FIG. 9 is a schematic view showing the arrangement of a gate conductive layer, an active layer, and a source/drain conductive layer in the array substrate shown in FIG. 7;
  • FIG. 10 is a schematic view showing the arrangement of the first conductive layer in the array substrate shown in FIG. 7.
  • FIG. 10 is a schematic view showing the arrangement of the first conductive layer in the array substrate shown in FIG. 7.
  • FIG. 1 is a schematic diagram of an array substrate provided by an embodiment of the present disclosure.
  • an array substrate of an embodiment of the present disclosure includes a plurality of sub-pixel regions Px arranged in a row and column arrangement (the horizontal direction is a row direction and the vertical direction is a column direction) (the different sub-pixel regions are indicated by grid lines in FIG. 1).
  • the boundary line between Px), the sub-pixel region Px includes the pixel opening region P0.
  • the pixel opening area that is, the array substrate, is configured to transmit an area that displays light.
  • a pixel electrode D1 and a common electrode D2 are provided in the sub-pixel region Px, and thus can be used to form a planar electric field between each other to form a liquid crystal display of a planar conversion IPS mode.
  • the electrodes D1 and D2 are in the shape of fingers.
  • the common electrode D2 is connected to the common voltage line L0 (for the sake of clarity of illustration, the common electrode D2 connected to the uppermost common voltage line L0 in FIG. 1 is not drawn), and the common voltage line L0 is disposed in the pixel opening area P0 of the adjacent two rows. Between (ie, the direction in which the common voltage line L0 extends is consistent with the row direction).
  • the common voltage line L0 can be used to supply a common voltage to the common electrode D2 in each sub-pixel region Px.
  • a conductive pattern D3 is provided between two sub-pixel regions Px adjacent in the row direction, and each of the conductive patterns D3 has at least a portion located between the pixel opening regions P0 of the two sub-pixel regions Px adjacent in the row direction, and The conductive pattern is connected to a common voltage.
  • the way in which the conductive pattern D3 is connected to the common voltage can be a common connection Electrode D2 and/or common voltage line L0 (which may be directly or indirectly connected, not shown in Figure 1).
  • the electric field lines (also referred to as power lines) starting from the pixel electrode D1 not only terminate on the common electrode D2 in the same sub-pixel region Px, but also terminate the adjacent ones in the row direction.
  • the common electrode D2 in the pixel region Px causes mutual interference of electric fields between the two sub-pixel regions adjacent in the row direction.
  • the degree of deformation of the electric field in the pixel opening region P0 reaches a certain level, the liquid crystal molecules at the edge of the pixel opening region P0 are deflected abnormally, causing problems such as light leakage and color mixing.
  • the electric field lines of the cross-sub-pixel region Px may be more likely to terminate at a distance.
  • the conductive pattern D3 of the common voltage is applied near and also to the extent that the mutual interference of the electric fields between the two adjacent sub-pixel regions in the row direction is alleviated.
  • Conductive patterns are provided between two adjacent pixel opening regions in the row direction, conductive patterns are at least partially located between adjacent pixel opening regions in the row direction, and a conductive pattern is connected to the common voltage.
  • the conductive layer in the embodiment of the present disclosure The pattern can change the electric field distribution of the surrounding space such that the electric field lines starting at the pixel electrode and pointing to the adjacent sub-pixel regions can at least partially terminate in the conductive pattern, thereby improving mutual interference of electric fields between adjacent sub-pixel regions, and correcting the present
  • the electric field is chaotic at the edge of the pixel of the display device with planar conversion IPS mode.
  • the embodiments of the present disclosure can improve the problems of light leakage and color mixing caused by electric field chaos at the edge of the pixel, contribute to the improvement of the pixel aperture ratio and the realization of high resolution, and optimize the display performance of the display device. .
  • the size, shape, and arrangement of the sub-pixel regions shown in FIG. 1 the size, shape, and relative position relationship between the pixel electrode and the common electrode, the size, shape, and position of the pixel opening region, and the common voltage line.
  • the size, the shape, and the like of the specifications, the shape, and the shape of the conductive pattern are only an example, and may be modified according to actual application requirements in the specific implementation, and the disclosure does not limit this.
  • the conductive pattern D3 may be a straight line extending longitudinally in FIG. 1, or may have a broken line or Curved type.
  • a projection of at least a portion of the conductive pattern D3 in the row direction is located between adjacent two common electrodes D2.
  • connection of the common electrode line L2 to the common voltage line L0 through the first via hole H1 in FIG. 1 is only an example.
  • the connection between the common electrode and the common voltage may be formed in other manners according to actual application requirements (for example, The conductive black matrix pattern forms a connection between the common electrode and the common voltage), and the common voltage line may also be disposed between the pixel open areas of the adjacent two columns, which is not limited in the present disclosure.
  • the white small squares in the drawing indicate the arrangement positions of the via holes and the layer structure through the via connection positions, and do not indicate that the layer structure must be hollowed out or left blank at the position.
  • FIG. 2 is a schematic diagram of an array substrate provided by another embodiment of the present disclosure.
  • the array substrate in the embodiment of the present disclosure includes a substrate substrate, a gate conductive layer 11, a first insulating layer, an active layer 12, a second insulating layer, a source/drain conductive layer 13, and a third insulating layer which are sequentially stacked.
  • a layer, a second conductive layer 14, a first conductive layer 15, and a fourth insulating layer wherein the base substrate, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are not shown in the drawing Out.
  • the gate conductive layer 11 includes a common voltage line L0 and a gate line L1, and the common voltage line L0 and the gate line L1 are both located between the adjacent pixel openings P0 of the two rows.
  • the gate conductive layer 11 is formed on the surface of the base substrate by a patterning process on the conductive material, and the conductive material used may be, for example, copper, aluminum, molybdenum, nickel, or the like, because the pixel is disposed in the pixel. Outside the open area P0, it can thus be formed of a light-tight conductive material.
  • FIG. 4 is a schematic view showing the arrangement of a gate conductive layer and an active layer in the array substrate shown in FIG. 2.
  • the active layer 12 is disposed in a region where a switching transistor (for example, a thin film transistor TFT) is formed, and overlaps with the gate line L1, and the material for forming can be selected from the semiconductor material according to the switching transistor to be formed.
  • a switching transistor for example, a thin film transistor TFT
  • the gate conductive layer 11 and the active layer 12 are vertically spaced apart by the first insulating layer, and the first insulating layer may be on the base substrate and the gate conductive layer 11 by a transparent insulating material such as silicon oxide, silicon nitride, transparent resin or the like. It is formed by a fabrication process such as chemical vapor deposition as a gate insulating layer (Gate Insulator, GI) of a switching transistor to be formed.
  • Gate Insulator, GI Gate Insulator
  • FIG. 5 is a schematic view showing the arrangement of a gate conductive layer, an active layer, and a source/drain conductive layer in the array substrate shown in FIG. 2.
  • the source/drain metal layer 13 includes a data line L2, an extended pattern Es of the data lines, and a drain pattern Ed of the switching transistor.
  • the data line L2 is located in the adjacent two columns of pixels Between the open areas P0, for example, the data lines and the conductive pattern D3 overlap each other; the extended pattern Es is provided with an opening Op at the intersection with the gate line L1, and passes through the via holes in the second insulating layer and the left end of the active layer 12.
  • the drain pattern Ed is connected to the right end of the active layer 12 through a via hole in the second insulating layer.
  • a switching transistor is formed in each sub-pixel region, and a gate of the switching transistor is formed by a gate line L1 overlapping the active layer 12 (ie, a gate line corresponding to a sub-pixel region where the gate is connected), a source of the switching transistor
  • the pole is formed by the extended pattern Es connected to the active layer 12 (ie, the data line corresponding to the sub-pixel region where the source is connected by the extended pattern), and the drain of the switching transistor passes through the second via H2 in the third insulating layer
  • the pixel electrodes D1 in the second conductive layer 14 are connected (ie, the pixel electrodes corresponding to the sub-pixel regions where the drain is connected).
  • the line width of the gate line L1 at the intersection with the data line L2 is smaller than the line width between the adjacent two data lines L2, and the common voltage line L0 is at the same with the data line L2.
  • the line width of the intersection is smaller than the line width between the adjacent two data lines L2.
  • the second insulating layer may be formed of a transparent insulating material such as silicon oxide, silicon nitride, transparent resin or the like on the first insulating layer and the active layer 12 by a process such as chemical vapor deposition, and passed through
  • the patterning process forms a connection via of the source and the drain in the second insulating layer, and then forms the source/drain metal layer 13 on the second insulating layer by a patterning process of the conductive material
  • the conductive material used may be, for example, Copper, aluminum, molybdenum, nickel, etc., may be formed by a non-transmissive conductive material because it is disposed outside the pixel opening region P0.
  • a third insulating layer may be formed on the second insulating layer and the source/drain metal layer 13 by a process such as chemical vapor deposition from a transparent insulating material such as silicon oxide, silicon nitride, transparent resin, or the like, and passed through a patterning process.
  • a second via hole H2 is formed in the third insulating layer, and the second conductive layer 14 is formed on the third insulating layer by a patterning process of a transparent conductive material.
  • the third insulating layer may also be formed as a planarization layer in some possible embodiments to provide a flat surface for the formation of the pixel electrode D1.
  • FIG. 6 is a schematic view showing the arrangement of the first conductive layer in the array substrate shown in FIG. 2.
  • the first conductive layer 15 includes a common electrode D2, a conductive pattern D3, and a first connection pattern D4.
  • the conductive pattern D3 is located between the adjacent two gate lines L1; the common electrode D2 is connected to two adjacent conductive patterns, and the adjacent conductive pattern refers to the sub-pixel area where the common electrode D2 is located and the adjacent sub-pixel area.
  • Conductive pattern D3. Thereby, the two conductive patterns D3 disposed on both sides of the same sub-pixel region in the row direction are connected by the common electrode D2.
  • the common electrode in each sub-pixel region D2 is connected to the corresponding common voltage line L0 through the first via hole H1 disposed in the third insulating layer, the second insulating layer, and the first insulating layer, and is formed by the first conductive layer 15 as shown in FIG.
  • the grid-like pattern conducts a common voltage across the common voltage line L0 to each location in the grid-like pattern.
  • the first via hole H1 may be formed in the third insulating layer, the second insulating layer and the first insulating layer by a patterning process; the first conductive layer 15 may be patterned by a transparent conductive material.
  • the fourth insulating layer may be, for example, a chemical vapor phase on the third insulating layer, the first conductive layer 15 and the second conductive layer 14 by a transparent insulating material such as silicon oxide, silicon nitride, transparent resin or the like.
  • a deposition process is formed to form a protective layer and a planarization layer of the pixel electrode D1 and the common electrode D2.
  • the layer structure in the array substrate may be increased, decreased, or exchanged according to application requirements, for example, an insulating material layer may be added between the first conductive layer 15 and the second conductive layer 14, or the first layer may be The conductive layer 15 is combined with the second conductive layer 14, or the second insulating layer is removed to directly connect the source/drain conductive layer 13 to the active layer 12, or the top gate structure is used to form a switching transistor in the sub-pixel region, etc., the present disclosure There is no limit to this.
  • the array substrate shown in FIG. 2 to FIG. 6 is provided with conductive patterns at least partially adjacent to the pixel opening regions adjacent in the row direction and connected to a common voltage, thereby changing the electric field distribution of the surrounding space.
  • the electric field lines that cause the starting point on the pixel electrode and pointing to the adjacent sub-pixel region may at least partially terminate in the conductive pattern, thereby improving mutual interference of electric fields between adjacent sub-pixel regions, and correcting the display device pixel of the existing planar conversion IPS mode.
  • the electric field at the edge is chaotic.
  • the embodiments of the present disclosure can improve the problems of light leakage and color mixing caused by electric field chaos at the edge of the pixel, contribute to the improvement of the pixel aperture ratio and the realization of high resolution, and optimize the display performance of the display device. .
  • first conductive layer and the second conductive layer in this embodiment are formed by using a transparent conductive material (for example, a silver nanowire material or an indium tin oxide ITO), but in other implementations of the present disclosure, A conductive layer and/or a second conductive layer may also be formed of a metal material (for example, aluminum, copper, aluminum alloy, copper alloy, etc.), and a pattern of thin metal lines may be used to form a common electrode in the pixel opening region and/or Pixel electrode, which can improve public electricity based on the lower resistivity of metal materials The uniformity of the pressure and the thickness that the conductive pattern needs to achieve in meeting the conductive requirements.
  • a transparent conductive material for example, a silver nanowire material or an indium tin oxide ITO
  • a conductive layer and/or a second conductive layer may also be formed of a metal material (for example, aluminum, copper, aluminum alloy, copper alloy, etc.), and a pattern of thin metal lines may be used to form a common electrode in the pixel opening region and/
  • FIG. 7 is a schematic diagram of an array substrate provided by another embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a manner of setting a gate conductive layer and an active layer in the array substrate illustrated in FIG. 7
  • 9 is a schematic view showing the arrangement of the gate conductive layer, the active layer and the source/drain conductive layer in the array substrate shown in FIG. 7,
  • FIG. 10 is a schematic view showing the arrangement of the first conductive layer in the array substrate shown in FIG.
  • the array substrate in the embodiment of the present disclosure includes a substrate substrate, a gate conductive layer 11, a first insulating layer, an active layer 12, a second insulating layer, a source/drain conductive layer 13, a third insulating layer, and a second layer which are sequentially stacked.
  • the conductive layer 14, the first conductive layer 15, and the fourth insulating layer, wherein the base substrate, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are not shown in the drawings.
  • the main differences between the array substrate shown in FIGS. 7 to 10 (abbreviated as the first array substrate) and the array substrate shown in FIGS. 2 to 6 (referred to as the second array substrate) are as follows:
  • the gate line L1 and the common voltage line L0 corresponding to each sub-pixel region are respectively located above and below the pixel opening region P0, and the extending portion D11 and the gate extending in the row direction of the pixel electrode D1 are included.
  • the lines L1 overlap each other, and the common voltage line L0 and the common electrode D2 overlap each other; and in the array substrate shown in FIG. 7, the gate line L1 and the common voltage line L0 corresponding to each sub-pixel area are located.
  • the extending portion D11 extending in the row direction included in the pixel electrode D1 and the common voltage line L0 overlap each other.
  • the mutual overlap between the pixel electrode D1 and the common voltage line L0 in FIG. 7 can increase the storage capacitance of the sub-pixel region, which helps to improve the liquid crystal display performance; and the implementation manner shown in FIG. Simplifying the connection manner between the pixel electrode D1 and the drain pattern Es of the switching transistor, and the connection manner between the common electrode D2 and the common voltage line L0, reducing the area of the drain pattern Es, and omitting part of the first connection pattern D4
  • the setting can improve the reliability of the electrical connection between the layer structures and help to reduce the area of a single sub-pixel area. It can be understood that the relative positional relationship between the gate line L1 and the common voltage line L0 and the pixel opening area P0 can be arbitrarily set according to the application requirements, and the disclosure does not limit this.
  • the first array substrate and the second array substrate have the following aspects in common:
  • the array substrates of the two structures each include a first conductive layer, and the conductive pattern and the common electrode are both disposed in the first conductive layer.
  • the conductive pattern is formed together with the common electrode, which is advantageous for simplifying the fabrication process of the array substrate.
  • the common electrode is connected to two adjacent conductive patterns (the adjacent conductive pattern is A conductive pattern is disposed between the sub-pixel region where the common electrode is located and the adjacent sub-pixel region).
  • the fabrication of the connection structure of the corresponding portion can be reduced; when the conductive pattern is connected to the common electrode, the uniformity of the common voltage on the common electrode and the conductive pattern can be improved by forming a parallel connection and stability. It can be understood that at least some of the above effects can be obtained when the common electrode is connected to only one adjacent conductive pattern.
  • two conductive patterns disposed on both sides of the same sub-pixel region in the row direction are connected to each other, and two conductive patterns disposed on the same side of two sub-pixel regions adjacent in the column direction are connected to each other, thereby achieving conduction
  • the network format of the graphics helps to improve the uniformity and stability of the common voltage on the conductive pattern.
  • the first conductive layers each include a first connection pattern, wherein the first connection pattern is disposed between two conductive patterns on the same side of the two sub-pixel regions adjacent in the column direction, and the first connection pattern is The data lines are separated from each other. In this way, the parasitic capacitance between the first connection pattern and the data line can be reduced, which helps to improve the signal delay on the data line and also helps to improve the crosstalk phenomenon.
  • the difference between the first array substrate and the second array substrate is that the first conductive layer 15 shown in the former includes not only the first connection pattern disposed between the two conductive patterns D3 disposed on both sides of the same sub-pixel region.
  • connection pattern D5 disposed between the two conductive patterns D3 disposed on the same side of the two sub-pixel regions adjacent in the column direction, and the second connection pattern D5 is also separated from the data line L2, Thereby reducing the parasitic capacitance between the two.
  • the difference between the first array substrate and the second array substrate is that the conductive pattern D3 is located between the adjacent two common voltage lines L0, and the first connection pattern D4 is still at the intersection with the common voltage line L0.
  • the connection between the conductive pattern D3 and the common voltage is realized by the third via hole H3 instead of the first via hole H1 in FIGS.
  • the conductive pattern D3 realizes the above-mentioned common voltage line L0 by the first connection pattern D4.
  • the common electrode and the conductive pattern may also be connected to the common electrode line at a plurality of locations, respectively, to further improve the uniformity and stability of the common voltage on the first conductive layer.
  • a first connection pattern is disposed between two conductive patterns disposed on the same side of two sub-pixel regions adjacent in the column direction in the first conductive layer, and the first connection pattern is in a row direction
  • the projection length is smaller than the projection length of the conductive pattern in the row direction (such as the row width of the first connection pattern D4 in FIGS. 2 and 7 is smaller than the row width of the conductive pattern D3).
  • the conductive patterns are each located between adjacent two gate lines. In this way, the conductive pattern can be prevented from overlapping the gate lines, and the parasitic capacitance between each other can be reduced.
  • the line width of the gate line at the intersection with the data line is smaller than the line width between the adjacent two data lines. In this way, the parasitic capacitance between the gate line and the data line can be reduced.
  • the line width of the common voltage line at the intersection with the data line is smaller than the line width between the adjacent two data lines. In this way, the parasitic capacitance between the layer structure and the data line loaded with the common voltage in the first conductive layer can be reduced, which helps to improve the signal delay on the data line and also helps to improve the crosstalk phenomenon.
  • the data line and the first pole of the switching transistor are each connected by an extended pattern of data lines, and the extended pattern is provided with an opening at an intersection with the gate line. It can be seen that the parasitic capacitance between the data line and the gate line can be reduced based on the design in which the extended pattern is provided with an opening at the intersection with the gate line.
  • the above-described extended pattern includes two linear portions Es1 and Es2 extending in the extending direction (shown in Figs. 5 and 9). Thereby, when one of the linear portions is accidentally broken by the process or the external force, the electrical connection between the first poles of the switching transistors and the data lines can still be maintained by the other linear portions.
  • the embodiment of the present disclosure further provides a display device including any of the above array substrates.
  • the display device in the embodiment of the present disclosure may be, for example, a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • the display device of the embodiment of the present disclosure can improve the light leakage and color mixing caused by the electric field disorder at the edge of the pixel, and contribute to the improvement of the pixel aperture ratio, as compared with the prior art. And high-resolution implementation to optimize the display performance of the display device.

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Abstract

一种阵列基板和显示装置。阵列基板包括行列排布的若干个子像素区域(Px)，子像素区域(Px)包括像素开口区，其中，行方向上相邻的两个子像素区域之间设有导电图形(D3)，至少部分的导电图形(D3)位于行方向上相邻的两个子像素区域(Px)中的像素开口区之间；导电图形(D3)连接公共电压。导电图形可以改变周围空间的电场分布，从而改善现有平面转换类型的显示器件由像素边缘处的电场混乱所造成的显示性能下降。

Description

阵列基板和显示装置 技术领域
本公开涉及液晶显示领域，特别涉及一种阵列基板和显示装置。
背景技术
现有的液晶显示器件中，平面转换(In Plane Switching，IPS)模式主要利用设置在液晶层同一侧的像素电极与公共电极，通过彼此间形成的平面电场来使液晶分子在平行于显示面的平面内偏转，相较于传统的扭转向列(Twisted Nematic，TN)模式可以实现更高的对比度与更宽广的视角。然而由于IPS模式下，相邻像素区域之间容易产生电场间的相互干扰，使得相邻像素区域边缘处的电场混乱，产生漏光和混色等现象，降低像素开口率，影响了显示器件的显示性能。
发明内容
本公开实施例提供一种阵列基板及其显示装置，可以改善现有平面转换类型的显示器件由像素边缘处的电场混乱所造成的显示性能下降。
根据本公开第一方面，提供一种阵列基板，包括行列排布的若干个子像素区域，所述子像素区域包括像素开口区；其中，行方向上相邻的两个子像素区域之间设有导电图形，至少部分的所述导电图形位于行方向上相邻的两个子像素区域中的像素开口区之间；所述导电图形连接公共电压。
一个示例中，所述子像素区域内设有一个公共电极；所述公共电极通过连接公共电压线连接公共电压，所述公共电压线设置在相邻两行的像素开口区之间。
一个示例中，所述阵列基板包括第一导电层，所述导电图形与所述公共电极均设置在所述第一导电层中。
一个示例中，所述公共电极与至少一个邻近导电图形相连，所述邻近导电图形是设置在所述公共电极所在的子像素区域与相邻的子像素区域之间的导电图形。
一个示例中，行方向上设置在同一子像素区域两侧的两个所述导电图形相连。
一个示例中，设置在列方向上相邻的两个子像素区域的同一侧的两个所述导电图形相连。
一个示例中，所述第一导电层中设置在列方向上相邻的两个子像素区域的同一侧的两个所述导电图形之间设有第一连接图形，相邻两列的所述像素开口区之间设有数据线，所述第一连接图形的至少部分与所述数据线相互分离。
一个示例中，所述第一导电层中行方向上设置在同一子像素区域两侧的两个所述导电图形之间设有第二连接图形；相邻两列的所述像素开口区之间设有数据线，所述第二连接图形的设置区域的至少部分与所述数据线的设置区域相互分离。
一个示例中，所述导电图形位于相邻的两条所述公共电压线之间；所述第一连接图形还在与所述公共电压线的交叠处连接所述公共电压线，所述导电图形藉由所述第一连接图形连接所述公共电压线。
一个示例中，所述第一连接图形在行方向上的投影长度小于所述导电图形在行方向上的投影长度。
一个示例中，所述第一导电层的材料为金属材料。
一个示例中，所述子像素区域内设有一个像素电极，所述像素电极包括沿行方向延伸的延伸部；所述延伸部与所述公共电压线之间相互交叠。
一个示例中，相邻两行的所述像素开口区之间设有栅线；相邻两列的所述像素开口区之间设有数据线；
所述栅线在与所述数据线的交汇处的线宽小于在相邻的两条所述数据线之间的线宽，和/或，所述公共电压线在与所述数据线的交汇处的线宽小于在相邻的两条所述数据线之间的线宽。
一个示例中，相邻两行的所述像素开口区之间设有栅线，所述导电图形位于相邻的两条所述栅线之间。
一个示例中，所述子像素区域内设有一个像素电极；相邻两行的所述像素开口区之间设有栅线；相邻两列的所述像素开口区之间设有数据线；所述子像素区域内还设有一个开关晶体管，所述开关晶体管的栅极连接所述栅线， 栅极以外的第一极连接所述数据线，第二极连接所述像素电极；其中，所述数据线与所述开关晶体管的第一极之间藉由所述数据线的延伸图形连接，所述延伸图形在与所述栅线的交叠处设有开口。
一个示例中，相邻两行的所述像素开口区之间设有栅线；相邻两列的所述像素开口区之间设有数据线；所述子像素区域内还设有一个开关晶体管，所述开关晶体管的栅极连接所述栅线，栅极以外的第一极连接所述数据线，第二极连接所述像素电极；其中，所述数据线与所述开关晶体管的第一极之间藉由所述数据线的延伸图形连接，所述延伸图形包括一个以上沿行方向延伸的线形部。
根据本公开第二方面，提供了一种显示装置，包括上述任意一种阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开一个实施例提供的阵列基板的结构示意图；
图2是本公开另一实施例提供的阵列基板的结构示意图；
图3是图2所示的阵列基板中栅极导电层的设置方式示意图；
图4是图2所示的阵列基板中栅极导电层和有源层的设置方式示意图；
图5是图2所示的阵列基板中栅极导电层、有源层和源漏导电层的设置方式示意图；
图6是图2所示的阵列基板中第一导电层的设置方式示意图；
图7是本公开又一实施例提供的阵列基板的结构示意图；
图8是图7所示的阵列基板中栅极导电层和有源层的设置方式示意图；
图9是图7所示的阵列基板中栅极导电层、有源层和源漏导电层的设置方式示意图；
图10是图7所示的阵列基板中第一导电层的设置方式示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1是本公开一个实施例提供的阵列基板的示意图。参见图1，本公开实施例的阵列基板包括行列排布(附图中的横向为行方向，纵向为列方向)的若干个子像素区域Px(图1中以网格线表示出不同子像素区域Px之间的分界线)，子像素区域Px包括像素开口区P0。所述的像素开口区即阵列基板被配置用于透过显示光线的区域。子像素区域Px内设有一个像素电极D1和一个公共电极D2，因而可以用于在彼此间形成平面电场来形成平面转换IPS模式的液晶显示。例如，电极D1、D2为插指状。公共电极D2连接公共电压线L0(为了图示清晰，图1中与最上方的公共电压线L0相连的公共电极D2没有绘出)，公共电压线L0设置在相邻两行的像素开口区P0之间(即公共电压线L0延伸的方向与行方向一致)。由此，公共电压线L0可以用来为每一子像素区域Px内的公共电极D2提供公共电压。此外，行方向上相邻的两个子像素区域Px之间设有导电图形D3，每一导电图形D3均有至少一部分位于行方向上相邻的两个子像素区域Px中的像素开口区P0之间，并且导电图形连接公共电压。导电图形D3连接公共电压的方式可以是连接公共 电极D2和/或公共电压线L0(可以是直接相连或者间接相连，未在图1中示出)。
参见图1，当所有子像素区域Px内的像素电极D1与公共电极D2之间均加载有各自的数据电压时，同一子像素区域Px内的像素电极D1与公共电极D2之间形成电场强度与数据电压的大小相对应的平面电场，从而可以通过使液晶分子偏转来实现平面转换IPS模式下的液晶显示。在没有设置导电图形D3的情况下，起点在像素电极D1上的电场线(也称电力线)不仅会终止在同一子像素区域Px内的公共电极D2上，还会终止在行方向上相邻的子像素区域Px内的公共电极D2上(即电场线跨越两个行方向上相邻的子像素区域之间的分界线)，从而引发行方向上相邻的两个子像素区域之间电场的相互干扰。当其所导致的像素开口区P0内的电场变形程度达到一定水平之后，就会使像素开口区P0边缘处的液晶分子偏转异常，引发漏光和混色等问题。然而，本公开实施例中，通过至少部分地设置在行方向上相邻的两个像素开口区P0之间的导电图形D3，可使上述跨子像素区域Px的电场线更倾向于终止在距离更近且同样加载公共电压的导电图形D3上，从而减轻了行方向上相邻的两个子像素区域之间电场的相互干扰的程度。
基于行方向上相邻的两个像素开口区之间设有导电图形，导电图形至少部分位于行方向上相邻的像素开口区之间，以及导电图形连接公共电压的设计，本公开实施例中的导电图形可以改变周围空间的电场分布，使得起点在像素电极上并指向相邻子像素区域的电场线可以至少部分地终止于导电图形，从而改善相邻子像素区域之间电场的相互干扰，矫正现有平面转换IPS模式的显示器件像素边缘处的电场混乱。相比于现有技术，本公开实施例可以改善像素边缘处的电场混乱所带来的漏光和混色等问题，有助于像素开口率的提高和高分辨率的实现，优化显示器件的显示性能。
需要说明的是，图1中示出的子像素区域的大小、形状、排列方式，像素电极与公共电极的大小、形状、相对位置关系，像素开口区的大小、形状、位置，公共电压线的规格、形状，以及导电图形的大小、形状等等均仅是一种示例，在具体实施时可根据实际应用需求进行更改，本公开对此不做限制。例如，导电图形D3可以为图1中沿纵向延伸的直线型，也可以具有折线或 弯曲型。例如，至少一部分导电图形D3在行方向的投影位于相邻两个公共电极D2之间。而且，图1中公共电极D2通过第一过孔H1连接公共电压线L0仅是一种示例，在具体实施时可根据实际应用需求采用其他方式形成公共电极与公共电压之间的连接(比如通过导电的黑矩阵图形形成公共电极与公共电压之间的连接)，另外公共电压线还可以设置在相邻两列的像素开口区之间，本公开对此不做限制。需要说明的是，附图中的白色小方块表示过孔的设置位置和层结构通过过孔连接位置，而不表示层结构须在该位置处挖空或留白。
作为一种可能的实现方式，图2是本公开又一实施例提供的阵列基板的示意图。参见图2，本公开实施例中的阵列基板包括依次层叠的衬底基板、栅极导电层11、第一绝缘层、有源层12、第二绝缘层、源漏导电层13、第三绝缘层、第二导电层14、第一导电层15和第四绝缘层，其中的衬底基板、第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层未在附图中示出。
图3是图2所示的阵列基板中栅极导电层的设置方式示意图。参见图2和图3，栅极导电层11包括公共电压线L0和栅线L1，公共电压线L0和栅线L1均位于相邻两行的像素开口区P0之间。本公开实施例中，栅极导电层11通过对导电材料的图案化工艺形成在衬底基板的表面上，所采用的导电材料可以例如是铜、铝、钼、镍等等，因设置在像素开口区P0之外，因此可以由不透光的导电材料形成。
图4是图2所示的阵列基板中栅极导电层和有源层的设置方式示意图。参见图2和图4，有源层12设置在形成开关晶体管(例如薄膜晶体管TFT)的区域内，并与栅线L1相互交叠，其形成材料可根据所要形成的开关晶体管在半导体材料中选取，本公开对此不做限制。栅极导电层11与有源层12被第一绝缘层上下间隔开，第一绝缘层可由例如氧化硅、氮化硅、透明树脂等等的透明绝缘材料在衬底基板和栅极导电层11上采用例如化学气相沉积的制作工艺形成，以作为所要形成的开关晶体管的栅绝缘层(Gate Insulator，GI)。
图5是图2所示的阵列基板中栅极导电层、有源层和源漏导电层的设置方式示意图。参见图2至图5，源漏金属层13包括数据线L2、数据线的延伸图形Es，以及开关晶体管的漏极图形Ed。数据线L2位于相邻两列的像素 开口区P0之间，例如数据线与导电图形D3彼此重叠；延伸图形Es在与栅线L1的交叠处设有开口Op，并通过第二绝缘层中的过孔与有源层12的左端连接；漏极图形Ed通过第二绝缘层中的过孔与有源层12的右端连接。由此在每一子像素区域形成一个开关晶体管，开关晶体管的栅极通过与有源层12交叠的栅线L1形成(即栅极连接所在子像素区域对应的栅线)，开关晶体管的源极通过与有源层12连接的延伸图形Es形成(即源极藉由延伸图形连接所在子像素区域对应的数据线)，开关晶体管的漏极通过第三绝缘层中的第二过孔H2与第二导电层14中的像素电极D1相连(即漏极连接所在子像素区域对应的像素电极)。此外，参照图4和图5可知，栅线L1在与数据线L2的交汇处的线宽小于在相邻的两条数据线L2之间的线宽，公共电压线L0在与数据线L2的交汇处的线宽小于在相邻的两条数据线L2之间的线宽。
在制作方式上，上述第二绝缘层可由例如氧化硅、氮化硅、透明树脂等等的透明绝缘材料在第一绝缘层和有源层12上采用例如化学气相沉积的制作工艺形成，并通过图案化工艺在第二绝缘层中形成源极、漏极的连接过孔，然后通过导电材料的图案化工艺在第二绝缘层上形成上述源漏金属层13(所采用的导电材料可以例如是铜、铝、钼、镍等等，因设置在像素开口区P0之外，所以可采用不透光的导电材料形成)。此后，可由例如氧化硅、氮化硅、透明树脂等等的透明绝缘材料在第二绝缘层和源漏金属层13上采用例如化学气相沉积的制作工艺形成第三绝缘层，并通过图案化工艺在第三绝缘层中形成第二过孔H2，再通过透明导电材料的图案化工艺在第三绝缘层上形成上述第二导电层14。第三绝缘层除了保持像素电极D1与下方结构之间的绝缘之外，在一些可能的实施方式中还可以制作为平坦化层，从而为像素电极D1的形成提供一平坦的表面。
图6是图2所示的阵列基板中第一导电层的设置方式示意图。参见图2和图6，第一导电层15包括公共电极D2、导电图形D3和第一连接图形D4。导电图形D3位于相邻的两条栅线L1之间；公共电极D2与两个邻近导电图形相连，邻近导电图形指的是公共电极D2所在的子像素区域与相邻的子像素区域之间的导电图形D3。由此，行方向上设置在同一子像素区域两侧的两个导电图形D3藉由公共电极D2相连。而且，每个子像素区域内的公共电极 D2通过设置在第三绝缘层、第二绝缘层和第一绝缘层中的第一过孔H1与对应的公共电压线L0相连，并且由第一导电层15所形成的如图6所示的类网格状图形将公共电压线L0上的公共电压传导至类网格状图形中的每一位置处。参照图2和图6，设置在列方向上相邻的两个子像素区域的同一侧的两个导电图形D3藉由第一连接图形D4相连，第一连接图形D4的设置区域与数据线L2的设置区域相互分离，即第一连接图形D4与数据线L2在垂直基板的方向上不重叠。在制作方式上，上述第一过孔H1可以通过图案化工艺在第三绝缘层、第二绝缘层和第一绝缘层中形成；上述第一导电层15可由透明导电材料的图案化工艺在第三绝缘层上形成，上述第四绝缘层可由例如氧化硅、氮化硅、透明树脂等等的透明绝缘材料在第三绝缘层、第一导电层15和第二导电层14上采用例如化学气相沉积的制作工艺形成，以形成像素电极D1和公共电极D2的保护层和平坦化层。
在其他可能的实现方式中，阵列基板内的层结构可以根据应用需求增加、减少或者位置交换，比如可以在第一导电层15与第二导电层14之间增加绝缘材料层，或者将第一导电层15与第二导电层14合并，或者去除第二绝缘层使源漏导电层13直接与有源层12连接，或者改用顶栅结构形成子像素区域内的开关晶体管等等，本公开对此不做限制。
可以看出的是，图2至图6所示出的阵列基板中设置了至少部分位于行方向上相邻的像素开口区之间并连接公共电压的导电图形，因而可以改变周围空间的电场分布，使得起点在像素电极上并指向相邻子像素区域的电场线可以至少部分地终止于导电图形，从而改善相邻子像素区域之间电场的相互干扰，矫正现有平面转换IPS模式的显示器件像素边缘处的电场混乱。相比于现有技术，本公开实施例可以改善像素边缘处的电场混乱所带来的漏光和混色等问题，有助于像素开口率的提高和高分辨率的实现，优化显示器件的显示性能。
需要说明的是，本实施例中的第一导电层和第二导电层采用了透明导电材料(例如银纳米线材料或者铟锡氧化物ITO)形成，但在本公开的其他实现方式中，第一导电层和/或第二导电层还可以采用金属材料(例如铝、铜、铝合金、铜合金等等)形成，并可以采用细金属线的图形形成像素开口区内的公共电极和/或像素电极，可以基于金属材料较低电阻率的特性提高公共电 压的均匀性，并减小导电图形在满足导电要求的情况下所需达到的厚度。
作为又一种可能的实现方式，图7是本公开又一实施例提供的阵列基板的示意图，图8是图7所示的阵列基板中栅极导电层和有源层的设置方式示意图，图9是图7所示的阵列基板中栅极导电层、有源层和源漏导电层的设置方式示意图，图10是图7所示的阵列基板中第一导电层的设置方式示意图。
本公开实施例中的阵列基板包括依次层叠的衬底基板、栅极导电层11、第一绝缘层、有源层12、第二绝缘层、源漏导电层13、第三绝缘层、第二导电层14、第一导电层15和第四绝缘层，其中的衬底基板、第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层未在附图中示出。将图7至图10所示的阵列基板(简称第一阵列基板)与图2至图6所示的阵列基板(简称第二阵列基板)的主要区别在于：
图2所示的阵列基板中，每个子像素区域所对应的栅线L1和公共电压线L0分别位于像素开口区P0的上方和下方，像素电极D1所包含的行方向延伸的延伸部D11与栅线L1之间相互交叠，公共电压线L0与公共电极D2之间相互交叠；而在图7所示的阵列基板中，每个子像素区域所对应的栅线L1和公共电压线L0均位于子像素开口区P0的上方，像素电极D1所包含的行方向延伸的延伸部D11与公共电压线L0之间相互交叠。
基于上述区别，图7中像素电极D1与公共电压线L0之间的相互交叠，能够增大子像素区域的存储电容，有助于提升液晶显示性能；而图2所示的实现方式则可以简化像素电极D1与开关晶体管的漏极图形Es之间的连接方式，以及公共电极D2与公共电压线L0之间的连接方式，缩小漏极图形Es的面积，省去部分第一连接图形D4的设置，可以提升层结构间电连接的可靠性，并有助于减小单个子像素区域的面积。可理解的是，栅线L1、公共电压线L0与像素开口区P0之间的相对位置关系是可以根据应用需求任意设置的，本公开对此不做限制。
上述第一阵列基板与第二阵列基板存在以下多个方面的共同点：
第一方面，两种结构的阵列基板均包括第一导电层，并且导电图形与公共电极均设置于所述第一导电层中。这样，导电图形随公共电极一并制作，有利于简化阵列基板的制作工艺。
第二方面，公共电极均与两个邻近导电图形彼此相连(邻近导电图形是 设置在公共电极所在的子像素区域与相邻的子像素区域之间的导电图形)。这样，在导电图形不与公共电极相连时，可以减少相应部分的连接结构的制作；在导电图形与公共电极相连时，可以通过形成并联来提升公共电压在公共电极和导电图形上的均匀性和稳定性。可以理解的是，在公共电极仅与一个邻近导电图形相连时，也至少可以取得上述的部分效果。
第三方面，行方向上设置在同一子像素区域两侧的两个导电图形彼此相连，并且设置在列方向上相邻的两个子像素区域的同一侧的两个导电图形彼此相连这样，可以实现导电图形的类网格式设置，有助于提升导电图形上公共电压的均匀性和稳定性。
第四方面，第一导电层均包括第一连接图形，其中的第一连接图形设置在列方向上相邻的两个子像素区域的同一侧的两个导电图形之间，并且第一连接图形与数据线相互分离。这样，可以减小第一连接图形与数据线之间的寄生电容，有助于改善数据线上的信号时延，也有助于改善串扰现象。第一阵列基板与第二阵列基板之间的区别在于，前者示出的第一导电层15中不仅包括设置在同一子像素区域两侧的两个导电图形D3之间所设置的第一连接图形D4，还包括设置在列方向上相邻的两个子像素区域的同一侧的两个导电图形D3之间所设置的第二连接图形D5，并且第二连接图形D5也与数据线L2相互分离，从而减小二者之间的寄生电容。而且，第一阵列基板与第二阵列基板之间的区别还在于，导电图形D3位于相邻的两条公共电压线L0之间，第一连接图形D4还在与公共电压线L0的交叠处通过第三过孔H3替代图2至图6中的第一过孔H1实现导电图形D3与公共电压之间的连接(即导电图形D3藉由第一连接图形D4实现上述与公共电压线L0之间的连接)，以及公共电极D1与公共电压线L0之间的连接。而在本公开的其他实现方式中，公共电极与导电图形还可以分别在多个位置处与公共电极线相连，以进一步提升公共电压在第一导电层上的均匀性和稳定性。
第五方面，第一导电层中设置在列方向上相邻的两个子像素区域的同一侧的两个导电图形之间均设有第一连接图形，并且所述第一连接图形在行方向上的投影长度小于所述导电图形在行方向上的投影长度(比如图2和图7中第一连接图形D4的行向宽度均小于导电图形D3的行向宽度)。由此，可以减少起点在像素电极上的电场线终止于第一连接图形上的情况，从而减小 第一连接图形的设置对列方向上电场分布的干扰。
第六方面，导电图形均位于相邻的两条栅线之间。这样，可以避免导电图形与栅线交叠，减小彼此间的寄生电容。
第七方面，栅线在与数据线的交汇处的线宽均小于在相邻的两条数据线之间的线宽。这样，可以减少栅线与数据线之间的寄生电容。
第八方面，公共电压线在与数据线的交汇处的线宽均小于在相邻的两条数据线之间的线宽。这样，可以减少第一导电层中加载公共电压的层结构与数据线之间的寄生电容，有助于改善数据线上的信号时延，也有助于改善串扰现象。
第九方面，数据线与开关晶体管的第一极之间均藉由数据线的延伸图形连接，并且延伸图形在与栅线的交叠处设有开口。可以看出的是，基于延伸图形在与栅线的交叠处设有开口的设计，可以减少数据线与栅线之间的寄生电容。此外，在两种结构的阵列基板中，上述延伸图形包括两个延行方向延伸的线形部Es1和Es2(在图5和图9中示出)。由此，在其中一个线形部受工艺或外力影响而意外断开时，仍可以由其他线形部维持开关晶体管的第一极之间与数据线之间的电连接。可以看出，基于延伸图形包括一个以上的沿行方向延伸的线形部的设计，可以减小开关晶体管与数据线的连接位置处的断路不良发生的概率，有利于产品良率的提升。需要说明的是，上述每一方面都可以各自取得其所带来的技术效果，本领域技术人员在实施本公开时，可以根据应用需求选取上述的任意一个或一个以上的方面的设计，本公开对此不做限制。
本公开实施例还提供了一种显示装置，该显示装置包括上述任一种阵列基板。
本公开实施例中的显示装置例如可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于具有上述实施例相同的导电图形，相比于现有技术，本公开实施例的显示装置可以改善像素边缘处的电场混乱所带来的漏光和混色等问题，有助于像素开口率的提高和高分辨率的实现，优化显示器件的显示性能。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范 围，本公开的保护范围由所附的权利要求确定。
本申请基于并且要求于2016年12月5日递交的中国专利申请第201621322702.2号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (17)

  1. 一种阵列基板，其中，包括行列排布的若干个子像素区域，所述子像素区域包括像素开口区；
    其中，行方向上相邻的两个子像素区域之间设有导电图形，至少部分的所述导电图形位于行方向上相邻的两个子像素区域中的像素开口区之间；所述导电图形连接公共电压。
  2. 根据权利要求1所述的阵列基板，其中，所述子像素区域内设有一个公共电极；所述公共电极通过连接公共电压线连接公共电压，所述公共电压线设置在相邻两行的像素开口区之间。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括第一导电层，所述导电图形与所述公共电极均设置在所述第一导电层中。
  4. 根据权利要求3所述的阵列基板，其中，所述公共电极与至少一个邻近导电图形相连，所述邻近导电图形是设置在所述公共电极所在的子像素区域与相邻的子像素区域之间的导电图形。
  5. 根据权利要求3或4所述的阵列基板，其中，行方向上设置在同一子像素区域两侧的两个所述导电图形相连。
  6. 根据权利要求3或4所述的阵列基板，其中，设置在列方向上相邻的两个子像素区域的同一侧的两个所述导电图形相连。
  7. 根据权利要求3所述的阵列基板，其中，所述第一导电层中设置在列方向上相邻的两个子像素区域的同一侧的两个所述导电图形之间设有第一连接图形，相邻两列的所述像素开口区之间设有数据线，所述第一连接图形的至少部分与所述数据线相互分离。
  8. 根据权利要求3所述的阵列基板，其中，所述第一导电层中行方向上设置在同一子像素区域两侧的两个所述导电图形之间设有第二连接图形；相邻两列的所述像素开口区之间设有数据线，所述第二连接图形的设置区域的至少部分与所述数据线的设置区域相互分离。
  9. 根据权利要求7所述的阵列基板，其中，所述导电图形位于相邻的两条所述公共电压线之间；所述第一连接图形还在与所述公共电压线的交叠处连接所述公共电压线，所述导电图形藉由所述第一连接图形连接所述公共电 压线。
  10. 根据权利要求7所述的阵列基板，其中，所述第一连接图形在行方向上的投影长度小于所述导电图形在行方向上的投影长度。
  11. 根据权利要求3所述的阵列基板，其中，所述第一导电层的材料为金属材料。
  12. 根据权利要求2所述的阵列基板，其中，所述子像素区域内设有一个像素电极，所述像素电极包括沿行方向延伸的延伸部；所述延伸部与所述公共电压线之间相互交叠。
  13. 根据权利要求2所述的阵列基板，其中，相邻两行的所述像素开口区之间设有栅线；相邻两列的所述像素开口区之间设有数据线；
    所述栅线在与所述数据线的交汇处的线宽小于在相邻的两条所述数据线之间的线宽，和/或，所述公共电压线在与所述数据线的交汇处的线宽小于在相邻的两条所述数据线之间的线宽。
  14. 根据权利要求1所述的阵列基板，其中，相邻两行的所述像素开口区之间设有栅线，所述导电图形位于相邻的两条所述栅线之间。
  15. 根据权利要求1所述的阵列基板，其中，所述子像素区域内设有一个像素电极；相邻两行的所述像素开口区之间设有栅线；相邻两列的所述像素开口区之间设有数据线；所述子像素区域内还设有一个开关晶体管，所述开关晶体管的栅极连接所述栅线，栅极以外的第一极连接所述数据线，第二极连接所述像素电极；其中，所述数据线与所述开关晶体管的第一极之间藉由所述数据线的延伸图形连接，所述延伸图形在与所述栅线的交叠处设有开口。
  16. 根据权利要求1所述的阵列基板，其中，相邻两行的所述像素开口区之间设有栅线；相邻两列的所述像素开口区之间设有数据线；所述子像素区域内还设有一个开关晶体管，所述开关晶体管的栅极连接所述栅线，栅极以外的第一极连接所述数据线，第二极连接所述像素电极；其中，所述数据线与所述开关晶体管的第一极之间藉由所述数据线的延伸图形连接，所述延伸图形包括一个以上沿行方向延伸的线形部。
  17. 一种显示装置，包括如权利要求1至16中任一项所述的阵列基板。
PCT/CN2017/092174 2016-12-05 2017-07-07 阵列基板和显示装置 WO2018103330A1 (zh)

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