WO2018094595A1 - 阵列基板的制造方法 - Google Patents

阵列基板的制造方法 Download PDF

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Publication number
WO2018094595A1
WO2018094595A1 PCT/CN2016/106886 CN2016106886W WO2018094595A1 WO 2018094595 A1 WO2018094595 A1 WO 2018094595A1 CN 2016106886 W CN2016106886 W CN 2016106886W WO 2018094595 A1 WO2018094595 A1 WO 2018094595A1
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Prior art keywords
photoresist
metal layer
layer
array substrate
metal
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French (fr)
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洪日
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201680036538.5A priority Critical patent/CN107836039A/zh
Priority to PCT/CN2016/106886 priority patent/WO2018094595A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

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  • the present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate.
  • a metal oxide material is used as an active layer in the array substrate.
  • the conventional wet etching performs the patterning process of the source and the drain
  • an acid etching pattern is used, and the metal oxide is generally not resistant to acid, so that the conventional process may corrode part.
  • the active layer affects the performance of the array substrate. If dry etching is used, the etching gas damages the surface of the source and drain metal layers, which also affects the performance of the array substrate.
  • the purpose of the application is to provide a method for manufacturing an array substrate, which can avoid corrosion of the active layer during the manufacturing process and improve the performance of the array substrate.
  • the present application provides a method of fabricating an array substrate, the method comprising:
  • the photoresist is removed.
  • the step of dry etching the exposed metal layer under the semi-exposed region to expose the metal oxide semiconductor layer to form a trench includes using an etching gas to the source/drain layer metal layer A portion exposed to the fully exposed region is bombarded to expose the metal oxide semiconductor layer to form a channel.
  • the metal oxide semiconductor layer is partially exposed to the channel, wherein an etching rate and the etching time are both Is the default value.
  • the etching gas is a mixture of one or any of SF6, O2, Cl2, He, Ar.
  • the photoresist is used as a shielding layer, and the metal layer is etched, so that the etched metal layer has a source/drain layer pattern with the photoresist as a shielding layer, and the source and drain electrodes are The layer is etched such that the source and drain layer patterning step includes etching the etchant on the source/drain layer metal layer for etching, and removing the etchant after the source/drain layer metal layer is patterned.
  • the etching solution comprises H2O2, a metal chelating agent or an organic acid.
  • the step of removing the photoresist at the semi-exposed region to expose the metal layer under the semi-exposed region comprises ashing the photoresist to make the semi-exposed region The photoresist at the place is removed.
  • the ashing treatment comprises exciting oxygen into a plasma to react with the photoresist, so that the photoresist at the half-exposed region is removed.
  • the step of removing the photoresist comprises: removing the photoresist by an ashing process or a wet etching process.
  • the multi-gray mask is a halftone mask or a gray mask.
  • the metal oxide semiconductor layer is made of an IGZO material.
  • a photoresist is coated on the source/drain metal layer, and a half-exposure region is formed on the photoresist by a multi-gray mask, and the photoresist is used as a mask.
  • the metal layer is etched such that the metal layer has a source/drain layer pattern, and then the semi-exposed region of the photoresist is converted into a fully exposed region, and the metal layer under the half-exposed region is dried Etching to expose the metal oxide semiconductor layer, thereby causing no damage to the metal layer during dry etching to expose the metal oxide semiconductor layer, improving the production yield of the array substrate.
  • FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 2 to 8 are schematic views of processes of the manufacturing method shown in Fig. 1.
  • the array substrate produced by the manufacturing method of the present application can be applied to a liquid crystal display or an organic display.
  • the flexible display screen according to the embodiment of the present invention is used for, but not limited to, a mobile phone, a tablet computer, a palmtop computer, a personal digital assistant (PDA), or an e-reader.
  • PDA personal digital assistant
  • FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present application.
  • the manufacturing method provided by the present application mainly includes the following steps:
  • Step S001 sequentially forming a gate electrode, a gate insulating layer, a metal oxide semiconductor layer, and a metal layer on the substrate.
  • the substrate 10 is a transparent glass substrate on which a first metal thin film is deposited.
  • the first metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • a pattern of a gate line (not shown), a common electrode line (not shown), and a gate electrode 20 is formed by a patterning process using a conventional photoresist.
  • the gate insulating layer 30 is deposited by a PECVD (plasma enhanced chemical vapor deposition) method, and the gate insulating layer 30 may be an oxide, a nitride or an oxynitride.
  • the metal oxide semiconductor layer 40 is deposited on the gate insulating layer 30 by sputtering or thermal evaporation.
  • the metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO. , a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide.
  • IGZO indium gallium zinc oxide
  • a metal layer 50 is formed on the substrate 10 by sputtering or thermal evaporation.
  • the metal layer 50 is made of a metal or an alloy which is excellent in electrical conductivity and which is easy to dry.
  • a metal or an alloy such as Al, Cr, W, Cu, Ti, Ta, or Mo may be used, and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • it may be made of a copper or copper alloy material.
  • Step S002 coating a photoresist on the metal layer.
  • the thickness of the photoresist may be between 1.5 um and 2 um, and the specific thickness may be adjusted according to actual conditions.
  • Step S003 providing a multi-gray mask, the photoresist is patterned by using the multi-gray mask to form a half-exposure region on the photoresist.
  • a photoresist 60 is coated on the metal layer 50; a multi-gray mask 80 is provided over the photoresist 60.
  • the multi-gray mask 70 may be a half tone mask or a gray tone mask.
  • the photoresist 60 is exposed and developed (i.e., patterned).
  • the multi-gray mask 80 is provided with a fully transparent region 81, a semi-transmissive region 82, and an opaque region 83.
  • the photoresist 60 is photolithographically exposed through the multi-gray mask 80. Referring to FIG.
  • the photoresist 60 under the fully transparent region 81 is completely photolithographically formed to form the full exposed region 61, and the metal layer 50 under the fully exposed region 61 is exposed to the photoresist 60.
  • the photoresist 60 under the semi-transmissive region 82 is partially photolithographic to form a half-exposure region 62.
  • the photoresist 60 under the opaque region 81 is retained. That is, the photoresist 60 is patterned to form a half-exposure region 81 thereon.
  • the thickness of the half-exposure region 81 may be between 0.5 um and 1 um, and the specific thickness may be adjusted according to actual conditions.
  • S004 etching the metal layer by using the photoresist as a shielding layer, and the etched metal layer has a source/drain layer pattern.
  • An etchant may be sprayed on the photoresist 60 and the metal layer 50, and the etchant etches the metal layer 50 through the full exposed region 61 on the photoresist 60 until the The metal layer 50 is formed with a source and drain layer pattern, and finally the etching liquid is removed to complete the patterning process of the metal layer 52.
  • the etching solution may be selected from H 2 O 2 , a metal chelating agent or an organic acid.
  • the photoresist 60 may be subjected to ashing treatment so that the photoresist at the half exposure region 62 is removed.
  • ashing treatment is to excite oxygen into a plasma, and then react the oxygen excited into the plasma with the photoresist, thereby thinning the photoresist 60 as a whole, and the photoresist 60 as a whole.
  • the photoresist at the half-exposure region 62 will first be completely removed, i.e., the half-exposed regions will be converted to the fully exposed regions 62.
  • the metal layer 50 is partially exposed to the fully exposed region 62.
  • S006 dry etching the metal layer exposed under the half exposed region to expose the metal oxide semiconductor layer to form a channel.
  • a channel 53 needs to be formed, and a source 51 and a drain 52 are formed on the metal layer 50.
  • a channel 53 can be etched on the metal layer 50 by dry etching, and the metal oxide semiconductor layer 40 is partially exposed to the channel 53.
  • the source 51 and the drain 52 are formed by the channel 53.
  • the etching gas may be placed in a low pressure environment, and a voltage is applied to excite the etching gas into a plasma, and then the metal layer 50 is bombarded to etch the metal layer 50. Due to the presence of photoresist 60, metal layer 50 underlying fully exposed region 62 will be etched. Located below the photoresist 60 except for the area corresponding to the full exposure region 62, the metal layer 50 under the non-full exposure region of the photoresist 60 is protected from etching by the etching gas due to the presence of the photoresist 60.
  • the depth of the etching may be controlled by controlling the etching time of the etching gas on the metal layer 50 until the portion of the metal layer 50 directly under the full exposure region 62 is completely etched, thereby forming the channel 53, and The metal oxide semiconductor layer 40 partially exposes the channel 53.
  • the etching time is a preset value. At this time, the metal layer 50 is divided into the source 51 and the drain 52 through the channel 53.
  • the etching gas may be appropriately selected according to the material selected for the metal layer 50.
  • the material selected for the metal layer 50 For example, one or a combination of SF 6 , O 2 , Cl 2 , He, Ar (argon) may be selected.
  • the photoresist 60 can function to protect other portions of the metal layer 50, thereby avoiding surface quality degradation of the metal layer 50 due to dry etching. And improve the performance of the array substrate.
  • the dry etching may be stopped, the photoresist 60 may be removed, and the subsequent steps may be continued to complete the fabrication of the array substrate.
  • the subsequent steps are not the focus of the protection of the present invention and will not be described here.
  • Removing the photoresist 60 may strip the photoresist using a wet etch process.
  • the process can use the prior art photoresist stripping method, and details are not described herein again.
  • the photoresist may be removed using the ashing process described above.
  • a photoresist is coated on the metal layer, and a half-exposure region is formed on the photoresist by a multi-gray mask, and the photoresist is used as a shielding layer.
  • the metal layer is etched such that the metal layer has a source/drain layer pattern, and then the half exposed region of the photoresist is converted into a full exposed region, and the metal layer under the half exposed region is dry etched to The channel is formed and the metal oxide semiconductor layer is exposed, so that the metal layer is not damaged during dry etching to expose the metal oxide semiconductor layer, and the production yield of the array substrate is improved.

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Abstract

本申请提供一种阵列基板的制造方法，包括：在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层和金属层；在所述金属层上涂覆光刻胶；提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域；以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，使得蚀刻后的金属层具有源漏极层图案；去除所述半曝光区域处的光刻胶，以露出所述半曝光区域下方的所述金属层；干法蚀刻所述半曝光区域下方露出的所述金属层，以露出所述金属氧化物半导体层从而形成沟道；去除所述光刻胶。本申请在形成沟道过程中不会对金属层造成损伤，提高了阵列基板的生产良率。

Description

阵列基板的制造方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板的制造方法。
背景技术
目前，在阵列基板中采用金属氧化物材料作为有源层。现有技术中阵列基板的制造过程中，主要有如下问题：传统湿法蚀刻进行源漏极的构图工艺时，会使用酸刻蚀图案，而金属氧化物一般不耐酸，从而传统工艺会腐蚀部分有源层，从而影响到阵列基板的性能。若采用干法蚀刻，蚀刻气体对源漏极金属层表面造成损伤，同样影响到阵列基板的性能。
发明内容
本申请的目的在于提供一种阵列基板的制造方法，可以避免制造过程中造成有源层的腐蚀，提升阵列基板的性能。
为实现上述目的，本申请提供如下技术方案：
本申请提供一种阵列基板的制造方法，所述方法包括：
在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层和源漏极金属层；
在所述形成覆盖所述栅极绝缘层、金属氧化物半导体层的金属层并且在金属层上源漏极层上涂覆光刻胶；
提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域；
以所述光刻胶为遮蔽层，对所述金属层源漏极层进行蚀刻，使得蚀刻后的金属层具有源漏极层图案化；
去除所述半曝光区域处的光刻胶，以露出所述半曝光区域下方的所述金属层；
干法蚀刻所述半曝光区域下方露出的所述金属层，以露出所述金属氧化物半导体层从而形成沟道；
去除所述光刻胶。
其中，所述干法蚀刻所述半曝光区域下方露出的所述金属层，以露出所述金属氧化物半导体层从而形成沟道步骤中，包括使用蚀刻气体对所述源漏极层金属层之露出于所述全曝光区域的部分进行轰击，以露出所述金属氧化物半导体层从而形成沟道。
其中，通过控制所述蚀刻气体在所述源漏极层金属层的蚀刻速率和蚀刻时间，使得所述金属氧化物半导体层部分露出于所述沟道，其中，蚀刻速率和所述蚀刻时间均为预设值。
其中，所述蚀刻气体为SF6、O2、Cl2、He、Ar中一种或任意几种的混合。
其中，所述以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，使得蚀刻后的金属层具有源漏极层图案以所述光刻胶为遮蔽层，对所述源漏极层进行蚀刻，使得源漏极层图案化步骤中，包括在所述源漏极层金属层上喷淋蚀刻液进行蚀刻，在所述源漏极层金属层图案化后去除所述蚀刻液。
其中，所述蚀刻液包括H2O2、金属螯合剂或有机酸。
其中，所述去除所述半曝光区域处的光刻胶，以露出所述半曝光区域下方的所述金属层步骤中，包括对所述光刻胶进行灰化处理，使得所述半曝光区域处的光刻胶被去除。
其中，所述灰化处理包括将氧气激发成电浆与所述光刻胶反应，从而使得所述半曝光区域处的光刻胶被去除。
其中，所述去除所述光刻胶步骤中包括：采用灰化工艺或湿法蚀刻工艺将所述光刻胶去除。
其中，所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。
其中，所述金属氧化物半导体层采用IGZO材料。
本申请实施例具有如下优点或有益效果：
本申请的阵列基板的制造方法中，在源漏极金属层上涂覆光刻胶，通过多灰阶掩膜版在所述光刻胶上形成半曝光区域，以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，使得金属层具有源漏极层图案，然后将所述光刻胶的所述半曝光区域转化为全曝光区域，对半曝光区域下方的金属层进行干法蚀刻，以露出所述金属氧化物半导体层，从而在干法蚀刻以露出所述金属氧化物半导体层过程中不会对金属层造成损伤，提高了阵列基板的生产良率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的制造方法流程图。
图2～图8为图1的所示制造方法的过程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请以下实施例中所采用的序数限定词，第一、第二等仅是为了清楚地说明本申请中相似的特征的区别性的用语，不代表相应的特征的排列顺序或者使用顺序。
本申请的制造方法生产出的阵列基板可以应用于液晶显示屏或者有机显示屏中。本发明实施例涉及的柔性显示屏用于但不限于手机、平板电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)或电子阅读器等，本发明实施例对此不作具体限定。
请参阅图1，图1为本申请实施例提供的一种阵列基板的制造方法流程图。本申请提供的制造方法主要包括如下步骤：
步骤S001：在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层和金属层。
具体的，请结合参阅图2。所述基板10为透明玻璃基板，在所述基板10上沉积第一金属薄膜。所述第一金属薄膜可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。通过构图工艺利用普通光刻胶形成栅线(图未示出)、公共电极线(图未示出)和栅极20的图形。然后在此基础上通过PECVD(等离子体增强化学气相沉积法)方法沉积栅极绝缘层30，栅极绝缘层30可以选用氧化物、氮化物或者氧氮化合物等。
然后，在栅绝缘层30上通过溅射或热蒸发的方法沉积金属氧化物半导体层40，金属氧化物半导体层40可以是采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。优选的，可以选用IGZO材料制成。
接着，在基板10上采用溅射或热蒸发的方法形成金属层50。所述金属层50采用导电性好，且易于干刻的金属或合金。例如可以选用Al、Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。优选的，可以选用铜或铜合金材料制成。
步骤S002：在所述金属层上涂覆光刻胶。
可选的，所述光刻胶的厚度可以介于1.5um-2um之间，具体厚度可以依实际情况可以调整。
步骤S003：提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域。
具体的，请结合参阅图3。在所述金属层50上涂覆光刻胶60；提供一多灰阶掩膜版80遮盖在所述光刻胶60上方。可选的，所述多灰阶掩膜版70可以为半色调掩膜版(Half tone mask)或灰色调掩膜版(Gray tone mask)。对所述光刻胶60进行曝光、显影(即图案化)。所述多灰阶掩膜版80上设有全透光区域81、半透光区域82和不透光区域83。曝光光线经所述多灰阶掩膜版80后对所述光刻胶60进行光刻。请参阅图4，全透光区域81下方光刻胶60被完全光刻形成全曝光区域61，全曝光区域61下方的金属层50露出于所述光刻胶60。半透光区域82下方的光刻胶60被部分光刻从而形成半曝光区域62。不透光区域81下方光刻胶60被保留。也就是说，光刻胶60经过图案化后在其上形成半曝光区域81。
可选的，所述半曝光区域81的厚度可以介于0.5um-1um之间，具体厚度可以依实际情况可以调整。
S004：以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，蚀刻后的金属层具有源漏极层图案。
具体的，请参阅图5。可以在所述光刻胶60及金属层50上喷淋蚀刻液，蚀刻液经由光刻胶60上的全曝光区域61对金属层50进行蚀刻，直至将所述 金属层50形成具有源漏极层图案，最后去除所述蚀刻液完成所述金属层52的图案化过程。
优选的，所述蚀刻液可以选用H2O2、金属螯合剂或有机酸等。
S005：去除所述半曝光区域处的光刻胶，以露出所述半曝光区域下方的所述金属层。
请结合参阅图6。具体的，可以对所述光刻胶60进行灰化处理，使得所述半曝光区域62处的光刻胶被去除。可以理解的是，所述“灰化处理”即将氧气激发成电浆，再将激发成电浆的氧气与光刻胶反应，从而将所述光刻胶60整体打薄，光刻胶60整体打薄后，半曝光区域62处的光刻胶会首先被完全去除，即所述半曝光区域将会转化为全曝光区域62。此时，所述金属层50部分暴露于所述全曝光区域62。
S006：干法蚀刻所述半曝光区域下方露出的所述金属层，以露出所述金属氧化物半导体层从而形成沟道。
请结合参阅图7，在本步骤中，需要形成沟道53，以及在所述金属层50上形成了源极51和漏极52。具50体的，可以通过干法蚀刻的方法在所述金属层50上蚀刻出沟道53，所述金属氧化物半导体层40部分露出于所述沟道53。同时藉由所述沟道53形成源极51和漏极52。
进一步具体的，在干法蚀刻过程中，可以将蚀刻气体置于低压环境，并施以电压，将蚀刻气体激发成电浆，再对所述金属层50进行轰击，以蚀刻金属层50。由于光刻胶60的存在，位于全曝光区域62下方的金属层50会被蚀刻。位于光刻胶60下方除与全曝光区域62对应以外区域，由于有光刻胶60的存在，光刻胶60非全曝光区域下方的金属层50免于被蚀刻气体蚀刻。进一步的，可以通过控制蚀刻气体在金属层50上的蚀刻的时间来控制蚀刻的深度，直至将所述金属层50之位于全曝光区域62正下方的部分完全蚀刻，从而形成沟道53，并且所述金属氧化物半导体层40部分露出所述沟道53。其中，所述蚀刻时间为预设值。此时，通过沟道53将金属层50分为源极51和漏极52。
优选的，所述蚀刻气体可以根据金属层50选用的材料适当的选用，例如可以选择SF6、O2、Cl2、He、Ar(氩气)中一种或任意几种的混合等。
本申请中，通过干法蚀刻形成沟道过程中，光刻胶60可以起到保护金属层50其他部分的作用，避免金属层50由于干法蚀刻造成的表面质量下降，从 而提升阵列基板的性能。
S007：去除所述光刻胶。
请参阅图8，当金属氧化物半导体层40部分露出所述沟道53后，可以停止干法蚀刻，并去除所述光刻胶60，并继续后续步骤，完成阵列基板的制作。后续步骤不是本发明保护的重点，此处不再赘述。
去除光刻胶60可以采用湿法蚀刻工艺剥离所述光刻胶。该过程可以采用现有技术的光刻胶剥离方法，在此不再赘述。或者，还可以采用上述的灰化工艺去除所述光刻胶。
本申请的阵列基板的制造方法中，在金属层上涂覆光刻胶，通过多灰阶掩膜版在所述光刻胶上形成半曝光区域，以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，使得金属层具有源漏极层图案，然后将所述光刻胶的所述半曝光区域转化为全曝光区域，对半曝光区域下方的金属层进行干法蚀刻，以形成沟道并露出所述金属氧化物半导体层，从而在干法蚀刻以露出所述金属氧化物半导体层过程中不会对金属层造成损伤，提高了阵列基板的生产良率。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (11)

  1. 一种阵列基板的制造方法，其特征在于，所述方法包括：
    在基板上依次形成栅极、栅极绝缘层、金属氧化物半导体层和金属层；
    在所述金属层上涂覆光刻胶；
    提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述光刻胶进行图案化，以在所述光刻胶上形成半曝光区域；
    以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，使得蚀刻后的金属层具有源漏极层图案；
    去除所述半曝光区域处的光刻胶，以露出所述半曝光区域下方的所述金属层；
    干法蚀刻所述半曝光区域下方露出的所述金属层，以露出所述金属氧化物半导体层从而形成沟道；
    去除所述光刻胶。
  2. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述干法蚀刻所述半曝光区域下方露出的所述金属层，以露出所述金属氧化物半导体层从而形成沟道步骤中，包括使用蚀刻气体对所述金属层之露出于所述全曝光区域的部分进行轰击，以露出所述金属氧化物半导体层从而形成沟道以露出所述金属氧化物半导体层从而形成沟道。
  3. 如权利要求2所述的阵列基板的制造方法，其特征在于，通过控制所述蚀刻气体在所述金属层的蚀刻时间，使得所述金属氧化物半导体层部分露出于所述沟道，其中，所述蚀刻时间为预设值。
  4. 如权利要求2所述的阵列基板的制造方法，其特征在于，所述蚀刻气体为SF6、O2、Cl2、He、Ar中一种或任意几种的混合。
  5. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述以所述光刻胶为遮蔽层，对所述金属层进行蚀刻，使得蚀刻后的金属层具有源漏极层图案步骤中，包括在所述金属层上喷淋蚀刻液进行蚀刻，在所述金属层图案化后去除所述蚀刻液。
  6. 如权利要求5所述的阵列基板的制造方法，其特征在于，所述蚀刻液包括H2O2、金属螯合剂或有机酸。
  7. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述去除所述半曝光区域处的光刻胶，以露出所述半曝光区域下方的所述金属层步骤中，包括对所述光刻胶进行灰化处理，使得所述半曝光区域处的光刻胶被去除。
  8. 如权利要求7所述的阵列基板的制造方法，其特征在于，所述灰化处理包括将氧气激发成电浆与所述光刻胶反应，从而使得所述半曝光区域处的光刻胶被去除。
  9. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述去除所述光刻胶步骤中包括：采用灰化工艺或湿法蚀刻工艺将所述光刻胶去除。
  10. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。
  11. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述金属氧化物半导体层采用IGZO材料。
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