WO2018082363A1 - 导电粒子、各向异性导电膜层和显示装置及其制造方法 - Google Patents

导电粒子、各向异性导电膜层和显示装置及其制造方法 Download PDF

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Publication number
WO2018082363A1
WO2018082363A1 PCT/CN2017/097990 CN2017097990W WO2018082363A1 WO 2018082363 A1 WO2018082363 A1 WO 2018082363A1 CN 2017097990 W CN2017097990 W CN 2017097990W WO 2018082363 A1 WO2018082363 A1 WO 2018082363A1
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Prior art keywords
layer
conductive film
anisotropic conductive
fluorescent
conductive particles
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English (en)
French (fr)
Inventor
倪欢
吕凤珍
张新霞
郭霄
李群
解晓龙
姚成鹏
李明光
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/752,107 priority Critical patent/US10866613B2/en
Publication of WO2018082363A1 publication Critical patent/WO2018082363A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1601—Constructional details related to the housing of computer displays, e.g. of CRT monitors, of flat displays
    • G06F1/1607—Arrangements to support accessories mechanically attached to the display housing
    • G06F1/1609—Arrangements to support accessories mechanically attached to the display housing to support filters or lenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/16—Optical coatings produced by application to, or surface treatment of, optical elements having an anti-static effect, e.g. electrically conducting coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
    • H01B5/14—Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B2207/00—Coding scheme for general features or characteristics of optical elements and systems of subclass G02B, but not including elements and systems which would be classified in G02B6/00 and subgroups
    • G02B2207/113—Fluorescence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0221—Insulating particles having an electrically conductive coating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • the present disclosure relates to a conductive particle, an anisotropic conductive film layer, and a display device and a method of fabricating the same.
  • the pins of the integrated circuit chip and the outer leads of the array substrate are joined to each other by foot-to-foot, and an anisotropic conductive film layer is used as a medium in the middle, using, for example, heat.
  • the way of pressing causes the pins of the integrated circuit chip and the outer pins of the array substrate to be turned on.
  • the conductive particles in the anisotropic conductive film layer are crushed, so that the pins of the integrated circuit chip and the outer leads of the array substrate are connected.
  • the conductive particles themselves have a small electrical resistance, and the on-resistance depends on the contact resistance between the conductive particles and the outer leads of the array substrate and the number of conductive particles on the outer leads of the array substrate.
  • the compression ratio is larger within a certain range, and the contact area is larger. The smaller the contact resistance.
  • the pressure is too small, the heat conduction is insufficient, the resin cannot be completely reacted, the conductive particles in the anisotropic conductive film layer are less deformed, the compression ratio is small, and the conduction is small.
  • the contact resistance of the particles is large, and the leads of the integrated circuit chip and the outer leads of the array substrate are not conductive; if the pressure is too large, the conductive particles in the anisotropic conductive film layer are too fragmented, which makes the integrated circuit easy.
  • the pins of the chip are connected to the outer pins of the array substrate and then disconnected, and when the display device operates in a high temperature environment, the integrated circuit chip is deformed, which will cause the pins of the integrated circuit chip and the outer pins of the array substrate.
  • the distance increases, the elasticity of the conductive particles disappears, and a short circuit occurs between the pins of the integrated circuit chip and the outer pins of the array substrate.
  • the present disclosure provides a conductive particle, an anisotropic conductive film layer, and a display device and a method of fabricating the same, which can facilitate monitoring the degree of breakage of conductive particles during pressurization and improve the yield of the display device during the preparation process.
  • the present disclosure provides a conductive particle having a core of a fluorescent resin core.
  • the fluorescent resin core of each conductive particle is coated with at least one opaque layer.
  • At least one of the opaque layers is an opaque conductive layer.
  • the opaque conductive layer is an opaque metal layer.
  • the material of the fluorescent resin core is a fluorescent polymer material.
  • the fluorescent polymer material is polyaniline or polythiophene.
  • the inner core of each of the conductive particles is coated with a nickel layer, and the nickel layer is coated with a gold plating layer.
  • the present disclosure provides an anisotropic conductive film layer comprising an adhesive layer, wherein the adhesive layer is provided with a plurality of conductive particles according to any one of the above.
  • the present disclosure provides a display device including an array substrate and an integrated circuit chip, further comprising: the anisotropic conductive film layer described above, wherein the anisotropic conductive film layer is used to The outer leads of the substrate are in communication with the pins of the integrated circuit chip.
  • the present disclosure also provides a method for preparing an anisotropic conductive film layer, comprising:
  • a plurality of the conductive particles are bonded by an adhesive to form an adhesive layer.
  • the method for preparing the anisotropic conductive film layer further comprises: coating a plurality of conductive particles having a core of a fluorescent resin core with at least one opaque layer.
  • At least one of the opaque layers is an opaque metal layer.
  • the fluorescent resin core is formed by doping a phosphor and a quantum dot phosphor into a resin.
  • the fluorescent resin core is formed by grafting fluorescent small molecules into a resin segment.
  • the fluorescent resin core is formed using a fluorescent polymer material.
  • the fluorescent polymer material is polyaniline or polythiophene.
  • the present disclosure further provides a method of manufacturing a display device, comprising: an array substrate, an integrated circuit chip, and an anisotropic conductive film layer as described above, the manufacturing method comprising: a pin of the integrated circuit chip and an outer pin of the array substrate are joined to the foot, and the anisotropic conductive film layer is disposed between the pin and the outer pin; An integrated circuit chip provided with an indenter extrusion on the opposite side of the anisotropic conductive film side An anisotropic conductive film layer, while emitting excitation light to the conductive particles by using a light source emitting device and monitoring fluorescence emitted by the conductive particles by using a monitoring device; when the detected fluorescence intensity of the fluorescent light reaches a predetermined value, The pressing of the indenter is stopped such that the outer leads of the array substrate and the pins of the integrated circuit chip are in communication.
  • the predetermined value ranges from 1 nit to 10 nit.
  • FIG. 1 is a schematic structural view of conductive particles provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing changes in conductivity of conductive particles provided by an embodiment of the present disclosure
  • 3a-3f are schematic diagrams showing the breakdown of conductive particles as a function of compression ratio according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural view of an anisotropic conductive film layer according to an embodiment of the present disclosure
  • 5a to 5b are schematic diagrams showing changes of conductive particles in an anisotropic conductive film layer before and after compression according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a state in which a pin of an integrated circuit chip and an outer lead of an array substrate are heat-pressed and bonded according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of conductive particles provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a conductive particle 1 , and the core 11 of the conductive particle 1 is a fluorescent resin core.
  • the fluorescent resin core of each of the conductive particles 11 is coated with at least one opaque layer.
  • the at least one opaque layer is an opaque conductive layer.
  • the opaque conductive layer is an opaque metal layer.
  • the conductive particle 1 provided by the embodiment of the present disclosure adopts a fluorescent resin core as the core 11 of the conductive particle 1, and when the conductive particle is not broken, since the fluorescent resin core is coated by the opaque layer, no fluorescence is emitted, when the conductive After the particles are broken, the fluorescent resin core is at least partially exposed, and the laser light can be received, so that the degree of cracking of the conductive particles 1 can be monitored by monitoring the change of the fluorescence during the hot pressing, thereby reducing the conductive connection of the conductive particles 1 due to insufficient pressure. It is good or the pressure has almost caused the phenomenon that the conductive particles 1 are broken and lose conductivity.
  • the conductive particles provided by the embodiments of the present disclosure have better conductivity and can improve the yield of the display device during the preparation process.
  • the conductive particles 1 provided by the present disclosure gradually increase the degree of damage of the conductive particles 1 during hot pressing, and monitor the degree of rupture of the conductive particles 1 by monitoring the change of fluorescence during the hot pressing, thereby avoiding the connection failure due to insufficient pressure, or When the pressure is too large and the compression ratio is too large, the conductive particles 1 are excessively broken and the phenomenon of poor conductivity is lost due to the disappearance of elasticity.
  • FIG. 2 is a schematic diagram showing changes in conductivity of conductive particles according to an embodiment of the present disclosure
  • FIG. 3a to FIG. 3f are diagrams showing that conductive particles according to the embodiments of the present disclosure are broken with a change in compression ratio.
  • the material of the above fluorescent resin core may be various.
  • the material of the fluorescent resin core is a fluorescent polymer material.
  • the fluorescent polymer material may be polyaniline or polythiophene.
  • the above-mentioned fluorescent resin core may be formed by doping a phosphor and a quantum dot fluorescent substance into a resin, or may be formed by grafting a fluorescent small molecule into a resin segment.
  • the core 11 of each of the conductive particles 1 is coated with a nickel layer 12, and the nickel layer 12 is covered with a gold layer 13. That is, the gold plating process is formed outside the nickel layer, and the gold plating layer outside the nickel layer functions as a conductive layer.
  • FIG. 4 is a schematic structural diagram of an anisotropic conductive film layer according to an embodiment of the present disclosure; an embodiment of the present disclosure further provides an anisotropic conductive film layer 2, including an adhesive layer 21, and bonded. A plurality of conductive particles 1 described in the above embodiments are provided in the layer 21.
  • the adhesive layer functions to prevent moisture, heat, insulation, and maintain contact area between the electrode and the conductive particles.
  • the anisotropic conductive film layer 2 further includes a bottom mold 22 which is disposed to protect the adhesive layer 21 from external contamination when the anisotropic conductive film layer is prepared.
  • the embodiment of the present disclosure further provides a method for preparing an anisotropic conductive film layer, including:
  • the plurality of conductive particles are bonded by an adhesive to form an adhesive layer.
  • the formation of the above adhesive layer may be performed by extrusion molding, and the conductive particles may also be formed by sequentially coating a material layer, which is first formed into a core of a fluorescent resin core, and then sequentially coated with nickel outside the core to form a nickel layer, and then in nickel.
  • the layer is gold plated to form a gold layer.
  • the fluorescent resin core is formed by doping a phosphor and a quantum dot phosphor into the resin.
  • the fluorescent resin core is formed by grafting fluorescent small molecules into the resin segment.
  • the fluorescent resin core is formed using a fluorescent polymer material.
  • the fluorescent polymer material is polyaniline or polythiophene.
  • an embodiment of the present disclosure further provides a display device including an array substrate 3 and an integrated circuit chip 6, and further comprising: the anisotropic conductive film layer 2 described above, anisotropic conductive
  • the film layer 2 is for connecting the outer leads 31 of the array substrate 3 and the leads 61 of the integrated circuit chip 6.
  • the display device generally includes a color filter substrate 4 disposed in alignment with the array substrate 3.
  • the conductive particles 1 in the anisotropic conductive film layer 2 are made of a fluorescent resin core. 11.
  • the pressure can be monitored in real time during the hot pressing stage to avoid excessive or too small pressure, and the connection between the lead 61 of the integrated circuit chip 6 and the outer lead of the array substrate 3 is improved.
  • the display device provided by the embodiment of the present disclosure has a better display effect.
  • the embodiment further provides a method for manufacturing the above display device, comprising: bonding the pins of the integrated circuit chip and the outer pins of the array substrate as foot-to-foot, and providing anisotropy between the pins and the outer pins Conductive film layer;
  • the pressing of the indenter is stopped, so that the outer lead of the array substrate and the pin of the integrated circuit chip are in communication.
  • the predetermined value is 1 nit to 10 nit.
  • the pins 61 of the integrated circuit chip 6 and the outer leads 31 of the array substrate 3 are required to be foot-to-foot bonding, and the anisotropic conductive film layer 2 is used as a medium.
  • the conductive particles 1 in the anisotropic conductive film layer 2 are pressed by, for example, hot pressing by the indenter 5 disposed on the opposite side of the integrated circuit chip 6 on which the anisotropic conductive film side 2 is provided, usually under pressure
  • a buffer material layer 8 is placed between the head 5 and the integrated circuit chip 6.
  • the conductive particles 1 are deformed, and the pins 61 of the integrated circuit chip 6 and the outer leads 31 of the array substrate 3 can be placed.
  • the light source emitting device integrated into the monitoring device 7 for example, a light source emitting device that emits ultraviolet light or visible light, emits excitation light to the conductive particles and monitors the fluorescence emitted by the conductive particles by the monitoring device 7, due to the conductive particles (1)
  • the fluorescent resin is used as the core 11, so that when the conductive particles 1 in the anisotropic conductive film layer 2 are pressed by means of hot pressing, the degree of cracking of the conductive particles 1 can be monitored by monitoring the change in fluorescence by the monitoring device 7.
  • the pressure is insufficient, causing the occurrence of an open circuit of the pins of the integrated circuit chip 6 and the outer leads 31 of the array substrate 3, and the occurrence of a phenomenon in which the pressure is excessively large, the conductive particles 1 are broken, and the connectivity is lost.
  • the monitoring device 7 may be disposed on one side of the array substrate, but in practice, as long as the light emitted by the monitoring device can be directed to the conductive particles and it is capable of receiving the fluorescence emitted by the conductive particles.
  • the monitoring device emits excitation light to the conductive particles.
  • the fluorescent resin core in the conductive particles is not excited.
  • the excitation light excites the fluorescent resin core in the conductive particles.
  • the monitoring device receives the fluorescence, and according to experience, the degree of rupture of the conductive particles corresponding to different fluorescence intensities and the corresponding relationship of the pressures can be formed.
  • the conductive particles are monitored, the fluorescence intensity obtained according to the experience and the corresponding relationship can be obtained according to experience. The degree of damage of the conductive particles is obtained.
  • the fluorescence intensity measured by the monitoring device is proportional to the degree of rupture of the corresponding conductive particles, and the greater the degree of rupture of the conductive particles, the higher the fluorescence intensity measured by the monitoring device, and the fluorescence intensity corresponding to the degree of rupture of the conductive particles of FIG. 3d, for example. It can be in the range of 1 nit to 10 nit.
  • the fluorescence intensity measured by the monitoring device 7 is small, and at this time, the pressure is continuously applied, and when the fluorescence intensity measured by the monitoring device 7 reaches a range of 1 nit to 10 nit, The degree of rupture of the conductive particles reaches a state of 3d. At this time, the application of the pressure is stopped, and the pin connection process between the outer leads of the array substrate and the integrated circuit chip is completed, because if the pressure is continuously applied, the degree of rupture of the conductive particles will change. Large enough to break the conductive particles and lose connectivity.
  • the conductive particles provided by the present disclosure can monitor the degree of cracking of the conductive particles by monitoring the change of the fluorescence during the hot pressing by using the fluorescent resin core as the core of the conductive particles, thereby reducing the conductivity.
  • the phenomenon that the electric particles are not sufficiently conductive due to insufficient pressure or the pressure is excessively caused to cause the conductive particles to rupture and lose conductivity.
  • the conductive particles provided by the present disclosure have better conductivity and can improve the yield of the display device during the preparation process.

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Abstract

一种导电粒子、各向异性导电膜和显示装置及其制造方法，可以便于对热压过程中导电粒子的破裂程度进行监测，提高显示装置在制备过程中的成品率。该导电粒子（1）的内核（11）为荧光树脂核。对于该导电粒子（1），通过采用荧光树脂核作为导电粒子（1）的内核（11），可以通过监测热压过程中荧光的变化来监控导电粒子（1）的破裂程度，从而减少导电粒子（1）因压力不够导电连接性不好或压力过大致使导电粒子（1）破裂失去导电性的现象的发生。

Description

导电粒子、各向异性导电膜层和显示装置及其制造方法 技术领域
本公开涉及一种导电粒子、各向异性导电膜层和显示装置及其制造方法。
背景技术
在对阵列基板的外引脚进行贴合的技术中，将集成电路芯片的引脚和阵列基板的外引脚作脚对脚的接合，中间使用各向异性导电膜层作为媒介，利用例如热压的方式使集成电路芯片的引脚和阵列基板的外引脚导通。在对各向异性导电膜层进行加热、加压过程中，各向异性导电膜层中的导电粒子被压扁，可使得集成电路芯片的引脚和阵列基板的外引脚连通。
导电粒子自身的电阻小，导通电阻取决于导电粒子与阵列基板的外引脚的接触电阻以及阵列基板的外引脚上的导电粒子数目，压缩率在一定范围内越大，接触面积越大，接触电阻越小。
但是，在对各向异性导电膜层进行例如热压过程中，如果压力太小，热传导不够，树脂不能反应完全，各向异性导电膜层中的导电粒子形变较小，压缩率较小，导电粒子的接触电阻较大，导致集成电路芯片的引脚和阵列基板的外引脚不能导通；如果压力太大，各向异性导电膜层中的导电粒子碎裂程度太过，容易使得集成电路芯片的引脚和阵列基板的外引脚连接后又断开，而且当显示装置在高温环境下工作时，集成电路芯片变形，将导致集成电路芯片的引脚和阵列基板的外引脚之间的距离增大，导电粒子弹性消失，集成电路芯片的引脚和阵列基板的外引脚之间出现短路。
现有技术中，不便于对导电粒子的受损情况进行实时监测，也就不便于控制对阵列基板的外引脚进行贴合时的压力的大小，故容易造成显示装置在制备过程中成品率较低。
发明内容
本公开提供了一种导电粒子、各向异性导电膜层和显示装置及其制造方法，可以便于对加压过程中导电粒子的破裂程度进行监测，提高显示装置在制备过程中的成品率。
一方面，本公开提供了一种导电粒子，所述导电粒子的内核为荧光树脂核。
例如，每个导电粒子的荧光树脂核外包覆有至少一层不透光层。
例如，至少一层不透光层为不透光导电层。
例如，不透光导电层为不透光金属层。
在一些可选的实施方式中，所述荧光树脂核的材料为荧光高分子材料。
在一些可选的实施方式中，所述荧光高分子材料为聚苯胺或聚噻吩。
在一些可选的实施方式中，每个所述导电粒子的内核外包覆有镍层，所述镍层外包覆有镀金层。
另一方面，本公开还提供了一种各向异性导电膜层，包括粘合层，所述粘合层内设有多个如上述任一项所述的导电粒子。
再一方面，本公开还提供了一种显示装置，包括阵列基板和集成电路芯片，还包括：上述所述的各向异性导电膜层，所述各向异性导电膜层用于将所述阵列基板的外引脚和所述集成电路芯片的引脚连通。
再一方面，本公开还提供了一种各向异性导电膜层的制备方法，包括：
形成多个内核为荧光树脂核的导电粒子；
将多个所述导电粒子之间通过粘合胶粘合形成粘合层。
例如，该各向异性导电膜层的制备方法，还包括：将多个内核为荧光树脂核的导电粒子外包覆至少一层不透光层。
例如，至少一层不透光层为不透光金属层。
在一些可选的实施方式中，所述荧光树脂核通过将荧光粉和量子点荧光物掺杂入树脂中形成。
在一些可选的实施方式中，所述荧光树脂核通过将荧光小分子接枝于树脂链段中形成。
在一些可选的实施方式中，所述荧光树脂核采用荧光高分子材料形成。
在一些可选的实施方式中，所述荧光高分子材料为聚苯胺或聚噻吩。
再一方面，本公开还提供了一种显示装置的制造方法，该显示装置包括：阵列基板、集成电路芯片以及如上任意所述的各向异性导电膜层，该制造方法，包括：将所述集成电路芯片的引脚和所述阵列基板的外引脚作脚对脚的接合，所述引脚与所述外引脚之间设置有所述各向异性导电膜层；利用设置在所述集成电路芯片的设置有所述各向异性导电膜侧的相反侧的压头挤压所 述各向异性导电膜层，同时利用光源发射装置向所述导电粒子发射激发光且利用监测装置监测所述导电粒子发射的荧光；当监测到的所述荧光的荧光强度达到一预定值时，停止所述压头的挤压，使得所述阵列基板的外引脚和所述集成电路芯片的引脚连通。
例如，该预定值的范围为1nit～10nit。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例提供的导电粒子的结构示意图；
图2为本公开实施例提供的导电粒子的导电率变化示意图；
图3a～图3f为本公开实施例提供的导电粒子随压缩率变化破裂示意图；
图4为本公开实施例提供的各向异性导电膜层的结构示意图；
图5a～图5b为本公开实施例提供的各向异性导电膜层内的导电粒子受压前后变化示意图；
图6a～图6b为本公开实施例提供的集成电路芯片的引脚和阵列基板的外引脚进行热压贴合的状态示意图。
图中：
1-导电粒子                               11-内核
12-镍层                                  13-镀金层
2-各向异性导电膜层                       21-粘合层
22-底模                                  3-阵列基板
31-外引脚                                4-彩膜基板
5-压头                                   6-集成电路芯片
61-引脚                                  7-监测装置
8-缓冲材料层
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开专利保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。
实施例一
如图1所示，图1为本公开实施例提供的导电粒子的结构示意图；本公开实施例提供了一种导电粒子1，导电粒子1的内核11为荧光树脂核。
例如，每个所述导电粒子11的所述荧光树脂核外包覆有至少一层不透光层。
例如，所述至少一层不透光层为不透光导电层。
例如，所述不透光导电层为不透光金属层。
本公开实施例提供的导电粒子1，通过采用荧光树脂核作为导电粒子1的内核11，在导电粒子未破裂时，由于荧光树脂核被不透光层包覆，所以不会发出荧光，当导电粒子破裂后，荧光树脂核至少部分被暴露，可以接受到激光光，从而可以通过监测热压过程中荧光的变化来监控导电粒子1的破裂程度，从而减少导电粒子1因压力不够导电连接性不好或压力过大致使导电粒子1破裂失去导电性的现象的发生。
所以，本公开实施例提供的导电粒子，具有较好的导电性，可以提高显示装置在制备过程中的成品率。
本公开提供的导电粒子1，在热压过程中，导电粒子1的破损程度逐步增加，通过监测热压过程中的荧光变化来监控导电粒子1破裂程度，从而避免出现因为压力不够连接不良，抑或压力过大，压缩率过大导致的导电粒子1碎裂太多及弹性消失导致的导通性不良的现象的发生。如图2和图3a～图3f所示，其中：图2为本公开实施例提供的导电粒子的导电率变化示意图；图3a～图3f为本公开实施例提供的导电粒子随压缩率变化破裂示意图；从图2上可以看出，导电粒子1在0％-30％压缩率之间电阻随压缩率的增加迅速降低，对应的导电粒子1受压后的受损程度如图3a和图3b所示，导电粒子1在30％-55％压缩率之间电阻随压缩率的增加缓慢降低，达到最佳效果，对应的导电粒子1受压后的受损程度如图3c和图3d所示，继续增加压缩率，导电粒子1将被压碎，丧失导电能力，对应的导电粒子1受压后的受损程度如图3e和3f所示，此时导电粒子1失去连通性，将造成断路，引发显示装置中电路连接不良。
上述荧光树脂核的材料可以有多种，可选的，荧光树脂核的材料为荧光高分子材料。
可选的，上述荧光高分子材料可以为聚苯胺或聚噻吩。
上述荧光树脂核可以通过将荧光粉和量子点荧光物掺杂入树脂中形成，也可以通过将荧光小分子接枝于树脂链段中形成。
如图1所示，每个导电粒子1的内核11外包覆有镍层12，镍层12外包覆有金层13。即采用镀金工艺形成在镍层外，镍层其外的镀金层起到导电的作用。
实施例二
如图4所示，图4为本公开实施例提供的各向异性导电膜层的结构示意图；本公开实施例还提供了一种各向异性导电膜层2，包括粘合层21，粘合层21内设有多个以上实施例所述的导电粒子1。粘合层功能可以防湿气、防热、绝缘、维持电极与导电粒子间的接触面积。
通常各向异性导电膜层2还包括：底模22，底模22的设置可以保护在制备各向异性导电膜层时粘结层21免受外界污染。
实施例三
本公开实施例还提供了一种各向异性导电膜层的制备方法，包括：
形成多个内核为荧光树脂核的导电粒子；
将多个导电粒子之间通过粘合胶粘合形成粘合层。
上述粘合层的形成可以涂覆挤压成型，导电粒子也可以通过依次涂覆材料层形成，先形成为荧光树脂核的内核，再在内核外依次涂覆镍，形成镍层，再在镍层镀金形成金层。
一种可选的实施方式中，荧光树脂核通过将荧光粉和量子点荧光物掺杂入树脂中形成。
一种可选的实施方式中，荧光树脂核通过将荧光小分子接枝于树脂链段中形成。
一种可选的实施方式中，荧光树脂核采用荧光高分子材料形成。
可选的，上述荧光高分子材料为聚苯胺或聚噻吩。
实施例四
如图6a和图6b所示，本公开实施例还提供了一种显示装置，包括阵列基板3和集成电路芯片6，还包括：上述所述的各向异性导电膜层2，各向异性导电膜层2用于将阵列基板3的外引脚31和集成电路芯片6的引脚61连通。上述显示装置一般还包括与阵列基板3对合设置的彩膜基板4，由于本公开实施例提供的显示装置中，使用的各向异性导电膜层2中的导电粒子1采用荧光树脂核作为内核11，可以在制作显示装置过程中，在热压阶段实时监测压力的大小，避免压力过大或过小，提高集成电路芯片6的引脚61和阵列基板3的外引脚之间连接的稳定性，故本公开实施例提供的显示装置具有较好的显示效果。
该实施例还提供一种上述显示装置的制造方法，包括：将集成电路芯片的引脚和阵列基板的外引脚作脚对脚的接合，引脚与外引脚之间设置有各向异性导电膜层；
利用设置在集成电路芯片的设置有各向异性导电膜侧的相反侧的压头挤压所述各向异性导电膜层，同时利用光源发射装置向所述导电粒子发射激发光且利用监测装置监测所述导电粒子发射的荧光；
当监测到的所述荧光的荧光强度达到一预定值时，停止所述压头的挤压，使得所述阵列基板的外引脚和所述集成电路芯片的引脚连通。
例如，所述预定值为1nit～10nit。
下面结合附图对以上制造方法进行示例性说明。
如图5a～图5b和图6a～图6b所示，在显示装置的制造方法中，在对阵列 基板3的外引脚进行贴合的技术中，需要将集成电路芯片6的引脚61和阵列基板3的外引脚31作脚对脚的接合，中间使用各向异性导电膜层2作为媒介，通过设置在集成电路芯片6的设置有各向异性导电膜侧2的相反侧的压头5利用例如，热压的方式挤压各向异性导电膜层2中的导电粒子1，通常在压头5和集成电路芯片6之间会放置缓冲材料层8，在压头挤压过程中，导电粒子1将发生形变，可以将集成电路芯片6的引脚61和阵列基板3的外引脚31导通。同时，利用集成到监测装置7的光源发射装置，例如，发射紫外光或可见光的光源发射装置，向所述导电粒子发射激发光且利用监测装置7监测所述导电粒子发射的荧光，由于导电粒子1采用荧光树脂作为内核11，故在利用热压的方式挤压各向异性导电膜层2中的导电粒子1时，可以通过监测装置7监测荧光的变化来监控导电粒子1的破裂程度，减少压力不够，造成集成电路芯片6的引脚和阵列基板3的外引脚31断路现象的发生，以及减少压力过大，导电粒子1被破损，失去连通性的现象的发生。
例如，监测装置7可以设置在阵列基板的一侧，但实际中，只要该监测装置发射的光能够射向导电粒子且其能够接收到导电粒子发射的荧光即可。
例如，监测装置会发出激发光射向导电粒子，导电粒子在未破裂时，导电粒子内的荧光树脂核不会被激发，当导电粒子破裂时，激发光会激发导电粒子内的荧光树脂核，监测装置会接收到荧光，根据经验可以形成不同荧光强度对应的导电粒子破裂程度以及所受压力的对应关系式，再监测导电粒子时，可以根据预先根据经验得到的荧光强度以及对应的关系式，得到导电粒子的破损程度。
例如，监测装置测量的荧光强度和对应的导电粒子破裂程度成正比，导电粒子的破裂程度越大，监测装置测到的荧光强度越高，对应于图3d的导电粒子的破裂程度的荧光强度例如可以在1nit～10nit的范围内。
例如，当对应于图3a-图3c的状态，监测装置7测到的荧光强度较小，这时候压头继续施加压力，当监测装置7测到的荧光强度达到1nit～10nit的范围时，说明导电粒子破裂程度达到了3d的状态，此时停止施加压力，完成了阵列基板的外引脚和所述集成电路芯片的引脚连通过程，因为如果继续施加压力，则导电粒子的破裂程度将变大而使得导电粒子破损而失去连通性。
本公开提供的导电粒子，通过采用荧光树脂核作为导电粒子的内核，可以通过监测热压过程中荧光的变化来监控导电粒子的破裂程度，从而减少导 电粒子因压力不够导电连接性不好或压力过大致使导电粒子破裂失去导电性的现象的发生。
所以，本公开提供的导电粒子，具有较好的导通性，可以提高显示装置在制备过程中的成品率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
本申请要求于2016年11月1日提交的中国专利申请第201610943540.2的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。

Claims (18)

  1. 一种导电粒子，所述导电粒子的内核为荧光树脂核。
  2. 根据权利要求1所述的导电粒子，其中每个所述导电粒子的所述荧光树脂核外包覆有至少一层不透光层。
  3. 根据权利要求2所述的导电粒子，其中所述至少一层不透光层为不透光导电层。
  4. 根据权利要求3所述的导电粒子，其中所述不透光导电层为不透光金属层。
  5. 根据权利要求4所述的导电粒子，其中每个所述导电粒子的内核外包覆有镍层，所述镍层外包覆有金层。
  6. 根据权利要求1所述的导电粒子，其中所述荧光树脂核的材料为荧光高分子材料。
  7. 根据权利要求6所述的导电粒子，其中所述荧光高分子材料为聚苯胺或聚噻吩。
  8. 一种各向异性导电膜层，包括粘合层，其中所述粘合层内设有多个如权利要求1-7中任一项所述的导电粒子。
  9. 一种显示装置，包括：
    阵列基板和集成电路芯片；
    各向异性导电膜层，如权利要求8所述，其中所述各向异性导电膜层用于将所述阵列基板的外引脚和所述集成电路芯片的引脚连通。
  10. 一种各向异性导电膜层的制备方法，包括：
    形成多个内核为荧光树脂核的导电粒子；
    将多个所述导电粒子之间通过粘合胶粘合形成粘合层。
  11. 根据权利要求10所述的各向异性导电膜层的制备方法，还包括：将多个内核为荧光树脂核的导电粒子外包覆至少一层不透光层。
  12. 根据权利要求11所述的各向异性导电膜层的制备方法，其中所述至少一层不透光层为不透光金属层。
  13. 根据权利要求10-12中任一项所述的各向异性导电膜层的制备方法，其中荧光树脂核通过将荧光粉和量子点荧光物掺杂入树脂中形 成。
  14. 根据权利要求10-12中任一项所述的各向异性导电膜层的制备方法，其中所述荧光树脂核通过将荧光小分子接枝于树脂链段中形成。
  15. 根据权利要求10-12中任一项所述的各向异性导电膜层的制备方法，其中所述荧光树脂核采用荧光高分子材料形成。
  16. 根据权利要求15所述的各向异形导电膜的制备方法，其中所述荧光高分子材料为聚苯胺或聚噻吩。
  17. 一种显示装置的制造方法，该显示装置包括：阵列基板、集成电路芯片以及如权利要求8所述的各向异性导电膜层，
    该制造方法，包括：
    将所述集成电路芯片的引脚和所述阵列基板的外引脚作脚对脚的接合，所述引脚与所述外引脚之间设置有所述各向异性导电膜层；
    利用设置在所述集成电路芯片的设置有所述各向异性导电膜侧的相反侧的压头挤压所述各向异性导电膜层，同时利用光源发射装置向所述导电粒子发射激发光且利用监测装置监测所述导电粒子发射的荧光；
    当监测到的所述荧光的荧光强度达到一预定值时，停止所述压头的挤压，使得所述阵列基板的外引脚和所述集成电路芯片的引脚连通。
  18. 根据权利要求17所述的显示装置的制造方法，其中所述预定值的范围为1nit～10nit。
PCT/CN2017/097990 2016-11-01 2017-08-18 导电粒子、各向异性导电膜层和显示装置及其制造方法 Ceased WO2018082363A1 (zh)

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CN106782758B (zh) * 2017-01-05 2018-09-25 京东方科技集团股份有限公司 导电粒子及其制造方法和各向异性导电胶
CN118642289B (zh) * 2024-08-16 2025-02-28 Tcl华星光电技术有限公司 显示面板和显示装置

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