WO2018076722A1 - 一种倒装芯片封装的片上系统 - Google Patents

一种倒装芯片封装的片上系统 Download PDF

Info

Publication number
WO2018076722A1
WO2018076722A1 PCT/CN2017/089079 CN2017089079W WO2018076722A1 WO 2018076722 A1 WO2018076722 A1 WO 2018076722A1 CN 2017089079 W CN2017089079 W CN 2017089079W WO 2018076722 A1 WO2018076722 A1 WO 2018076722A1
Authority
WO
WIPO (PCT)
Prior art keywords
protection circuit
wire
bump
chip
core
Prior art date
Application number
PCT/CN2017/089079
Other languages
English (en)
French (fr)
Inventor
杨劲松
Original Assignee
深圳市中兴微电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市中兴微电子技术有限公司 filed Critical 深圳市中兴微电子技术有限公司
Publication of WO2018076722A1 publication Critical patent/WO2018076722A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Definitions

  • the present invention relates to the field of electronic product technologies, and in particular, to a system for a flip-chip package.
  • SOC System On a Chip
  • the internal signal of the chip must be connected to the packaged BUMP (a bump used in the chip package technology called BUMP process) or a bonding pad (a type of wire) through the input and output unit.
  • BUMP bump used in the chip package technology
  • a bonding pad a type of wire
  • the input and output unit is an important part of the SOC design, which occupies part of the chip area. In the SOC technology, reducing the chip area is a major way to reduce the development cost.
  • an embodiment of the present invention provides a system for on-chip package flip-chip, which can be reduced.
  • the use of input and output units reduces the size of the on-chip system chip.
  • Embodiments of the present invention provide a system for a flip-chip package, the first IP core of the system-on-chip is connected to an analog power supply BUMP and an analog ground BUMP, and the first IP core and the analog power supply BUMP pass through the first wire.
  • the first IP core and the analog ground BUMP are connected by a second wire, and a first protection circuit is connected between the first wire and the second wire.
  • the digital ground BUMP is connected to the second wire through the second protection circuit.
  • the distance between the first protection circuit and the analog power supply BUMP is much smaller than the distance between the first protection circuit and the IP core; the first protection circuit and the analog ground BUMP The distance between them is much smaller than the distance between the first protection circuit and the IP core.
  • the first wire and/or the second wire is a multilayer metal wire.
  • the resistance between the analog power supply BUMP and the analog ground BUMP is less than 0.2 ohms.
  • the digital ground BUMP and the second protection circuit are connected by a plurality of metal wires, and the second protection circuit and the second wire are connected by a plurality of metal wires.
  • the resistance of the digital ground BUMP through the second protection circuit to the analog ground BUMP is less than 0.2 ohms.
  • the first protection circuit includes a detection portion, a trigger portion, and a release portion.
  • the detecting portion includes an RC detecting circuit
  • the trigger portion includes an inverter circuit
  • the releasing portion includes a field effect transistor
  • the second protection circuit includes two diodes connected in anti-parallel.
  • the first IP core of the system-on-chip of the flip chip package according to the embodiment of the present invention is connected to the analog power supply BUMP and the analog ground BUMP, and the first IP core and the analog power supply BUMP are connected by the first wire, the first The IP core and the analog ground BUMP are connected by a second wire Compared with the BUMP and the IP core, the BUMP and the IP core need to be connected through the input and output unit, the connection is simpler, the input and output unit is reduced, and the chip area is saved. Meanwhile, the first The first protection circuit connected between the wire and the second wire can effectively discharge the ESD current to ensure the normal operation of the SOC system.
  • FIG. 1 is a partial schematic structural diagram of a system for a flip chip package according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a first protection circuit 5 in an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of the second protection circuit 6 in the embodiment of the present invention.
  • FIG. 1 is a partial schematic structural diagram of a system for a flip-chip package according to an embodiment of the present invention.
  • the first IP core of the system-on-chip in the embodiment of the present invention is connected to an analog power supply BUMP2 and an analog ground BUMP3.
  • the first IP core 1 and the analog power supply BUMP2 are connected by a first wire 7, and the first IP core 1 and The analog ground BUMP3 is connected by a second wire 8, and a first protection circuit 5 is connected between the first wire 7 and the second wire 8.
  • the SOC system has multiple IP cores, and the technical solution of the analog power supply and the analog ground directly connected to the IP core in the embodiment of the present invention is applicable to the first IP core 1 and the like. Only the analog power supply and the analog ground signal are from the analog power supply BUMP2 and Simulate the IP core of BUMP3.
  • the analog power supply BUMP2 and the analog ground BUMP3 are directly connected to the IP core, which can reduce the number of input and output units in the chip and save the chip area; the connection between the first wire 7 and the second wire 8
  • the first protection circuit 5 is an ESD (Electro-Static discharge) protection circuit, which can effectively discharge the ESD current and ensure the normal operation of the SOC system.
  • the first protection circuit 5 includes a detection portion, a trigger portion, and a release portion.
  • the detecting portion includes an RC detecting circuit
  • the trigger portion includes an inverter circuit
  • the releasing portion includes a field effect transistor
  • the RC detection circuit includes a resistor R and a capacitor C connected in series, and the inverter circuit is composed of an Mn2 tube and an Mp2 tube.
  • the first protection circuit 5 is a Clamp Cell, which implements an ESD protection function. Both ends of the first protection circuit 5 are connected to the analog power supply BUMP2 and the analog ground BUMP3, respectively.
  • the digital ground BUMP4 is connected to the second wire 8 through the second protection circuit 6.
  • the second protection circuit 6 includes two diodes connected in anti-parallel. Both ends of the second protection circuit 6 are connected to the analog ground BUMP3 and the digital ground BUMP4, respectively.
  • the ESD protection of the first protection circuit only reaches the first protection circuit 5 before the current is applied. Only when you reach the IP core can you fully play it.
  • the distance between the first protection circuit 5 and the analog power supply BUMP2 is much smaller than the distance between the first protection circuit 5 and the IP core, so that the current is first reached to the first protection circuit 5 and then reaches the IP core.
  • the distance between the first protection circuit 5 and the analog ground BUMP3 is much smaller than the distance between the first protection circuit 5 and the IP core.
  • the first wire 7 and the second wire 8 use a plurality of metal wires to reduce the wire resistance.
  • the wiring between the first protection circuit 5 and the first wire 7 and the second wire 8 also uses a plurality of metal wires.
  • the resistance between the analog power supply BUMP2 through the first protection circuit 5 to the analog ground BUMP3 is less than 0.2 ohms.
  • the digital ground BUMP4 and the second protection circuit 6 are connected by a plurality of metal wires, and the second protection circuit 6 and the second wire 8 are connected by a plurality of metal wires.
  • the resistance of the digital ground BUMP4 through the second protection circuit 6 to the analog ground BUMP3 is less than 0.2 ohms.
  • the IP core of the system-on-chip of the flip chip package provided by the embodiment of the present invention is connected to the analog power supply BUMP2 and the analog ground BUMP3, and the first IP core 1 and the analog power supply BUMP2 are connected by the first wire 7, the first The IP core 1 and the analog ground BUMP3 are connected by the second wire 8, and the BUMP is directly connected to the IP core for interconnection.
  • the BUMP and the IP core need to be connected through the input and output unit, and the connection is simpler.
  • the input and output unit is cut, and the chip area is saved.
  • the first protection circuit 5 connected between the first wire 7 and the second wire 8 can effectively discharge the ESD current to ensure the normal operation of the SOC system.
  • the first IP core is connected to the analog power supply BUMP and the analog ground BUMP.
  • the first IP core and the analog power supply BUMP are connected by a first wire
  • the first IP core and the analog ground BUMP are connected by a second wire
  • the interconnection is performed by using a BUMP directly connected to the IP core.
  • the BUMP and the IP core need to be connected through the input and output unit, the connection is simpler, the input and output unit is reduced, and the chip area is saved; meanwhile, the first protection circuit connected between the first wire and the second wire can be Effectively discharge ESD current to ensure normal operation of the SOC system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种倒装芯片封装的片上系统，所述片上系统的第一IP核（1）只连接模拟电源BUMP（2）和模拟地BUMP（3），所述第一IP核（1）与所述模拟电源BUMP（2）通过第一导线（7）连接，所述第一IP核（1）和所述模拟地BUMP（3）通过第二导线（8）连接，所述第一导线（7）和第二导线（8）之间连接有第一保护电路（5）。

Description

一种倒装芯片封装的片上系统
相关申请的交叉引用
本申请基于申请号为201610930989.5、申请日为2016年10月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及电子产品技术领域，尤其涉及一种倒装芯片封装的片上系统。
背景技术
随着芯片制造工艺不断发展，单位面积的晶片可以集成的门电路不断增多，出现了具有一定功能的整个系统集成到一个芯片中的片上系统(SOC，System On a Chip)。最近十年以来，蓬勃发展的消费类电子产品中越来越多应用SOC技术，同时，SOC技术也在缩短设计周期，降低开发成本方面不断进步。
在设计SOC采用flip chip封装的芯片时，芯片内部信号必须通过输入输出单元才能连接到封装的BUMP(一种名为BUMP工艺的芯片封装技术采用的凸块)或bonding pad(一种名为线焊工艺的芯片封装技术采用的焊盘)上，输入输出单元是SOC设计中重要的组成部分，占用了部分芯片面积；而在SOC技术中，缩小芯片面积是降低开发成本的一种主要方式。
发明内容
有鉴于此，本发明实施例提供一种倒装芯片封装的片上系统，可减少 输入输出单元的使用，从而减少片上系统芯片的大小。为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种倒装芯片封装的片上系统，所述片上系统的第一IP核连接模拟电源BUMP和模拟地BUMP，所述第一IP核与所述模拟电源BUMP通过第一导线连接，所述第一IP核和所述模拟地BUMP通过第二导线连接，所述第一导线和第二导线之间连接有第一保护电路。
上述方案中，数字地BUMP通过第二保护电路连接到所述第二导线上。
上述方案中，所述第一保护电路与所述模拟电源BUMP之间的距离远小于所述第一保护电路与所述IP核之间的距离；所述第一保护电路与所述模拟地BUMP之间的距离远小于所述第一保护电路与所述IP核之间的距离。
上述方案中，所述第一导线和/或第二导线为多层金属线。
上述方案中，所述模拟电源BUMP经过第一保护电路至模拟地BUMP间的电阻小于0.2欧姆。
上述方案中，所述数字地BUMP与所述第二保护电路之间通过多层金属线连接，所述第二保护电路与所述第二导线之间通过多层金属线连接。
上述方案中，所述数字地BUMP经过第二保护电路至所述模拟地BUMP间的电阻小于0.2欧姆。
上述方案中，所述第一保护电路包括检测部分、触发部分和释放部分。
上述方案中，所述检测部分包括RC检测电路，所述触发部分包括反相器电路，所述释放部分包括场效应管。
上述方案中，所述第二保护电路包括两个反向并联的二极管。
本发明实施例所提供的倒装芯片封装的片上系统的第一IP核连接模拟电源BUMP和模拟地BUMP，所述第一IP核与所述模拟电源BUMP通过第一导线连接，所述第一IP核和所述模拟地BUMP通过第二导线连接，采 用BUMP直接连接IP核的方式进行互连相比较现有技术中BUMP和IP核需要通过输入输出单元转接连接，连接更为简单，削减了输入输出单元，节省了芯片面积；同时，第一导线和第二导线之间连接的第一保护电路可有效泄放ESD电流，保证SOC系统正常工作。
附图说明
图1为本发明实施例中的倒装芯片封装的片上系统的部分组成结构示意图；
图2为本发明实施例中的第一保护电路5的电路图；
图3为本发明实施例中的第二保护电路6的电路图。
具体实施方式
为了能够更加详尽地了解本发明的特点与技术内容，下面结合附图对本发明的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明。
图1为本发明实施例中的倒装芯片封装的片上系统的部分组成结构示意图。
如图1所示，本发明实施例中的片上系统的第一IP核连接模拟电源BUMP2和模拟地BUMP3，第一IP核1与模拟电源BUMP2通过第一导线7连接，第一IP核1和模拟地BUMP3通过第二导线8连接，第一导线7和第二导线8之间连接有第一保护电路5。
SOC系统中具有多个IP核，本发明实施例中的模拟电源和模拟地直接与IP核连接的技术方案适用于第一IP核1等外部只有模拟电源和模拟地信号来自于模拟电源BUMP2和模拟地BUMP3的IP核。
模拟电源BUMP2和模拟地BUMP3与IP核直接连接，可以减少芯片中输入输出单元的数量，节省芯片面积；第一导线7和第二导线8之间连 接的第一保护电路5为静电释放(ESD，Electro-Static discharge)保护电路，可有效泄放ESD电流，保证SOC系统正常工作。
如图2所示，本发明实施例中，第一保护电路5包括检测部分、触发部分和释放部分。
其中，检测部分包括RC检测电路，触发部分包括反相器电路，释放部分包括场效应管。
如图2所示，RC检测电路包括串联的电阻R和电容C，反相器电路由Mn2管和Mp2管组成。
第一保护电路5为钳位单元(Clamp Cell)，可实现ESD保护功能。第一保护电路5的两端分别连接模拟电源BUMP2和模拟地BUMP3。
如图1和图2所示，当模拟电源BUMP2上被加上ESD电压时，电压通过Clamp Cell的电源管脚传递到Clamp Cell内部的RC检测电路，RC检测电路经过一个反相器来触发Mn1管，将大的ESD电流通过大尺寸的Mn1管释放到Clamp Cell的地管脚，Clamp Cell的地管脚通过与之连接的模拟地BUMP3将ESD电流泄放到芯片外部，从而避免了ESD电流对芯片内部电路造成损伤。
为了平衡不同地之间的压降，如图1所示，本发明实施例中，数字地BUMP4通过第二保护电路6连接到第二导线8上。
如图3所示，本发明实施例中，第二保护电路6包括两个反向并联的二极管。第二保护电路6的两端分别连接模拟地BUMP3和数字地BUMP4。
如图1和图3所示，当模拟地BUMP连接的线路上ESD电压过大，只要超过二级管的击穿电压阈值，二级管就会导通，此时模拟地BUMP3通过导通的二极管与数字地BUMP4形成一个泄放通路，达到泄放ESD电流的作用。
第一保护电路的ESD保护作用只有在通电电流先到达第一保护电路5， 再到达IP核的情况下才能充分发挥。为使得通电电流先到达第一保护电路5，再到达IP核，本发明实施例中，第一保护电路5与模拟电源BUMP2之间的距离远小于第一保护电路5与IP核之间的距离；第一保护电路5与模拟地BUMP3之间的距离远小于第一保护电路5与IP核之间的距离。
在本发明实施例中，第一导线7和第二导线8使用多层金属线，以降低连线电阻。第一保护电路5与第一导线7和第二导线8之间的连线也使用多层金属线。
具体地，模拟电源BUMP2经过第一保护电路5至模拟地BUMP3间的电阻小于0.2欧姆。
同样的道理，为降低连线电阻，数字地BUMP4与第二保护电路6之间通过多层金属线连接，第二保护电路6与第二导线8之间通过多层金属线连接。
具体地，数字地BUMP4经过第二保护电路6至模拟地BUMP3间的电阻小于0.2欧姆。
本发明实施例所提供的倒装芯片封装的片上系统的IP核连接模拟电源BUMP2和模拟地BUMP3，所述第一IP核1与所述模拟电源BUMP2通过第一导线7连接，所述第一IP核1和所述模拟地BUMP3通过第二导线8连接，采用BUMP直接连接IP核的方式进行互连相比较现有技术中BUMP和IP核需要通过输入输出单元转接连接，连接更为简单，削减了输入输出单元，节省了芯片面积；同时，第一导线7和第二导线8之间连接的第一保护电路5可有效泄放ESD电流，保证SOC系统正常工作。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，第一IP核连接模拟电源BUMP和模拟地BUMP， 所述第一IP核与所述模拟电源BUMP通过第一导线连接，所述第一IP核和所述模拟地BUMP通过第二导线连接，采用BUMP直接连接IP核的方式进行互连相比较现有技术中BUMP和IP核需要通过输入输出单元转接连接，连接更为简单，削减了输入输出单元，节省了芯片面积；同时，第一导线和第二导线之间连接的第一保护电路可有效泄放ESD电流，保证SOC系统正常工作。

Claims (10)

  1. 一种倒装芯片封装的片上系统，所述片上系统的第一IP核连接模拟电源BUMP(2)和模拟地BUMP(3)，所述第一IP核(1)与所述模拟电源BUMP(2)通过第一导线(7)连接，所述第一IP核(1)和所述模拟地BUMP3通过第二导线(8)连接，所述第一导线(7)和第二导线(8)之间连接有第一保护电路(5)。
  2. 根据权利要求1所述的片上系统，其中，数字地BUMP(4)通过第二保护电路(6)连接到所述第二导线(8)上。
  3. 根据权利要求1或2所述的片上系统，其中，所述第一保护电路5与所述模拟电源BUMP(2)之间的距离远小于所述第一保护电路(2)与所述IP核之间的距离；所述第一保护电路(5)与所述模拟地BUMP3之间的距离远小于所述第一保护电路(5)与所述IP核之间的距离。
  4. 根据权利要求3所述的片上系统，其中，所述第一导线(7)和/或第二导线(8)为多层金属线。
  5. 根据权利要求4所述的片上系统，其中，所述模拟电源BUMP(2)经过第一保护电路(5)至模拟地BUMP(3)间的电阻小于0.2欧姆。
  6. 根据权利要求2所述的片上系统，其中，所述数字地BUMP(4)与所述第二保护电路(6)之间通过多层金属线连接，所述第二保护电路(6)与所述第二导线(8)之间通过多层金属线连接。
  7. 根据权利要求6所述的片上系统，其中，所述数字地BUMP(4)经过第二保护电路(6)至所述模拟地BUMP(3)间的电阻小于0.2欧姆。
  8. 根据权利要求1或2所述的片上系统，其中，所述第一保护电路(5)包括检测部分、触发部分和释放部分。
  9. 根据权利要求8所述的片上系统，其中，所述检测部分包括RC检测电路，所述触发部分包括反相器电路，所述释放部分包括场效应管。
  10. 根据权利要求1或2所述的片上系统，其中，所述第二保护电路(6)包括两个反向并联的二极管。
PCT/CN2017/089079 2016-10-31 2017-06-19 一种倒装芯片封装的片上系统 WO2018076722A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610930989.5 2016-10-31
CN201610930989.5A CN108022911A (zh) 2016-10-31 2016-10-31 一种倒装芯片封装的片上系统

Publications (1)

Publication Number Publication Date
WO2018076722A1 true WO2018076722A1 (zh) 2018-05-03

Family

ID=62023082

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/089079 WO2018076722A1 (zh) 2016-10-31 2017-06-19 一种倒装芯片封装的片上系统

Country Status (2)

Country Link
CN (1) CN108022911A (zh)
WO (1) WO2018076722A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1473362A (zh) * 2001-07-13 2004-02-04 ������������ʽ���� 具有改进的静电放电耐压的半导体装置
CN1507052A (zh) * 2002-12-06 2004-06-23 松下电器产业株式会社 半导体集成电路装置及半导体集成电路装置的制造方法
CN102117803A (zh) * 2009-12-31 2011-07-06 无锡中星微电子有限公司 一种具有高静电释放性能的芯片
CN103165599A (zh) * 2011-12-19 2013-06-19 Arm有限公司 集成电路和在集成电路内提供静电放电保护的方法
US20160268248A1 (en) * 2015-03-09 2016-09-15 Apple Inc. Modular Electrostatic Discharge (ESD) Protection

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245852B2 (en) * 2011-09-08 2016-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection for 2.5D/3D integrated circuit systems
CN103515945A (zh) * 2013-10-23 2014-01-15 青岛歌尔声学科技有限公司 Esd补强电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1473362A (zh) * 2001-07-13 2004-02-04 ������������ʽ���� 具有改进的静电放电耐压的半导体装置
CN1507052A (zh) * 2002-12-06 2004-06-23 松下电器产业株式会社 半导体集成电路装置及半导体集成电路装置的制造方法
CN102117803A (zh) * 2009-12-31 2011-07-06 无锡中星微电子有限公司 一种具有高静电释放性能的芯片
CN103165599A (zh) * 2011-12-19 2013-06-19 Arm有限公司 集成电路和在集成电路内提供静电放电保护的方法
US20160268248A1 (en) * 2015-03-09 2016-09-15 Apple Inc. Modular Electrostatic Discharge (ESD) Protection

Also Published As

Publication number Publication date
CN108022911A (zh) 2018-05-11

Similar Documents

Publication Publication Date Title
JP5972473B2 (ja) スタック型マルチチップ集積回路の静電気保護
US9048655B2 (en) ESD protection scheme using I/O pads
US10964651B2 (en) Method and apparatus of ESD protection in stacked die semiconductor device
US9929139B2 (en) Modular electrostatic discharge (ESD) protection
US20130342940A1 (en) Electrostatic discharge protection circuit
US9385527B2 (en) Enhanced charge device model clamp
CN103247621B (zh) 静电放电保护电路
JP2007180578A (ja) 多チップモジュール用ｅｓｄ回路を含む集積回路及びその方法
US9001478B2 (en) Self-reset transient-to-digital convertor and electronic product utilizing the same
US9882377B2 (en) Electrostatic discharge protection solutions
CN102569290A (zh) 多电源集成电路的静电放电保护电路
JP2011139009A (ja) 半導体装置
US20140071567A1 (en) Semiconductor device
WO2018076722A1 (zh) 一种倒装芯片封装的片上系统
US20080123231A1 (en) Circuit for discharging static electricity
Olson et al. CDM-ESD induced damage in components using stacked-die packaging
TW201816975A (zh) 靜電放電防護電路及積體電路
TWI387024B (zh) 半導體裝置以及修改積體電路的方法
Rosenbaum et al. ESD protection networks for 3D integrated circuits
TWI573242B (zh) 具自身靜電防護功能的輸出緩衝電路
TWI441318B (zh) 負電源積體電路之靜電放電保護電路
TWI504091B (zh) 靜電放電保護裝置
Maeda et al. Area-efficient ESD design using power clamps distributed outside I/O cell ring
TWI502721B (zh) 晶片靜電放電保護裝置及其靜電放電保護方法
JP2010216996A (ja) 半導体装置および該半導体装置の検査方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17864815

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17864815

Country of ref document: EP

Kind code of ref document: A1