WO2018076645A1 - 移位寄存器及驱动方法、栅驱动电路以及显示装置 - Google Patents

移位寄存器及驱动方法、栅驱动电路以及显示装置 Download PDF

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Publication number
WO2018076645A1
WO2018076645A1 PCT/CN2017/082328 CN2017082328W WO2018076645A1 WO 2018076645 A1 WO2018076645 A1 WO 2018076645A1 CN 2017082328 W CN2017082328 W CN 2017082328W WO 2018076645 A1 WO2018076645 A1 WO 2018076645A1
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Prior art keywords
transistor
compensation
pull
signal
circuit
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PCT/CN2017/082328
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English (en)
French (fr)
Inventor
王梓轩
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/569,216 priority Critical patent/US10475362B2/en
Publication of WO2018076645A1 publication Critical patent/WO2018076645A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a shift register and a driving method, a gate driving circuit, and a display device.
  • the instability of the gate driving circuit composed of a plurality of transistors is further unstable due to the instability factor caused by the threshold voltage of the transistor, and the operating life of the gate driving circuit is shortened.
  • At least one embodiment of the present disclosure provides a shift register including: a driving unit configured to provide a gate line signal to a corresponding pixel unit group; and a compensation circuit disposed corresponding to the driving unit; wherein the compensation The circuit is configured to compensate for a threshold voltage offset of one or more of the drive units.
  • the compensation circuit includes: a compensation transistor, a gate of the compensation transistor being coupled to a compensation control line, a first pole of the compensation transistor and a first compensation signal line Connected, the second pole of the compensation transistor is connected to the pull-up node; wherein the compensation control line is used to provide a control signal for controlling the conduction of the compensation transistor to the gate; the first compensation signal line is used Providing a forward compensation voltage or a negative compensation voltage to the first pole.
  • the compensation circuit includes: a first compensation transistor and a second compensation transistor; wherein the first compensation transistor is an N-type transistor and the second compensation transistor is a P-type transistor; a gate of the first compensation transistor is simultaneously connected to a second compensation signal line and a first electrode of the first compensation transistor, a second pole of the first compensation transistor and an upper portion of the driving unit a pull node is connected; a gate of the second compensation transistor is simultaneously connected to the second compensation signal line and a first pole of the second compensation transistor, the second compensation crystal a second pole of the body tube is connected to the pull-up node of the driving unit; wherein the second compensation signal line is used for the first pole of the first compensation transistor or the second compensation transistor The first pole provides a compensation voltage.
  • the driving unit includes: a pull-up circuit configured to output a first clock signal as a gate line signal; and a pull-up control circuit configured to control the upper a pull-down circuit; a pull-down circuit configured to pull the gate line signal low to a low potential at a first time; a pull-down sustain circuit configured to maintain a low potential state of the gate line signal; and a pull-down sustain control circuit Configuring to maintain the pull-down control point at a low potential; the pull-up circuit or the pull-down sustain control circuit each include at least one transistor; wherein the compensation circuit is configured to be in the pull-up circuit or the pull-down sustain control circuit Part of the transistor writes the compensation voltage.
  • the pull-up control circuit includes a first transistor, a first pole of the first transistor coupled to an input signal line to receive an input signal, the first transistor a gate is connected to the first pole, a second pole of the first transistor is connected to the pull-up node;
  • the pull-up circuit includes a second transistor, a gate of the second transistor and the pull-up node Connected, the first pole of the second transistor is connected to the first clock, the second pole of the second transistor is connected to the output;
  • the pull-down circuit comprises a third transistor, the first of the third transistor a pole is connected to the output end, a gate of the third transistor is connected to a reset signal line, and a second pole of the third transistor is connected to a first power line; wherein the first voltage line is used for a transmission a first voltage; the reset signal line is for transmitting the reset signal;
  • the pull-down sustain control circuit includes a fourth transistor and a fifth transistor, and the first pole of the fourth transistor is connected to the second clock signal line
  • the pull-down sustain control circuit further includes The eighth transistor and the ninth transistor are connected; the first electrode of the eighth transistor is connected to the second pull-down node, the gate of the eighth transistor is connected to the pull-up node, and the eighth transistor is a second pole is connected to the first power line; a first pole of the ninth transistor is connected to the second clock signal to receive a second clock signal, and a gate of the ninth transistor is connected to the first pole The second pole of the ninth transistor is connected to the second pull-down node.
  • the shift register further includes a reset circuit configured to initialize the stage to cause the pull-up node to discharge.
  • the reset circuit includes a tenth transistor, a first pole of the tenth transistor is connected to the pull-up node, and a gate of the tenth transistor is The reset signal is connected, and the second pole of the tenth transistor is connected to the first power line.
  • Embodiments of the present disclosure also provide a gate drive circuit including any of the shift registers described above.
  • At least one embodiment of the present disclosure also provides a display device including the gate driving circuit of the above embodiment and a display panel connected to the gate driving circuit.
  • the method further includes: a timing temperature measuring device configured to measure a working time of each driving unit of the gate driving circuit and a temperature during operation when the display panel is powered on, based on The time and temperature of the statistics obtain the threshold voltage offset of the transistors in the pull-up circuit or the pull-down sustain control circuit of each driving unit, and calculate the compensation duration and the compensation voltage of the transistor according to the threshold voltage offset condition;
  • the control device is configured to store a compensation voltage and a compensation duration calculated by the timing temperature measuring device, and providing the compensation voltage to a compensation circuit corresponding to each driving unit of the gate driving circuit; and a built-in power supply configured to drive to the gate The compensation circuit of the circuit and the control device are powered.
  • control device is further configured to: when determining that the display panel is in a shutdown state, providing the compensation voltage to a compensation circuit of the gate driving circuit, wherein The compensation voltage is used to perform threshold voltage compensation on a pull-up circuit of the driving unit or a part of transistors in the pull-down sustain control circuit.
  • control device is further configured to provide a compensation voltage to the compensation circuit during the compensation period.
  • the compensation voltage includes a forward compensation voltage or a negative compensation voltage; when performing forward bias compensation, the control device transmits to the first compensation signal line a forward compensation voltage; when performing negative bias compensation, the control device is A compensation signal line transmits a negative compensation voltage.
  • At least one embodiment of the present disclosure further provides a driving method for the shift register, including: setting a input signal to a valid signal during a charging phase, setting a first clock signal to be an invalid signal, and setting a second clock signal to The effective signal sets the reset signal to a turn-off voltage; in the output stage, the input signal is set to be an invalid signal, the first clock signal is set to be a valid signal, the second clock signal is set to be an invalid signal, and the reset signal is set To turn off the voltage; in the discharging phase, set the input signal to be an invalid signal, set the first clock signal to be an invalid signal, set the second clock signal to be an invalid signal, and set the reset signal to be an on-voltage; a step of setting the input signal to be an invalid signal, setting the second clock signal to be an invalid signal, setting the second clock signal to be an invalid signal, setting the reset signal to a shutdown voltage, and setting the The input signal is an invalid signal, and the first clock signal is set to be an invalid signal, and the first The clock signal is
  • FIG. 1 is a schematic diagram of a shift register provided by an embodiment of the present disclosure
  • 2A is a schematic diagram of a compensation circuit provided by an embodiment of the present disclosure.
  • 2B is a schematic diagram of a compensation circuit according to another embodiment of the present disclosure.
  • 3A is a schematic block diagram of a driving unit and a compensation circuit according to an embodiment of the present disclosure
  • FIG. 3B is an exemplary circuit diagram of the driving unit and the compensation circuit shown in FIG. 3A;
  • 3C is another exemplary circuit diagram of the driving unit and the compensation circuit shown in FIG. 3A;
  • FIG. 4 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • 5A and 5B are driving timing diagrams for the circuit structure shown in FIGS. 3B and 3C according to an embodiment of the present disclosure
  • 6A-6D are schematic diagrams showing the operation of each transistor based on the timing diagram of FIG. 5B according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register having a threshold drift correction function.
  • embodiments of the present disclosure apply a back gate voltage or a forward gate voltage to a plurality of transistors in the shift register to restore threshold voltage drift generated by the display device during operation, thereby extending gate shift The lifetime of the register.
  • the embodiment of the present disclosure can achieve a large extension of the life of the shift register due to the threshold voltage compensation of the associated transistor during the inactivity of the display device, so that the service life of the shift register can be greatly extended, and is particularly suitable for use in a similar public display.
  • Embodiments of the present disclosure provide a shift register including: a driving unit configured to provide a gate line signal to a corresponding pixel unit group; and a compensation circuit disposed corresponding to the driving unit; wherein the compensation circuit is configured To compensate for the threshold voltage offset of one or more transistors in the drive unit.
  • the shift register 100 includes a plurality of driving units 115 (for example, 115a, 115b, ..., 115n) and a compensation circuit 110 (for example, 110a, 110b) provided in one-to-one correspondence with each driving unit 115. , ..., 110n).
  • Each drive unit 115 can be configured to provide a gate line signal to a respective set of pixel cells.
  • Each of the compensation circuits 110 is configured to compensate for a threshold voltage offset of one or more of the transistors in its corresponding drive unit 115.
  • the shift register 100 may include one or more driving units 115 and a compensation circuit 110 disposed in one-to-one correspondence with each of the driving units 115.
  • the driving unit 115 and the compensation circuit 110 included in one shift register 100 The number of the disclosure is not limited herein.
  • the structure of one pixel cell group is related to the arrangement of the pixel cells on the display panel.
  • one pixel unit group is an entire row of pixel units.
  • one pixel unit group may also be an entire column of pixel units.
  • the embodiment of the present disclosure does not limit the arrangement of the pixel units.
  • the pixel units may also be arranged on the display panel in a diagonal manner. In this case, one pixel unit group may also be all pixel units included on one oblique line.
  • one or more transistors compensated by compensation circuit 110 are associated with a particular circuit configuration of drive unit 115.
  • the drive unit 115 includes a plurality of transistors, and these transistors can be used as timing control tubes or output tubes. Since different transistors are in different states during operation, their threshold voltage drift is also different. Therefore, it is necessary to obtain a transistor that needs to be compensated by the compensation circuit 110 according to the operating state of each transistor in the specific driving circuit.
  • the compensation circuit 110 can be employed to compensate for the pull-down transistors included in the drive unit 115.
  • the driving units 115a, 115b, ..., 115n shown in Fig. 1 may be referred to as a first stage driving unit 115a, a second stage driving unit 115b, ..., an nth stage driving unit 115n, respectively.
  • the compensation circuit 110 may include a compensation transistor 211 whose gate is connected to a compensation control line 213, and the compensation transistor 211 The first pole is coupled to the first compensation signal line 215, and the second pole of the compensation transistor 211 is coupled to a pull-up node (shown in FIG. 3A) in the drive unit 115.
  • the compensation control line 213 is used to provide a control signal for controlling the turn-on of the compensating transistor 211 to the gate of the compensating transistor 211.
  • the control signal may be a pulse signal.
  • the first compensation signal line is used to supply a forward compensation voltage or a negative compensation voltage to the first electrode of the compensation transistor 211.
  • the compensation control line 213 shown in FIG. 2A supplies a high level to the gate of the compensation transistor 211
  • the compensation transistor 211 is turned on, and at this time, a high level is input through the first compensation signal line 215 to achieve driving.
  • the compensation circuit 110 provided in FIG. 2A can perform forward bias compensation or negative bias compensation on one or more transistors included in the driving unit 115, thereby correcting the threshold of the compensated transistor.
  • the voltage Vth drifts to improve the operating life of the gate drive circuit.
  • FIG. 2B shows another schematic diagram of the compensation circuit 110 provided by the embodiment of the present disclosure.
  • the compensation circuit 110 includes a first compensation transistor 212 and a second compensation transistor 213, wherein one of the first compensation transistor 212 and the second compensation transistor 213 is an N-type transistor and the other is a P-type transistor.
  • the gate of the first compensation transistor 212 is simultaneously connected to the second compensation signal line 225 and the first electrode of the first compensation transistor 212, and the second electrode of the first compensation transistor 212 is connected to the corresponding driving unit. Pull nodes (shown in Figure 3A) are connected.
  • the gate of the second compensation transistor 213 is simultaneously connected to the second poles of the second compensation signal line 225 and the second compensation transistor 213, and the second pole of the second compensation transistor 213 is connected to the pull-up node of the corresponding driving unit (shown In Figure 3A).
  • the second pole of the first compensation transistor 212 is connected to the second pole of the second compensation transistor 213; the gate of the first compensation transistor 212 is connected to the gate of the second compensation transistor 213; wherein the second compensation signal line 225 A compensation voltage is provided to the first pole of the first compensation transistor 212 or to the first pole of the second compensation transistor 213.
  • the second compensation signal line 225 can be used to apply a forward compensation voltage to the gate and the first pole of the first compensation transistor 212 such that the first compensation transistor 212 is turned on, and then by the second pole of the first compensation transistor 212.
  • the pull-up node outputs the forward compensation voltage.
  • the second compensation signal line 225 can be used to apply the negative compensation voltage to the gate and the first pole of the second compensation transistor 213, so that the second compensation transistor 213 is turned on, and then the second polarity of the second compensation transistor 213 is upward.
  • the pull node outputs the negative compensation voltage.
  • a high level signal can be input through the second compensation signal line 225 shown in FIG. 2B to achieve positive bias compensation for one or more transistors in the driving unit 115 by the conduction of the first compensation transistor 212.
  • a low level signal may be input through the second compensation signal line 225 shown in FIG. 2B to achieve negative bias compensation for one or more transistors in the driving unit 115 by the conduction of the second compensation transistor 213.
  • FIG. 3A shows only one driving unit in the shift register and one compensation circuit 310 provided corresponding to the driving unit.
  • the structure of the compensation circuit 310 can be complemented by the compensation shown in FIG. 2A or FIG. 2B.
  • the structure of the compensation circuit 110 is the same or similar.
  • the driving unit shown in FIG. 3A may include a pull-up circuit 316, a pull-up control circuit 312, a pull-down circuit 318, a pull-down sustain circuit 320, and a pull-down sustain control circuit 314.
  • the pull-up circuit 316 is configured to output the first clock signal as a gate line signal (which will be transmitted to the pixel cell group as, for example, a scan signal).
  • Pull-up control circuit 312 is configured to control the turn-on time of pull-up circuit 316.
  • the pull-down circuit 318 is configured to pull the gate line signal output from the output terminal low to a low level at a first time.
  • the pull-down sustain circuit 320 is configured to maintain a low potential state of the gate line signal.
  • Pull-down sustain control circuit 314 is configured to maintain a pull-down control point (eg, the first pull-down node shown in the figure) at a low potential.
  • pull-up circuit 316 or pull-down sustain control circuit 314 each include at least one transistor.
  • the compensation circuit 310 is configured to write a compensation voltage to a portion of the transistors in the pull-up circuit 316 or the pull-down sustain control circuit 314.
  • pull-up control circuit 312 is coupled to the input to receive an input signal, for example, the input signal can be a signal output at the output of the upper stage drive unit.
  • the pull-down sustain control circuit 314 is coupled to the second clock signal to receive the second clock signal.
  • the pull-up circuit 316 is coupled to the first clock signal to receive the first clock signal, for example, the first clock signal is a pulse signal.
  • Pull-down circuit 318 and pull-down sustain circuit 320 are also coupled to the first power line to receive the first voltage.
  • the first voltage can be a low level signal.
  • the input signal at the input is a signal output from the output of the upper stage drive unit (for example, for the second stage drive unit 115b shown in FIG.
  • the upper stage drive unit is the first stage drive unit 115a).
  • the second clock signal is opposite in phase to the first clock signal.
  • the reset signal on the reset line is a signal outputted from the output terminal of the next stage drive unit (for example, the drive unit 115a of the first stage is shown in FIG. 1, and the drive unit 115b of the next stage is the second stage drive unit 115b). Since the drive unit 115a does not have the upper stage drive unit, a pulse activation signal can be input at its input.
  • the drive unit may further include a reset circuit 322 connected to the reset signal line to receive the reset signal.
  • the reset circuit 322 is configured to discharge the pull-up node during the initialization phase in preparation for stable operation of the drive unit.
  • the drive unit illustrated in FIG. 3A further includes a second pull-down node (shown in FIGS. 3B and 3C) that is in turn coupled to pull-down maintenance control circuit 314, respectively.
  • a second pull-down node shown in FIGS. 3B and 3C
  • the structure of the shift register shown in FIG. 3A will be described in detail below by taking the transistors in FIGS. 3B and 3C as N-type transistors as an example.
  • Figure 3B shows a drive unit and a compensation circuit in the shift register.
  • the pull-up control circuit 312 of the driving unit includes a first transistor M1, the first pole of the first transistor M1 is connected to the input signal line to receive the input signal, and the gate of the first transistor M1 is connected to the first pole, the first transistor M1 The second pole is connected to the pull-up node pu.
  • the pull-up circuit 316 of the driving unit includes a second transistor M2 whose gate is connected to the pull-up node pu, the first pole of the second transistor M2 is connected to the first clock, and the second pole of the second transistor M2 Connected to the output.
  • the pull-down circuit 318 of the driving unit includes a third transistor M3, the first pole of the third transistor M3 is connected to the output terminal, the gate of the third transistor M3 is connected to the reset signal line, and the second pole of the third transistor M3 is connected to the first power source.
  • a line connection for example, a first voltage line for transmitting a first voltage VSS; a reset signal line for transmitting a reset signal; and a pull-down sustain circuit including a sixth transistor M6 and a seventh transistor M7, a sixth transistor M6 and a seventh transistor M7
  • the first poles are all connected to the first power line, the gates of the sixth transistor M6 and the seventh transistor M7 are both connected to the first pull-down node pd, and the second poles of the sixth transistor M6 and the seventh transistor M7 are both pulled up and pulled up.
  • the node pu is connected; the first voltage line is for transmitting the first voltage Vss; the pull-down sustain control circuit comprises a fourth transistor M4 and a fifth transistor M5, the first pole of the fourth transistor M4 is connected to the second clock signal line, and the fourth transistor
  • the gate of M4 is connected to the second pull-down node PD-CN, the second pole of the fourth transistor M4 is connected to the first pull-down node pd; the first pole of the fifth transistor M5 is connected to the first pull-down node pd, fifth Gate of transistor M5 Pu connected to pull-up node, a second electrode of the fifth transistor M5 is connected to the first power supply line; wherein the second clock signal line for transmitting a second clock signal, a first line for transmitting a first power voltage VSS.
  • FIG. 3B shows that the pull-down sustain control circuit 314 of the driving unit may further include an eighth transistor M8 and a ninth transistor M9; the first pole of the eighth transistor M8 is connected to the second pull-down node PD-CN, and the eighth transistor M8 The gate is connected to the pull-up node pu, the second pole of the eighth transistor M8 is connected to the first power line Vss; the first pole of the ninth transistor M9 is connected to the second clock signal to receive the second clock signal, the ninth transistor M9 The gate is connected to the first pole, and the second pole of the ninth transistor M9 is connected to the second pull-down node PD-CN.
  • the reset circuit of the driving unit shown in FIG. 3B includes a tenth transistor M10, the first pole of the tenth transistor M10 is connected to the pull-up node pu, and the gate of the tenth transistor M10 is connected with the reset signal to receive the reset signal RESET.
  • the second pole of the tenth transistor M10 is connected to the first power line to receive the first voltage Vss.
  • the compensation circuit shown in FIG. 3B may specifically refer to the compensation circuit provided in FIG. 2A. at this time
  • the output of the compensation circuit is connected to the pull-up node pu.
  • the second transistor M2 included in the pull-up circuit and the fifth transistor M5 and the eighth transistor M8 included in the pull-up maintaining circuit 314 can perform forward bias compensation or negative bias compensation by the compensation circuit of FIG. 3B. .
  • the analysis process of the transistor included in the driving unit is as follows: a driving unit in the shift register of the array substrate gate driving circuit shown in FIG. 3B, The driving unit controls the noise level of the first pull-down node pd by using a second clock signal inverted from the first clock signal to reduce the noise level when the output terminal outputs VGL, thereby maintaining stable operation of the shift register.
  • the voltages of the first pull-down node (pd point) are controlled by the fourth transistor M4, the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9, thereby knowing that the fourth transistor M4, the fifth transistor M5,
  • the states of the four transistors of the eighth transistor M8 and the ninth transistor M9 determine the normal operation of the gate driving circuit.
  • the external factors that affect the threshold voltage shift under continuous operating conditions of the transistor mainly include two points, one is the voltage applied to the gate of the transistor, and the other is the duty ratio of the voltage signal applied to the gate. In this example, the duty ratios of the four transistor gate voltages of the fourth transistor M4, the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 are significantly different.
  • the estimated duty cycle is listed in Table 1 below. Only the failure of the gate drive circuit due to the transistor threshold voltage Vth drift is considered below. Referring to Table 1, it can be seen that the duty ratio of the voltage applied to the gate of the fifth transistor M5 and the eighth transistor M8 which are responsible for the pull-down of the first pull-down node pd and the second pull-down node PD-CN is about 99.2 when the gate driving circuit operates. % is much higher than the fourth transistor M4 and the ninth transistor M9 responsible for charging the first pull-down node pd and the second pull-down node PD-CN, and the second transistor M2 responsible for output also has a problem of high negative pressure.
  • the threshold voltage Vth of the fifth transistor M5 and the eighth transistor M8 shifts heavily negatively, so that the fifth transistor M5 and the eighth transistor M8 are at a lower gate voltage. It will be easy to open, which will further cause the gate drive circuit to be unstable. At this time, if the pull-up node pu points input noise, the fifth transistor M5 and the eighth transistor M8 will be simultaneously turned on, causing the first pull-down node pd to point to a lower level, and the sixth transistor M6 is to the pull-up node pu point.
  • the discharge effect is weakened due to the decrease of the gate voltage, and the noise of the pull-up node pu point is accumulated due to the rapid release, and is transmitted to the subsequent row through the output of the second transistor M2, thereby causing the entire gate drive circuit to fail.
  • the threshold voltage offset of the second transistor M2, the fifth transistor M5, and the eighth transistor M8 included in the driving unit can be compensated by the compensation circuit shown in FIG. 3B, where the offset includes a forward offset or a negative offset.
  • the compensation circuit shown in FIG. 3B can specifically refer to the compensation circuit provided in FIG. 2A, and the compensation circuit shown in FIG. 2B can also be used.
  • FIG. 3C differs from FIG. 3B in the compensation circuit portion.
  • the specific structure of the compensation circuit of FIG. 3C can be referred to the compensation circuit provided in FIG. 2B.
  • the threshold voltage offset of the second transistor M2, the fifth transistor M5, and the eighth transistor M8 included in the driving unit can be compensated by using the compensation circuit provided in FIG. 3C, where the compensation includes only forward offset compensation.
  • the threshold voltages of the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are compensated by the forward bias provided by the second compensation signal of FIG. 2B (corresponding to the compensation signal of FIG. 3C).
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first pole of the transistor of the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source
  • the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor, and the embodiment of the present disclosure adopts the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5,
  • the sixth transistor M6, the seventh transistor M7, and the like are all N-type transistors as an example.
  • those skilled in the art can easily realize the implementation of the P-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without making creative efforts. These implementations are also within the scope of the present disclosure.
  • Embodiments of the present disclosure also provide a gate drive circuit including any of the shift registers described above.
  • the gate drive circuit can include a plurality of cascaded shift registers.
  • an embodiment of the present disclosure further provides a display device including a gate driving circuit 199 (which includes a shift register) and a display panel connected to the gate driving circuit 199.
  • 420. 4 shows a shift register in the gate driving circuit 199, which includes compensation circuits (110a, 110b, ..., 110n) and driving units (115a, 115b, ..., 115n) provided corresponding to the respective compensation circuits,
  • the specific structure of the compensation circuit and the driving unit can be referred to FIG. 1, FIG. 2A-2B, and FIGS. 3A-3C.
  • FIG. 4 only shows a partial unit included in the display device.
  • the display device of FIG. 4 may further include a data driving circuit, a plurality of scanning lines, a plurality of data lines or clock circuits (not shown), and the like.
  • the display device further includes a timing temperature measuring device 430, a control device 440, and a built-in power source 450.
  • the timing temperature measuring device 430 is configured to measure the working time of each driving unit 115 of the gate driving circuit 199 when the display panel 420 is turned on and the temperature during operation, and then obtain the pull-up circuit or pull-down of each driving unit 115 based on the statistical time and temperature.
  • the threshold voltage shift of the transistor in the control circuit is maintained, and finally the compensation duration and the compensation voltage of the transistor are calculated according to the threshold voltage shift condition.
  • the control device 440 is configured to store the compensation voltage and the compensation duration calculated by the timing temperature measuring device 430, and supply the compensation voltage to the compensation circuit 110 corresponding to each of the driving units 115 of the gate driving circuit 199.
  • the built-in power supply 450 is configured to supply power to the compensation circuit of the gate drive circuit 199 and the control device.
  • the chronograph temperature measuring device 430 can acquire relevant data in real time using a timing sensor and a temperature measuring sensor, and the processor calculates a compensation voltage based on the collected data.
  • the timing temperature measuring device 430 may further be provided with a memory, and the memory may be used to pre-store a threshold compensation comparison table, the threshold compensation comparison table providing a threshold voltage compensation reference value or a threshold voltage compensation reference range according to the temperature and time of operation of the transistor. Then, the timing temperature measuring device 430 obtains a corresponding compensation voltage or compensation range by looking up the table according to the working time and temperature of the statistical transistor.
  • control device 440 is further configured to provide the compensation voltage obtained by the timing temperature measuring device 430 to the compensation circuit 110 of the gate driving circuit 199 when it is determined that the display panel is in the off state.
  • the compensation voltage is used to perform threshold voltage compensation on a pull-up circuit of the driving unit 115 connected to the compensation circuit 110 or a part of transistors in the pull-down sustain control circuit.
  • control device 440 is also configured to provide a compensation voltage to compensation circuit 110 within a compensation duration calculated by timing temperature measurement device 430.
  • the compensation voltage includes a forward compensation voltage or a negative compensation voltage.
  • the control device 440 is directed to the first compensation signal line (refer to the figure The first compensation signal shown in 2A transmits a forward compensation voltage.
  • the control device 3440 transmits a negative compensation voltage to the first compensation signal line (shown in FIG. 2A).
  • the compensation voltage may only include a forward compensation voltage.
  • the control device 440 transmits a forward compensation voltage to the second compensation signal line (refer to the figure. 2B shows the second compensation signal line 225).
  • an embodiment of the present disclosure further provides a driving timing chart for driving the shift register shown in FIGS. 3B and 3C.
  • the driving method includes a charging phase, an output phase, a discharging phase, a holding phase, and a compensation phase.
  • the input signal Out(n-1) is set as a valid signal
  • the first clock signal CLK is set as an invalid signal
  • the second clock signal CLKB is set as a valid signal
  • the reset signal Out(n+1) is set as a turn-off voltage.
  • the input signal Out(n-1) is set as an invalid signal
  • the first clock signal CLK is set as a valid signal
  • the second clock signal CLKB is set as an invalid signal
  • the reset signal Out(n+1) is set as the off voltage.
  • the input signal Out(n-1) is set as an invalid signal
  • the first clock CLK signal is set as an invalid signal
  • the second clock signal CLKB is set as an invalid signal
  • the reset signal Out(n+1) is set as the turn-on voltage.
  • the input signal Out(n-1) is set as an invalid signal
  • the first clock signal CLK is set as an invalid signal
  • the second clock signal CLKB is set as an invalid signal
  • the reset signal Out(n+1) is set as the off voltage.
  • the input signal Out(n-1) is set as an invalid signal
  • the first clock signal CLK is set as an invalid signal
  • the second clock signal CLKB is set as an invalid signal
  • the reset signal Out(n+1) is set as the off voltage.
  • the valid signal is a high voltage signal and the invalid signal is a low voltage signal.
  • the active signal is a low voltage signal and the invalid signal is a high voltage signal. The disclosure is not limited herein.
  • the input signal Out(n-1) signal in the above example is the output signal of the upper stage driving unit of the nth stage driving unit (i.e., the "n-1"th stage driving unit).
  • the reset signal Out(n+1) signal is an output signal of the next-stage driving unit of the nth stage driving unit (ie, the "n+1"th stage driving unit).
  • the Out(n-1) signal can be set as an excitation pulse signal as an Out(n+1) signal at this time since it does not have the upper stage driving unit.
  • an excitation pulse signal can also be set as the Out(n+1) signal.
  • the timing temperature measuring device 430 is responsible for counting the operating time and operating temperature of the driving unit 115, and evaluating the threshold voltage shift of the second transistor M2, the fifth transistor M5, and the eighth transistor M8, and storing the result in In the control device 440.
  • the operation process of the circuit shown in FIG. 3B includes the charging process of the first phase, the output process of the second phase, the discharging process of the third phase, and the sustaining process of the fourth phase.
  • the timing chart of each phase can refer to FIG. 5A and FIG. 5B. .
  • the four stages corresponding to the turned-on transistors are as shown in FIGS. 6A-6D (wherein the compensation circuit portion of the figure includes only the first compensation transistor of FIG. 2B or one of the compensation circuits of FIG. 3C).
  • the thickened portion of the solid line in FIGS. 6A-6D indicates that the transistor is in an on state, and the other is not in a closed state.
  • Phase 1 The charging phase inputs the input signal Out(n-1) to the input terminal INPUT, the first transistor M1 is turned on, and the pull-up node pu is charged to Vgh (for example, a high level).
  • the fifth transistor M5 and the eighth transistor M8 are turned on to pull the first pull-down node pd and the second pull-down node PD-CN to a low level;
  • Phase 2 In the output phase, the pull-up node pu is pulled up to the high level during the charging phase, and the fifth transistor M5 and the eighth transistor M8 are turned on, and the first pull-down node pd and the second pull-down node PD_CN are continuously discharged. A clock signal CLK becomes a high level. Under the action of the capacitor C1, the pull-up node pu is bootstrapped to a higher potential, and the second transistor M2 is more fully turned on to output the first clock CLK to the output terminal.
  • Phase 3 The discharge phase inputs Out(n+1) to the reset signal line RESET, and the tenth transistor M10 and the third transistor M3 are turned on, respectively discharging the pull-up node pu and the output terminal, and the potential of the pull-up node pu decreases.
  • the fourth transistor M4 and the fifth transistor M5 are turned on to pull the first pull-down node pd to a high potential.
  • Phase 4 The sustain phase pull-down node pd has been pulled high to the discharge phase, at which time the fourth transistor M4, the ninth transistor M9, the sixth transistor M6, and the seventh transistor M7 are turned on, and the pull-up node pu point and the output terminal are Pulling low, keeps the output of the driver unit in the shutdown state as Vgl (for example, low level).
  • the control device 440 relies on the power provided by the power supply device Force, output a forward bias to the second compensation signal line for forward bias compensation.
  • the timing and the turned-on transistor are as shown in FIG. 5B.
  • the forward bias turns on the eleventh transistor M11, and outputs it to the pull-up node pu point, and the second transistor M2, the fifth transistor M5, and the eighth transistor M8.
  • the negative threshold voltage Vth offset accumulated by the three transistors during operation of the drive unit can be recovered.
  • the output time T of the second compensation signal Off_Compensation is calculated from the data recorded by the timing temperature measuring device 430. After the recovery process is over, the compensation circuit stops working.

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Abstract

一种移位寄存器、显示装置和驱动方法。移位寄存器包括：驱动单元（115），被配置为给相应的像素单元组提供栅线信号；和与驱动单元（115）对应设置的补偿电路（110）；其中，补偿电路（110）被配置为补偿驱动单元（115）中的一或多个晶体管的阈值电压偏移。该移位寄存器在显示装置不工作期间进行相关晶体管的阈值电压补偿，可以实现移位寄存器使用寿命的延长。

Description

移位寄存器及驱动方法、栅驱动电路以及显示装置 技术领域
本公开的实施例涉及一种移位寄存器及驱动方法、栅驱动电路以及显示装置。
背景技术
当今人类不仅对产品的外观和质量有高要求，而且对产品的价格和实用性有更高的关注。在显示领域，由于晶体管阈值电压导致的不稳定性因素，会进一步导致由多个晶体管构成的栅驱动电路的工作不稳定且缩短栅驱动电路的工作寿命。
发明内容
本公开的至少一个实施例提供一种移位寄存器，包括：驱动单元，被配置为给相应的像素单元组提供栅线信号；和与所述驱动单元对应设置的补偿电路；其中，所述补偿电路被配置为补偿所述驱动单元中的一个或多个晶体管的阈值电压偏移。
例如，在所述移位寄存器的一些实施例中，所述补偿电路包括：补偿晶体管，所述补偿晶体管的栅极与补偿控制线相连，所述补偿晶体管的第一极与第一补偿信号线相连，所述补偿晶体管的第二极与上拉节点相连；其中，所述补偿控制线用于向所述栅极提供控制所述补偿晶体管导通的控制信号；所述第一补偿信号线用于向所述第一极提供正向补偿电压或者负向补偿电压。
例如，在所述移位寄存器的一些实施例中，所述补偿电路包括：第一补偿晶体管以及第二补偿晶体管；其中所述第一补偿晶体管为N型晶体管和所述第二补偿晶体管中为P型晶体管；所述第一补偿晶体管的栅极同时与第二补偿信号线和所述第一补偿晶体管的第一极相连，所述第一补偿晶体管的第二极与所述驱动单元的上拉节点相连；所述第二补偿晶体管的栅极同时与所述第二补偿信号线和所述第二补偿晶体管的第一极相连，所述第二补偿晶 体管的第二极与所述驱动单元的所述上拉节点相连；其中，所述第二补偿信号线用于向所述第一补偿晶体管的第一极或者向所述第二补偿晶体管的第一极提供补偿电压。
例如，在所述移位寄存器的一些实施例中，所述驱动单元包括：上拉电路，被配置为将第一时钟信号输出为栅线信号；上拉控制电路，被配置为控制所述上拉电路的打开时间；下拉电路，被配置为在第一时间将所述栅线信号拉低为低电位；下拉维持电路，被配置为维持所述栅线信号的低电位状态；下拉维持控制电路，被配置为维持下拉控制点处于低电位；所述上拉电路或者下拉维持控制电路均至少包含一个晶体管；其中，所述补偿电路，被配置为向所述上拉电路或者下拉维持控制电路中的部分晶体管写入补偿电压。
例如，在所述移位寄存器的一些实施例中，所述上拉控制电路包括第一晶体管，所述第一晶体管的第一极与输入信号线连接以接收输入信号，所述第一晶体管的栅极与所述第一极连接，所述第一晶体管的第二极与所述上拉节点相连；所述上拉电路包括第二晶体管，该第二晶体管的栅极与所述上拉节点相连，所述第二晶体管的第一极与所述第一时钟相连，所述第二晶体管的第二极与输出端相连；所述下拉电路包括第三晶体管，所述第三晶体管的第一极与所述输出端连接，所述第三晶体管的栅极与复位信号线连接，所述第三晶体管的第二极与第一电源线连接；其中，所述第一电压线用于传输所述第一电压；所述复位信号线用于传输所述复位信号；所述下拉维持控制电路包括第四晶体管和第五晶体管，所述第四晶体管的第一极与第二时钟信号线连接，所述第四晶体管的栅极与所述第二下拉节点相连，所述第四晶体管的第二极与所述第一下拉节点相连；所述第五晶体管的第一极与所述下拉节点相连，所述第五晶体管的栅极与所述上拉节点相连，所述第五晶体管的第二极与所述第一电源线连接；其中，所述第二时钟限号线用于传输第二时钟信号；所述第一电源线用于传输所述第一电压；所述下拉维持电路包括第六晶体管以及第七晶体管，所述第六晶体管与所述第七晶体的第一极均与所述第一电源线连接，所述第六晶体管与所述第七晶体管的栅极均与第一下拉节点连接，所述第六晶体管与所述第七晶体管的第二极均与所述上拉节点连接；其中，所述第一电压线用于传输所述第一电压。
例如，在所述移位寄存器的一些实施例中，所述下拉维持控制电路还包 括第八晶体管和第九晶体管；所述第八晶体管的第一极与所述第二下拉节点相连，所述第八晶体管的栅极与所述上拉节点相连，所述第八晶体管的第二极与所述第一电源线连接；所述第九晶体管的第一极与所述第二时钟信号连接以接收第二时钟信号，所述第九晶体管的栅极与所述第一极相连，所述第九晶体管的第二极与所述第二下拉节点相连。
例如，在所述移位寄存器的一些实施例中，所述移位寄存器还包括复位电路，被配置为初始化阶段使得所述上拉节点放电。
例如，在所述移位寄存器的一些实施例中，所述复位电路包括第十晶体管，所述第十晶体管的第一极与所述上拉节点相连，所述第十晶体管的栅极与所述复位信号连接，所述第十晶体管的第二极与所述第一电源线连接。
本公开实施例还提供一种栅驱动电路，包括如上所述的任一移位寄存器。
本公开的至少一个实施例还提供一种显示装置，包括上述实施例的栅驱动电路以及与所述栅驱动电路相连的显示面板。
例如，在所述显示装置的一些实施例中，还包括：计时测温装置，被配置为测量所述显示面板开机时所述栅驱动电路的各驱动单元的工作时长以及工作时的温度，基于统计的时间和温度得到各驱动单元的上拉电路或者下拉维持控制电路中晶体管的阈值电压偏移情况，并依据阈值电压偏移情况计算晶体管的补偿时长及补偿电压；控制装置，被配置为存储由所述计时测温装置计算得到的补偿电压和补偿时长，并向与所述栅驱动电路的各驱动单元对应的补偿电路提供所述补偿电压；以及内置电源，被配置为向所述栅驱动电路的补偿电路及所述控制装置供电。
例如，在所述显示装置的一些实施例中，所述控制装置还被配置为：当判断所述显示面板处于关机状态时，向所述栅驱动电路的补偿电路提供所述补偿电压，其中所述补偿电压用于对驱动单元的上拉电路或者下拉维持控制电路中部分晶体管进行阈值电压补偿。
例如，在所述显示装置的一些实施例中，所述控制装置还被配置为在所述补偿时间段内向所述补偿电路提供补偿电压。
例如，在所述显示装置的一些实施例中，所述补偿电压包括正向补偿电压或负向补偿电压；当执行正向偏压补偿时，所述控制装置向所述第一补偿信号线传输正向补偿电压；当执行负向偏压补偿时，所述控制装置向所述第 一补偿信号线传输负向补偿电压。
本公开的至少一个实施例还提供一种驱动方法，用于所述移位寄存器，包括：在充电阶段，设置输入信号为有效信号，设置第一时钟信号为无效信号，设置第二时钟信号为有效信号，设置复位信号为关闭电压；在输出阶段，设置所述输入信号为无效信号，设置所述第一时钟信号为有效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为关闭电压；在放电阶段，设置所述输入信号为无效信号，设置所述第一时钟信号为无效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为开启电压；在保持阶段，设置所述输入信号为无效信号，设置所述第二时钟信号为无效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为关闭电压；以及在补偿阶段，设置所述输入信号为无效信号，设置所述第一时钟信号为无效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为关闭电压，设置所述补偿控制信号为开启电压并设置所述第一补偿信号线在补偿时间内传输有效信号，或者设置所述第二补偿信号线在补偿时长内传输有效信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开的一个实施例提供的移位寄存器的示意图；
图2A为本公开的一个实施例提供的补偿电路的示意图；
图2B为本公开的另一个实施例提供的补偿电路的示意图；
图3A为本公开的一个实施例提供的驱动单元和补偿电路的示意框图；
图3B为图3A所示的驱动单元和补偿电路的一个示例性的电路图；
图3C为图3A所示的驱动单元和补偿电路的另一个示例性的电路图；
图4为本公开的一个实施例提供的显示装置的示意图；
图5A和图5B为本公开的一个实施例提供的用于图3B和图3C所示的电路结构的驱动时序图；
图6A-图6D为本公开的一个实施例提供的基于图5B时序图的各个晶体管的工作示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管该连接是直接还是间接的。
本公开的实施例提供了一种具备阈值漂移修正功能的移位寄存器。在显示面板不工作期间，本公开的实施例对移位寄存器中的多个晶体管施加反向栅压或者正向栅压，以恢复显示装置在工作中产生的阈值电压漂移，进而延长栅移位寄存器的寿命。此外，本公开实施例由于在显示装置不工作期间进行相关晶体管的阈值电压补偿因而对显示器的电量消耗较少，所以可以实现移位寄存器使用寿命的大大延长，尤其适合用于类似公共显示等需要超长时间持续稳定工作的应用场景中的显示器。
本公开实施例提供一种移位寄存器，包括：驱动单元，被配置为给相应的像素单元组提供栅线信号；以及与所述驱动单元对应设置的补偿电路；其中，所述补偿电路被配置为补偿所述驱动单元中的一个或多个晶体管的阈值电压偏移。如图1所示，移位寄存器100包括：多个驱动单元115(例如，115a、115b，……，115n)和与每个驱动单元115一一对应设置的补偿电路110(例如，110a、110b、……，110n)。各驱动单元115可以被配置为给相应的像素单元组提供栅线信号。各所述补偿电路110被配置为补偿与其对应的驱动单元115中的一或多个晶体管的阈值电压偏移。当然，移位寄存器100可以包括一或多个驱动单元115以及与每个驱动单元115一一对应设置的补偿电路110。对于一个移位寄存器100中所包含的驱动单元115和补偿电路110 的数量，本公开在此不作限定。
在一些实施例中，一个像素单元组的结构与像素单元的在显示面板上的排列方式相关。例如，当像素单元以行的形式排列时，一个像素单元组为一整行的像素单元。当像素单元以列的方式排列时，一个像素单元组也可以为一整列的像素单元。本公开实施例并不对像素单元的排列方式进行限制，例如像素单元也可以以斜线的方式在显示面板上排列，此时一个像素单元组也可以为一条斜线上所包含的所有像素单元。
在一些实施例中，补偿电路110所补偿的一个或多个晶体管与驱动单元115的具体电路结构相关。通常驱动单元115包含多个晶体管，且这些晶体管可以被用作时序控制管或输出管。由于不同的晶体管在工作中所处的状态各不相同，因此它们阈值电压漂移的程度也不相同。所以需要根据具体驱动电路中各晶体管的工作状态而获得需要采用补偿电路110进行补偿的晶体管。例如，可以采用补偿电路110来补偿驱动单元115中所包含的下拉晶体管。此外，图1中示出的驱动单元115a、115b,……,115n可以分别称为第一级驱动单元115a、第二级驱动单元115b，……，第n级驱动单元115n。
下面结合图2A和图2B分析两种不同的补偿电路。
图2A示出了本公开的实施例提供的一种补偿电路110的具体结构,该补偿电路110可以包括：补偿晶体管211，该补偿晶体管211的栅极与补偿控制线213相连，补偿晶体管211的第一极与第一补偿信号线215相连，补偿晶体管211的第二极与驱动单元115中的上拉节点(示出于图3A中)相连。补偿控制线213用于向补偿晶体管211的栅极提供用来控制该补偿晶体管211导通的控制信号，例如，控制信号可以为脉冲信号。此外，第一补偿信号线用于向补偿晶体管211的第一极提供正向补偿电压或者负向补偿电压。
例如，当图2A示出的补偿控制线213向补偿晶体管211的栅极提供高电平时，该补偿晶体管211被导通，此时再通过第一补偿信号线215输入高电平以实现对驱动单元115中一个或多个晶体管的正偏压补偿，或者通过第一补偿信号线215输入低电平信号以实现对驱动单元115中一个或多个晶体管的负偏压补偿。
图2A提供的补偿电路110可以对驱动单元115中包括的一个或多个晶体管进行正向偏压补偿或者负向偏压补偿，进而校正被补偿的晶体管的阈值 电压Vth漂移，提高栅驱动电路的工作寿命。
图2B示出了本公开的实施例提供的补偿电路110的另一结构示意图。该补偿电路110包括：第一补偿晶体管212和第二补偿晶体管213，其中第一补偿晶体管212和第二补偿晶体管213中的一个为N型晶体管而另一个为P型晶体管。此外，参考图2B可知第一补偿晶体管212的栅极同时与第二补偿信号线225和第一补偿晶体管212的第一极相连，第一补偿晶体管212的第二极与相应的驱动单元的上拉节点(示出在图3A中)相连。第二补偿晶体管213的栅极同时与第二补偿信号线225和第二补偿晶体管213的第一极相连，第二补偿晶体管213的第二极与相应的驱动单元的上拉节点相连(示出在图3A中)。例如，第一补偿晶体管212的第二极与第二补偿晶体管213的第二极相连；第一补偿晶体管212的栅极与第二补偿晶体管213的栅极相连；其中，第二补偿信号线225用于向第一补偿晶体管212的第一极或者向第二补偿晶体管213的第一极提供一个补偿电压。例如，可以采用图2B示出的第二补偿信号线225向第一补偿晶体管212或者第二补偿晶体管213的第一极提供一个正向补偿电压或者负向补偿电压，进而对驱动单元115中的一个或多个晶体管进行偏压补偿。例如，可以采用第二补偿信号线225向第一补偿晶体管212的栅极和第一极加载正向补偿电压，使得第一补偿晶体管212导通，之后再由第一补偿晶体管212的第二极向上拉节点输出该正向补偿电压。同时可以采用第二补偿信号线225向第二补偿晶体管213的栅极和第一极加载负向补偿电压，使得第二补偿晶体管213导通，之后再由第二补偿晶体管213的第二极向上拉节点输出该负向补偿电压。具体为，可以通过图2B示出的第二补偿信号线225输入高电平信号，以通过第一补偿晶体管212的导通，实现对驱动单元115中一个或多个晶体管的正偏压补偿。或者，也可以通过图2B示出的第二补偿信号线225输入低电平信号，以通过第二补偿晶体管213的导通，实现对驱动单元115中一个或多个晶体管的负偏压补偿。
下面结合图3A-图3C中提供的驱动单元的电路结构进一步阐述移位寄存器以及栅驱动电路的结构。
图3A仅示出了移位寄存器中的一个驱动单元以及与该驱动单元对应设置的一个补偿电路310。补偿电路310的结构可以与图2A或图2B所示的补 偿电路110的结构相同或相类似。图3A示出的驱动单元可以包括：上拉电路316、上拉控制电路312、下拉电路318、下拉维持电路320以及下拉维持控制电路314。
上拉电路316被配置为将第一时钟信号输出为栅线信号(该栅线信号将被传输到像素单元组作为，例如，显示扫描信号)。上拉控制电路312被配置为控制上拉电路316的打开时间。下拉电路318被配置为在第一时间将输出端输出的栅线信号拉低为低电位。下拉维持电路320被配置为维持栅线信号的低电位状态。下拉维持控制电路314被配置为维持下拉控制点(例如，图中示出的第一下拉节点)处于低电位。例如，上拉电路316或者下拉维持控制电路314均至少包含一个晶体管。补偿电路310，被配置为向上拉电路316或者下拉维持控制电路314中的部分晶体管写入补偿电压。
例如，上拉控制电路312与输入端相连以接收输入信号，例如，输入信号可以为上一级驱动单元的输出端输出的信号。下拉维持控制电路314与第二时钟信号相连以接收第二时钟信号。上拉电路316与第一时钟信号相连以接收第一时钟信号，例如，第一时钟信号为脉冲信号。下拉电路318以及下拉维持电路320还与第一电源线相连以接收第一电压。例如，第一电压可以为一个低电平信号。例如，输入端的输入信号为上一级驱动单元的输出端输出的信号(例如，对于图1示出的第二级驱动单元115b，其上一级驱动单元为第一级驱动单元115a)。第二时钟信号与第一时钟信号相位相反。复位线上的复位信号为下一级驱动单元的输出端输出的信号(例如，对于图1示出第一级的驱动单元115a，其下一级驱动单元为第二极驱动单元115b)。由于驱动单元115a不存在上一级驱动单元，因此可以在其输入端输入一脉冲激活信号。
例如，驱动单元还可以包括复位电路322，该复位电路322与复位信号线相连以接收复位信号。复位电路322被配置为在初始化阶段使得上拉节点放电，为驱动单元稳定工作做好准备。
例如，图3A示出的驱动单元还包括第二下拉节点(图3B和图3C中示出)，第一下拉节点与第二下拉节点又分别与下拉维持控制电路314相连。
下面以图3B和图3C中的晶体管均为N型晶体管为例，详细说明图3A示出的移位寄存器的结构。
图3B示出了移位寄存器中的一个驱动单元和一个补偿电路。驱动单元的上拉控制电路312包括第一晶体管M1，第一晶体管M1的第一极与输入信号线连接以接收输入信号，第一晶体管M1的栅极与第一极连接，第一晶体管M1的第二极与上拉节点pu相连。驱动单元的上拉电路316包括第二晶体管M2，该第二晶体管M2的栅极与上拉节点pu相连，第二晶体管M2的第一极与第一时钟相连，第二晶体管M2的第二极与输出端相连。驱动单元的下拉电路318包括第三晶体管M3，第三晶体管M3的第一极与输出端连接，第三晶体管M3的栅极与复位信号线连接，第三晶体管M3的第二极与第一电源线连接，例如，第一电压线用于传输第一电压VSS；复位信号线用于传输复位信号；下拉维持电路包括第六晶体管M6以及第七晶体管M7，第六晶体管M6与第七晶体M7的第一极均与第一电源线连接，第六晶体管M6与第七晶体管M7的栅极均与第一下拉节点pd连接，第六晶体管M6与第七晶体管M7的第二极均与上拉节点pu连接；第一电压线用于传输第一电压Vss；下拉维持控制电路包括第四晶体管M4和第五晶体管M5，第四晶体管M4的第一极与第二时钟信号线连接，第四晶体管M4的栅极与第二下拉节点PD-CN相连，第四晶体管M4的第二极与第一下拉节点pd相连；第五晶体管M5的第一极与第一下拉节点pd相连，第五晶体管M5的栅极与上拉节点pu相连，第五晶体管M5的第二极与第一电源线连接；其中，第二时钟信号线用于传输第二时钟信号，第一电源线用于传输第一电压VSS。
例如，图3B示出驱动单元的下拉维持控制电路314还可以包括第八晶体管M8和第九晶体管M9；第八晶体管M8的第一极与第二下拉节点PD-CN相连，第八晶体管M8的栅极与上拉节点pu相连，第八晶体管M8的第二极与第一电源线Vss连接；第九晶体管M9的第一极与第二时钟信号连接以接收第二时钟信号，第九晶体管M9的栅极与第一极相连，第九晶体管M9的第二极与第二下拉节点PD-CN相连。
例如，图3B示出的驱动单元的复位电路包括第十晶体管M10，第十晶体管M10的第一极与上拉节点pu相连，第十晶体管M10的栅极与复位信号连接以接收复位信号RESET，第十晶体管M10的第二极与第一电源线连接以接收第一电压Vss。
例如，图3B示出的补偿电路具体可以参考图2A提供的补偿电路。此时 补偿电路的输出端与上拉节点pu相连。例如，通过图3B的补偿电路可以实现对上拉电路包括的第二晶体管M2、以及上拉维持电路314包括的第五晶体管M5以及第八晶体管M8进行正向偏压补偿或者负向偏压补偿。
此外，针对图3B示出的补偿电路所补偿的驱动单元，该驱动单元所包括的晶体管的分析过程如下：如图3B所示的阵列基板栅驱动电路的移位寄存器中的一个驱动单元，该驱动单元采用一个与第一时钟信号反相的第二时钟信号控制第一下拉节点pd电压来降低输出端输出VGL时的噪音水平，进而维持移位寄存器的稳定工作。结合图3B可知通过第四晶体管M4、第五晶体管M5、第八晶体管M8以及第九晶体管M9控制第一下拉节点(pd点)的电压，由此可知第四晶体管M4、第五晶体管M5、第八晶体管M8以及第九晶体管M9这四个晶体管的状态决定了栅驱动电路的正常工作与否。影响晶体管持续工作条件下阈值电压偏移的外界因素主要包括两点，其一是施加在晶体管栅极上的电压，其二是加在栅极上的电压信号的占空比。在本例中，第四晶体管M4、第五晶体管M5、第八晶体管M8以及第九晶体管M9这四个晶体管栅压的占空比有显著不同。如下表1列出了估算得到的占空比。下面仅考虑由于晶体管阈值电压Vth漂移造成栅驱动电路的失效现象。结合表1可知负责第一下拉节点pd点与第二下拉节点PD-CN点下拉的第五晶体管M5和第八晶体管M8在栅驱动电路工作时栅极所受电压的占空比约为99.2％，远高于负责第一下拉节点pd和第二下拉节点PD-CN充电的第四晶体管M4和第九晶体管M9，负责输出的第二晶体管M2同样有负向压力高的问题。因此经过较长时间的持续工作后，第五晶体管M5和第八晶体管M8的阈值电压Vth偏移会严重的负向漂移，所以导致第五晶体管M5以及第八晶体管M8在较低栅压下就会很容易打开，而进一步导致栅驱动电路不稳定。此时，若上拉节点pu点输入噪声，则第五晶体管M5和第八晶体管M8将同时打开，导致第一下拉节点pd点至较低电平，第六晶体管M6对上拉节点pu点的放电作用由于其栅压降低而减弱，上拉节点pu点的噪声由于得不到很快释放而积累，并通过第二晶体管M2的输出传递给后续行，而造成整个栅驱动电路失效。
表1
编号 节点 占空比
M5 PD-CN 50％
M3 pu 99.2％
M6 pu 99.2％
M8 pu 99.2％
M9 第二时钟 50％
通过图3B示出的补偿电路可以补偿驱动单元包括的第二晶体管M2，第五晶体管M5以及第八晶体管M8的阈值电压偏移，该处偏移包括正向偏移或者负向偏移。此外，图3B示出的补偿电路具体可以参考图2A提供的补偿电路，也可以采用图2B示出的补偿电路。
图3C与图3B的不同在于补偿电路部分，图3C的补偿电路的具体结构可以参考图2B提供的补偿电路。采用图3C提供的补偿电路可以对驱动单元包括的第二晶体管M2，第五晶体管M5以及第八晶体管M8的阈值电压偏移进行补偿，该处补偿仅包括正向偏移补偿。例如，通过图2B的第二补偿信号(对应于图3C的补偿信号)提供的正向偏压补偿第二晶体管M2，第五晶体管M5以及第八晶体管M8的阈值电压偏移。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管，本公开的实施例以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6以及第七晶体管M7等均为N型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用P型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
本公开实施例还提供一种栅驱动电路，包括如上所述的任一移位寄存器。例如，所述栅驱动电路可以包括多个级联的移位寄存器。
如图4所示，本公开的实施例还提供一种显示装置，该显示装置包括栅驱动电路199(其包含移位寄存器)以及与栅驱动电路199相连的显示面板 420。图4示出了栅驱动电路199中的移位寄存器，其包括补偿电路(110a、110b、……、110n)以及与各补偿电路对应设置的驱动单元(115a、115b、……、115n)，补偿电路和驱动单元的具体结构可以参考图1、图2A-2B以及图3A-3C。此外，图4仅示出了显示装置包含的部分单元，例如，图4的显示装置还可以包括数据驱动电路，多条扫描线，多条数据线或者时钟电路(图中未示出)等。
在一些实施例中，显示装置还包括：计时测温装置430，控制装置440以及内置电源450。计时测温装置430被配置为测量显示面板420开机时栅驱动电路199的各驱动单元115的工作时长以及工作时的温度，之后基于统计的时间和温度得到各驱动单元115的上拉电路或者下拉维持控制电路中晶体管的阈值电压偏移情况，最后依据阈值电压偏移情况计算晶体管的补偿时长及补偿电压。控制装置440被配置为存储由计时测温装置430计算得到的补偿电压和补偿时长，并向与栅驱动电路199的各驱动单元115对应的补偿电路110提供补偿电压。内置电源450被配置为向所述栅驱动电路199的补偿电路及所述控制装置供电。
例如，在一些实施例中计时测温装置430可以采用计时传感器和温度测量传感器实时采集相关的数据,并采用处理器基于采集的数据计算补偿电压。计时测温装置430还可以设置有存储器，该存储器可以用于预先存储一阈值补偿对照表，该阈值补偿对照表依据晶体管工作的温度和时间提供一个阈值电压补偿参考值或者阈值电压补偿参考范围。之后计时测温装置430再根据统计的晶体管的工作时长和温度通过查表获得对应的补偿电压或者补偿范围。
例如，在一些实施例中，控制装置440还被配置为：当判断显示面板处于关机状态时，向栅驱动电路199的补偿电路110提供计时测温装置430得到的补偿电压。例如，补偿电压用于对与补偿电路110相连的驱动单元115的上拉电路或者下拉维持控制电路中的部分晶体管进行阈值电压补偿。
例如，在一些实施例中控制装置440还被配置为在计时测温装置430计算得到的补偿时长内向补偿电路110提供补偿电压。
例如，在一些实施例中，补偿电压包括正向补偿电压或负向补偿电压。当执行正向偏压补偿时，控制装置440向第一补偿信号线(具体可以参考图 2A示出的第一补偿信号)传输正向补偿电压。当执行负向偏压补偿时，控制装置3440向第一补偿信号线(图2A示出的)传输负向补偿电压。
例如，在一些实施例中，补偿电压可以仅包括正向补偿电压，此时当监测显示面板处于不工作状态时，由控制装置440向第二补偿信号线传输正向补偿电压(具体可以参考图2B示出的第二补偿信号线225)。
如图5A和图5B所示，本公开实施例还提供一种用于驱动图3B和图3C示出的移位寄存器的驱动时序图。
如5A所示，驱动方法包括充电阶段、输出阶段、放电阶段、保持阶段以及补偿阶段。
在充电阶段1，设置输入信号Out(n-1)为有效信号，设置第一时钟信号CLK为无效信号，设置第二时钟信号CLKB为有效信号，设置复位信号Out(n+1)为关闭电压。在输出阶段2，设置输入信号Out(n-1)为无效信号，设置第一时钟信号CLK为有效信号，设置第二时钟信号CLKB为无效信号，设置复位信号Out(n+1)为关闭电压。在放电阶段3，设置输入信号Out(n-1)为无效信号，设置第一时钟CLK信号为无效信号，设置第二时钟信号CLKB为无效信号，设置复位信号Out(n+1)为开启电压。在保持阶段4，设置输入信号Out(n-1)为无效信号，设置第一时钟信号CLK为无效信号，设置第二时钟信号CLKB为无效信号，设置复位信号Out(n+1)为关闭电压。在补偿阶段，设置输入信号Out(n-1)为无效信号，设置第一时钟信号CLK为无效信号，设置第二时钟信号CLKB为无效信号，设置复位信号Out(n+1)为关闭电压，设置补偿控制信号Off_Compensation_Ctrl为开启电压并设置所述第一补偿信号线Off_Compensation_PW在补偿时间T内传输有效信号，或者设置所述第二补偿信号线在补偿时长T(如图5B所示)内传输有效信号。在一些例子中，有效信号为高电压信号，无效信号为低电压信号。而在另一些例子中，有效信号为低电压信号，无效信号为高电压信号。本公开在此不作限定。
以上示例中的输入信号Out(n-1)信号为第n级驱动单元的上一级驱动单元(即第“n-1”级驱动单元)的输出端信号。复位信号Out(n+1)信号为第n级驱动单元的下一级驱动单元(即第“n+1”级驱动单元)的输出端信号。此外，当n等于1时，由于其不存在上一级驱动单元所以此时可以设置Out(n-1)信号为一激励脉冲信号作为Out(n+1)信号。当n为最后一级驱动单元时，其 不存在下一级驱动单元此时也可以设置一激励脉冲信号作为Out(n+1)信号。
下面结合图4、图5A、图5B以及图6A-6D详细说明用于驱动图3C电路的驱动过程。
当显示装置开机时计时测温装置430负责统计驱动单元115的工作时间和工作温度，并评估第二晶体管M2、第五晶体管M5和第八晶体管M8的阈值电压偏移情况，并将结果保存在控制装置440中。图3B示出的电路的工作过程包括阶段一的充电过程，阶段二的输出过程，阶段三的放电过程，阶段四的保持过程共四个部分，各个阶段的时序图可以参考图5A和图5B。此外，这四个阶段对应开启的晶体管如图6A-6D(其中图中的补偿电路部分仅包含图2B中的第一补偿晶体管或者图3C提供的补偿电路中的一个补偿晶体管)中所示，其中图6A-6D中以实线加粗的部分表示晶体管为导通状态，其他无加粗为关闭状态。
阶段一：充电阶段将输入信号Out(n-1)输入至输入端INPUT，第一晶体管M1打开，上拉节点pu被充电至Vgh(例如，高电平)。第五晶体管M5及第八晶体管M8打开，将第一下拉节点pd和第二下拉节点PD-CN下拉至低电平；
阶段二：输出阶段在充电阶段上拉节点pu被拉升至高电平，第五晶体管M5和第八晶体管M8打开，继续对第一下拉节点pd和第二下拉节点PD_CN放电，此时由于第一时钟信号CLK变为高电平，在电容C1的作用下，上拉节点pu点自举至更高的电位，第二晶体管M2更为充分的打开，将第一时钟CLK输出至输出端。
阶段三：放电阶段将Out(n+1)输入至复位信号线RESET，第十晶体管M10及第三晶体管M3开启，分别对上拉节点pu和输出端放电，随着上拉节点pu电位降低，第四晶体管M4和第五晶体管M5开启，将第一下拉节点pd拉升至高电位。
阶段四：保持阶段在放电阶段下拉节点pd已被拉升至高电位，此时第四晶体管M4、第九晶体管M9、第六晶体管M6以及第七晶体管M7打开，将上拉节点pu点和输出端拉至低电位，保持该级驱动单元在关机状态下的输出为Vgl(例如，低电平)。
关机阶段：在显示器关机状态下，控制装置440依赖电源装置提供的电 力，向第二补偿信号线输出一个正向偏压，进行正向偏压补偿。此时的时序和开启的晶体管如图5B所示，该正向偏压使第十一晶体管M11导通，输出至上拉节点pu点，对第二晶体管M2、第五晶体管M5和第八晶体管M8施加正向偏压，可以恢复这三个晶体管在驱动单元工作期间积累的负向阈值电压Vth偏移。此外，第二补偿信号Off_Compensation的输出时间T由计时测温装置430记录的数据计算得出。在恢复过程结束后，则补偿电路停止工作。
本公开实施例附图只涉及到与本公开实施例涉及到的结构，而其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的不同特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
本公开要求于2016年10月31日递交的中国专利申请第201610928693.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。

Claims (15)

  1. 一种移位寄存器，包括：
    驱动单元，被配置为给相应的像素单元组提供栅线信号；和
    与所述驱动单元对应设置的补偿电路；
    其中，所述补偿电路被配置为补偿所述驱动单元中的一个或多个晶体管的阈值电压偏移。
  2. 如权利要求1所述移位寄存器，其中，所述补偿电路包括：
    补偿晶体管，所述补偿晶体管的栅极与补偿控制线相连，所述补偿晶体管的第一极与第一补偿信号线相连，所述补偿晶体管的第二极与上拉节点相连；
    其中，所述补偿控制线用于向所述栅极提供控制所述补偿晶体管导通的控制信号；所述第一补偿信号线用于向所述第一极提供正向补偿电压或者负向补偿电压。
  3. 如权利要求1所述移位寄存器，其中，所述补偿电路包括：第一补偿晶体管以及第二补偿晶体管；其中所述第一补偿晶体管为N型晶体管和所述第二补偿晶体管中为P型晶体管；
    所述第一补偿晶体管的栅极同时与第二补偿信号线和所述第一补偿晶体管的第一极相连，所述第一补偿晶体管的第二极与所述驱动单元的上拉节点相连；
    所述第二补偿晶体管的栅极同时与所述第二补偿信号线和所述第二补偿晶体管的第一极相连，所述第二补偿晶体管的第二极与所述驱动单元的所述上拉节点相连；
    其中，所述第二补偿信号线用于向所述第一补偿晶体管的第一极或者向所述第二补偿晶体管的第一极提供补偿电压。
  4. 如权利要求1所述移位寄存器，其中，
    所述驱动单元包括：
    上拉电路，被配置为将第一时钟信号输出为栅线信号；
    上拉控制电路，被配置为控制所述上拉电路的打开时间；
    下拉电路，被配置为在第一时间将所述栅线信号拉低为低电位；
    下拉维持电路，被配置为维持所述栅线信号的低电位状态；
    下拉维持控制电路，被配置为维持下拉控制点处于低电位；
    所述上拉电路或者下拉维持控制电路均至少包含一个晶体管；
    其中，所述补偿电路被配置为向所述上拉电路或者下拉维持控制电路中的部分晶体管写入补偿电压。
  5. 如权利要求4所述的移位寄存器，其中，
    所述上拉控制电路包括第一晶体管，所述第一晶体管的第一极与输入信号线连接以接收输入信号，所述第一晶体管的栅极与所述第一极连接，所述第一晶体管的第二极与所述上拉节点相连；
    所述上拉电路包括第二晶体管，该第二晶体管的栅极与所述上拉节点相连，所述第二晶体管的第一极与所述第一时钟相连，所述第二晶体管的第二极与输出端相连；
    所述下拉电路包括第三晶体管，所述第三晶体管的第一极与所述输出端连接，所述第三晶体管的栅极与复位信号线连接，所述第三晶体管的第二极与第一电源线连接；其中，所述第一电压线用于传输所述第一电压；所述复位信号线用于传输所述复位信号；
    所述下拉维持控制电路包括第四晶体管和第五晶体管，所述第四晶体管的第一极与第二时钟信号线连接，所述第四晶体管的栅极与所述第二下拉节点相连，所述第四晶体管的第二极与所述第一下拉节点相连；所述第五晶体管的第一极与所述第一下拉节点相连，所述第五晶体管的栅极与所述上拉节点相连，所述第五晶体管的第二极与所述第一电源线连接；其中，所述第二时钟限号线用于传输第二时钟信号；所述第一电源线用于传输所述第一电压；
    所述下拉维持电路包括第六晶体管以及第七晶体管，所述第六晶体管与所述第七晶体的第一极均与所述第一电源线连接，所述第六晶体管与所述第七晶体管的栅极均与第一下拉节点连接，所述第六晶体管与所述第七晶体管的第二极均与所述上拉节点连接；其中，所述第一电压线用于传输所述第一电压。
  6. 如权利要求5所述的移位寄存器，其中，
    所述下拉维持控制电路还包括第八晶体管和第九晶体管；
    所述第八晶体管的第一极与所述第二下拉节点相连，所述第八晶体管的 栅极与所述上拉节点相连，所述第八晶体管的第二极与所述第一电源线连接；
    所述第九晶体管的第一极与所述第二时钟信号连接以接收第二时钟信号，所述第九晶体管的栅极与所述第一极相连，所述第九晶体管的第二极与所述第二下拉节点相连。
  7. 如权利要求5所述移位寄存器，其中，还包括复位电路，被配置为初始化阶段使得所述上拉节点放电。
  8. 如权利要求7所述的移位寄存器，其中，所述复位电路包括第十晶体管，所述第十晶体管的第一极与所述上拉节点相连，所述第十晶体管的栅极与所述复位信号连接，所述第十晶体管的第二极与所述第一电源线连接。
  9. 一种栅驱动电路，包括权利要求1-8中任一项所述的移位寄存器。
  10. 一种显示装置，包括权利要求9所述的栅驱动电路以及与所述栅驱动电路相连的显示面板。
  11. 如权利要求10所述的显示装置，还包括：
    计时测温装置，被配置为测量所述显示面板工作时所述栅驱动电路的各驱动单元的工作时长以及工作时的温度，基于统计的时间和温度得到各驱动单元的上拉电路或者下拉维持控制电路中晶体管的阈值电压偏移情况，并依据阈值电压偏移情况计算晶体管的补偿时长及补偿电压；
    控制装置，被配置为存储由所述计时测温装置计算得到的补偿电压和补偿时长，并向与所述栅驱动电路的各驱动单元对应的补偿电路提供所述补偿电压；以及
    内置电源，被配置为向所述栅驱动电路的补偿电路及所述控制装置供电。
  12. 如权利要求11所述的显示装置，其中，
    所述控制装置还被配置为：当判断所述显示面板处于关机状态时，向所述栅驱动电路的补偿电路提供所述补偿电压，其中所述补偿电压用于对驱动单元的上拉电路或者下拉维持控制电路中部分晶体管进行阈值电压补偿。
  13. 如权利要求12所述的显示装置，其中，所述控制装置还被配置为在所述补偿时间段内向所述补偿电路提供补偿电压。
  14. 如权利要求12所述的显示装置，其中，
    所述补偿电压包括正向补偿电压或负向补偿电压；
    当执行正向偏压补偿时，所述控制装置向所述第一补偿信号线传输正向 补偿电压；
    当执行负向偏压补偿时，所述控制装置向所述第一补偿信号线传输负向补偿电压。
  15. 一种驱动方法，用于驱动权利要求1-8任一项所述的移位寄存器，包括：
    在充电阶段，设置输入信号为有效信号，设置第一时钟信号为无效信号，设置第二时钟信号为有效信号，设置复位信号为关闭电压；
    在输出阶段，设置所述输入信号为无效信号，设置所述第一时钟信号为有效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为关闭电压；
    在放电阶段，设置所述输入信号为无效信号，设置所述第一时钟信号为无效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为开启电压；
    在保持阶段，设置所述输入信号为无效信号，设置所述第二时钟信号为无效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为关闭电压；以及
    在补偿阶段，设置所述输入信号为无效信号，设置所述第一时钟信号为无效信号，设置所述第二时钟信号为无效信号，设置所述复位信号为关闭电压，设置补偿控制信号为开启电压并设置所述第一补偿信号线在补偿时间内传输有效信号，或者设置所述第二补偿信号线在补偿时长内传输有效信号。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240379057A1 (en) * 2022-05-30 2024-11-14 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and driving method therefor, and display panel and display apparatus

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356015B (zh) * 2016-10-31 2020-05-12 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置
CN106652882B (zh) * 2017-03-17 2019-09-06 京东方科技集团股份有限公司 移位寄存器单元、阵列基板和显示装置
CN106910470A (zh) * 2017-04-19 2017-06-30 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、显示面板
CN106875913A (zh) * 2017-04-21 2017-06-20 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路
CN106920526B (zh) * 2017-05-04 2020-02-14 合肥鑫晟光电科技有限公司 移位寄存器及其驱动方法和栅极驱动电路
CN107146584B (zh) * 2017-05-05 2019-10-11 惠科股份有限公司 移位暂存电路及其波形产生方法与其应用的显示面板
CN107705762B (zh) 2017-09-27 2020-03-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动装置和显示装置
CN109658879B (zh) * 2017-10-12 2022-01-04 咸阳彩虹光电科技有限公司 显示器的驱动电压补偿方法及电路
CN108230980B (zh) * 2018-01-08 2020-11-13 京东方科技集团股份有限公司 移位寄存器及其放噪控制方法、栅极驱动电路和显示装置
CN107993606B (zh) * 2018-01-22 2021-02-26 京东方科技集团股份有限公司 驱动电路及其驱动方法、电子装置
CN109935198B (zh) * 2018-05-31 2021-01-22 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109935197B (zh) 2018-02-14 2021-02-26 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
CN109935196B (zh) 2018-02-14 2020-12-01 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
WO2019157865A1 (zh) 2018-02-14 2019-08-22 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108447438B (zh) * 2018-04-10 2020-12-08 京东方科技集团股份有限公司 显示装置、栅极驱动电路、移位寄存器及其控制方法
CN108364622B (zh) * 2018-04-24 2020-11-06 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、驱动装置和显示装置
CN108766381B (zh) 2018-06-01 2020-08-11 京东方科技集团股份有限公司 一种移位寄存器电路、阵列基板和显示装置
CN108766383B (zh) * 2018-06-12 2020-12-11 京东方科技集团股份有限公司 移位寄存器单元及移位寄存器电路、显示装置
CN108962157B (zh) * 2018-06-15 2019-11-26 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器及其驱动方法以及显示装置
CN109935199B (zh) * 2018-07-18 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN112639940A (zh) * 2018-09-30 2021-04-09 深圳市柔宇科技股份有限公司 阵列基板栅极驱动电路、薄膜晶体管及显示装置
CN109448630B (zh) * 2019-01-11 2022-06-21 合肥鑫晟光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2020146997A1 (zh) * 2019-01-15 2020-07-23 深圳市柔宇科技有限公司 扫描驱动单元、扫描驱动电路、阵列基板与显示装置
CN110047450A (zh) * 2019-04-01 2019-07-23 深圳市华星光电技术有限公司 栅极驱动电路及阵列基板
CN112133355B (zh) * 2019-06-25 2023-08-04 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置和控制方法
CN112309340A (zh) 2019-08-01 2021-02-02 京东方科技集团股份有限公司 补偿模块及方法、移位寄存器单元、驱动电路、显示装置
CN110634436B (zh) * 2019-09-26 2022-09-23 合肥京东方卓印科技有限公司 栅极驱动电路及显示面板
CN111243543B (zh) * 2020-03-05 2021-07-23 苏州华星光电技术有限公司 Goa电路、tft基板、显示装置及电子设备
CN111243516B (zh) * 2020-03-19 2021-11-05 京东方科技集团股份有限公司 驱动电路、显示面板、显示装置及电路驱动方法
US12340754B2 (en) * 2020-11-24 2025-06-24 Hefei Boe Joint Technology Co., Ltd. Shift register circuit, gate driver circuit and driving method therefor, and display apparatus
CN113658556B (zh) * 2021-08-18 2023-01-20 福州京东方光电科技有限公司 一种电压控制电路、控制方法及显示装置
TWI777777B (zh) * 2021-09-17 2022-09-11 友達光電股份有限公司 位移暫存器及顯示裝置
US11423643B1 (en) * 2021-11-29 2022-08-23 Deeping Source Inc. Method for generating obfuscated image to be used in training learning net work and labeling device using the same
CN114023281B (zh) * 2021-11-30 2023-03-31 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置
CN117198355A (zh) * 2022-05-30 2023-12-08 长鑫存储技术有限公司 半导体器件和存储器
CN115512672B (zh) * 2022-10-25 2023-10-27 业成科技（成都）有限公司 扫描驱动电路及其操作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140091997A1 (en) * 2012-09-28 2014-04-03 Lg Display Co., Ltd. Shift register and flat panel display device having the same
CN104064158A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104318883A (zh) * 2014-10-10 2015-01-28 北京大学深圳研究生院 移位寄存器及其单元、显示器和阈值电压补偿电路
CN105206243A (zh) * 2015-10-28 2015-12-30 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN106356015A (zh) * 2016-10-31 2017-01-25 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI342544B (en) * 2006-06-30 2011-05-21 Wintek Corp Shift register
US20100188385A1 (en) * 2007-07-24 2010-07-29 Koninklijke Philips Electronics N.V. Shift register circuit having threshold voltage compensation
BRPI0920739A2 (pt) * 2008-10-30 2015-12-29 Sharp Kk circuito de registro de deslocamento e dispositivo de exibição, e método para acionar circuito de registro
US9373414B2 (en) * 2009-09-10 2016-06-21 Beijing Boe Optoelectronics Technology Co., Ltd. Shift register unit and gate drive device for liquid crystal display
CN102708824B (zh) * 2012-05-31 2014-04-02 京东方科技集团股份有限公司 薄膜晶体管阈值电压偏移补偿电路及goa电路、显示器
KR101951940B1 (ko) * 2012-09-27 2019-02-25 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 포함한 표시장치
CN103714781B (zh) * 2013-12-30 2016-03-30 京东方科技集团股份有限公司 栅极驱动电路、方法、阵列基板行驱动电路和显示装置
US10810920B2 (en) * 2014-05-02 2020-10-20 Lg Display Co., Ltd. Shift register and display device using the same
CN104332144B (zh) * 2014-11-05 2017-04-12 深圳市华星光电技术有限公司 液晶显示面板及其栅极驱动电路
CN106340273B (zh) * 2015-07-16 2019-02-15 南京瀚宇彩欣科技有限责任公司 移位寄存器和显示装置
TWI587190B (zh) * 2015-11-04 2017-06-11 友達光電股份有限公司 觸控顯示裝置及其移位暫存器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140091997A1 (en) * 2012-09-28 2014-04-03 Lg Display Co., Ltd. Shift register and flat panel display device having the same
CN104064158A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104318883A (zh) * 2014-10-10 2015-01-28 北京大学深圳研究生院 移位寄存器及其单元、显示器和阈值电压补偿电路
CN105206243A (zh) * 2015-10-28 2015-12-30 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
CN106356015A (zh) * 2016-10-31 2017-01-25 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240379057A1 (en) * 2022-05-30 2024-11-14 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and driving method therefor, and display panel and display apparatus
US12592191B2 (en) * 2022-05-30 2026-03-31 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and driving method therefor, and display panel and display apparatus

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