WO2018076501A1 - 一种光放大器突发模式下的光功率和增益探测装置和方法 - Google Patents

一种光放大器突发模式下的光功率和增益探测装置和方法 Download PDF

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WO2018076501A1
WO2018076501A1 PCT/CN2016/110664 CN2016110664W WO2018076501A1 WO 2018076501 A1 WO2018076501 A1 WO 2018076501A1 CN 2016110664 W CN2016110664 W CN 2016110664W WO 2018076501 A1 WO2018076501 A1 WO 2018076501A1
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optical power
optical
fpga device
gain
value
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PCT/CN2016/110664
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English (en)
French (fr)
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于龙
张蔚青
李春雨
陈志�
余春平
卜勤练
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武汉光迅科技股份有限公司
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Priority to US16/345,815 priority Critical patent/US10797798B2/en
Priority to EP16919711.8A priority patent/EP3534549A4/en
Publication of WO2018076501A1 publication Critical patent/WO2018076501A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/29—Repeaters
    • H04B10/291—Repeaters in which processing or amplification is carried out without conversion of the main signal from optical form
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/29—Repeaters
    • H04B10/291—Repeaters in which processing or amplification is carried out without conversion of the main signal from optical form
    • H04B10/293—Signal power control
    • H04B10/2931—Signal power control using AGC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3084—Automatic control in amplifiers having semiconductor devices in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
    • H04B10/0795—Performance monitoring; Measurement of transmission parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
    • H04B10/0795—Performance monitoring; Measurement of transmission parameters
    • H04B10/07955—Monitoring or measuring power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
    • H04B10/0797—Monitoring line amplifier or line repeater equipment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J14/00—Optical multiplex systems
    • H04J14/02—Wavelength-division multiplex systems
    • H04J14/0221—Power control, e.g. to keep the total optical power constant

Definitions

  • the present invention relates to optical communication technologies, and more particularly to improvements in optical amplifiers, and more particularly to an apparatus and method for optical power and gain detection in burst mode for optical amplifiers.
  • the invention is used for solving the problem of detecting optical power and gain of an optical amplifier in the communication field, and is mainly used for accurately detecting optical power and gain in burst mode in the field of broadband optical fiber passive optical network access.
  • the access network is the bridge for users to enter the metropolitan area network/backbone network, and is the “last mile” of the information transmission channel.
  • bandwidth speed has become an urgent need.
  • various new technologies are emerging, and access network technology has become a research focus and investment hotspot.
  • PONs passive optical networks
  • the PON system is a pure medium network, which avoids the electromagnetic interference and lightning impact of external equipment, reduces the failure rate of lines and external equipment, improves system reliability, and saves maintenance costs, so it is most widely used.
  • the PON system mainly includes an optical line terminal (OLT), an optical wiring (ODN), and an optical network unit (ONU) located at the central office.
  • PON is a point-to-multipoint optical fiber transmission and access technology.
  • the data is from the OLT to the ONU in the downlink direction and broadcast.
  • the data is from the ONU to the OLT in the uplink direction, and the time division multiple access is a burst mode.
  • the OLT test usually adds an optical amplifier.
  • the data rate sent by the OLT is much higher than the detection bandwidth, and the optical signal Power is stable, and traditional optical amplifiers accurately detect optical power and gain.
  • each ONU works in burst mode. Only the data packet is sent, and there is an optical signal on the optical fiber. When there is no data, the ONU is in an idle state and does not transmit any optical signal. Therefore, the optical signal on the optical fiber in the uplink direction is For the burst mode, new requirements are placed on the design of the upstream optical amplifier, especially the power detection and gain calculation.
  • the conventional optical amplifier mainly includes a photoelectric converter, a transconductance circuit, an ADC conversion chip, a single chip microcomputer, and the like for the optical power detection scheme.
  • the photoelectric converter converts the optical signal into a current signal
  • the transconductance circuit converts the current signal into a voltage signal
  • the ADC conversion chip converts the analog voltage signal into a digital signal and transmits it to the single chip microcomputer. Because the speed of the single-chip microcomputer is slow, the single-chip microcomputer can detect the accurate optical power only when the optical power changes slowly. Since the MCU can only be operated in series, the input and output optical power cannot be simultaneously sampled, so for the burst mode, accurate gain cannot be obtained.
  • the detection of burst mode optical power and gain can be realized by both analog and digital aspects, and different detecting devices and methods affect cost and performance.
  • the patent "a receiving end optical power online detecting device and its implementation method” (patent number 201110200643.7), need to add BNC terminals and other acquisition modules on the universal ONU module, the algorithm itself needs to add additional trigger signals;
  • the method and system for realizing burst mode optical power measurement (patent number 200610093150.7) adopts the method of adding a current mirror, and the analog circuit is complicated, which is disadvantageous for the use of the optical amplifier.
  • the implementation methods in the prior art all need to modify the ONU module, and even modify the algorithm, which increases the complexity of the system design and does not meet the development requirements of the current broadband communication system.
  • the present invention fully utilizes the design of current amplifiers, combines the advantages of digital circuits and FPGA devices, and proposes an apparatus and method for burst mode optical power and gain detection for optical amplifiers; the present invention does not require any changes to the ONU modules. It can better adapt to the current use of broadband communication systems, and the algorithm directly uses the sampled analog signals for processing. The hardware does not increase the trigger circuit and reduces the system design. the complexity.
  • the present invention proposes an apparatus and method for optical power and gain detection in burst mode.
  • the invention solves the problem of realizing optical power and gain detection in burst mode in an optical amplifier, mainly in a passive optical network, when the system polls the input and output optical power and gain of the optical amplifier, the optical amplifier can be timely, Accurately report values.
  • the present invention provides a burst mode optical power detecting apparatus, including: a multi-channel optical power detecting circuit, an FPGA device, and a temperature detecting circuit; wherein each optical power detecting circuit adopts the same structure and Implementation manners, and both include independent photoelectric converters, transconductance circuits, analog signal conditioning circuits, filters, and analog-to-digital conversion chips; photoelectric converters in each optical power detection circuit are used to convert optical signals from corresponding optical paths into The current signal, the transconductance circuit is used to convert the current signal outputted by the photoelectric converter into a voltage signal, and the analog signal conditioning circuit is used for correcting the voltage signal outputted by the transconductance circuit, amplifying and translating the voltage signal, and the filter is used for filtering the simulation.
  • the analog to digital conversion chip converts the filtered analog voltage signal into a digital signal, and outputs the signal to the FPGA device; the FPGA device calculates a digital signal input to each optical path The optical power and gain of the corresponding optical path.
  • the temperature detecting circuit includes a temperature sensor for detecting the temperature of the optical amplifier, and converting the detected temperature into a digital signal, which is then transmitted to the FPGA device, and the FPGA device is based on the detected temperature.
  • the value compensates for the obtained optical power and/or gain.
  • the FPGA device further includes a communication interface for setting a power threshold, a timer interval, and a temperature compensation coefficient.
  • the optical amplifier may be a Raman fiber amplifier, an erbium doped fiber amplifier, an erbium doped fiber amplifier, a hybrid fiber amplifier, or a high power fiber amplifier.
  • the analog signal detected by each optical power detecting circuit is converted into a digital signal by the analog-to-digital conversion chip and sent to the FPGA device, and the FPGA device calculates the actual optical power according to the scaling coefficient in the pre-existing parameter table.
  • the FPGA device performs a moving average on the effective optical power, records the effective value, and performs power judgment, only when this detection is performed.
  • the optical power value exceeds the last detected optical power value, the value of the internal memory of the FPGA device is updated, otherwise the optical power value detected this time is discarded, thereby ensuring storage in the internal memory of the FPGA device.
  • the maximum value of optical power in burst mode is a moving average on the effective optical power, records the effective value, and performs power judgment, only when this detection is performed.
  • the FPGA device is internally provided with a timer, and when the value of the internal memory of the FPGA device is updated, the timer starts counting, when the timing time exceeds the set value, or the FPGA device communicates
  • the interface receives the update command and the value of the memory inside the FPGA device is re-updated.
  • the FPGA device further includes a temperature compensation parameter table for compensating the optical power calculation using the temperature data input by the temperature detecting circuit.
  • the invention also provides a method for performing optical power detection of an optical amplifier, comprising the steps of:
  • Step 401 initializing the optical power detection module, in the initial state, the FPGA device configures the analog-to-digital conversion chip in each optical power detection circuit, after the configuration is completed, proceeds to step 402;
  • Step 402 start ADC sampling, the analog-to-digital conversion chip performs continuous sampling, and outputs the converted optical power data to the FPGA device, and proceeds to step 403;
  • Step 403 the FPGA device reads the sampling data input by the analog-to-digital conversion chip, calculates the currently detected optical power, and proceeds to step 404;
  • Step 404 determining whether to perform the data update operation by determining whether the update data command is received, if the update data command is received, proceeding to step 405, otherwise proceeding to step 406;
  • Step 405 using the current optical power value to update the data, returning to step 404;
  • Step 406 comparing the optical power value calculated by the FPGA device with a preset threshold. When the optical power value is lower than the set threshold, it indicates that the sample is detected as a no-light signal state, the data is invalid, and the process proceeds to step 407; when the power value exceeds the set threshold, it indicates that the sample is detected by the current sample. Light signal state, proceeds to step 408;
  • Step 407 start the internal timer to time, and then proceeds to step 409;
  • Step 408 Comparing the currently detected optical power value with the last detected optical power value. If the optical power value is less than the last detected optical power value, the current optical power value is considered invalid, and the process proceeds to step 407, otherwise the current optical power is considered. The value is valid, proceed to step 410;
  • Step 409 it is determined whether the internal timer counts the set time delay, if the preset delay is reached, then proceeds to step 411, otherwise proceeds to step 404;
  • Step 410 performing a sliding average with the optical power values obtained from the previous N times to obtain a current optical power value to reduce the influence of noise interference, and then proceeding to step 411;
  • step 411 the internal timer is reset, and the process proceeds to step 405.
  • the FPGA device stores a temperature compensation coefficient table in the form of a lookup table, and obtains a compensation coefficient according to the temperature data input by the temperature detecting circuit, and multiplies the current detected optical power value to obtain the current Actual optical power value at temperature.
  • the invention also provides a method for performing optical amplifier gain detection, comprising the steps of:
  • the FPGA device completes the initialization of the variable and the storage space, and then enters the synchronous control state to ensure that the clock and control signals of the ADC analog-to-digital conversion chip in each detection circuit are identical, so that the ADC analog-to-digital conversion chip and the output channel of the input channel are
  • the ADC analog-to-digital conversion chip operates in a simultaneous sampling state
  • the FPGA device calculates the input optical power of the input channel and the input optical power of the output channel, respectively, and then determines the validity of the detected input optical power and output optical power;
  • the detected input optical power or output optical power is less than the threshold, it indicates that the detection is an invalid value, and the timer is started; if the timer exceeds the timing time, the gain data is updated, and the current gain value is indicated as invalid data, and the timer is cleared. Zero, the next gain detection process;
  • the detected input optical power or output optical power is greater than the threshold, it indicates that the effective value is detected, and the judgment is performed.
  • the gain data is updated immediately; otherwise, the gain of the optical amplifier is calculated by inputting the optical power and the output optical power, the gain data is stored, and the moving average is performed to scan the averaged data. Update the gain data in the internal memory, clear the timer, and perform the next gain detection process.
  • the invention also includes a communication interface and a parameter table for dynamically controlling the length of the timer, the threshold size, and the temperature compensation coefficient. By adjusting various parameters, the accuracy and time requirements of the detection are met.
  • the invention also includes simply copying the control module within the FPGA device to enable simultaneous operation of multiple optical signals and gain circuits, with significantly reduced external components.
  • the algorithm can accurately and stably detect the optical power, and the application range is wider.
  • the internal storage data is always the latest and effective data, reflecting the optical signal on the fiber in real time and accurately.
  • the amplifier gain is calculated more accurately by tightly controlling the synchronism of the ADC samples and the calculated delay.
  • the temperature detection circuit and the compensation coefficient are added to improve the detection accuracy of the system. Take full advantage of the features of FPGA devices and perform multi-channel control without compromising performance.
  • Figure 1 is a schematic diagram of a PON system
  • Figure 2 is a burst mode sampling diagram
  • FIG. 3 is a schematic structural diagram of an apparatus for detecting optical power and gain in a burst mode of an optical amplifier according to the present invention
  • Figure 5 is a schematic diagram of gain control and calculation
  • Figure 6 is a schematic diagram of temperature compensation.
  • first optical power detecting circuit 101 Marked in the figure: first optical power detecting circuit 101, photoelectric converter 102, transconductance circuit 103, analog signal conditioning circuit 104, filter 105, high-speed high-precision ADC analog-to-digital conversion chip 106, FPGA device 107, temperature detecting circuit 108.
  • a typical PON system is simplified as shown in FIG. 1 , and mainly includes: an OLT unit 201, an optical amplifier 202, a plurality of ONU units 203, and an optical fiber connection line 204; in order to increase the transmission distance and improve the signal-to-noise ratio, the OLT unit 201 and the ONU
  • An optical amplifier 202 is provided between the plurality of ONU units 203.
  • the uplink port and the downlink port of the OLT unit 201 are four ports. Therefore, for the corresponding optical amplifier 202, it is also necessary to simultaneously support detection and amplification of four uplink signals and downlink signals (that is, it is necessary to support detection and amplification of eight signals).
  • Each of the OLT units 201 (four channels shown in the figure, but also other numbers) is connected to the input end of the corresponding optical path of the optical amplifier 202 through the optical fiber, and the optical amplifier 202 is downwardly amplified by the corresponding optical path.
  • the output end is connected to the input end of the plurality of ONU units 203 through the optical fiber, and the output end of the plurality of ONU units 203 is connected to the input end of the corresponding optical path of the optical amplifier 202 through the optical fiber, and the output end of the optical amplifier 202 corresponding to the optical path is amplified.
  • the optical fiber is connected to the corresponding optical path uplink input end of the OLT unit 201.
  • the detection and sampling of the optical signal power of the optical amplifier 202 is as shown in FIG. 2: for the downlink direction 301, since the optical signal on the optical fiber is always present, the optical signal power changes relatively slowly, and for the uplink direction 302, when there is no data transmission, There is no optical signal on the optical fiber, and it is in an idle state. When there is data service, an optical signal suddenly appears on the optical fiber. In order to convert the optical signal in the direction of the corresponding optical path into a voltage signal, the ADC chip on the optical amplifier 202 continuously performs ADC sampling 303.
  • the ADC chip can always sample the effective optical power, and the PON system (the OLT unit 201 in the PON system) can always read the corresponding (suitable) optical power through the communication interface.
  • the PON system the OLT unit 201 in the PON system
  • the optical power of the idle state that is, the reactive power. Since the optical power detected on the upstream optical path is invalid, the calculation of the internal gain of the corresponding upstream optical path by the optical amplifier 202 may also be invalid.
  • the temperature of the optical amplifier 202 itself changes during operation, and temperature compensation must also be considered in order to improve accuracy.
  • the problem to be solved by the present invention is to realize the problem of optical power and gain detection in burst mode in an optical amplifier, especially in a passive optical network, when the PON system polls the input and output optical power and gain of the optical amplifier, Optical amplifiers can report values in a timely and accurate manner.
  • the present invention provides an apparatus for optical power and gain detection in a burst mode of an optical amplifier, as shown in FIG. 3, including: multiple optical power detecting circuits 101-109 and an FPGA device 107.
  • the temperature detecting circuit 108 wherein the first optical power detecting circuit 101 to the Nth optical power detecting circuit 109 adopt the same structure and implementation, and each includes a separate optical-to-electrical converter 102, a transconductance circuit 103, and an analog signal.
  • the photoelectric converter 102 in each optical power detecting circuit is configured to convert the optical signal of the corresponding optical path into a current signal, which can be implemented by using a photodiode; the transconductance circuit 103 is configured to convert the current signal output by the photoelectric converter 102 Is a voltage signal; the analog signal conditioning circuit 104 is used to correct the transconductance circuit The output voltage signal of 103, amplifies and translates the voltage signal, and adjusts the amplitude thereof to a suitable range of the high-speed high-precision ADC analog-to-digital conversion chip 106; the filter 105 is used to filter out the high output signal of the analog signal conditioning circuit 104. Frequency interference signal to improve signal to noise ratio.
  • the high speed high precision ADC analog to digital conversion chip 106 converts the analog signal output by the analog signal conditioning circuit 104 into a digital signal and outputs it to the FPGA device 107.
  • the FPGA device 107 calculates the optical power and gain of the corresponding optical path through digital signals input by respective optical paths (in a table lookup or exponential, logarithmic operation, etc.).
  • the temperature detecting circuit 108 includes a temperature sensor disposed on the optical amplifier for detecting the temperature of the optical amplifier, and converting the detected temperature into a digital signal for transmission to the FPGA device 107, and the FPGA device 107 according to the detected temperature value. Compensate for the detected optical power/gain of the optical amplifier.
  • the FPGA device 107 also includes a communication interface for connecting the FPGA device 107 and the (PON) system to set a power threshold, a timer interval, a temperature compensation factor, or other parameters and commands for the (PON) system.
  • the optical amplifiers targeted may be Raman fiber amplifiers, erbium doped fiber amplifiers, erbium doped fiber amplifiers, hybrid fiber amplifiers, high power fiber amplifiers, and the like.
  • the optical power and gain detecting device performs optical power and gain detection on optical paths in each direction of the PON system, and the analog signal obtained by sampling detection in each optical power detecting circuit passes through the ADC analog-to-digital conversion chip 106.
  • the digital signal is sent to the FPGA device 107, and the FPGA device 107 calculates the actual optical power based on the scaling factor pre-existing in the parameter table. And through the exponential and logarithmic operations, the power in milliwatts (mW) and decibel milliwatts (dBm) are obtained simultaneously for subsequent control needs.
  • mW milliwatts
  • dBm decibel milliwatts
  • the FPGA device 107 performs a moving average on the effective optical power, records the current effective value, and performs power judgment. Only when the detected value exceeds the last detected value, the value of the internal memory is updated. Otherwise, the current detected value is discarded, that is, the internal memory stores the maximum value of the burst packet.
  • the FPGA device 107 is internally designed with a timer, and when the value of the internal memory is updated, the timer starts counting. When the time is over After the set value is received, or an update command is received through the communication interface, the value of the internal memory is re-updated, and the latest detected optical power is stored.
  • the FPGA device 107 also includes a temperature compensation parameter table to improve optical power detection accuracy.
  • Step 401 initializing an optical power detection module. After the power-on or reset is completed, the optical power detection module is in an initial state. In the initial state, the FPGA device 107 configures the ADC analog-to-digital conversion chip 106. After the configuration is completed, the process proceeds to step 402.
  • Step 402 the ADC samples.
  • the ADC analog-to-digital conversion chip 106 performs continuous sampling, that is, enters the ADC sampling state.
  • step 403 the optical power is calculated by the ADC sampling result.
  • the FPGA device 107 reads the sampled data of the ADC analog-to-digital conversion chip 106, performs an algorithm or look-up table to calculate the optical power.
  • Step 404 performing a data update operation by determining whether an update data command is received, and proceeding to step 405 when receiving the update data command, otherwise proceeding to step 406.
  • step 405 If the optical power detection module receives the update data command at this time, the process proceeds to step 405; if the optical power detection module does not receive the data update command, the process proceeds to step 406.
  • Step 405 updating the data using the current optical power value, and returning to step 404.
  • the optical power data calculated by the FPGA device 107 is used to update the data output by the corresponding optical power detecting circuit, and then returns to step 404 to wait for the next data update process to begin.
  • step 406 it is judged whether the optical signal is detected. When the optical signal is not detected, the process proceeds to step 407, otherwise, the process proceeds to step 408.
  • the optical power value calculated by the FPGA device 107 is compared with a preset threshold value. When the optical power value is lower than the set threshold, it indicates that the sampled signal is in the state of no light signal, and the data is invalid. 407; when the power value exceeds a set threshold, indicating that the sample is detected to have light Signal state proceeds to step 408.
  • step 407 the internal timer is started for timing, and then proceeds to step 409.
  • step 408 it is determined whether the optical power value is valid. When the optical power value is invalid, the process proceeds to step 407, otherwise, the process proceeds to step 410.
  • step 409 it is determined whether the timer count reaches the set delay. If the preset delay is reached, the process proceeds to step 411, otherwise, the process proceeds to step 404.
  • the time counted after the internal timer is started is accumulated, and it is determined whether the accumulated time count exceeds the set time. When the timer count exceeds the set time, the process proceeds to step 411. If the timer does not overflow, the process proceeds to step 404.
  • Step 410 Perform a sliding average with the optical power values obtained from the previous N detections to obtain a current optical power value to reduce the influence of noise interference, and then proceed to step 411.
  • N is 16-128, which can be dynamically adjusted according to the real-time requirements of the detection device.
  • step 411 the internal timer is reset, and the process proceeds to step 405.
  • the internal timer is cleared, and the data output by the corresponding optical power detection circuit is updated using the currently detected optical power value, and the next process is performed.
  • the delay is set by setting the timer to judge whether it is in a short time without signal state.
  • the timer overflows, it indicates that there is no light on the fiber for a long time, and the previous effective value is no longer maintained (effective after the sliding average) Value), and the output data is updated with the current optical power value read at this time.
  • the actual state of the optical signal on the optical fiber can be reflected in real time; by dynamically adjusting the threshold size, the invalid power range is determined to meet different system requirements; by the above method, the latest valid value detected is stored, and a large number of invalid values are filtered, and the optical fiber is filtered.
  • the size of the business data optical signal is accurately reflected.
  • the invention also proposes a method for gain detection of an optical amplifier, comprising: the FPGA device 107 simultaneously outputs a clock and a control signal on the hardware through synchronous control logic, so that the ADC analog-to-digital conversion chip 106 of each optical power detecting circuit Simultaneous acquisition, internal data is strictly synchronized, and input and output optical power is obtained at the same time. By determining the effectiveness of the optical power, an accurate gain is obtained.
  • a method of detecting gain by the FPGA device 107 is further illustrated in conjunction with the flow chart depicted in FIG.
  • the gain detection module in the FPGA device 107 is in an initial state 501, completes the initialization of the variables and storage space, and then enters the synchronous control state 502 to ensure that the ADC analog-to-digital conversion chip 106 in each detection circuit
  • the clock and control signals are identical, so that the ADC analog-to-digital conversion chip of the input channel and the ADC analog-to-digital conversion chip of the output channel operate in the simultaneous sampling states 503 and 504, respectively calculating the input optical power 505 of the input channel and the input of the output channel.
  • Optical power 506 the internal algorithm of FPGA device 107 ensures synchronization of the input optical power of the input channel and the input optical power of the output channel. Then, the validity of the detected input optical power (ie, the optical power input from the input channel) and the output optical power (ie, the optical power input from the output channel) are determined 507, that is, whether the detected input and output optical power exceeds the preset
  • the threshold is set to start the timer 508 when the detected input optical power or output optical power is less than the threshold, indicating that the detection is an invalid value. If the timing time 509 is exceeded, the gain data 510 is updated while the current gain value is indicated as invalid data, and the timer is cleared 515 for the next gain detection process.
  • the update command 511 When the valid value is detected, it is judged whether the update command 511 is received, and if the update command is received, the gain data 510 is immediately updated, otherwise the gain 512 of the optical amplifier is calculated by the input optical power and the output optical power, and the gain data 513 is stored and performed.
  • the moving average 514 is used to update the gain data 510 with the data after the moving average, and the timer is cleared 515 to perform the next gain data calculation flow.
  • the temperature compensation method is further explained in conjunction with the flowchart depicted in FIG.
  • the system configures a temperature compensation coefficient table 602 through the communication interface 601, and the temperature compensation coefficient table 602 is stored in the form of a lookup table inside the FPGA device 107.
  • the temperature detecting circuit obtains the ambient temperature 603 at the optical amplifier through the temperature sensor 108, and transmits the ambient temperature data at the optical amplifier to the FPGA device 107.
  • the FPGA device 107 obtains the compensation coefficient 604 according to the ambient temperature data value, and multiplies the currently detected power 605 to obtain the actual power 606 at the current temperature, thereby improving the accuracy of the system detection.
  • the present invention realizes simultaneous operation of multiple optical signals and gain circuits by simply copying the control module inside the FPGA device 107, and the external devices used can be significantly reduced.

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Abstract

本发明提供一种用于光放大器的突发模式下光功率和增益探测的装置和方法，包括：多路光功率探测电路、FPGA器件、温度探测电路；每路光功率探测电路采用相同的结构和实现方式，且均包括各自独立的光电转换器、跨导电路、模拟信号调理电路、滤波器和模数转换芯片；通过对常规光放大器中模拟电路、数字检测和控制进行改进，利用FPGA器件的特性，通过算法，实现了对突发模式下光信号和增益的探测。避免增加复杂的模拟电路，同时也避免模拟控制方案中元器件不一致性带来的影响，无论光信号是稳定模式还是突发模式，算法都可以准确、稳定的探测光功率，适用范围广泛；通过严格控制ADC采样的同步性、计算的延时，更准确地计算放大器增益。

Description

一种光放大器突发模式下的光功率和增益探测装置和方法 技术领域
本发明涉及光通信技术，尤其涉及对光放大器的改进，具体涉及一种用于光放大器的突发模式下光功率和增益探测的装置和方法。本发明用于解决通信领域中光放大器对光功率和增益的探测问题，主要用于在宽带光纤无源光网络接入领域实现对突发模式下光功率和增益准确地探测
背景技术
接入网是用户进入城域网/骨干网的桥梁，是信息传送通道的“最后一公里”。随着互联网和高带宽的消耗业务逐步涌现，带宽提速成为迫切需求。为了满足用户的需求，各种新技术不断涌现，接入网技术己成为研究焦点和投资的热点。
在各种宽带接入技术中，无源光网络(PON)以其容量大、传输距离长、较低成本、全业务支持等优势成为热门技术。PON系统中是一种纯介质网络，避免了外部设备的电磁干扰和雷电影响，减少线路和外部设备的故障率，提高了系统可靠性，同时节省了维护成本，因此得到最广泛应用。
PON系统主要包括位于局端的光线路终端(OLT)、光配线(ODN)、光网络单元(ONU)。PON是一种点对多点的光纤传输和接入技术，数据从OLT到ONU为下行方向，采用广播方式。数据从ONU到OLT为上行方向，采用时分多址即突发方式。
为了延伸OLT到ONU的光纤通信传输距离，提高信噪比，OLT测通常增加一光放大器。对于下行方向，OLT发送的数据速率远高于探测带宽，光信号 功率稳定，传统的光放大器均能准确探测光功率和增益。但对于上行方向，每个ONU工作于突发模式，只有发送数据包，光纤上才有光信号，没有数据时，ONU处于空闲状态，不发送任何光信号，因此，上行方向光纤上的光信号为突发模式，对上行方向光放大器的设计，特别是功率探测和增益计算提出新的要求。
具体来说，传统的光放大器对于光功率探测方案主要包括光电转换器、跨导电路、ADC转换芯片、单片机等。光电转换器将光信号转为电流信号，跨导电路将电流信号转为电压信号，ADC转换芯片将模拟电压信号转为数字信号并传送到单片机。由于单片机速度较慢，只有当光功率缓变变化时，单片机才能探测准确的光功率。由于单片机只能串行操作，对输入和输出光功率不能同时采样，因此对于突发模式，不能得到准确的增益。
现有技术中，突发模式光功率和增益的探测可以通过模拟和数字两个方面实现，不同的探测装置和方法影响成本和性能。例如专利《一种接收端光功率在线检测装置及其实现方法》(专利号201110200643.7)，需在通用ONU模块上增加BNC端子及其他采集模块，算法本身还需增加额外的触发信号；专利《用于实现突发模式光功率测量的方法和系统》(专利号200610093150.7)采用增加电流镜的方式，模拟电路复杂，不利于在光放大器的使用。现有技术中的实现方式均需要对ONU模块进行改动，甚至对算法进行修改，增加了系统设计的复杂度，不适应目前宽带通信系统的发展需求。
本发明充分利用目前放大器的设计，结合数字电路和FPGA器件的优点，提出一种用于光放大器的突发模式光功率和增益探测的装置和方法；本发明不需要对ONU模块做任何更改，更能适应目前宽带通信系统的使用，同时算法直接利用采样的模拟信号进行处理，硬件上不再增加触发电路，减少系统设计的 复杂度。
发明内容
为了克服现有光放大器中光功率和增益探测的一些缺陷，本发明提出了一种用于突发模式下光功率和增益探测的装置和方法。
本发明解决的是光放大器中实现突发模式下光功率和增益探测的问题，主要是在无源光网络中，系统轮询光放大器的输入、输出光功率和增益时，光放大器能及时、准确地上报数值。
为了实现上述目的，本发明提出了一种用于突发模式光功率探测装置，包括：多路光功率探测电路、FPGA器件、温度探测电路；其中，每路光功率探测电路采用相同的结构和实现方式，且均包括各自独立的光电转换器、跨导电路、模拟信号调理电路、滤波器和模数转换芯片；每路光功率探测电路中的光电转换器用于将由相应光路的光信号转为电流信号，跨导电路用于将光电转换器输出的电流信号转为电压信号，模拟信号调理电路用于校正跨导电路输出的电压信号，对电压信号进行放大和平移，滤波器用于滤除模拟信号调理电路输出的电压信号中的高频干扰信号，模数转换芯片将滤波后的模拟电压信号转为数字信号，并输出到所述FPGA器件；所述FPGA器件对各个光路输入的数字信号计算相应光路的光功率和增益。
在上述技术方案中，所述温度探测电路包括温度传感器，用于探测光放大器的温度，并将探测到的温度转换为数字信号后传送给所述FPGA器件，所述FPGA器件根据探测到的温度值对所获得光功率和/或增益进行补偿。
在上述技术方案中，所述FPGA器件还包括通信接口，用以设定功率阈值、定时器时间间隔、温度补偿系数。
在上述技术方案中，所述光放大器可为拉曼光纤放大器、掺铒光纤放大器、掺镱光纤放大器、混合光纤放大器、高功率光纤放大器。
在上述技术方案中，每路光功率探测电路探测得到的模拟信号经过模数转换芯片转为数字信号发送到FPGA器件，所述FPGA器件根据预存在参数表中的定标系数，计算实际光功率；当实际光功率超过设定的阈值，触发所述FPGA器件内部的探测状态机，所述FPGA器件对有效光功率进行滑动平均，记录其有效值，同时进行功率判断，只有当本次探测到的光功率值超过上次探测到的光功率值时，所述FPGA器件内部的存储器的数值才进行更新，否则放弃本次探测到的光功率值，从而保证所述FPGA器件内部的存储器中保存的是突发模式下光功率的最大值。
在上述技术方案中，所述FPGA器件内部设有定时器，当所述FPGA器件内部的存储器的数值进行更新后，定时器开始计时，当计时时间超过设定值，或者所述FPGA器件通过通信接口接收到更新命令，所述FPGA器件内部的存储器的数值重新更新。
在上述技术方案中，所述FPGA器件中还包含有温度补偿参数表，用于使用由所述温度探测电路输入的温度数据来对光功率计算进行补偿。
本发明还提供一种进行光放大器光功率探测的方法，包括步骤：
步骤401，初始化光功率探测模块，在初始状态下FPGA器件对每路光功率探测电路中的模数转化芯片进行配置，配置完成后，进入步骤402；
步骤402，启动ADC采样，模数转换芯片进行不断采样，将转换得到的光功率数据输出到FPGA器件，进入步骤403；
步骤403，FPGA器件读取由模数转化芯片输入的采样数据，计算当前探测到的光功率，进入步骤404；
步骤404，通过判断是否接收到更新数据命令来确定是否执行数据更新操作，如果接收到更新数据命令时进入步骤405，否则进入步骤406；
步骤405，使用当前光功率值更新数据，返回步骤404；
步骤406，将FPGA器件计算得到的光功率值与预先设定的阈值进行比较， 当该光功率值低于设定阈值时，表明本次采样探测到的为无光信号状态，数据无效，进入步骤407；当该功率值超过设定阈值时表明本次采样探测到的为有光信号状态，进入步骤408；
步骤407，启动内部定时器进行计时，然后进入步骤409；
步骤408，将当前探测到的光功率值与上次探测到光功率值进行比较，如果小于上次探测到的光功率值，则认为当前光功率值无效，进入步骤407，否则认为当前光功率值有效，进入步骤410；
步骤409，判断内部定时器计时是否到达设定的时延，如果到达预先设定的时延，则进入步骤411，否则进入步骤404；
步骤410，与前N次探测得到的光功率值进行滑动平均获得当前光功率值，以降低噪声干扰的影响，然后进入步骤411；
步骤411，复位内部定时器，进入步骤405。
在上述技术方案中，FPGA器件以查找表形式存储有温度补偿系数表，根据温度探测电路输入的温度数据，查表求得补偿系数，并与当前探测得到的光功率值相乘，求得当前温度下的实际光功率值。
本发明还提供一种进行光放大器增益探测的方法，包括步骤：
FPGA器件完成变量和存储空间的初始化，然后进入同步控制状态，保证每路探测电路中的ADC模数转换芯片的时钟、控制信号完全相同，以使输入通道的ADC模数转换芯片、输出通道的ADC模数转换芯片工作于同时采样状态；
所述FPGA器件分别计算输入通道的输入光功率和输出通道的输入光功率，然后判断探测到的输入光功率和输出光功率的有效性；
当探测到的输入光功率或输出光功率小于阈值时，表示探测为无效值，启动定时器；如果定时器超过定时时间，则更新增益数据，同时标明当前增益值为无效数据，对定时器清零，进行下一次增益探测流程；
当探测到的输入光功率或输出光功率大于阈值时，表示探测到有效值，判 断是否接收到更新命令，如果收到更新命令，则立即更新增益数据，否则通过输入光功率和输出光功率计算光放大器的增益，存储该增益数据，并进行滑动平均，以滑动平均后的数据更新内部存储器中的增益数据，对定时器清零，进行下一次增益探测流程。
本发明还包括通信接口和参数表，用于动态的控制定时器的长度、阈值大小、温度补偿系数。通过调整各种参量，满足探测的精度和时间要求。
本发明还包括简单地在FPGA器件内部复制控制模块，实现多路光信号和增益电路同时工作，所用外部器件显著减少。
本发明取得了以下技术效果：
首先避免增加复杂的模拟电路，同时也避免模拟控制方案中元器件不一致性带来的影响。基于数字控制方案的装置，只需简单的校准就可达到一致性的要求。
其次无论光信号是稳定模式还是突发模式，算法都可以准确、稳定的探测光功率，适用范围更加广泛。内部的存储数据总是最新、有效的数据，实时、准确的反映光纤上光信号。通过严格控制ADC采样的同步性、计算的延时，更准确地计算放大器增益。
最后增加温度探测电路和补偿系数，提升系统探测精度。充分利用FPGA器件的特性，进行多路控制，而不影响性能。
附图说明
图1为PON系统示意图；
图2为突发模式采样图；
图3为本发明的用于光放大器的突发模式下光功率和增益探测的装置结构原理图；
图4为光功率探测示意图；
图5为增益控制和计算示意图；
图6为温度补偿示意图。
图中标记：第1路光功率探测电路101、光电转换器102、跨导电路103、模拟信号调理电路104、滤波器105、高速高精度ADC模数转换芯片106、FPGA器件107、温度探测电路108、第N路光功率探测电路109、OLT单元201、光放大器202、ONU单元203、光纤连接线204、下行方向301、上行方向302、采样303。
具体实施方式
为了便于本领域普通技术人员理解和实施本发明，下面结合附图及具体实施方式对本发明作进一步的详细描述。
典型的PON系统简化后如图1所示，主要包括：OLT单元201、光放大器202、多个ONU单元203、以及光纤连接线204；为了增加传输距离，提高信噪比，OLT单元201和ONU(即多个ONU单元203)之间设置有光放大器202。OLT单元201的上行端口和下行端口为4路端口，因此，对于相应的光放大器202也必须同时支持四路上行信号和下行信号的探测与放大(即需要支持8路信号的探测和放大)。其中，OLT单元201的每路(图中示出的为4路，也可为其他数量)下行输出端通过光纤连接到光放大器202相应光路下行放大的输入端，光放大器202相应光路下行放大的输出端通过光纤与多个ONU单元203的输入端相连，多个ONU单元203的输出端通过光纤与光放大器202相应光路上行放大的输入端相连，光放大器202相应光路上行放大的输出端通过光纤与OLT单元201相应光路上行输入端相连。
光放大器202的光信号功率的探测和采样如图2所示：对于下行方向301，由于光纤上的光信号一直存在，光信号功率变化相对缓慢，而对于上行方向302，当无数据传输时，光纤上没有光信号，处于空闲状态，当有数据业务时，光纤上突发出现光信号。为了将相应光路方向上的光信号转为电压信号，光放大器202上的ADC芯片不断的进行ADC采样303。对于下行方向301，ADC芯片总是能够采样到有效的光功率，PON系统(中的OLT单元201)通过通信接口总能读取到相应(合适)的光功率。而对于上行方向302上光信号的突发模式，如果PON系统没有与光放大器202上的ADC采样同步，有可能读取的一直是空闲状态的光功率，即无效功率。由于在上行光路上探测到的光功率的无效，则光放大器202对相应上行光路的内部增益的计算也可能无效。另外光放大器202在工作时本身的温度会发生变化，为了提高准确性，还必须考虑温度补偿。
即本发明所要解决的是在光放大器中实现突发模式下光功率和增益探测的问题，特别是在无源光网络中，在PON系统轮询光放大器的输入、输出光功率和增益时，光放大器能及时、准确地上报数值。
为了解决上述技术问题，本发明提供的一种用于光放大器的突发模式下光功率和增益探测的装置，如图3所示，包括：多路光功率探测电路101-109和FPGA器件107、温度探测电路108；其中，第1路光功率探测电路101至第N路光功率探测电路109采用相同的结构和实现方式，均包括各自独立的光电转换器102、跨导电路103、模拟信号调理电路104、滤波器105、高速高精度ADC模数转换芯片106。
其中，每路光功率探测电路中的光电转换器102用于将由相应光路的光信号转为电流信号，可采用光电二极管来实现；跨导电路103用于将光电转换器102输出的电流信号转为电压信号；模拟信号调理电路104用于校正跨导电路 103输出的电压信号，对电压信号进行放大和平移，将其幅值调整为高速高精度ADC模数转换芯片106适合的范围；滤波器105用于滤除模拟信号调理电路104输出信号中的高频干扰信号，提高信噪比。高速高精度ADC模数转换芯片106将由模拟信号调理电路104输出的模拟信号转为数字信号，并输出到FPGA器件107。FPGA器件107通过各个光路输入的数字信号(以查表或者指数、对数运算等方式)计算相应光路的光功率和增益。温度探测电路108包括温度传感器，温度传感器设置于光放大器上，用于探测光放大器的温度，并将探测到的温度转换为数字信号后传送给FPGA器件107，FPGA器件107根据探测到的温度值对探测到的光放大器光功率/增益进行补偿。FPGA器件107还包括通信接口，用于连接FPGA器件107和(PON)系统，以设定(PON)系统的功率阈值、定时器时间间隔、温度补偿系数或者其他参量和命令。
所针对的光放大器可为拉曼光纤放大器、掺铒光纤放大器、掺镱光纤放大器、混合光纤放大器、高功率光纤放大器等。
使用本发明所提供的光功率和增益探测装置进行PON系统各方向光路上的光功率和增益探测的方法，每路光功率探测电路中通过采样探测得到的模拟信号经过ADC模数转换芯片106，转为数字信号发送到FPGA器件107，FPGA器件107根据预存在参数表中的定标系数，计算实际光功率。并通过指数和对数运算，同时得到以毫瓦(mW)和分贝毫瓦(dBm)为单位的功率，分别用于后续的控制需要。当功率超过一定的阈值，触发FPGA器件107的内部探测状态机。FPGA器件107对有效光功率做滑动平均，记录本次有效值，同时进行功率判断。只有当本次探测值超过上次的探测值，内部存储器的数值进行更新，否则放弃本次探测值，即保证内部存储器保存的是突发包的最大值。FPGA器件107内部设计有定时器，当内部存储器的数值进行更新，定时器开始计时。当计时时间超 过设定值，或者通过通信接口接收到更新命令，内部存储器的数值重新更新，最新的探测到的光功率被存储。FPGA器件107还包含温度补偿参数表，提高光功率探测精度。
如图4所示，具体包括如下步骤。
步骤401，初始化光功率探测模块。在刚上电或者复位结束后，光功率探测模块处于初始状态，在初始状态下FPGA器件107对ADC模数转化芯片106进行配置，配置完成后，进入步骤402。
步骤402，ADC采样。ADC模数转换芯片106进行不断采样，即进入ADC采样状态。
步骤403，通过ADC采样结果计算光功率。FPGA器件107读取ADC模数转化芯片106的采样数据，进行算法或者查表来计算光功率。
步骤404，通过判断是否接收到更新数据命令来执行数据更新操作，接收到更新数据命令时进入步骤405，否则进入步骤406。
如果此时光功率探测模块接收到更新数据命令，进入步骤405；如果此时光功率探测模块没有接收到数据更新命令，进入步骤406。
步骤405，使用当前光功率值更新数据，返回步骤404。
使用FPGA器件107计算得到的光功率数据来更新相应光功率探测电路输出的数据，然后返回步骤404，等待开始下一次数据更新流程。
步骤406，判断是否探测到光信号，当未探测到光信号时进入步骤407，否则进入步骤408。
将FPGA器件107计算得到的光功率值与预先设定的阈值进行比较判断，当该光功率值低于设定阈值时，表明本次采样探测到的为无光信号状态，数据无效，进入步骤407；当该功率值超过设定阈值时表明本次采样探测到的为有光 信号状态，进入步骤408。
步骤407，启动内部定时器进行计时，然后进入步骤409。
步骤408，判断光功率值是否有效，当光功率值无效时进入步骤407，否则进入步骤410。
将当前探测到的光功率值与上次探测到光功率值(有效值)进行比较，如果小于上次探测到的光功率值，则认为当前光功率值无效，进入步骤407，启动内部定时器，否则认为当前光功率值有效，进入步骤410。
步骤409，判断定时器计时是否到达设定的时延，如果到达预先设定的时延，则进入步骤411，否则进入步骤404。
并对内部定时器启动后的计时时间进行累计，判断累计的计时时间是否超过设定时间，当定时器计时超过设定时间，则进入步骤411，如果定时器没有溢出，则进入步骤404。
步骤410，与前N次探测得到的光功率值进行滑动平均获得当前光功率值，以降低噪声干扰的影响，然后进入步骤411。其中N为16-128，可根据对探测装置的实时性要求进行动态调整。
步骤411，复位内部定时器，进入步骤405。
将内部定时器清零，使用当前探测到的光功率值更新相应光功率探测电路输出的数据，进入下一次流程。
具体来说，当光功率探测电路所探测的相应光线路上长时间没有光信号传输，则其探测到的光功率将会一直低于预先设定的阈值。因此先通过设定定时器进行延时以判断是否处于短时无信号状态，当定时器溢出，表明光纤上很长时间没有光了，不再继续保持上一次的有效值(滑动平均后的有效值)，而以此时读取的当前光功率值进行输出数据更新。通过动态地调整定时器计时长度， 光纤上光信号的实际状态可被实时反映；通过动态地调整阈值大小，判断无效功率范围，满足不同系统需求；通过上述方式，探测到的最新有效数值被存储，大量的无效数值被过滤，光纤上业务数据光信号大小被准确反映。
本发明还提出了一种用于光放大器增益探测的方法，包括：FPGA器件107通过同步控制逻辑，在硬件上同时输出时钟和控制信号，使每路光功率探测电路的ADC模数转换芯片106同时采集，内部将数据进行严格的同步对时，同时得到输入输出光功率。通过判断光功率的有效性，得到准确的增益。
结合图5描述的流程图，进一步说明FPGA器件107进行探测增益的方法。刚上电或者复位结束后，FPGA器件107中的增益探测模块处于初始状态501，完成变量和存储空间的初始化，然后进入同步控制状态502，保证每路探测电路中的ADC模数转换芯片106的时钟、控制信号等完全相同，以使输入通道的ADC模数转换芯片、输出通道的ADC模数转换芯片工作于同时采样状态503、504，分别计算输入通道的输入光功率505和输出通道的输入光功率506，FPGA器件107的内部算法保证输入通道的输入光功率和输出通道的输入光功率计算的同步性。然后判断探测到的输入光功率(即从输入通道输入的光功率)和输出光功率(即从输出通道输入的光功率)的有效性507，即探测到的输入和输出光功率是否超过预先设定的阈值，当探测到的输入光功率或输出光功率小于阈值时，表示探测为无效值，启动定时器508。如果超过定时时间509，更新增益数据510，同时标明当前增益值为无效数据，定时器清零515，进行下一次增益探测流程。当探测到有效值，判断是否接收到更新命令511，如果收到更新命令，则立即更新增益数据510，否则通过输入光功率和输出光功率计算光放大器的增益512，存储增益数据513，并进行滑动平均514，以滑动平均后的数据更新增益数据510，定时器清零515，进行下一次增益数据计算流程。
结合图6描述的流程图，进一步说明温度补偿方法。系统通过通信接口601，配置温度补偿系数表602，温度补偿系数表602以查找表形式存储在FPGA器件107的内部。温度探测电路通过温度传感器108获得光放大器处的环境温度603，将光放大器处的环境温度数据传送给FPGA器件107。FPGA器件107根据该环境温度数据值，查表求得补偿系数604，并与当前探测的功率605相乘，求得当前温度下的实际功率606，提高系统探测的准确性。
本发明通过简单地在FPGA器件107内部复制控制模块，实现多路光信号和增益电路同时工作，所用外部器件可以显著减少。
以上实施例仅为本发明的一种实施方式，其描述较为具体和详细，但不能因此而理解为对本发明专利范围的限制。其具体结构和尺寸可根据实际需要进行相应的调整。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。

Claims (10)

  1. 一种用于光放大器突发模式下的光功率和增益探测装置，其特征在于包括：多路光功率探测电路、FPGA器件、温度探测电路；其中，每路光功率探测电路采用相同的结构和实现方式，且均包括各自独立的光电转换器、跨导电路、模拟信号调理电路、滤波器和模数转换芯片；每路光功率探测电路中的光电转换器用于将由相应光路的光信号转为电流信号，跨导电路用于将光电转换器输出的电流信号转为电压信号，模拟信号调理电路用于校正跨导电路输出的电压信号，对电压信号进行放大和平移，滤波器用于滤除模拟信号调理电路输出的电压信号中的高频干扰信号，模数转换芯片将滤波后的模拟电压信号转为数字信号，并输出到所述FPGA器件；所述FPGA器件对各个光路输入的数字信号计算相应光路的光功率和增益。
  2. 根据权利要求1所述的用于光放大器突发模式下的光功率和增益探测装置，其特征在于：所述温度探测电路包括温度传感器，用于探测光放大器的温度，并将探测到的温度转换为数字信号后传送给所述FPGA器件，所述FPGA器件根据探测到的温度值对所获得光功率和/或增益进行补偿。
  3. 根据权利要求1所述的用于光放大器突发模式下的光功率和增益探测装置，其特征在于：所述FPGA器件还包括通信接口，用以设定功率阈值、定时器时间间隔、温度补偿系数。
  4. 根据权利要求1所述的用于光放大器突发模式下的光功率和增益探测装置，其特征在于：所述光放大器可为拉曼光纤放大器、掺铒光纤放大器、掺镱光纤放大器、混合光纤放大器、高功率光纤放大器。
  5. 根据权利要求1-4中任一项所述的用于光放大器突发模式下的光功率和增益探测装置，其特征在于：每路光功率探测电路探测得到的模拟信号经过模数转换芯片转为数字信号发送到FPGA器件，所述FPGA器件根据预存在参数表中的定标系数，计算实际光功率；当实际光功率超过设定的阈值，触发所述FPGA器件内部的探测状态机，所述FPGA器件对有效光功率进行滑动平均， 记录其有效值，同时进行功率判断，只有当本次探测到的光功率值超过上次探测到的光功率值时，所述FPGA器件内部的存储器的数值才进行更新，否则放弃本次探测到的光功率值，从而保证所述FPGA器件内部的存储器中保存的是突发模式下光功率的最大值。
  6. 根据权利要求5所述的用于光放大器突发模式下的光功率和增益探测装置，其特征在于：所述FPGA器件内部设有定时器，当所述FPGA器件内部的存储器的数值进行更新后，定时器开始计时，当计时时间超过设定值，或者所述FPGA器件通过通信接口接收到更新命令，所述FPGA器件内部的存储器的数值重新更新。
  7. 根据权利要求1-6中任一项所述一种用于光放大器突发模式下的光功率和增益探测装置，其特征在于：所述FPGA器件中还包含有温度补偿参数表，用于使用由所述温度探测电路输入的温度数据来对光功率计算进行补偿。
  8. 一种使用如权利要求1-7中任一项所述的用于光放大器突发模式下的光功率和增益探测装置来进行光放大器光功率探测的方法，其特征在于包括步骤：
    步骤401，初始化光功率探测模块，在初始状态下FPGA器件对每路光功率探测电路中的模数转化芯片进行配置，配置完成后，进入步骤402；
    步骤402，启动ADC采样，模数转换芯片进行不断采样，将转换得到的光功率数据输出到FPGA器件，进入步骤403；
    步骤403，FPGA器件读取由模数转化芯片输入的采样数据，计算当前探测到的光功率，进入步骤404；
    步骤404，通过判断是否接收到更新数据命令来确定是否执行数据更新操作，如果接收到更新数据命令时进入步骤405，否则进入步骤406；
    步骤405，使用当前光功率值更新数据，返回步骤404；
    步骤406，将FPGA器件计算得到的光功率值与预先设定的阈值进行比较， 当该光功率值低于设定阈值时，表明本次采样探测到的为无光信号状态，数据无效，进入步骤407；当该功率值超过设定阈值时表明本次采样探测到的为有光信号状态，进入步骤408；
    步骤407，启动内部定时器进行计时，然后进入步骤409；
    步骤408，将当前探测到的光功率值与上次探测到光功率值进行比较，如果小于上次探测到的光功率值，则认为当前光功率值无效，进入步骤407，否则认为当前光功率值有效，进入步骤410；
    步骤409，判断内部定时器计时是否到达设定的时延，如果到达预先设定的时延，则进入步骤411，否则进入步骤404；
    步骤410，与前N次探测得到的光功率值进行滑动平均获得当前光功率值，以降低噪声干扰的影响，然后进入步骤411；
    步骤411，复位内部定时器，进入步骤405。
  9. 根据权利要求8所述的进行光放大器光功率探测的方法，其特征在于：FPGA器件以查找表形式存储有温度补偿系数表，根据温度探测电路输入的温度数据，查表求得补偿系数，并与当前探测得到的光功率值相乘，求得当前温度下的实际光功率值。
  10. 一种使用如权利要求1-7中任一项所述的用于光放大器突发模式下的光功率和增益探测装置来进行光放大器增益探测的方法，其特征在于包括步骤：
    FPGA器件完成变量和存储空间的初始化，然后进入同步控制状态，保证每路探测电路中的ADC模数转换芯片的时钟、控制信号完全相同，以使输入通道的ADC模数转换芯片、输出通道的ADC模数转换芯片工作于同时采样状态；
    所述FPGA器件分别计算输入通道的输入光功率和输出通道的输入光功率，然后判断探测到的输入光功率和输出光功率的有效性；
    当探测到的输入光功率或输出光功率小于阈值时，表示探测为无效值，启动定时器；如果定时器超过定时时间，则更新增益数据，同时标明当前增益值为无效数据，对定时器清零，进行下一次增益探测流程；
    当探测到的输入光功率或输出光功率大于阈值时，表示探测到有效值，判断是否接收到更新命令，如果收到更新命令，则立即更新增益数据，否则通过输入光功率和输出光功率计算光放大器的增益，存储该增益数据，并进行滑动平均，以滑动平均后的数据更新内部存储器中的增益数据，对定时器清零，进行下一次增益探测流程。
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