WO2018072398A1 - 在晶片的表面形成曲面的方法 - Google Patents

在晶片的表面形成曲面的方法 Download PDF

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Publication number
WO2018072398A1
WO2018072398A1 PCT/CN2017/078825 CN2017078825W WO2018072398A1 WO 2018072398 A1 WO2018072398 A1 WO 2018072398A1 CN 2017078825 W CN2017078825 W CN 2017078825W WO 2018072398 A1 WO2018072398 A1 WO 2018072398A1
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wafer
curved surface
forming
mask
mask opening
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PCT/CN2017/078825
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English (en)
French (fr)
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徐元俊
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上海新微技术研发中心有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • the present application relates to the field of semiconductor manufacturing technology, and in particular, to a method of forming a curved surface on a surface of a wafer.
  • the surface processing of silicon materials is characterized by planarization, that is, processing in the X and Y directions of the surface of the silicon wafer.
  • planarization that is, processing in the X and Y directions of the surface of the silicon wafer.
  • a deep trench process has been developed in which trenches are formed on the surface of silicon using dry etching or wet etching.
  • the present application provides a method for forming a curved surface on a surface of a wafer, which can perform surface processing by using a correspondence relationship between line width and etching depth in a planar process, thereby forming a curved surface on the surface of the wafer.
  • a surface is formed on a surface of a wafer Method, the method comprising:
  • the oxide converted by the partition is removed.
  • a region of the wafer corresponding to the groove and the spacer is oxidized to form an oxide layer, and the oxide layer is removed.
  • the etching time for the mask openings of different sizes is the same.
  • the mask openings of different sizes correspond to the grooves of different depths.
  • the mask opening having a larger size corresponds to the deeper groove.
  • the partitions at different locations have the same width or different widths.
  • the size of the mask opening is according to a target curved surface, a depth of a corresponding groove at different positions of the target curved surface, and a depth between the groove and the size of the mask opening. Relationship to determine.
  • the surface processing is completed by a planar process
  • the crystal can be
  • the surface of the sheet forms the desired surface.
  • FIG. 1 is a schematic view showing a method of forming a curved surface on a surface of a wafer in an embodiment of the present application
  • FIG. 2 is a schematic flow chart of a process for forming a curved surface on a surface of a wafer in the embodiment of the present application.
  • Embodiment 1 of the present application provides a method of forming a curved surface on a surface of a wafer for forming a curved surface on a surface of the wafer.
  • FIG. 1 is a schematic diagram of a method for forming a curved surface on a surface of a wafer in an embodiment of the present application. As shown in FIG. 1, the method includes:
  • Step 101 forming a mask pattern on a surface of the wafer, the mask pattern having at least two adjacent mask openings, a surface of the wafer being exposed from the mask opening;
  • Step 102 etching a surface of the wafer exposed from the mask opening, so that the wafer forms a groove corresponding to the mask opening, and the wafer is formed between the adjacent grooves a partition formed by the material;
  • Step 103 oxidizing the wafer to completely convert the isolation portion into an oxide
  • Step 104 removing the oxide converted by the partition.
  • the surface processing can be completed by using the correspondence between the line width and the etching depth in the planar process, thereby forming a curved surface on the surface of the wafer based on the existing planar processing.
  • the substrate may be a substrate commonly used in the field of semiconductor fabrication, such as silicon wafers, silicon-on-insulator (SOI) wafers, silicon germanium wafers, or gallium nitride. (Gallium Nitride, GaN) wafers, etc.; and, the wafer It may be a wafer that has not been subjected to a semiconductor process, or a wafer that has been processed, such as a wafer that has been subjected to ion implantation, etching, and/or diffusion processes, which is not limited in this embodiment. .
  • the etching rate of the semiconductor planar processing process there is a loading effect, that is, when the etched material is exposed in the etching reaction plasma plasma or solution, the etching rate is larger than the bare area when the exposed area is larger.
  • the smaller one is slower.
  • the reason for the load effect is that the reactive material is consumed to a greater extent in a region with a large exposed area, resulting in a lower concentration of the reactant, and the etching rate is proportional to the concentration of the reactant, so the exposed area is relatively small.
  • the etch rate of the larger one is smaller.
  • the loading effect shows the opposite situation, that is, the etching rate is larger than that of the bare area, and the reason is that when the size of the bare area is
  • the smaller the exposed area the easier the reaction product in the etching process will hinder the etching process and reduce the etching speed.
  • the larger the exposed area the easier the reaction product in the etching process is. Discharge, thereby reducing the obstruction of the etching process, so that the etching process is maintained at a higher speed.
  • a mask pattern may be formed on the surface of the wafer, the mask pattern having at least two adjacent mask openings, the surface of the wafer being exposed from the mask opening.
  • the size of the mask opening determines the size of the wafer exposed to the etched material. Therefore, the correspondence between the size of the mask opening and the etch depth can be determined experimentally in advance.
  • the target curved surface formed on the surface of the wafer can be formed according to the need. Determining the depth of the corresponding mask opening at different positions of the target curved surface by determining the depth distance from the original plane of the wafer (ie, the depth of the groove) and the relationship between the etching depth of the groove and the size of the mask opening . In this embodiment, depending on the shape of the target curved surface, the size of the mask openings at different positions may be the same or different.
  • the mask pattern on the surface of the substrate may be a photoresist, but the embodiment is not limited thereto, and the mask pattern may also be a material such as nitride and/or oxide.
  • the shape of the mask opening may be a square, a rectangle, and/or a ring shape.
  • the wafer may be dry etched or wet etched to form a trench corresponding to the mask opening on the surface of the wafer, and an isolation formed by the material of the wafer is formed between adjacent trenches. unit.
  • the etching time of the mask openings of different sizes is the same, whereby the depth of the grooves formed in the mask openings of different sizes is also different, for example, the size of the opening of the mask is 100.
  • the larger the size of the mask opening corresponds to the deeper groove, whereby the bottom of a series of grooves having different depths forms a pattern similar to the target surface.
  • the isolation portions at different positions may have the same width; in the case where the separation distances between different mask openings are not equal, different positions
  • the partitions can have different widths.
  • step 103 the mask pattern on the surface of the wafer may be removed and the wafer may be oxidized, and the time of the oxidation treatment may be controlled such that the spacer is completely converted into an oxide.
  • other portions of the wafer from which the mask pattern is removed are also oxidized, for example, the upper surface of the wafer and the bottom of the groove.
  • the oxide converted by the isolation portion may be removed such that the bottoms of the adjacent grooves are no longer separated, but are connected to each other, whereby the bottoms of the respective grooves are connected to each other.
  • the oxide layer at the bottom of each of the grooves can also be removed simultaneously.
  • the method may further include the following step 105 after step 104:
  • Step 105 oxidize a region of the wafer corresponding to the trench and the isolation portion to form an oxide layer and remove the oxide layer.
  • step 105 the surface of the curved surface formed by the bottoms of the grooves connected to each other is made smoother by the process of oxidizing and removing the oxide layer on the bottoms of the grooves connected to each other.
  • step 105 may be performed once or more until the surface of the curved surface formed by the bottoms of the grooves connected to each other reaches a predetermined smoothness.
  • the surface processing can be completed by using the correspondence between the line width and the etching depth in the planar process, thereby forming a curved surface on the surface of the wafer based on the existing planar processing.
  • FIG. 2 is a schematic flow chart of a process for forming a curved surface according to an embodiment of the present application.
  • a mask pattern 202 is formed on the surface of the silicon wafer 201, and the mask pattern 202 has a mask opening 2021.
  • the size of the mask openings 2021 at different locations may be the same or different depending on the shape requirements of the target curve.
  • the mask pattern 202 can be formed of a photoresist.
  • the silicon wafer in the mask opening 2021 is etched by a deep trench etching process to form trenches 203, and the etching time corresponding to each mask opening 2021 may be the same.
  • adjacent trenches 203 may have different depths or the same depth; and adjacent trenches 203 have spacers 204 therebetween.
  • the ruler The larger the mask opening 202 corresponds to the deeper groove.
  • the photoresist mask pattern 202 is removed.
  • the silicon wafer 201 is oxidized to convert all of the spacers 204 into oxides 204a, and an oxide layer 203a is also formed on the bottom of the trenches 203 and the upper surface of the silicon wafer.
  • the oxide 204a and the oxide layer 203a are removed such that the bottom surfaces of the adjacent grooves 203 are joined to form a curved surface 205.
  • the silicon wafer 201 is again subjected to oxidation treatment to form an oxide layer 205a on the surface of the curved surface 205.
  • the oxide layer 205a is removed to make the curved surface 205 smoother.
  • (F) and (G) of FIG. 2 may be repeated a plurality of times until the curved surface 205 reaches a predetermined smoothness requirement.
  • a smooth curved surface can be formed on the surface of the substrate, and the processing capability for the wafer is improved.

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Abstract

提供一种在晶片（201）的表面形成曲面（205）的方法，该方法包括：在晶片（201）的表面形成掩模图形（202），掩模图形（202）具有至少两个相邻的掩模开口（2021），晶片（201）的表面从掩模开口（2021）露出；对从掩模开口（2021）露出的晶片（201）的表面进行刻蚀，以使晶片（201）形成与掩模开口（2021）对应的槽（203），相邻的槽（203）之间形成有晶片（201）的材料形成的隔离部（204）；对晶片（201）进行氧化，以将隔离部（204）完全转化为氧化物（204a）；去除由隔离部（204）所转化成的氧化物（204a）。该方法能够在晶片（201）表面形成曲面（205）。

Description

在晶片的表面形成曲面的方法 技术领域
本申请涉及半导体制造技术领域，尤其涉及一种在晶片的表面形成曲面的方法。
背景技术
在半导体技术中，硅材料表面加工工艺的特点是平面化加工，即，在硅晶片表面的X方向和Y方向进行加工。近年来，发展出了深槽工艺，即，使用干法刻蚀或湿法刻蚀的方式在硅表面形成沟槽。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
申请内容
在现有的半导体材料表面加工工艺中，只能制造与半导体材料的表面平行或呈特定夹角的平面，即使是深槽工艺，也只是在平面工艺的基础上对与半导体材料的表面垂直的面进行开槽加工以形成平面，而无法加工出光滑曲面。
本申请提供一种在晶片的表面形成曲面的方法，能够利用平面工艺中线宽与刻蚀深度的对应关系来完成曲面加工，从而在晶片的表面形成曲面。
根据本申请实施例的一个方面，提供一种在晶片的表面形成曲面 的方法，所述方法包括：
在晶片的表面形成掩模图形，所述掩模图形具有至少两个相邻的掩模开口，所述晶片的表面从所述掩模开口露出；
对从所述掩模开口露出的所述晶片的表面进行刻蚀，以使所述晶片形成与所述掩模开口对应的槽，相邻的所述槽之间形成有所述晶片的材料形成的隔离部；
对所述晶片进行氧化，以将所述隔离部完全转化为氧化物；以及
去除由所述隔离部所转化成的氧化物。
根据本申请实施例的另一个方面，其中，在去除由所述隔离部所转化成的氧化物之后，至少进行一次如下的步骤：
对所述晶片的与所述槽以及隔离部对应的区域进行氧化，以形成氧化层，并去除所述氧化层。
根据本申请实施例的另一个方面，其中，对不同尺寸的所述掩模开口的刻蚀时间相同。
根据本申请实施例的另一个方面，其中，不同尺寸的所述掩模开口对应不同深度的所述槽。
根据本申请实施例的另一个方面，其中，在所述掩模开口的尺寸为100微米以内的情况下，尺寸越大的所述掩模开口对应越深的所述槽。
根据本申请实施例的另一个方面，其中，不同位置的隔离部具有相同的宽度或不同的宽度。
根据本申请实施例的另一个方面，其中，所述掩模开口的尺寸是根据目标曲面，所述目标曲面不同位置处对应的槽的深度，以及槽的深度和掩模开口的尺寸之间的关系来确定的。
本申请的有益效果在于：利用平面工艺完成曲面加工，能够在晶 片的表面形成所需要的曲面。
参照后文的说明和附图，详细公开了本申请的特定实施方式，指明了本申请的原理可以被采用的方式。应该理解，本申请的实施方式在范围上并不因而受到限制。在所附权利要求的精神和条款的范围内，本申请的实施方式包括许多改变、修改和等同。
针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用，与其它实施方式中的特征相组合，或替代其它实施方式中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、整件、步骤或组件的存在，但并不排除一个或更多个其它特征、整件、步骤或组件的存在或附加。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例中在晶片的表面形成曲面的方法的一个示意图；
图2是本申请实施例中在晶片的表面形成曲面的方法的一个工艺流程示意图。
具体实施方式
参照附图，通过下面的说明书，本申请的前述以及其它特征将变得明显。在说明书和附图中，具体公开了本申请的特定实施方式，其表明了其中可以采用本申请的原则的部分实施方式，应了解的是，本申请不限于所描述的实施方式，相反，本申请包括落入所附权利要求的范围内的全部修改、变型以及等同物。
实施例1
本申请实施例1提供一种在晶片的表面形成曲面的方法，用于在晶片的表面形成曲面。
图1是本申请实施例中在晶片的表面形成曲面的方法的一个示意图，如图1所示，该方法包括：
步骤101、在晶片的表面形成掩模图形，所述掩模图形具有至少两个相邻的掩模开口，所述晶片的表面从所述掩模开口露出；
步骤102、对从所述掩模开口露出的所述晶片的表面进行刻蚀，以使所述晶片形成与所述掩模开口对应的槽，相邻的所述槽之间形成有所述晶片的材料形成的隔离部；
步骤103、对所述晶片进行氧化，以将所述隔离部完全转化为氧化物；以及
步骤104、去除由所述隔离部所转化成的氧化物。
通过本实施例，能够利用平面工艺中线宽与刻蚀深度的对应关系来完成曲面加工，从而基于现有的平面加工工艺，在晶片的表面形成曲面。
在本实施例中，该基片可以是半导体制造领域中常用的基片，例如硅晶圆、绝缘体上的硅(Silicon-On-Insulator，SOI)晶圆、锗硅晶圆、或氮化镓(Gallium Nitride，GaN)晶圆等；并且，该晶圆 可以是没有进行过半导体工艺处理的晶圆，也可以是已经进行过处理的晶圆，例如进行过离子注入、蚀刻和/或扩散等工艺处理过的晶圆，本实施例对此并不限制。
在半导体平面加工工艺的刻蚀工艺中，存在负载效应(loading effect)，即，当被刻蚀材料裸露在刻蚀用反应气体等离子或溶液中时，裸露面积较大者刻蚀速率较裸露面积较小者为慢的情形。负载效应的原因在于，反应物质在裸露面积较大的区域中被消耗掉的程度较为严重，导致反应物质浓度变低，而刻蚀速率却又与反应物质浓度成正比关系，所以，裸露面积较大者的刻蚀速率反而较小。此外，在一定的尺寸以下，例如100微米以下，负载效应表现出相反的情况，即，裸露面积较大者刻蚀速率较裸露面积较小者更快，其原因在于，当裸露面积的尺寸在一定的尺寸以下时，裸露面积越小，那么刻蚀过程中的反应产物越容易对刻蚀过程产生阻碍并使得刻蚀速度降低，而裸露面积越大，刻蚀过程中的反应产物越容易被排出，从而减少对刻蚀过程的阻碍，以使刻蚀过程保持较高速度。
可见，在刻蚀工艺中，在刻蚀时间固定的情况下，半导体材料的裸露面积与刻蚀深度之间具有一定的关系，本实施例正是利用这种关系来形成曲面。
在本实施例的步骤101中，可以在晶片的表面形成掩模图形，所述掩模图形具有至少两个相邻的掩模开口，所述晶片的表面从所述掩模开口露出。
在本实施例中，掩模开口的尺寸决定了晶片裸露于刻蚀材料的尺寸，因此，可以提前通过实验的方式来确定掩模开口的尺寸与刻蚀深度之间的对应关系。
在本实施例中，可以根据需要在晶片表面形成的目标曲面，该目 标曲面不同位置处与晶片原始平面的深度距离(即，槽的深度)，以及槽的刻蚀深度和掩模开口的尺寸之间的关系来确定目标曲面不同位置处对应的掩模开口的尺寸。在本实施例中，决定于目标曲面的形状，不同位置处的掩模开口的尺寸可以相同，也可以不同。
在本实施例中，基片表面的掩模图形可以是光刻胶，但本实施例不限于此，该掩模图形也可以是氮化物和/或氧化物等材料。
在本实施例中，掩模开口的形状可以是正方形、矩形和/或环形等形状。
在本实施例的步骤102中，可以对晶片进行干法刻蚀或湿法腐蚀，以在晶片表面形成与掩模开口对应的槽，相邻的槽之间形成有由晶片的材料形成的隔离部。
在步骤102中，对不同尺寸的掩模开口的刻蚀时间相同，由此，不同尺寸的掩模开口中所形成的槽的深度也不相同，例如，在所述掩模开口的尺寸为100微米以内的情况下，尺寸越大的掩模开口对应越深的槽，由此，一系列深度各异的槽的底部所构成的图形与目标曲面相似。
在步骤102中，在不同掩模开口之间的间隔距离相等的情况下，不同位置的隔离部可以具有相同的宽度；在不同掩模开口之间的间隔距离不等的情况下，不同位置的隔离部可以具有不同的宽度。
在步骤103中，可以去除晶片表面的掩模图形，并对晶片进行氧化处理，氧化处理的时间可以被控制为使得隔离部完全转化为氧化物。在该步骤中，去除了掩模图形后的晶片的其他部位也会被氧化，例如，晶片的上表面以及槽的底部等部位。
在步骤104中，可以去除由隔离部转化成的氧化物，使得相邻的槽的底部不再被隔开，而是彼此连接，由此，各个槽的底部连接以构 成与目标曲面相似的图形。在该步骤中，各个槽的底部的氧化层也可以被同时去除。
在本实施例中，如图1所示，该方法还可以在步骤104之后进一步具备如下的步骤105：
步骤105、对所述晶片的与所述槽以及隔离部对应的区域进行氧化，以形成氧化层，并去除所述氧化层。
在步骤105中，通过对彼此连接的槽的底部进行氧化和去除氧化层的工艺，使得由彼此连接的槽的底部所形成的曲面的表面更加平滑。
在本实施例中，步骤105可以进行一次或一次以上，直到由彼此连接的槽的底部所形成的曲面的表面达到预定的平滑度。
通过本实施例，能够利用平面工艺中线宽与刻蚀深度的对应关系来完成曲面加工，从而基于现有的平面加工工艺，在晶片的表面形成曲面。
下面，结合具体实例，说明本实施例的形成曲面的方法。
图2是本申请实施例的形成曲面的工艺流程图示意图。
如图2的(A)所示，在硅晶片201的表面形成掩模图形202，掩模图形202具有掩模开口2021。根据目标曲线的形状要求，不同位置的掩模开口2021的尺寸可以相同或不同。该掩模图形202可以由光刻胶形成。
如图2的(B)所示，利用深槽刻蚀工艺对掩模开口2021中的硅晶片进行刻蚀，以形成槽203，与各个掩模开口2021对应的刻蚀的时间可以相同。根据掩模开口202的尺寸，相邻的槽203可以具有不同的深度或相同的深度；并且，相邻的槽203之间具有隔离部204。如图2所示，在掩模开口202的尺寸均为100微米以内的情况下，尺 寸越大的掩模开口202对应越深的槽。
如图2的(C)所示，去除光刻胶掩模图形202。
如图2的(D)所示，对硅晶片201进行氧化处理，以将隔离部204全部转化为氧化物204a，同时，在槽203的底部和硅晶片的上表面也形成有氧化层203a。
如图2的(E)所示，去除氧化物204a和氧化层203a，使得相邻的槽203的底面连接，形成曲面205。
如图2的(F)所示，对硅晶片201再次进行氧化处理，以在曲面205的表面形成氧化层205a。
如图2的(G)所示，去除氧化层205a，以使曲面205更加平滑。
其中，图2的(F)和(G)可以反复进行多次，直到曲面205达到预定的平滑度要求。
根据本申请的实施例，能够在基片的表面形成平滑的曲面，提高了对晶片的加工能力。
以上结合具体的实施方式对本申请进行了描述，但本领域技术人员应该清楚，这些描述都是示例性的，并不是对本申请保护范围的限制。本领域技术人员可以根据本申请的精神和原理对本申请做出各种变型和修改，这些变型和修改也在本申请的范围内。

Claims (7)

  1. 一种在晶片的表面形成曲面的方法，其特征在于，该方法包括：
    在晶片的表面形成掩模图形，所述掩模图形具有至少两个相邻的掩模开口，所述晶片的表面从所述掩模开口露出；
    对从所述掩模开口露出的所述晶片的表面进行刻蚀，以使所述晶片形成与所述掩模开口对应的槽，相邻的所述槽之间形成有所述晶片的材料形成的隔离部；
    对所述晶片进行氧化，以将所述隔离部完全转化为氧化物；以及
    去除由所述隔离部所转化成的氧化物。
  2. 如权利要求1所述的在晶片的表面形成曲面的方法，其特征在于，该方法还包括：
    在去除由所述隔离部所转化成的氧化物之后，至少进行一次如下的步骤：
    对所述晶片的与所述槽以及隔离部对应的区域进行氧化，以形成氧化层，并去除所述氧化层。
  3. 如权利要求1所述的在晶片的表面形成曲面的方法，其特征在于，在对从所述掩模开口露出的所述晶片的表面进行刻蚀的步骤中，
    对不同尺寸的所述掩模开口的刻蚀时间相同。
  4. 如权利要求3所述的在晶片的表面形成曲面的方法，其特征在于，
    不同尺寸的所述掩模开口对应不同深度的所述槽。
  5. 如权利要求4所述的在晶片的表面形成曲面的方法，其特征在于，
    在所述掩模开口的尺寸为100微米以内的情况下，尺寸越大的所述掩模开口对应越深的所述槽。
  6. 如权利要求1所述的在晶片的表面形成曲面的方法，其特征在于，
    不同位置的隔离部具有相同的宽度或不同的宽度。
  7. 如权利要求1所述的在晶片的表面形成曲面的方法，其特征在于，
    所述掩模开口的尺寸是根据目标曲面，所述目标曲面不同位置处对应的槽的深度，以及槽的深度和掩模开口的尺寸之间的关系来确定的。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114530527A (zh) * 2022-02-18 2022-05-24 浙江拓感科技有限公司 光电子器件台面的制备方法及台面型光电子器件的刻蚀结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010044165A1 (en) * 2000-01-18 2001-11-22 Lee Seung B. Single crystal silicon micromirror and array
US20030139014A1 (en) * 2001-10-15 2003-07-24 Khalil Najafi Method of fabricating a device having a desired non-planar surface or profile and device produced thereby
US20080227299A1 (en) * 2007-03-12 2008-09-18 Advanced Micro Devices, Inc. Tapered edge exposure for removal of material from a semiconductor wafer
CN104882357A (zh) * 2014-02-28 2015-09-02 株洲南车时代电气股份有限公司 半导体器件耐压终端结构及其应用于SiC器件的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010044165A1 (en) * 2000-01-18 2001-11-22 Lee Seung B. Single crystal silicon micromirror and array
US20030139014A1 (en) * 2001-10-15 2003-07-24 Khalil Najafi Method of fabricating a device having a desired non-planar surface or profile and device produced thereby
US20080227299A1 (en) * 2007-03-12 2008-09-18 Advanced Micro Devices, Inc. Tapered edge exposure for removal of material from a semiconductor wafer
CN104882357A (zh) * 2014-02-28 2015-09-02 株洲南车时代电气股份有限公司 半导体器件耐压终端结构及其应用于SiC器件的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114530527A (zh) * 2022-02-18 2022-05-24 浙江拓感科技有限公司 光电子器件台面的制备方法及台面型光电子器件的刻蚀结构

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