WO2018040238A1 - 显示驱动电路及像素结构 - Google Patents

显示驱动电路及像素结构 Download PDF

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Publication number
WO2018040238A1
WO2018040238A1 PCT/CN2016/101955 CN2016101955W WO2018040238A1 WO 2018040238 A1 WO2018040238 A1 WO 2018040238A1 CN 2016101955 W CN2016101955 W CN 2016101955W WO 2018040238 A1 WO2018040238 A1 WO 2018040238A1
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Prior art keywords
thin film
film transistor
voltage
gate
input
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PCT/CN2016/101955
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English (en)
French (fr)
Inventor
龚强
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/325,969 priority Critical patent/US10192511B2/en
Publication of WO2018040238A1 publication Critical patent/WO2018040238A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a display driving circuit and a pixel structure.
  • MIP Memory In Pixel design is a design that stores grayscale signals that control pixel display in pixels.
  • the pixel design relied on Cst (storage capacitor) to maintain the grayscale voltage displayed by the pixel. Even if the same picture is displayed, each frame needs to be refreshed (recharge the pixel).
  • the pixel designed by the MIP stores the gray scale signal of the control pixel in the pixel. If the gray scale of the pixel is unchanged, the refresh signal can be omitted, that is, the data signal can be rewritten.
  • the scan line and the data line do not need to work, which can effectively reduce the power consumption of the panel; however, since the MIP circuit needs to be added to the pixel, the design is only applicable to the total reflection LCD and the OLED panel, and cannot be in the backlight. Used in LCD type.
  • the invention provides a display driving circuit, comprising:
  • a logic control unit having two logic control terminals, four voltage input terminals and a voltage output terminal, wherein the output end of the first latch and the output end of the second latch are respectively connected to a logic control end,
  • the four voltage input terminals are respectively connected to four different preset voltages, and the logic control unit is configured to select the four preset voltages according to the first data voltage input by the two logic control terminals and the second data voltage.
  • a predetermined voltage is output to the pixel electrode through the voltage output terminal.
  • the method further includes:
  • a first thin film transistor having a source for inputting the first data voltage, a gate for inputting a first scan voltage, and a drain connected to an input end of the first latch;
  • the second thin film transistor has a source for inputting a second data voltage, a gate for inputting a second scan voltage, and a drain connected to an input terminal of the second latch.
  • the logic control unit includes a selection module and four third thin film transistors, and the selection module has the two logic control terminals and four level output terminals;
  • the input ends of the four third thin film transistors are respectively connected to one of the voltage input ends, and the output ends of the four third thin film transistors are respectively connected to the voltage output end, and the gates of the four third thin film transistors are respectively The level output terminal is connected; the selection module selects one of the four third thin film transistors to be turned on according to the first data voltage and the second data voltage, and the other three of the third The thin film transistor is turned off.
  • the selection module includes a first input NOR of two inputs, a second NOR gate of two inputs, a third NOR gate of two inputs, and a first and a second of two inputs.
  • a first input terminal of the first NOR gate, a first input end of the second NOR gate, and a first input end of the first NAND gate respectively
  • the output end of the first latch is connected, the second input end of the first NOR gate, the first input end of the third NOR gate, and the second input end of the first NAND gate are respectively associated with the first
  • the output of the second latch is connected, the second input of the second NOR gate, the second input of the third NOR gate, and the output of the first NOR gate; the first counter
  • the input end of the phase detector is connected to the output end of the first NAND gate, and the first NOR gate, the second NOR gate, the third NOR gate, and the output end of the first inverter are respectively connected to a third film
  • the gate of the transistor is connected.
  • the first NAND gate includes a second N-channel thin film transistor, a third N-channel thin film transistor, a second P-channel thin film transistor, and a third P-channel thin film transistor. ;
  • the input ends of the second P-channel thin film transistor and the third P-channel thin film transistor are connected and connected to the first preset voltage at the connection point;
  • the output ends of the second N-channel thin film transistor, the second P-channel thin film transistor, and the third P-channel thin film transistor are connected and the connection point is the output end of the first NAND gate;
  • a gate of the second P-channel thin film transistor is connected to a gate of the second N-channel thin film transistor, and the connection point is used as a first input end of the first NAND gate;
  • a gate of the third P-channel thin film transistor is connected to a gate of the third N-channel thin film transistor, and the connection point is used as a second input end of the first NAND gate;
  • the input end of the third N-channel thin film transistor is connected to a second predetermined voltage.
  • the first latch and the second latch each include two second inverters connected end to end.
  • the second inverter includes a first N-channel thin film transistor and a first P-channel thin film transistor, the first N-channel thin film transistor and the first P-channel thin film.
  • An output end of the transistor is connected and the connection point is an output end of the second inverter, and a gate of the first N-channel thin film transistor and the first P-channel thin film transistor is connected and the connection point is the second
  • An input end of the inverter, the first N-channel thin film transistor and the input end of the first P-channel thin film transistor are respectively connected to a first preset voltage and a second preset voltage.
  • the present invention provides a pixel structure including a pixel capacitor and a display driving circuit
  • the pixel capacitor includes a common electrode and a pixel electrode
  • the display driving circuit includes:
  • a first thin film transistor having a source for inputting a first data voltage and a gate for inputting a first scan voltage
  • a first latch having an input connected to a drain of the first thin film transistor
  • a second thin film transistor having a source for inputting a second data voltage and a gate for inputting a second scan voltage
  • a second latch having an input coupled to a drain of the second thin film transistor
  • a logic control unit having two logic control terminals, four voltage input terminals and a voltage output terminal, wherein the output end of the first latch and the output end of the second latch are respectively connected to a logic control end,
  • the four voltage input terminals are respectively connected to four different preset voltages, and the logic control unit is configured to select the four preset voltages according to the first data voltage input by the two logic control terminals and the second data voltage.
  • a predetermined voltage is output to the pixel electrode through the voltage output terminal.
  • the method further includes a first data line, a first scan line, and a second scan line, wherein the first data line is respectively connected to the sources of the first thin film transistor and the second thin film transistor
  • the first scan line is connected to a gate of the first thin film transistor
  • the second scan line is connected to a gate of the second thin film transistor.
  • the method further includes a first data line, a second data line, and a first scan line, the first data line being connected to a source of the first thin film transistor, the second data A line is connected to a source of the second thin film transistor, and the first scan line is connected to gates of the first thin film transistor and the second thin film transistor.
  • the present invention also provides a pixel structure including a pixel capacitor and a display driving circuit
  • the pixel capacitor includes a common electrode and a pixel electrode
  • the display driving circuit includes:
  • a first thin film transistor having a source for inputting a first data voltage and a gate for inputting a first scan voltage
  • a first latch having an input connected to a drain of the first thin film transistor
  • a second thin film transistor having a source for inputting a second data voltage and a gate for inputting a second scan voltage
  • a second latch having an input coupled to a drain of the second thin film transistor
  • a logic control unit having two logic control terminals, four voltage input terminals and a voltage output terminal, wherein the output end of the first latch and the output end of the second latch are respectively connected to a logic control end,
  • the four voltage input terminals are respectively connected to four different preset voltages, and the logic control unit is configured to select the four preset voltages according to the first data voltage input by the two logic control terminals and the second data voltage.
  • a preset voltage is output to the pixel electrode through the voltage output terminal;
  • the logic control unit includes a selection module and four third thin film transistors, the selection module having the two logic control terminals and four level output terminals;
  • the input ends of the four third thin film transistors are respectively connected to one of the voltage input ends, and the output ends of the four third thin film transistors are respectively connected to the voltage output end, and the gates of the four third thin film transistors are respectively The level output terminal is connected; the selection module selects one of the four third thin film transistors to be turned on according to the first data voltage and the second data voltage, and the other three of the third The thin film transistor is turned off.
  • the display driving circuit and the pixel structure provided by the present invention use two latches to latch two data voltage signals.
  • the data lines and the scan lines can be Stop working, thus having the beneficial effect of reducing power consumption;
  • each pixel structure has four gray scales.
  • Figure 1 is a block diagram showing the structure of a pixel in a preferred embodiment of the present invention.
  • Figure 2 is a circuit diagram showing a portion of a pixel structure in the embodiment of Figure 1 of the present invention.
  • FIG. 3 is a circuit configuration diagram of a second inverter in the embodiment shown in FIG. 1 of the present invention.
  • FIG. 4 is a circuit configuration diagram of a first NOR gate in the embodiment shown in FIG. 1 of the present invention.
  • Figure 5 is a circuit diagram showing the structure of a first NAND gate in the embodiment of Figure 1 of the present invention.
  • Figure 6 is a structural diagram of a pixel structure in another preferred embodiment of the present invention.
  • FIG. 1 is a structural diagram of a pixel structure in a preferred embodiment of the present invention, which is mainly applied to a backlight LCD.
  • the pixel structure includes a first data line D11, a first scan line G11, a second scan line G12, a pixel capacitor, a storage capacitor (not shown), and a display driving circuit 100.
  • the pixel capacitor includes a common electrode and a pixel electrode.
  • the display driving circuit 100 includes a first thin film transistor 101, a first latch 102, a logic control unit 103, a second latch 104, and a second thin film transistor 105.
  • the source of the first thin film transistor 101 is connected to the first data line D11 for inputting a first data voltage, and the gate is connected to the first scan line G11 for inputting a first scan voltage.
  • An input end of the first latch 102 is connected to a drain of the first thin film transistor 101; a source of the second thin film transistor 105 is connected to the first data line D11, and is used for inputting a second data voltage;
  • the two scan lines G12 are connected and used to input the second scan voltage.
  • the input terminal of the second latch is connected to the drain of the second thin film transistor 105.
  • the logic control unit 103 has two logic control terminals, four voltage input terminals and one voltage output terminal.
  • the output terminal of the first latch 102 and the output terminal of the second latch 104 are respectively connected to a logic control terminal.
  • the four voltage input terminals are respectively connected to four different preset voltages, and the logic control unit 103 is configured to select the four preset voltages according to the first data voltage input by the two logic control terminals and the second data voltage.
  • One of the preset voltages is output to the pixel electrode through the voltage output terminal. Since the same data line is connected, the first data voltage and the second data voltage are the same.
  • the logic control unit 103 includes a selection module 1031 and an output module 1032.
  • the output module 1032 includes four third thin film transistors T3, and the selection module 1031 has the two logic control terminals and four Level output.
  • the input ends of the four third thin film transistors T3 are respectively connected to the voltage input terminals of the logic control unit 103, and the four voltage input terminals respectively input four different voltages of VL0, VL1, VL2, and VL3.
  • the output ends of the four third thin film transistors T3 are respectively connected to the voltage output end, and the gates of the four third thin film transistors T3 are respectively connected to one of the level output ends; the selection module is configured according to the first data.
  • the voltage and the second data voltage select one of the four third thin film transistors T3 to be turned on, and the other three of the third thin film transistors T3 are turned off, thereby making the VL0, VL1, VL2, and VL3 different.
  • One of the voltages is output to the pixel electrode of the pixel capacitor.
  • the selection module 1031 includes a first NOR gate U1 with two inputs, a second NOR gate U2 with two inputs, a third NOR gate U3 with two inputs, a first NAND gate U4 with two inputs, and a second input.
  • An inverter U5 a first input end of the first NOR gate U1, a first input end of the second NOR gate U2, and a first input end of the first NAND gate U4 are respectively associated with the first The output end of the latch 102 is connected, and the second input end of the first NOR gate U1, the first input end of the third NOR gate U3, and the second input end of the first NAND gate U4 are respectively The output of the second latch 104 is connected, the second input of the second NOR gate U2, the second input of the third NOR gate U3, and the output of the U1 of the first NOR gate Connecting; the input end of the first inverter U5 is connected to the output end of the first NAND gate U4, the first NOR gate U1, the second NOR gate U2, the third NOR gate U3, and the first The output terminals of the inverter U5 are respectively connected to the gate of a third thin film transistor T3.
  • the first latch 102 and the second latch 104 respectively include two second inverters U6 connected end to end.
  • the second inverter U6 includes a first N-channel thin film transistor N1 and a first P-channel thin film transistor P1, the first N-channel thin film transistor N1 and the first P-channel thin film transistor P1.
  • the output terminal is connected and the connection point is the output end of the second inverter U6, and the gates of the first N-channel thin film transistor N1 and the first P-channel thin film transistor P1 are connected and the connection point is the first
  • the input ends of the two N-channel thin film transistors N1 and the first P-channel thin film transistor P1 are respectively connected to a first preset voltage and a second preset voltage.
  • the first preset voltage is low.
  • the second preset voltage is at a high level.
  • the first NAND gate U4 includes a second N-channel thin film transistor N2, a third N-channel thin film transistor N3, a second P-channel thin film transistor P2, and a third P-channel thin film transistor P3.
  • the input ends of the second P-channel thin film transistor P2 and the third P-channel thin film transistor P3 are connected and connected to the second predetermined voltage at the connection point.
  • the output ends of the second N-channel thin film transistor N2, the second P-channel thin film transistor P2, and the third P-channel thin film transistor P3 are connected and the connection point is the output end of the first NAND gate U4.
  • a gate of the second P-channel thin film transistor P2 is connected to a gate of the second N-channel thin film transistor N2, and the connection point is used as a first input end of the first NAND gate U4;
  • the third P The gate of the channel thin film transistor P3 is connected to the gate of the third N-channel thin film transistor N3, and the connection point is used as the second input end of the first NAND gate U4.
  • the input end of the third N-channel thin film transistor N3 is connected to a first preset voltage.
  • each NOR gate includes: a fourth P-channel thin film transistor. P4, a fifth P-channel thin film transistor P5, a fourth N-channel thin film transistor N4, and a fifth-four N-channel thin film transistor N5.
  • the input end of the fourth P-channel thin film transistor P4 is connected to a first preset voltage.
  • An output end of the fourth P-channel thin film transistor P4 is connected to an input end of the fifth P-channel thin film transistor P5.
  • the output end of the fifth P-channel thin film transistor P5, the output terminals of the fourth N-channel thin film transistor N4 and the fifth-four N-channel thin film transistor N5 are connected, and the connection point is the output terminal of the NOR gate.
  • the input end of the fourth P-channel thin film transistor P4 is connected to a first preset voltage.
  • the gate of the fourth P-channel thin film transistor P4 and the gate of the fourth N-channel thin film transistor are connected, and the connection point is used as the first input end of the NOR gate.
  • the gate of the fifth N-channel thin film transistor N5 and the gate of the fifth P-channel thin film transistor P5 are connected, and the connection point is used as the second input terminal of the NOR gate.
  • the output of the fourth N-channel thin film transistor N4 and the fifth N-channel thin film transistor N5 are connected, and a second predetermined voltage is applied to the connection point.
  • one of the four gray scale voltages VL0, VL1, VL2, VL3 is controlled by the logic control unit 103 to output to the pixel electrode, so that each sub-pixel can display 4 gray scales, so that for one pixel, three sub-pixels of RGB are used.
  • the panel is composed of 64 colors.
  • a latch first latch or second latch
  • two signals controlling the gray scale voltage output are latched in the pixel. So that even if the pixel is not refreshed for a long time, the pixel can still display the gray level that has been stored before, which is equivalent to the pixel having the grayscale storage function.
  • the panel displays a static picture, that is, when the same picture is displayed for a long time, the gray level signal can be written only once for each pixel, and the panel is not refreshed thereafter.
  • the display driving circuit and the pixel structure provided by the present invention use two latches to latch two data signals.
  • the display screen is stationary, there is no need to scan again, and the data lines and the scan lines can be stopped. Thereby having the beneficial effect of reducing power consumption;
  • each pixel structure has four gray scales.
  • the pixel structure includes a first data line D11, a second data line D12, a first scan line G11, a pixel capacitor, and a storage capacitor (not Shown) and display drive circuit 100.
  • the first data line D11 is connected to the source of the first thin film transistor 101
  • the second data line D12 is connected to the source of the second thin film transistor 105
  • the first scan line G11 and the first thin film transistor 101 are The gates of the second thin film transistors 105 are connected.
  • the display driving circuit 100 includes a first thin film transistor 101, a first latch 102, a logic control unit 103, a second latch 104, and a second thin film transistor 105.
  • the source of the first thin film transistor 101 is connected to the first data line D11 for inputting a first data voltage, and the gate is connected to the first scan line G11 for inputting a first scan voltage.
  • An input end of the first latch 102 is connected to a drain of the first thin film transistor 101; a source of the second thin film transistor 105 is connected to the first data line D11, and is used for inputting a second data voltage;
  • the two scan lines G12 are connected and used to input the second scan voltage.
  • the input terminal of the second latch is connected to the drain of the second thin film transistor 105.
  • the logic control unit 103 has two logic control terminals, four voltage input terminals and one voltage output terminal.
  • the output terminal of the first latch 102 and the output terminal of the second latch 104 are respectively connected to a logic control terminal.
  • the four voltage input terminals are respectively connected to four different preset voltages, and the logic control unit 103 is configured to select the four preset voltages according to the first data voltage input by the two logic control terminals and the second data voltage.
  • One of the preset voltages is output to the pixel electrode through the voltage output terminal. Since the same data line is connected, the first data voltage and the second data voltage are the same.
  • one of the four gray scale voltages VL0, VL1, VL2, VL3 is controlled by the logic control unit 103 to output to the pixel electrode, so that each sub-pixel can display 4 gray scales, so that for one pixel, three sub-pixels of RGB are used.
  • the panel is composed of 64 colors.
  • a latch first latch or second latch
  • two signals controlling the gray scale voltage output are latched in the pixel. So that even if the pixel is not refreshed for a long time, the pixel can still display the gray level that has been stored before, which is equivalent to the pixel having the grayscale storage function.
  • the panel displays a static picture, that is, when the same picture is displayed for a long time, the gray level signal can be written only once for each pixel, and the panel is not refreshed thereafter.
  • the display driving circuit and the pixel structure provided by the present invention use two latches to latch two data signals.
  • the display screen is stationary, there is no need to scan again, and the data lines and the scan lines can be stopped. Thereby having the beneficial effect of reducing power consumption;
  • each pixel structure has four gray scales.

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Abstract

一种显示驱动电路(100)及像素结构，驱动电路(100)包括第一锁存器(102)、第二锁存器(104)、逻辑控制单元(103)，逻辑控制单元(103)用于根据两个逻辑控制端输入的第一数据电压以及第二数据电压选择将四个预设电压(VL0、VL1、VL2、VL3)中的一个预设电压通过电压输出端输出至像素电极。

Description

显示驱动电路及像素结构 技术领域
本发明涉及液晶显示领域，特别是涉及一种显示驱动电路及像素结构。
 背景技术
MIP（Memory In Pixel）设计是把控制像素显示的灰阶信号存储在像素中的一种设计。以往像素设计靠Cst（存储电容）维持像素显示的灰阶电压，即使显示相同的画面，每一帧均需要刷新（给像素重新充电）。采用MIP设计的像素，把控制像素显示的灰阶信号存储在像素中，若像素显示灰阶不变，可以不用刷新，即可以不用重新写入Data信号。这样在显示静态画面时，扫描线和数据线均不需要工作，可以有效降低面板的功耗；但是由于像素中需要加入MIP电路，此种设计只适用于全反射LCD和OLED面板，无法在背光型LCD中使用。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种显示驱动电路及像素结构；以解决现有的背光型LCD在显示每一帧画面均需要刷新从而导致功耗较高的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种显示驱动电路，包括：
第一锁存器，用于锁存第一数据电压；
第二锁存器，用于锁存第二数据电压；
逻辑控制单元，其具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器的输出端以及第二锁存器的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极。
在本发明所述的显示驱动电路中，还包括：
第一薄膜晶体管，其源极用于输入所述第一数据电压，其栅极用于输入第一扫描电压，其漏极与所述第一锁存器的输入端连接；
第二薄膜晶体管，其源极用于输入第二数据电压，其栅极用于输入第二扫描电压，其漏极与所述第二锁存器的输入端连接。
在本发明所述的显示驱动电路中，所述逻辑控制单元包括选择模块以及四个第三薄膜晶体管，所述选择模块具有所述两个逻辑控制端以及四个电平输出端；
该四个第三薄膜晶体管的输入端分别与一所述电压输入端连接，该四个第三薄膜晶体管的输出端分别与该电压输出端连接，该四个第三薄膜晶体管的栅极分别与一所述电平输出端连接；所述选择模块根据所述第一数据电压以及第二数据电压选择该四个第三薄膜晶体管中的一个第三薄膜晶体管导通，其余三个所述第三薄膜晶体管关闭。
在本发明所述的显示驱动电路中，所述选择模块包括二输入的第一或非门、二输入的第二或非门、二输入的第三或非门、二输入的第一与非门以及二输入的第一反相器；该第一或非门的第一输入端、该第二或非门的第一输入端、该第一与非门的第一输入端均分别与该第一锁存器的输出端连接，该第一或非门的第二输入端、该第三或非门的第一输入端、该第一与非门的第二输入端均分别与该第二锁存器的输出端连接，所述第二或非门的第二输入端、所述第三或非门的第二输入端以及该第一或非门的输出端连接；该第一反相器的输入端该第一与非门的输出端连接，该第一或非门、第二或非门、第三或非门以及该第一反相器的输出端分别与一第三薄膜晶体管的栅极连接。
在本发明所述的显示驱动电路中，所述第一与非门包括第二N沟道薄膜晶体管、第三N沟道薄膜晶体管、第二P沟道薄膜晶体管以及第三P沟道薄膜晶体管；
第二P沟道薄膜晶体管以及第三P沟道薄膜晶体管的输入端连接并在该连接点接入第一预设电压；
第二N沟道薄膜晶体管、第二P沟道薄膜晶体管以及第三P沟道薄膜晶体管的输出端连接并以该连接点为该第一与非门的输出端；
该第二P沟道薄膜晶体管的栅极与该第二N沟道薄膜晶体管的栅极连接，并以该连接点作为该第一与非门的第一输入端；
该第三P沟道薄膜晶体管的栅极与该第三N沟道薄膜晶体管的栅极连接，并以该连接点作为该第一与非门的第二输入端；
该第三N沟道薄膜晶体管的输入端接第二预设电压。
在本发明所述的显示驱动电路中，所述第一锁存器以及所述第二锁存器均分别包括两个首尾相连的第二反相器。
在本发明所述的显示驱动电路中，所述第二反相器包括第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的输出端连接并以该连接点为该第二反相器的输出端，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的栅极连接并以该连接点为该第二反相器的输入端，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的输入端分别接一第一预设电压以及第二预设电压。
本发明提供一种像素结构，包括像素电容以及显示驱动电路；
该像素电容包括公共电极以及像素电极；
该显示驱动电路包括：
第一薄膜晶体管，其源极用于输入第一数据电压，其栅极用于输入第一扫描电压；
第一锁存器，其输入端与第一薄膜晶体管的漏极连接；
第二薄膜晶体管，其源极用于输入第二数据电压，其栅极用于输入第二扫描电压；
第二锁存器，其输入端与第二薄膜晶体管的漏极连接
逻辑控制单元，其具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器的输出端以及第二锁存器的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极。
在本发明所述的像素结构中，还包括第一数据线、第一扫描线以及第二扫描线，所述第一数据线分别与所述第一薄膜晶体管以及第二薄膜晶体管的源极连接，所述第一扫描线与所述第一薄膜晶体管的栅极连接，所述第二扫描线与所述第二薄膜晶体管的栅极连接。
在本发明所述的像素结构中，还包括第一数据线、第二数据线以及第一扫描线，所述第一数据线与所述第一薄膜晶体管的源极连接，所述第二数据线与所述第二薄膜晶体管的源极连接，所述第一扫描线与所述第一薄膜晶体管以及所述第二薄膜晶体管的栅极连接。
本发明还提供了一种像素结构，其包括像素电容以及显示驱动电路；
该像素电容包括公共电极以及像素电极；
该显示驱动电路包括：
第一薄膜晶体管，其源极用于输入第一数据电压，其栅极用于输入第一扫描电压；
第一锁存器，其输入端与第一薄膜晶体管的漏极连接；
第二薄膜晶体管，其源极用于输入第二数据电压，其栅极用于输入第二扫描电压；
第二锁存器，其输入端与第二薄膜晶体管的漏极连接
逻辑控制单元，其具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器的输出端以及第二锁存器的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极；
所述逻辑控制单元包括选择模块以及四个第三薄膜晶体管，所述选择模块具有所述两个逻辑控制端以及四个电平输出端；
该四个第三薄膜晶体管的输入端分别与一所述电压输入端连接，该四个第三薄膜晶体管的输出端分别与该电压输出端连接，该四个第三薄膜晶体管的栅极分别与一所述电平输出端连接；所述选择模块根据所述第一数据电压以及第二数据电压选择该四个第三薄膜晶体管中的一个第三薄膜晶体管导通，其余三个所述第三薄膜晶体管关闭。
 有益效果
与现有技术相比，本发明提供的显示驱动电路及像素结构采用两个锁存器将两个数据电压信号进行锁存，当显示画面静止时，无需在进行扫描，数据线以及扫描线可以停止工作，从而具有降低功耗的有益效果；
并且，由于该逻辑控制单元将该两个数据电压扩展为四个数据电压，从而使得每一个像素结构具有四种灰阶。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1是本发明一优选实施例中的像素结构的结构图。
图2是本发明图1所示实施例中的像素结构的局部的电路结构图。
图3是本发明图1所示实施例中的第二反相器的电路结构图。
图4是本发明图1所示实施例中的第一或非门的电路结构图。
图5是本发明图1所示实施例中的第一与非门的电路结构图。
图6是本发明另一优选实施例中的像素结构的结构图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1是本发明一优选实施例中的像素结构的结构图，其主要应用于背光式LCD中。在本实施例中，该像素结构包括第一数据线D11、第一扫描线G11、第二扫描线G12、像素电容、存储电容（未示出）以及显示驱动电路100。
其中，该像素电容包括公共电极以及像素电极。
该显示驱动电路100包括第一薄膜晶体管101、第一锁存器102、逻辑控制单元103、第二锁存器104以及第二薄膜晶体管105。
第一薄膜晶体管101的源极与第一数据线D11连接用于输入第一数据电压，栅极与第一扫描线G11连接用于输入第一扫描电压。第一锁存器102的输入端与第一薄膜晶体管101的漏极连接；第二薄膜晶体管105的源极与该第一数据线D11连接，并用于输入第二数据电压；其栅极与第二扫描线G12连接，并用于输入第二扫描电压。第二锁存器的输入端与第二薄膜晶体管105的漏极连接。逻辑控制单元103具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器102的输出端以及第二锁存器104的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元103用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极。由于接同一根数据线，第一数据电压以及第二数据电压相同。
具体地，如图2所示，逻辑控制单元103包括选择模块1031以及输出模块1032，该输出模块1032包括四个第三薄膜晶体管T3，所述选择模块1031具有所述两个逻辑控制端以及四个电平输出端。该四个第三薄膜晶体管T3的输入端分别与逻辑控制单元103的电压输入端连接，四个电压输入端分别输入VL0、VL1、VL2、VL3四个不同的电压。四个第三薄膜晶体管T3的输出端分别与该电压输出端连接，该四个第三薄膜晶体管T3的栅极分别与一所述电平输出端连接；所述选择模块根据所述第一数据电压以及第二数据电压选择四个第三薄膜晶体管T3中的一个第三薄膜晶体管T3导通，其余三个所述第三薄膜晶体管T3关闭，从而将该VL0、VL1、VL2、VL3四个不同的电压中的一个电压输出给像素电容的像素电极。
该选择模块1031包括具有二输入的第一或非门U1、二输入的第二或非门U2、二输入的第三或非门U3、二输入的第一与非门U4以及二输入的第一反相器U5；该第一或非门U1的第一输入端、该第二或非门U2的第一输入端、该第一与非门U4的第一输入端均分别与该第一锁存器102的输出端连接，该第一或非门U1的第二输入端、该第三或非门U3的第一输入端、该第一与非门U4的第二输入端均分别与该第二锁存器104的输出端连接，所述第二或非门U2的第二输入端、所述第三或非门U3的第二输入端以及第一或非门的U1的输出端连接；该第一反相器U5的输入端与该第一与非门U4的输出端连接，该第一或非门U1、第二或非门U2、第三或非门U3以及该第一反相器U5的输出端分别与一第三薄膜晶体管T3的栅极连接。
其中，第一锁存器102以及所述第二锁存器104均分别包括两个首尾相连的第二反相器U6。
如图3所示，第二反相器U6包括第一N沟道薄膜晶体管N1以及第一P沟道薄膜晶体管P1，该第一N沟道薄膜晶体管N1以及第一P沟道薄膜晶体管P1的输出端连接并以该连接点为该第二反相器U6的输出端，该第一N沟道薄膜晶体管N1以及第一P沟道薄膜晶体管P1的栅极连接并以该连接点为该第二反相器U6的输入端，该第一N沟道薄膜晶体管N1以及第一P沟道薄膜晶体管P1的输入端分别接一第一预设电压以及第二预设电压。第一预设电压为低电平。第二预设电压为高电平。
如图4所示，第一与非门U4包括第二N沟道薄膜晶体管N2、第三N沟道薄膜晶体管N3、第二P沟道薄膜晶体管P2以及第三P沟道薄膜晶体管P3。
第二P沟道薄膜晶体管P2以及第三P沟道薄膜晶体管P3的输入端连接并在该连接点接入第二预设电压。第二N沟道薄膜晶体管N2、第二P沟道薄膜晶体管P2以及第三P沟道薄膜晶体管P3的输出端连接并以该连接点为该第一与非门U4的输出端。该第二P沟道薄膜晶体管P2的栅极与该第二N沟道薄膜晶体管N2的栅极连接，并以该连接点作为该第一与非门U4的第一输入端；该第三P沟道薄膜晶体管P3的栅极与该第三N沟道薄膜晶体管N3的栅极连接，并以该连接点作为该第一与非门U4的第二输入端。该第三N沟道薄膜晶体管N3的输入端接第一预设电压。
如图5所示，该第一或非门、第二或非门、第三或非门以及第四或非门的结构相同，每一或非门均分别包括：第四P沟道薄膜晶体管P4、第五P沟道薄膜晶体管P5、第四N沟道薄膜晶体管N4以及第五四N沟道薄膜晶体管N5。
该第四P沟道薄膜晶体管P4的输入端接入第一预设电压。
该第四P沟道薄膜晶体管P4的输出端与该第五P沟道薄膜晶体管P5的输入端连接。
第五P沟道薄膜晶体管P5的输出端、第四N沟道薄膜晶体管N4以及第五四N沟道薄膜晶体管N5的输出端连接，并以该连接点为或非门的输出端。
该第四P沟道薄膜晶体管P4的输入端接入第一预设电压。
该第四P沟道薄膜晶体管P4的栅极以及该第四N沟道薄膜晶体管的栅极连接，并以该连接点作为该或非门的第一输入端。
该第五N沟道薄膜晶体管N5的栅极以及该第五P沟道薄膜晶体管P5的栅极连接，并以该连接点作为该或非门的第二输入端。
第四N沟道薄膜晶体管N4以及该第五N沟道薄膜晶体管N5的输出连接，并在该连接点接入第二预设电压。
工作原理：通过逻辑控制单元103控制4个灰阶电压VL0、VL1、VL2、VL3中的一个输出到像素电极，使每个子像素都能显示4个灰阶，这样对于一个像素由RGB三个子像素组成的面板，就可以显示出64色。在每个子像素的数据电压的输入进入逻辑控制单元10之前，会经过一个锁存器（第一锁存器或第二锁存器），将控制灰阶电压输出的两个信号锁存在像素中，这样即使长时间不对像素刷新，像素依然能够显示之前已经存储的灰阶，相当于像素具有了灰阶存储功能。当面板显示静态画面，即长时间显示同一个画面时，可以只对每个像素写入一次灰阶信号，此后不用再刷新面板。
由上可知，本发明提供的显示驱动电路及像素结构采用两个锁存器将两个数据信号进行锁存，当显示画面静止时，无需再进行扫描，数据线以及扫描线均可以停止工作，从而具有降低功耗的有益效果；
并且，由于该逻辑控制单元将该两个数据电压扩展为四个数据电压，从而使得每一个像素结构具有四种灰阶。
如图6所示，可以理解地，在本发明提供的第二实施例中，该像素结构包括第一数据线D11、第二数据线D12、第一扫描线G11、像素电容、存储电容（未示出）以及显示驱动电路100。该第一数据线D11与第一薄膜晶体管101的源极连接，该第二数据线D12与第二薄膜晶体管105的源极连接，所述第一扫描线G11与所述第一薄膜晶体管101以及所述第二薄膜晶体管105的栅极连接。
该显示驱动电路100包括第一薄膜晶体管101、第一锁存器102、逻辑控制单元103、第二锁存器104以及第二薄膜晶体管105。
第一薄膜晶体管101的源极与第一数据线D11连接用于输入第一数据电压，栅极与第一扫描线G11连接用于输入第一扫描电压。第一锁存器102的输入端与第一薄膜晶体管101的漏极连接；第二薄膜晶体管105的源极与该第一数据线D11连接，并用于输入第二数据电压；其栅极与第二扫描线G12连接，并用于输入第二扫描电压。第二锁存器的输入端与第二薄膜晶体管105的漏极连接。逻辑控制单元103具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器102的输出端以及第二锁存器104的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元103用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极。由于接同一根数据线，第一数据电压以及第二数据电压相同。
工作原理：通过逻辑控制单元103控制4个灰阶电压VL0、VL1、VL2、VL3中的一个输出到像素电极，使每个子像素都能显示4个灰阶，这样对于一个像素由RGB三个子像素组成的面板，就可以显示出64色。在每个子像素的数据电压的输入进入逻辑控制单元10之前，会经过一个锁存器（第一锁存器或第二锁存器），将控制灰阶电压输出的两个信号锁存在像素中，这样即使长时间不对像素刷新，像素依然能够显示之前已经存储的灰阶，相当于像素具有了灰阶存储功能。当面板显示静态画面，即长时间显示同一个画面时，可以只对每个像素写入一次灰阶信号，此后不用再刷新面板。
由上可知，本发明提供的显示驱动电路及像素结构采用两个锁存器将两个数据信号进行锁存，当显示画面静止时，无需再进行扫描，数据线以及扫描线均可以停止工作，从而具有降低功耗的有益效果；
并且，由于该逻辑控制单元将该两个数据电压扩展为四个数据电压，从而使得每一个像素结构具有四种灰阶。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种显示驱动电路，其包括：
    第一锁存器，用于锁存第一数据电压；
    第二锁存器，用于锁存第二数据电压；
    逻辑控制单元，其具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器的输出端以及第二锁存器的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极。
  2. 根据权利要求1所述的显示驱动电路，其中，还包括：
    第一薄膜晶体管，其源极用于输入所述第一数据电压，其栅极用于输入第一扫描电压，其漏极与所述第一锁存器的输入端连接；
    第二薄膜晶体管，其源极用于输入第二数据电压，其栅极用于输入第二扫描电压，其漏极与所述第二锁存器的输入端连接。
  3. 根据权利要求2所述的显示驱动电路，其中，所述逻辑控制单元包括选择模块以及四个第三薄膜晶体管，所述选择模块具有所述两个逻辑控制端以及四个电平输出端；
    该四个第三薄膜晶体管的输入端分别与一所述电压输入端连接，该四个第三薄膜晶体管的输出端分别与该电压输出端连接，该四个第三薄膜晶体管的栅极分别与一所述电平输出端连接；所述选择模块根据所述第一数据电压以及第二数据电压选择该四个第三薄膜晶体管中的一个第三薄膜晶体管导通，其余三个所述第三薄膜晶体管关闭。
  4. 根据权利要求3所述的显示驱动电路，其中，所述选择模块包括二输入的第一或非门、二输入的第二或非门、二输入的第三或非门、二输入的第一与非门以及二输入的第一反相器；该第一或非门的第一输入端、该第二或非门的第一输入端、该第一与非门的第一输入端均分别与该第一锁存器的输出端连接，该第一或非门的第二输入端、该第三或非门的第一输入端、该第一与非门的第二输入端均分别与该第二锁存器的输出端连接，所述第二或非门的第二输入端、所述第三或非门的第二输入端以及该第一或非门的输出端连接；该第一反相器的输入端该第一与非门的输出端连接，该第一或非门、第二或非门、第三或非门以及该第一反相器的输出端分别与一第三薄膜晶体管的栅极连接。
  5. 根据权利要求4所述的显示驱动电路，其中，所述第一与非门包括第二N沟道薄膜晶体管、第三N沟道薄膜晶体管、第二P沟道薄膜晶体管以及第三P沟道薄膜晶体管；
    第二P沟道薄膜晶体管以及第三P沟道薄膜晶体管的输入端连接并在该连接点接入第一预设电压；
    第二N沟道薄膜晶体管、第二P沟道薄膜晶体管以及第三P沟道薄膜晶体管的输出端连接并以该连接点为该第一与非门的输出端；
    该第二P沟道薄膜晶体管的栅极与该第二N沟道薄膜晶体管的栅极连接，并以该连接点作为该第一与非门的第一输入端；
    该第三P沟道薄膜晶体管的栅极与该第三N沟道薄膜晶体管的栅极连接，并以该连接点作为该第一与非门的第二输入端；
    该第三N沟道薄膜晶体管的输入端接第二预设电压。
  6. 根据权利要求1所述的显示驱动电路，其中，所述第一锁存器以及所述第二锁存器均分别包括两个首尾相连的第二反相器。
  7. 根据权利要求6所述的显示驱动电路，其中，所述第二反相器包括第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的输出端连接并以该连接点为该第二反相器的输出端，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的栅极连接并以该连接点为该第二反相器的输入端，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的输入端分别接一第一预设电压以及第二预设电压。
  8. 根据权利要求2所述的显示驱动电路，其中，所述第一锁存器以及所述第二锁存器均分别包括两个首尾相连的第二反相器。
  9. 根据权利要求8所述的显示驱动电路，其中，所述第二反相器包括第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的输出端连接并以该连接点为该第二反相器的输出端，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的栅极连接并以该连接点为该第二反相器的输入端，该第一N沟道薄膜晶体管以及第一P沟道薄膜晶体管的输入端分别接一第一预设电压以及第二预设电压。
  10. 一种像素结构，其包括像素电容以及显示驱动电路；
    该像素电容包括公共电极以及像素电极；
    该显示驱动电路包括：
    第一薄膜晶体管，其源极用于输入第一数据电压，其栅极用于输入第一扫描电压；
    第一锁存器，其输入端与第一薄膜晶体管的漏极连接；
    第二薄膜晶体管，其源极用于输入第二数据电压，其栅极用于输入第二扫描电压；
    第二锁存器，其输入端与第二薄膜晶体管的漏极连接
    逻辑控制单元，其具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器的输出端以及第二锁存器的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极。
  11. 根据权利要求10所述的像素结构，其中，还包括第一数据线、第一扫描线以及第二扫描线，所述第一数据线分别与所述第一薄膜晶体管以及第二薄膜晶体管的源极连接，所述第一扫描线与所述第一薄膜晶体管的栅极连接，所述第二扫描线与所述第二薄膜晶体管的栅极连接。
  12. 根据权利要求10所述的像素结构，其中，还包括第一数据线、第二数据线以及第一扫描线，所述第一数据线与所述第一薄膜晶体管的源极连接，所述第二数据线与所述第二薄膜晶体管的源极连接，所述第一扫描线与所述第一薄膜晶体管以及所述第二薄膜晶体管的栅极连接。
  13. 一种像素结构，其包括像素电容以及显示驱动电路；
    该像素电容包括公共电极以及像素电极；
    该显示驱动电路包括：
    第一薄膜晶体管，其源极用于输入第一数据电压，其栅极用于输入第一扫描电压；
    第一锁存器，其输入端与第一薄膜晶体管的漏极连接；
    第二薄膜晶体管，其源极用于输入第二数据电压，其栅极用于输入第二扫描电压；
    第二锁存器，其输入端与第二薄膜晶体管的漏极连接
    逻辑控制单元，其具有两个逻辑控制端、四个电压输入端以及一个电压输出端，该第一锁存器的输出端以及第二锁存器的输出端分别与一逻辑控制端连接，该四个电压输入端分别接入四个不同的预设电压，该逻辑控制单元用于根据该两个逻辑控制端输入的第一数据电压以及第二数据电压选择将该四个预设电压中的一个预设电压通过所述电压输出端输出至像素电极；
    所述逻辑控制单元包括选择模块以及四个第三薄膜晶体管，所述选择模块具有所述两个逻辑控制端以及四个电平输出端；
    该四个第三薄膜晶体管的输入端分别与一所述电压输入端连接，该四个第三薄膜晶体管的输出端分别与该电压输出端连接，该四个第三薄膜晶体管的栅极分别与一所述电平输出端连接；所述选择模块根据所述第一数据电压以及第二数据电压选择该四个第三薄膜晶体管中的一个第三薄膜晶体管导通，其余三个所述第三薄膜晶体管关闭。
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