WO2018036559A1 - Jtag调试装置以及jtag调试方法 - Google Patents

Jtag调试装置以及jtag调试方法 Download PDF

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Publication number
WO2018036559A1
WO2018036559A1 PCT/CN2017/099073 CN2017099073W WO2018036559A1 WO 2018036559 A1 WO2018036559 A1 WO 2018036559A1 CN 2017099073 W CN2017099073 W CN 2017099073W WO 2018036559 A1 WO2018036559 A1 WO 2018036559A1
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WIPO (PCT)
Prior art keywords
signal
unit
jtag
debug
port
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PCT/CN2017/099073
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English (en)
French (fr)
Inventor
邓惠娟
马进
刘宇
汪浩
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华为技术有限公司
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Publication of WO2018036559A1 publication Critical patent/WO2018036559A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318561—Identification of the subpart
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31724—Test controller, e.g. BIST state machine
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318588—Security aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318597—JTAG or boundary scan test of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test

Definitions

  • the invention relates to the field of chip debugging, in particular to a JTAG debugging device and a JTAG debugging method.
  • SoC System-on-Chip
  • the debugging of the SoC chip integrated processor mainly adopts the JTAG (Joint Test Action Group) port.
  • the user can control the internal logic of the chip through the JTAG port to control the integrated processor in the SoC chip to execute the instructions desired by the user, access the internal registers of the CPU (Central Processing Unit) and the devices connected to the CPU bus.
  • JTAG Joint Test Action Group
  • the embodiment of the invention provides a JTAG debugging device and a JTAG debugging method, which can implement debugging of the internal logic of the chip in the case of a processor failure or no processor participation.
  • a JTAG debugging apparatus for debugging a unit to be debugged in a chip
  • the JTAG debugging apparatus comprising: a TAP controller configured to communicate with an external via an external JTAG port, and based on the The signal received by the JTAG port generates a debug signal including a unit address to be debugged and a debug command, the debug signal is a JTAG port signal based on a JTAG protocol, and a signal conversion unit configured to receive the debug output by the TAP controller Signaling and converting the debug signal from the JTAG port signal to a bus slave port signal capable of accessing a slave port of the unit to be debugged; and a bus configured to acquire a converted output of the signal conversion unit And transmitting, by the debug signal of the bus slave port signal, the debug command to the to-be-debuy unit indicated by the to-be-debuy unit address, based on the debug signal.
  • the bus since the debug signal is converted from the JTAG port signal to a bus slave port signal capable of accessing the slave port of the unit to be debugged, the bus uses the debug signal converted to the bus slave port signal to treat the debug unit. Read and write operations for debugging. Debugging of the internal logic of the chip without the participation of the processor is realized, thereby enabling debugging of the internal logic of the chip even if the processor fails.
  • the signal conversion unit transmits a signal received from the to-be-debug unit via the bus from the total A line slave port signal is converted to the JTAG port signal and output from the JTAG port via the TAP controller.
  • the signal conversion unit realizes bidirectional conversion between the JTAG port signal and the bus slave port signal, and smoothly realizes debugging of the JTAG debugging device to be debugged.
  • the bus may be an APB, an AXI, an AHB bus, etc.
  • the APB bus transmits a debug command to the slave port of the unit to be debugged indicated by the address of the unit to be debugged based on the AMBA protocol.
  • the slave port of the unit to be debugged is read and written.
  • the JTAG debugging apparatus further includes a non-volatile memory, a loading unit, and a security logic processing unit, the non-volatile memory storing security configuration information, the loading unit is configured to be powered when the chip is powered on The security configuration information stored by the non-volatile memory is automatically loaded into the security logic processing unit, and the security logic processing unit outputs an enable signal based on the loaded security configuration information to control whether to allow from the JTAG port.
  • the unit to be debugged is accessed via the TAP controller and the signal conversion unit. According to the above, it is possible to securely access the unit to be debugged without via a processor.
  • the security configuration information includes a security level, a password, and a chip identification number.
  • the security level includes a low security level, a medium security level, and a high security level
  • the security logic processing unit is configured to allow the user to pass through the JTAG port without restriction when the security level is a low security level. Accessing the unit to be debugged; when the security level is a medium security level, allowing the user to access the to-be-debuy unit through the JTAG port after correctly inputting the password; prohibiting the user when the security level is a high security level Accessing the unit to be debugged through the JTAG port.
  • the method further includes a first AND circuit, wherein an input terminal receives the enable signal, and another input terminal receives the debug signal in the JTAG port signal output by the TAP controller, the first A signal output from the circuit is transmitted to the signal conversion unit.
  • the method further includes a second AND circuit, wherein an input terminal receives the enable signal, and another input terminal receives a debug result signal output by the signal conversion unit and converted into the JTAG port signal, where A signal output from the circuit is transmitted to the TAP controller.
  • a JTAG debugging method for debugging a unit to be debugged in a chip, comprising: a signal received from a JTAG port, and generating a debugging signal including a unit address to be debugged and a debugging instruction based on the received signal,
  • the debug signal is a JTAG port based JTAG port signal; converting the debug signal from the JTAG port signal to a bus slave port signal capable of accessing a slave port of the unit to be debugged; and the bus based is converted to The bus transmits the debug command from the debug signal of the port signal to the to-be-debuy unit indicated by the address of the unit to be debugged.
  • the debug signal is converted from the JTAG port signal to a bus slave port signal capable of accessing the slave port of the unit to be debugged
  • the bus can be debugged by using a debug signal converted into a bus slave port signal.
  • the unit performs read and write operations to achieve debugging. Debugging of the internal logic of the chip without the participation of the processor is realized, thereby enabling debugging of the internal logic of the chip even if the processor fails.
  • a signal received from the to-be-debug unit via the bus is also converted from the bus port signal to the JTAG port signal and output to the JTAG port.
  • the signal conversion unit realizes bidirectional conversion between the JTAG port signal and the bus slave port signal, and the debugging of the unit to be debugged is smoothly realized.
  • the security configuration information is automatically loaded when the chip is powered on, and an enable signal is output based on the security configuration information to control whether the unit to be debugged is allowed to be accessed from the JTAG port.
  • the security configuration information includes a security level, a password, and a chip identification number.
  • the security level when the security level is a low security level, the user is allowed to access the unit to be debugged through the JTAG port without restriction; when the security level is a medium security level, the user is allowed to pass the password after correctly inputting the password.
  • the JTAG port accesses the to-be-debugged unit; when the security level is a high security level, the user is prohibited from accessing the to-be-debugged unit through the JTAG port.
  • a debug signal including a unit address to be debugged and a debug instruction is converted from a JATG port signal to a bus slave port signal, and the debug command is transmitted to the address of the unit to be debugged through a bus.
  • the indicated unit to be debugged realizes debugging of the internal logic of the chip without the participation of the processor, thereby enabling debugging of the internal logic of the chip even if the processor fails.
  • FIG. 1 is a schematic block diagram of a JTAG debugging apparatus according to an embodiment of the present invention
  • FIG. 2 is a schematic block diagram of a JTAG debugging apparatus according to still another embodiment of the present invention.
  • FIG. 3 is a flowchart of a JTAG debugging method according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a JTAG debugging method according to still another embodiment of the present invention. .
  • a system on chip (SoC) 100 includes a JTAG debug device 1 and a unit to be debugged 3.
  • SoC system on chip
  • the user and the JTAG debug device 1 perform signal input and output via the JTAG port 2, and the JTAG debug device 1 communicates with the unit to be debugged 3 to debug the debug unit 3.
  • the JTAG port 2 includes a clock input line TCK, a data input line TDI, a data output line TDO, a mode selection line TMS, and a reset line TRST.
  • the debug data is input from the JTAG port 2 through the data input line TDI.
  • the debug result data is output from the JTAG port 2 through the data output line TDO.
  • the mode select line TMS is used to set the JTAG port 2 to be in a particular mode.
  • the reset line TRST is optional and active low.
  • the JTAG debug device 1 shown in FIG. 1 is used to debug the unit to be debugged in the chip.
  • the JTAG debug device 1 includes a TAP controller 11 configured to communicate with the outside via an external JTAG port 2, and based on the slave JTAG.
  • the signal received by the port 2 generates a debug signal including the address of the unit to be debugged and the debug command, and the debug signal is a JTAG port signal based on the JTAG protocol;
  • the signal conversion unit 12 is configured to receive the debug signal output by the TAP controller 11 and debug The signal is converted from a JTAG port signal to a bus slave port signal accessible to the slave port of the debug unit;
  • the bus 19 is configured to acquire a debug signal output by the signal conversion unit 12 that is converted to a bus slave port signal and debug
  • the instruction is transmitted to the unit 3 to be debugged as indicated by the address of the unit to be debugged.
  • a TAP (Test Access Port) controller 11 is disposed inside the chip 100 according to the JTAG protocol, and inputs a signal from the JTAG port 2.
  • the TAP controller 11 selects a password input, a status/data output, accesses or activates a unit to be debugged, and the like according to a signal input from the JTAG port 2.
  • the TAP controller 11 generates a debug signal containing the unit address to be debugged and the debug command based on the signal received from the JTAG port 2, the debug signal being a JTAG port based JTAG port signal.
  • the unit to be debugged indicates the unit to be accessed, and the debugging instruction is used to refer to The operations performed on the unit to be accessed, such as a write command or a read command.
  • the TAP controller 11 sets the debug mode based on the signal input from the JTAG port 2, and controls the debugging of the unit 3 to be debugged.
  • the signal conversion unit 12 acquires a debug signal from the TAP controller 11 and converts the debug signal from the JTAG port signal into a bus slave port signal capable of accessing the slave port of the unit to be debugged.
  • the signal conversion unit 12 is also capable of converting a received bus signal, which will be described later, from a port signal to a JTAG port signal, thereby mutually converting the JTAG port signal and the bus slave port signal.
  • the signal conversion unit 12 converts the debug signal input from the TAP controller 11 for the JTAG port signal into a bus slave port signal.
  • the signal conversion unit 12 converts the signal for the bus slave port signal output from the unit 3 to be debugged which is being debugged into a JTAG port signal, and outputs it to the TAP controller 11, and outputs it to the outside via the JTAG port 2.
  • the JTAG port signal is a signal input to or output from the TAP controller. It is a set of bidirectional signals that are input from the JTAG port or output to the JTAG port and are signals that can be transmitted by the JTAG port based on the JTAG port protocol.
  • the bus 19 acquires the debug signal output from the signal conversion unit 12 and is converted into a bus slave port signal, and transmits the debug command to the unit 3 to be debugged indicated by the address of the unit to be debugged. After the debug signal is input to the bus 19, the bus 19 selects the unit to be debugged 3 according to the address of the unit to be debugged included in the debug signal, and transmits a debug signal to the bus slave port connected to the bus of the selected unit to be debugged.
  • debugging instructions thereby implementing debugging of the unit to be debugged 3
  • the debugging instruction is a write instruction
  • the bus is to be debugged by the instruction of the unit to be debugged
  • the write command is input from the port to realize the write operation of the unit 3 to be debugged.
  • the debug command is a read operation, and the read command is input from the bus slave port of the unit to be debugged indicated by the debug unit address to implement the read operation of the debug unit 3.
  • the bus slave port signal is a set of bidirectional signals that are signals that are accessible to the slave port of the unit to be debugged.
  • the unit to be debugged connected to the bus 19 is provided with a bus slave port (not shown), and by controlling the bus slave port, the debug unit 3 can be debugged. In other words, access to the internal logic of the debug unit 3 can only be achieved if the signal of the bus slave port is controlled.
  • the bus may be, for example, an APB bus, an AHB bus, an AXI bus or the like that can access the slave port based on the AMBA protocol, but the bus is not particularly limited as long as it can access the slave port of the debug unit.
  • a general-purpose timer will be described as a specific example of the unit to be debugged.
  • General-purpose timers generally have an AMBA APB bus (peripheral bus) slave port in addition to signals such as clock, reset, and interrupt.
  • AMBA APB bus peripheral bus
  • the APB bus selects a debug signal converted by the signal conversion unit based on the AMBA protocol by converting the debug signal generated by the TAP controller including the unit address to be debugged and the debug command from the JTAG port signal to the bus slave port signal via the signal conversion unit.
  • the general-purpose timer indicated by the address of the unit to be debugged outputs the debug command to the bus slave port of the general-purpose timer connected to the APB bus, and can access the bus slave port of the general-purpose timer, thereby realizing the internal reading of the general-purpose timer. Write operations to achieve debugging.
  • the debugging signal is converted from the JTAG port signal to be able to be adjusted
  • the bus slave port of the test unit accesses the port signal, and the bus uses the debug signal converted to the bus slave port signal to debug the debug unit. Therefore, it is not necessary to convert the JTAG port signal into an instruction of the control processor, but directly converts it into a bus slave port signal, thereby implementing debugging of the unit connected to the bus through the JTAG debug device without passing through the SoC system. processor. Thus, even if the processor fails or the processor does not participate, it is possible to debug the unit connected to the SoC inside the bus.
  • FIG. 2 is a schematic block diagram showing a JTAG debugging apparatus according to still another embodiment of the present invention.
  • Embodiment 2 differs from Embodiment 1 in that it also has a security protection unit.
  • FIG. 2 the same portions as those in the first embodiment are denoted by the same reference numerals, and the detailed description thereof will be omitted.
  • the second embodiment will be described below.
  • the system chip 1000 includes a JTAG debug device 10 and a unit to be debugged 3.
  • the JTAG debug device 10 includes a TAP controller 11, signal conversion units 12, 18, a non-volatile memory 13, a load circuit 14, a safety logic processing unit 15, and two two-input AND gates 16, 17.
  • the non-volatile memory 13, the loading circuit 14, the safety logic processing unit 15, and the two two-input and gates 16, 17 constitute a security protection unit for the unit 3 to be debugged, which can prevent unauthorized persons from being debugged.
  • the unit performs malicious access, steals or changes the information inside the unit to be debugged.
  • the nonvolatile memory 13 is a storage medium that stores security configuration information.
  • the security configuration information may include a security level, a password, and a chip identification number of the unit to be debugged.
  • the security level reflects the access restriction mode to be debugged unit 3, and is divided into low security level: open mode, and the user can access the unit to be debugged through JTAG port 2 without restriction; the medium security level is password protection mode. The user can access the unit to be debugged through JTAG port 2 only after entering the correct password; the high security level is the prohibition mode, and the user cannot access the unit to be debugged through JTAG port 2 under any circumstances.
  • the password corresponds to the chip identification number, and each chip has a unique chip identification number. Since each chip has a unique password, the chip identification number can be associated with the password, so that the password can be conveniently managed.
  • the security level and the chip identification number are publicly available information. In any case, the user can obtain the security level of the unit to be debugged and the chip identification number through the JTAG port, so that the user can take appropriate security measures to access the unit to be debugged.
  • a legitimate user can rewrite the security level in the non-volatile memory 13 and is limited to only a low security level to a high security level, and is irreversible; in addition, even a legitimate user is not allowed to modify the chip identification number and password. .
  • the non-volatile memory 13 may be an OTP (One Time Programmable) memory, and cannot be configured with any security information in the OTP memory due to the one-time programmable nature of the OTP memory. to modify.
  • OTP One Time Programmable
  • the non-volatile memory may be in various forms of memory, but it is only required that the security configuration information cannot be arbitrarily modified.
  • the load circuit 14 automatically reads the security configuration information from the non-volatile memory 13 when the chip is powered up, and The security configuration information is configured into the security logic processing unit 15 without the intervention of software, ie, no processor involvement.
  • the security logic processing unit 15 records the security configuration information loaded by the loading circuit 14.
  • the secure logic processing unit 15 includes a security level register, a password register, and a chip identification number register.
  • the above-mentioned register is provided in the secure logic processing unit 15 for the signal conversion unit 12 to read the chip identification number, write the password, and read the judgment result indicating whether the input password is correct.
  • the safety logic processing unit 15 determines and outputs an enable signal enable based on the safety configuration information from the loading circuit 14 and the input of the signal conversion unit 18, which enables or prohibits debugging from the JTAG port 2 to the debug unit 3.
  • the security level is a low security level
  • the output enable signal enable is "1" (active level), and the access path to the debug unit 3 from the JTAG port 2 is turned on.
  • the security level is the disable mode
  • the output enable signal enable is "0" (invalid level)
  • the access path from the JTAG port 2 to the debug unit 3 is turned off.
  • the security level is the password protection mode, it is determined whether the input password is consistent with the loaded password stored by the security logic processing unit 15.
  • the output enable signal enable is "1", and the debug unit 3 is turned on from the JTAG port 2.
  • the security logic processing unit 15 can be accessed through the JTAG port 2, the TAP controller 11, and the signal conversion unit 18 at any security level, without the enable signal enable. Impact. Therefore, the chip identification number register in the secure logic processing unit 15 can be read through the JTAG port 2 without restriction at any security level, and the password register in the secure logic processing unit 15 can also be configured. The chip identification number register is read only, the password register is write only, and the security logic processing unit 15 does not contain user sensitive information, effectively preventing information from leaking from the JTAG port 2 through the secure logic processing unit 15.
  • the signal conversion unit 18 is the same as the signal conversion unit 12 for performing conversion between the JTAG port signal and the bus slave port signal, and will not be described in detail herein.
  • the signal conversion unit 12 between the TAP controller 11 and the unit to be debugged 3.
  • An input terminal of the two-input and circuit 16 receives the enable signal enable, the other input terminal receives the debug data input signal TDI in the JTAG port signal output by the TAP controller 11, and the signal output from the two-input and circuit 16 is transmitted to the signal conversion unit. 12.
  • the two-input AND circuit 16 Through the two-input AND circuit 16, the input to the debug unit 3 via the JTAG port 2 can be limited.
  • the input terminal of the two-input and circuit gate 17 receives the enable signal enable, the other input terminal receives the debug result output signal TDO in the JTAG port signal output from the signal conversion unit 12, and the signal output from the two input and circuit 17 is transmitted to the TAP control. Device 11.
  • the two-input AND gate 17 it is possible to limit the data of the unit to be debugged 3 to be output via the JTAG port.
  • the security configuration information stored in the nonvolatile memory 13 including the security level, the password, and the chip identification number is loaded into the security logic processing unit 15 through the loading circuit 14, and the security level is stored to the security.
  • the level register, the chip identification number is stored in the chip identification number register.
  • the user can send the chip identification number from the security logic processing unit 15 through the JTAG port 2, the TAP controller 11, and the signal conversion unit 18.
  • the memory reads the chip identification number.
  • the security logic processing unit 15 determines the security level. In the case of a low security level, the safety logic processing unit 15 outputs the enable signal enable to "1", and the user can directly debug the debug unit 3 via the TAP controller 11, the two input and the circuits 16, 17 and the signal conversion unit 12. .
  • the security logic processing unit 15 determines whether the password input by the user into the password register via the JTAG port 2 is consistent with the stored password. In the case of a match, the output enable signal enable is "1". The user can debug the debug unit 3 via the TAP controller 11, the two input and circuits 16, 17 and the signal conversion unit 12. In the case of inconsistency, the output enable signal enable is "0", and the user cannot debug the debug unit 3 via the TAP controller 11, the two-input and circuits 16, 17 and the signal conversion unit 12.
  • the enable signal enable is not particularly limited as long as it has a signal capable of prohibiting or allowing debugging.
  • the safety logic processing unit 15 outputs the enable signal enable to "0", and the user cannot debug the unit 3 to be debugged via the TAP controller 11 and the input circuits 16 and 17 and the signal conversion unit 12.
  • the signal conversion unit 12 converts the JTAG port signal into a bus slave port signal, and the bus slave port signal is a bidirectional signal.
  • the unit to be debugged can be accessed by converting to the bus slave port signal, and the input signal for debugging is input.
  • the status signal or the like of the unit to be debugged 3 can be output as a bus slave port signal to the signal conversion unit 12, and then the bus signal is converted from the port signal to the JTAG port signal via the signal conversion unit 12, and output via the TAP controller 11.
  • only one signal conversion unit can be provided.
  • the signal conversion unit is provided with two, but it is not necessary to set two. Since the unit to be debugged 3 and the secure logic processing unit 15 can be distinguished by different addresses, the signal conversion unit can set only one, substantially different access address, and can determine which of the debug unit 3 and the secure logical processing unit 15 is to be performed. access.
  • multiple units to be debugged there may be multiple units to be debugged, and multiple units to be debugged may also be distinguished by different addresses.
  • the security protection unit By setting the security protection unit to the JTAG debugging apparatus 10 as described above, it is possible to prevent malicious access to the external debugging unit 3 and prevent information from being stolen or changed, thereby enabling secure debugging of the unit 3 to be debugged in the chip.
  • JTAG debugging device according to the embodiment of the present invention has been described above. The following describes the workflow of JTAG debugging.
  • FIG. 3 is a flow chart showing a JTAG debugging method according to an embodiment of the present invention. Next, the workflow of JTAG debugging will be described with reference to FIG. 3.
  • a JTAG debugging method for debugging a unit to be debugged in a chip comprising: step S11, receiving a signal from a JTAG port, and generating a debugging signal including a unit address to be debugged and a debugging instruction based on the received signal, the debugging The signal is a JTAG port signal based on the JTAG protocol; in step S12, the debug signal is converted from the JTAG port signal to a bus slave port signal readable by the slave port of the unit to be debugged; and in step S13, the bus is converted based on Transmitting the debug command to the debug signal indicated by the bus signal to be debugged by the debug signal of the bus slave port signal.
  • the TAP controller receives a signal from an external JTAG port, and generates a debug signal including a unit address to be debugged and a debug command based on the received signal.
  • the signal conversion unit converts the debug signal received from the TAP controller from the JTAG port signal to the bus slave port signal.
  • the bus is an APB bus
  • the APB bus transmits the debug command to the unit to be debugged indicated by the address of the unit to be debugged based on the AMBA protocol.
  • the signal conversion unit also converts a signal received from the to-be-debug unit via a bus from a bus signal to a JTAG port signal and outputs from the JTAG port via the TAP controller. In addition, the signal conversion unit further converts the bus signal received from the unit to be debugged into a JTAG port signal, and outputs the signal to the JTAG port.
  • FIG. 4 is a flow chart showing a JTAG debugging method according to still another embodiment of the present invention. Based on the debugging method shown in FIG. 3, the following operations are also performed.
  • the security configuration information is pre-burned into the non-volatile memory.
  • step S21 when the chip is powered on, the security configuration information in the non-volatile memory is loaded into the secure logic processing unit.
  • the security logic processing unit determines the security level. In the case where the security level is the low security level, as shown in step S23, the security logic processing unit outputs the enable signal "1". In the case that the security level is the medium security level, as shown in step S24, it is determined whether the input password is consistent with the password in the security configuration information. In the case of consistency, as shown in step S23, the security logic processing unit outputs an enable signal.
  • the safety logic processing unit outputs an enable signal "0".
  • the security level is a high security level
  • the secure logic processing unit outputs an enable signal "0".
  • the enable signal is "1”
  • the user is allowed to access the debug unit through the JTAG port.
  • the enable signal is "0" the user is not allowed to debug the debug unit through the JTAG port.
  • the user can read the chip identification number register in the secure logic processing unit through the JTAG port.
  • the user writes the password to the password register in the secure logic processing unit via the JTAG port according to the chip identification number.
  • the password register is compared to the password loaded from the non-volatile memory.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

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Abstract

一种JTAG调制装置以及JTAG调试方法，JTAG调试装置(1)用于调试芯片中的待调试单元(3)，JTAG调试装置(1)包括：TAP控制器(11)，被配置为经由外部的JTAG端口(2)与外部进行通信，并基于从JTAG端口(2)接收的信号生成包含待调试单元地址以及调试指令的调试信号，调试信号是基于JTAG协议的JTAG端口信号；信号转换单元(12)，被配置为接收TAP控制器(11)输出的调试信号，并将调试信号从JTAG端口信号转换成能够对所述待调试单元的从端口进行访问的总线从端口信号；以及总线(19)，被配置为获取信号转换单元(12)输出的被转换为总线从端口信号的调试信号，并基于调试信号将调试指令传输给待调试单元地址所指示的待调试单元(3)。上述JTAG装置及调试方法能够在处理器发生故障或者没有处理器参与的情况下实现对芯片内部逻辑的调试。

Description

JTAG调试装置以及JTAG调试方法 技术领域
本发明涉及芯片调试领域，尤其涉及JTAG调试装置以及JTAG调试方法。
背景技术
SoC(System-on-Chip，片上系统)的调试目的主要是便于芯片的应用开发或故障跟踪分析。针对SoC芯片集成的处理器的调试主要采用JTAG(Joint Test Action Group，联合测试工作组)端口。用户可以通过JTAG端口控制SoC芯片中集成的处理器执行用户期望的指令，访问CPU(中央处理器)的内部寄存器和连接到CPU总线上的设备，从而实现对芯片内部逻辑的访问。
另一方面，JTAG端口如果管理不当，会严重威胁芯片内部的数据安全。以往在JTAG端口与被待调试单元之间增加安全逻辑处理模块的方法。可以满足用户在芯片不同发行阶段的启闭JTAG端口的需求。其缺点是芯片产品化之后，如需进行芯片故障的跟踪分析，重新打开JTAG端口的调试功能时，需要通过软件配置芯片内部的寄存器，输入正确的密码才能实现。如果芯片故障是处理器导致的，处理器自身无法启动时，软件就无法运行，密码也就无从输入，无法实现JTAG端口重新打开的目的。
在实现本发明的过程中，发明人发现现有技术中至少存在以下问题：如何在没有处理器参与的情况下实现对芯片内部逻辑的调试。
发明内容
本发明实施例提供了一种JTAG调试装置以及JTAG调试方法，能够在处理器发生故障或没有处理器参与的情况下实现对芯片内部逻辑的调试。
第一方面，提供了一种JTAG调试装置，用于调试芯片中的待调试单元，所述JTAG调试装置包括：TAP控制器，被配置为经由外部的JTAG端口与外部进行通信，并基于从所述JTAG端口接收的信号生成包含待调试单元地址以及调试指令的调试信号，所述调试信号是基于JTAG协议的JTAG端口信号；信号转换单元，被配置为接收所述TAP控制器输出的所述调试信号，并将所述调试信号从所述JTAG端口信号转换成能够对所述待调试单元的从端口进行访问的总线从端口信号；以及总线，被配置为获取所述信号转换单元输出的被转换为所述总线从端口信号的所述调试信号，并基于所述调试信号将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元。
根据上述JTAG调试装置，由于将调试信号从JTAG端口信号转换为能够对所述待调试单元的从端口进行访问的总线从端口信号，总线利用被转换为总线从端口信号的调试信号来对待调试单元进行读写操作，从而实现调试。实现了在没有处理器参与的情况下对芯片内部逻辑的调试，由此即使处理器发生故障也能够执行对芯片内部逻辑的调试。
可选地，所述信号转换单元将经由所述总线从所述待调试单元接收的信号从所述总 线从端口信号转换成所述JTAG端口信号，并经由所述TAP控制器从所述JTAG端口输出。根据上述JTAG调试装置，通过信号转换单元实现JTAG端口信号与总线从端口信号的双向转换，顺利实现JTAG调试装置对待调试单元的调试。
可选地，总线可以是APB、AXI、AHB总线等，例如，在总线是APB总线的情况下，APB总线基于AMBA协议对将调试指令传输给待调试单元地址所指示的待调试单元的从端口，从而实现对待调试单元的从端口进行读写操作。
可选地，JTAG调试装置还包括非易失性存储器、装载单元及安全逻辑处理单元，所述非易失性存储器存储有安全配置信息，所述装载单元在所述芯片上电时将所述非易失性存储器所存储的安全配置信息自动装载到所述安全逻辑处理单元中，所述安全逻辑处理单元基于装载的所述安全配置信息输出使能信号，以控制是否允许从所述JTAG端口经由所述TAP控制器、所述信号转换单元访问所述待调试单元。根据上述，能够不经由处理器实现安全地对所述待调试单元进行访问。
可选地，所述安全配置信息包括安全等级、密码以及芯片标识号。
可选地，所述安全等级包括低安全等级、中安全等级及高安全等级，所述安全逻辑处理单元被配置为，在所述安全等级是低安全等级时，允许用户无限制地通过JTAG端口访问所述待调试单元；在所述安全等级是中安全等级时，允许用户在正确输入密码后通过所述JTAG端口访问所述待调试单元；在所述安全等级是高安全等级时，禁止用户通过所述JTAG端口访问所述待调试单元。
可选地，还包括第一与电路，其一输入端子接收所述使能信号，另一输入端子接收所述TAP控制器输出的所述JTAG端口信号中的所述调试信号，所述第一与电路输出的信号传输至所述信号转换单元。
可选地，还包括第二与电路，其一输入端子接收所述使能信号，另一输入端子接收所述信号转换单元输出的被转换为所述JTAG端口信号的调试结果信号，所述第二与电路输出的信号传输至所述TAP控制器。
第二方面，提供了一种JTAG调试方法，用于调试芯片中的待调试单元，包括：从JTAG端口接收的信号，并基于所接收的信号生成包含待调试单元地址以及调试指令的调试信号，所述调试信号是基于JTAG协议的JTAG端口信号；将所述调试信号从所述JTAG端口信号转换成能够对所述待调试单元的从端口进行访问的总线从端口信号；以及总线基于被转换为所述总线从端口信号的所述调试信号将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元。
根据上述JTAG调试方法，由于将调试信号从JTAG端口信号转换为能够对所述待调试单元的从端口进行访问的总线从端口信号，总线能利用被转换为总线从端口信号的调试信号来对待调试单元进行读写操作，从而实现调试。实现了在没有处理器参与的情况下对芯片内部逻辑的调试，由此即使处理器发生故障也能够执行对芯片内部逻辑的调试。
可选地，还将经由总线从所述待调试单元接收的信号从所述总线从端口信号转换成所述JTAG端口信号，并向所述JTAG端口输出。根据上述JTAG调试方法，通过信号转换单元实现JTAG端口信号与总线从端口信号的双向转换，顺利实现对待调试单元的调试。
可选地，在芯片上电时自动装载安全配置信息，并基于安全配置信息输出使能信号，以控制是否允许从所述JTAG端口访问所述待调试单元。
可选地，所述安全配置信息包括安全等级、密码以及芯片标识号。
可选地，在所述安全等级是低安全等级时，允许用户无限制地通过JTAG端口访问所述待调试单元；在所述安全等级是中安全等级时，允许用户在正确输入密码后通过所述JTAG端口访问所述待调试单元；在所述安全等级是高安全等级时，禁止用户通过所述JTAG端口访问所述待调试单元。
根据本发明实施例的上述技术方案，将包含待调试单元地址以及调试指令的调试信号从JATG端口信号转换为总线从端口信号，并通过总线将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元，实现了在没有处理器参与的情况下实现对芯片内部逻辑的调试，由此即使处理器发生故障也能够执行对芯片内部逻辑的调试。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施例涉及的JTAG调试装置的示意框图；
图2是本发明又一实施例涉及的JTAG调试装置的示意框图；
图3是本发明一实施例涉及的JTAG调试方法的流程图；
图4是本发明又一实施例涉及的JTAG调试方法的流程图。。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面将详细描述本发明的各个方面的特征和示例性实施例。在下面的详细描述中，提出了许多具体细节，以便提供对本发明的全面理解。但是，对于本领域技术人员来说，很明显本发明可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的 描述仅仅是为了通过示出本发明的示例来提供对本发明的更好的理解。本发明决不限于下面所提出的任何具体配置，而是在不脱离本发明精神的前提下覆盖了单元或步骤的任何修改、替换和改进。在附图和下面的描述中，没有示出公知的结构和技术，以便避免对本发明造成不必要的模糊。
现在，参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式，相反，提供这些实施方式使得本发明更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在附图中，相同的附图标记表示相同或类似的部分或单元，因而将适当省略对它们的重复描述
此外，所描述的特征或结构可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本发明实施例的充分理解。然而，本领域普通技术人员将意识到，可以实践本发明的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的单元或方法等。在其它情况下，不详细示出或描述公知结构或者操作以避免模糊本发明的主要技术创意。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
图1是本发明一实施例涉及的JTAG调试装置的示意框图。系统芯片(System on Chip，SoC)100包括JTAG调试装置1以及待调试单元3。用户与JTAG调试装置1之间经由JTAG端口2进行信号的输入输出，JTAG调试装置1与待调试单元3之间进行通信，从而对待调试单元3进行调试。
JTAG端口2包括：时钟输入线TCK、数据输入线TDI、数据输出线TDO、模式选择线TMS以及复位线TRST。调试用数据通过数据输入线TDI从JTAG端口2输入。调试结果数据通过数据输出线TDO从JTAG端口2输出。模式选择线TMS用来设置JTAG端口2处于某种特定模式。复位线TRST为可选的，低电平有效。
图1所示的JTAG调试装置1，用于调试芯片中的待调试单元3，JTAG调试装置1包括：TAP控制器11，被配置为经由外部的JTAG端口2与外部进行通信，并基于从JTAG端口2接收的信号生成包含待调试单元地址以及调试指令的调试信号，调试信号是基于JTAG协议的JTAG端口信号；信号转换单元12，被配置为接收TAP控制器11输出的调试信号，并将调试信号从JTAG端口信号转换成能够对待调试单元的从端口进行访问的总线从端口信号；以及总线19，被配置为获取信号转换单元12输出的被转换为总线从端口信号的调试信号，并将调试指令传输给待调试单元地址所指示的待调试单元3。以下来详细说明。
TAP(Test Access Port，测试访问端口)控制器11根据JTAG协议配置在芯片100内部，从JTAG端口2输入信号。TAP控制器11根据从JTAG端口2输入的信号选择密码输入、状态/数据输出、访问或启动待调试单元等。TAP控制器11基于从JTAG端口2接收的信号生成包含待调试单元地址以及调试指令的调试信号，所述调试信号是基于JTAG协议的JTAG端口信号。所述待调试单元地址指示要访问的单元，调试指令用于指 示对要访问的单元所进行的操作，例如是写指令或者读指令等。TAP控制器11基于从JTAG端口2输入的信号设置调试模式，控制对待调试单元3的调试。
信号转换单元12从TAP控制器11获取调试信号，并将调试信号从JTAG端口信号转换成能够对所述待调试单元的从端口进行访问的总线从端口信号。另一方面，信号转换单元12也能够将后述的接收的总线从端口信号转换成JTAG端口信号，实现对JTAG端口信号和总线从端口信号进行相互转换。信号转换单元12将从TAP控制器11输入的为JTAG端口信号的调试信号转换成总线从端口信号。另一方面，信号转换单元12将从进行调试的待调试单元3输出的为总线从端口信号的信号转换成JTAG端口信号，并输出给TAP控制器11，经由JTAG端口2向外部输出。
这里，JTAG端口信号是输入到TAP控制器或从TAP控制器输出的信号，是一组双向信号，从JTAG端口输入或者向JTAG端口输出，是基于JTAG端口协议的JTAG端口能够传输的信号。
总线19获取信号转换单元12输出的被转换为总线从端口信号的调试信号，并将调试指令传输给待调试单元地址所指示的待调试单元3。调试信号被输入到总线19上后，总线19按照调试信号中所包含的待调试单元地址选择待调试单元3，并对所选择的待调试单元的、与总线连接的总线从端口传送调试信号中所包含的调试指令，从而实现对待调试单元3的调试，例如调试指令是写指令，则对待调试单元地址所指示的待调试单元3的总线从端口输入写指令，实现对待调试单元3的写操作；或者调试指令是读操作，则对待调试单元地址所指示的待调试单元3的总线从端口输入读指令，实现对待调试单元3的读操作。
总线从端口信号是一组双向信号，是能够对所述待调试单元的从端口进行访问的的信号。连接到总线19上的待调试单元3具备总线从端口(图中未示出)，通过控制这个总线从端口，可以对待调试单元3进行调试。换而言之，仅在控制总线从端口的信号的情况下，才能实现对待调试单元3的内部逻辑的访问。总线例如可以是APB总线、AHB总线、AXI总线等能够基于AMBA协议对从端口进行访问的总线，但总线只要是能够对待调试单元的从端口进行访问的总线即可，不特别限定。
以通用定时器作为待调试单元的具体的一例来进行说明。通用定时器一般来说除了时钟、复位、中断等信号，还有一个AMBA APB总线(外围总线)从端口。通过控制这个APB总线从端口，可以设置通用定时器的计数初值、计数模式(单次计数还是周期计数等)或者读取当前计数值以及中断状态。通过经由信号转换单元将TAP控制器生成的包含待调试单元地址以及调试指令的调试信号从JTAG端口信号转换为总线从端口信号，APB总线基于AMBA协议选择被信号转换单元转换后的调试信号所包含的待调试单元地址指示的通用定时器，将调试指令输出到通用定时器的与APB总线连接的总线从端口，能够对通用定时器的总线从端口进行访问，从而实现对通用定时器内部的读写操作，实现调试。
根据上述的JTAG调试装置，由于将调试信号从JTAG端口信号转换为能够对待调 试单元的从端口进行访问的总线从端口信号，总线利用被转换为总线从端口信号的调试信号来对待调试单元进行调试。因此不需要将JTAG端口信号转换为控制处理器的指令，而是直接转换为总线从端口信号，因此实现了通过JTAG调试装置对连接到总线上的单元的调试，而不需要通过SoC系统中的处理器。从而即使在处理器发生故障或者处理器不参与的情况下也能够对SoC内部的连接在总线上的单元进行调试。
可选地，作为另一实施例，图2是示出本发明又一实施例涉及的JTAG调试装置的示意框图。实施例2相对于实施例1的不同点在于，还具有安全保护单元。在图2中，对与实施例1相同的部分标注相同的标号，并省略其详细说明。下面对实施例2进行说明。
系统芯片1000包含JTAG调试装置10和待调试单元3。JTAG调试装置10包括TAP控制器11、信号转换单元12、18、非易失性存储器13、装载电路14、安全逻辑处理单元15、两个二输入与门16、17。
如图2所示，非易失性存储器13、装载电路14、安全逻辑处理单元15、两个二输入与门16、17构成对待调试单元3的安全保护单元，能够防止无权限的人对待调试单元进行恶意访问、盗取或更改待调试单元内部的信息。
非易失性存储器13是存储安全配置信息的存储介质。该安全配置信息可包括待调试单元的安全等级、密码和芯片标识号。
这里，安全等级反映对待调试单元3的访问限制模式，由低到高分为：低安全等级即开放模式，用户可以无限制通过JTAG端口2访问待调试单元3；中安全等级即密码保护模式，用户只有在输入正确的密码后才能通过JTAG端口2访问待调试单元3；高安全等级即禁止模式，用户在任何情况下都不能通过JTAG端口2访问待调试单元3。
密码与芯片标识号一一对应，每个芯片有唯一的芯片标识号，由于每个芯片拥有唯一的密码，可将芯片标识号与密码关联起来，因此可以方便地实现密码的个性化管理。
安全等级和芯片标识号是可以公开的信息，用户在任何情况下都可以通过JTAG端口获取待调试单元的安全等级以及芯片标识号，以实现用户采取适当的安全措施访问待调试单元。
合法用户可以对非易失性存储器13中的安全等级进行改写，并且限制为只能从低安全等级修改到高安全等级，并且不可逆转；另外即使是合法用户也不允许修改芯片标识号以及密码。
作为一可选的实施例，非易失性存储器13可以是OTP(One Time Programmable，一次性可编程)存储器，由于OTP存储器的一次性可编程特性，因此无法对OTP存储器中的任何安全配置信息进行修改。另外，非易失性存储器可以是多种形式的存储器，但只要保证安全配置信息不能被任意修改即可。
装载电路14在芯片上电时，自动从非易失性存储器13中读取安全配置信息，并将 安全配置信息配置到安全逻辑处理单元15中，不需要软件的干预，即不需要处理器参与。
在装载电路14将安全配置信息自动配置到安全逻辑处理单元15中的情况下，安全逻辑处理单元15记录装载电路14所装载的安全配置信息。安全逻辑处理单元15包含安全等级寄存器、密码寄存器和芯片标识号寄存器。
安全逻辑处理单元15中设置有上述寄存器，以供信号转换单元12读取芯片标识号、写入密码、读取表示输入密码是否正确的判断结果。
安全逻辑处理单元15根据来自装载电路14的安全配置信息和信号转换单元18的输入，判断并输出使能信号enable，所述使能信号enable允许或者禁止从JTAG端口2对待调试单元3进行调试。在安全等级为低安全等级时，输出使能信号enable为“1”(有效电平)，开通对从JTAG端口2对待调试单元3的访问通路。在安全等级为禁止模式时，输出使能信号enable为“0”(无效电平)，关闭从JTAG端口2对待调试单元3的访问通路。在安全等级为密码保护模式时，判断输入的密码与安全逻辑处理单元15存储的被装载的密码是否一致，若一致则输出使能信号enable为“1”，开通从JTAG端口2对待调试单元3的访问通路；若不一致则输出使能信号enable为“0”，关闭从JTAG端口2对待调试单元3的访问通路。
在从JTAG端口2到安全逻辑处理单元15的通路上，在任何安全等级下，均可通过JTAG端口2、TAP控制器11、信号转换单元18访问安全逻辑处理单元15，不受使能信号enable的影响。因此在任何安全等级下都可以无限制地通过JTAG端口2对安全逻辑处理单元15中的芯片标识号寄存器进行读取，也可以对安全逻辑处理单元15中的密码寄存器进行配置。芯片标识号寄存器为只读，密码寄存器为只写，并且安全逻辑处理单元15不包含用户敏感信息，有效防止了信息通过安全逻辑处理单元15从JTAG端口2泄露。这里信号转换单元18与信号转换单元12是相同的，用于进行JTAG端口信号与总线从端口信号之间的转换，这里不再详细说明。
在TAP控制器11与待调试单元3之间具有信号转换单元12。在TAP控制器11与信号转换单元12之间具有二输入与电路16。二输入与电路16的一输入端子接收使能信号enable，另一输入端子接收TAP控制器11输出的JTAG端口信号中的调试数据输入信号TDI，二输入与电路16输出的信号传输至信号转换单元12。通过该二输入与电路16，能够限制经由JTAG端口2对待调试单元3的输入。
在信号转换单元12与TAP控制器11之间具有二输入与电路17。二输入与电路门17的一输入端子接收使能信号enable，另一输入端子接收信号转换单元12输出的JTAG端口信号中的调试结果输出信号TDO，二输入与电路17输出的信号传输至TAP控制器11。通过该二输入与门17，能够限制待调试单元3的数据经由JTAG端口输出。
具体地，当芯片上电后，非易失性存储器13存储的包含安全等级、密码以及芯片标识号的安全配置信息通过装载电路14被装载到安全逻辑处理单元15中，安全等级被存储到安全等级寄存器，芯片标识号被存储到芯片标识号寄存器中。用户可以通过JTAG端口2、TAP控制器11以及信号转换单元18从安全逻辑处理单元15中的芯片标识号寄 存器读取芯片标识号。安全逻辑处理单元15判断安全等级。在低安全等级的情况下，安全逻辑处理单元15输出使能信号enable为“1”，用户可以直接经由TAP控制器11、二输入与电路16、17以及信号转换单元12对待调试单元3进行调试。在中安全等级的情况下，安全逻辑处理单元15判断用户经由JTAG端口2输入到密码寄存器中的密码是否与所存储的密码一致，在一致的情况下，输出使能信号enable为“1”，用户可以经由TAP控制器11、二输入与电路16、17以及信号转换单元12对待调试单元3进行调试。在不一致的情况下，输出使能信号enable为“0”，用户无法经由TAP控制器11、二输入与电路16、17以及信号转换单元12对待调试单元3进行调试。这里，使能信号enable只要是具有能够禁止或者允许调试的信号即可，并不特别限制。在高安全等级的情况下，安全逻辑处理单元15输出使能信号enable为“0”，用户无法可以经由TAP控制器11二输入与电路16、17以及信号转换单元12对待调试单元3进行调试。
在通过上述的安全认证的情况下，信号转换单元12将JTAG端口信号转换为总线从端口信号，总线从端口信号是双向的信号。一方面，通过转换为总线从端口信号可以访问待调试单元3，输入调试用输入信号。另一方面，待调试单元3的状态信号等可作为总线从端口信号输出到信号转换单元12，然后经由信号转换单元12将总线从端口信号转换成JTAG端口信号，并经由TAP控制器11输出。
作为一个可选实施例，可以仅设置一个信号转换单元。在上述的实施例中，信号转换单元设置了两个，但不是必须设置两个。由于待调试单元3和安全逻辑处理单元15可以通过不同的地址来区分，因此信号转换单元可以仅设置一个，基本不同的访问地址而能够判断出对待调试单元3和安全逻辑处理单元15的哪个进行访问。
另外，待调试单元也可能有多个，多个待调试单元之间也可以通过不同的地址进行区分。
通过上述对JTAG调试装置10设置安全保护单元，能够防止外部对待调试单元3的恶意访问，防止信息被盗取或者更改，从而实现安全地对芯片内的待调试单元3进行调试。
以上对本发明实施例涉及的JTAG调试装置的进行了说明。下面对JTAG调试的工作流程进行说明。
图3是示出本发明一实施例涉及的JTAG调试方法的流程图。下面，参照图3对JTAG调试的工作流程进行说明。
一种JTAG调试方法，用于调试芯片中的待调试单元，包括：步骤S11，从JTAG端口接收的信号，并基于所接收的信号生成包含待调试单元地址以及调试指令的调试信号，所述调试信号是基于JTAG协议的JTAG端口信号；步骤S12，将所述调试信号从所述JTAG端口信号转换成基于待调试单元的从端口能够读取的总线从端口信号；以及步骤S13，总线基于被转换为所述总线从端口信号的所述调试信号将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元。
具体地，在上述的JTAG调试装置中，TAP控制器从外部的JTAG端口接收信号，并基于所接收的信号生成包含待调试单元地址以及调试指令的调试信号。信号转换单元将经从TAP控制器接收的调试信号从JTAG端口信号转换成总线从端口信号。例如总线是APB总线的情况下，APB总线基于AMBA协议将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元。
另外，所述信号转换单元还将经由总线从所述待调试单元接收的信号从总线从端口信号转换成JTAG端口信号，并经由所述TAP控制器从所述JTAG端口输出。另外，信号转化单元还将从所述待调试单元接收的总线从端口信号转换成JTAG端口信号，并向所述JTAG端口输出
通过上述的调试方法，能够在处理器发生故障或者没有处理器参与的情况下实现对芯片内部逻辑的调试。
图4是示出本发明又一实施例涉及的JTAG调试方法的流程图。在图3所示的调试方法的基础上，还进行以下操作。
安全配置信息被预先烧录到非易失存储器中。如步骤S21所示，芯片上电时，非易失性存储器中的安全配置信息被装载到安全逻辑处理单元中。如步骤S22所示，安全逻辑处理单元判断安全等级。在安全等级是低安全等级的情况下，如步骤S23所示，安全逻辑处理单元输出使能信号“1”。在安全等级是中安全等级的情况下，如步骤S24所示，判断输入密码是否与安全配置信息中的密码一致，在一致的情况下，如步骤S23所示，安全逻辑处理单元输出使能信号“1”，在不一致的情况下，如步骤S25所示，安全逻辑处理单元输出使能信号“0”。在安全等级是高安全等级的情况下，如步骤S25所示，安全逻辑处理单元输出使能信号“0”。在使能信号为“1”的情况下，允许用户通过JTAG端口对待调试单元进行访问。在使能信号为“0”的情况下，不允许用户通过JTAG端口对待调试单元进行调试。
另外，用户可以通过JTAG端口对安全逻辑处理单元中的芯片标识号寄存器进行读取。用户根据芯片标识号通过JTAG端口将密码写入安全逻辑处理单元中的密码寄存器。将密码寄存器与从非易失性存储器中装载的密码进行比较。
通过在JTAG调试方法中设置安全保护步骤，能够防止外部对待调试单元的恶意访问，防止信息被盗取或者更改，实现了安全地对芯片内的待调试单元进行调试。
需要明确，本发明并不局限于上文所描述并在图中示出的特定配置和处理。并且，为了简明起见，这里省略对已知方法和结构的详细描述。在上述实施例中，描述和示出了若干具体的结构、步骤作为示例。但是，本发明的方法过程并不限于所描述和示出的具体结构、步骤，本领域的技术人员可以在领会本发明的精神后作出各种改变、修改和添加，或者改变步骤之间的顺序。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬 件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种JTAG调试装置，用于调试芯片中的待调试单元，所述JTAG调试装置包括：
    TAP控制器，被配置为经由外部的JTAG端口与外部进行通信，并基于从所述JTAG端口接收的信号生成包含待调试单元地址以及调试指令的调试信号，所述调试信号是基于JTAG协议的JTAG端口信号；
    信号转换单元，被配置为接收所述TAP控制器输出的所述调试信号，并将所述调试信号从所述JTAG端口信号转换成能够对所述待调试单元的从端口进行访问的总线从端口信号；以及
    总线，被配置为获取所述信号转换单元输出的被转换为所述总线从端口信号的所述调试信号，并基于所述调试信号将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元。
  2. 根据权利要求1所述的JTAG调试装置，其中，
    所述信号转换单元将经由所述总线从所述待调试单元接收的信号从所述总线从端口信号转换成所述JTAG端口信号，并经由所述TAP控制器从所述JTAG端口输出。
  3. 根据权利要求1或2所述的JTAG调试装置，
    还包括非易失性存储器、装载单元及安全逻辑处理单元，
    所述非易失性存储器存储有安全配置信息，
    所述装载单元在所述芯片上电时将所述非易失性存储器所存储的安全配置信息自动装载到所述安全逻辑处理单元中，
    所述安全逻辑处理单元基于装载的所述安全配置信息输出使能信号，以控制是否允许从所述JTAG端口经由所述TAP控制器、所述信号转换单元访问所述待调试单元。
  4. 根据权利要求3所述的JTAG调试装置，其中，
    所述安全配置信息包括安全等级、密码以及芯片标识号。
  5. 根据权利要求3所述的JTAG调试装置，其中，
    所述安全等级包括低安全等级、中安全等级及高安全等级，
    所述安全逻辑处理单元被配置为，在所述安全等级是低安全等级时，允许用户无限制地通过JTAG端口访问所述待调试单元；在所述安全等级是中安全等级时，允许用户在正确输入密码后通过所述JTAG端口访问所述待调试单元；在所述安全等级是高安全等级时，禁止用户通过所述JTAG端口访问所述待调试单元。
  6. 根据权利要求3所述的JTAG调试装置，其中，
    还包括第一与电路，其一输入端子接收所述使能信号，另一输入端子接收所述TAP控制器输出的所述调试信号，所述第一与电路输出的信号传输至所述信号转换单元。
  7. 根据权利要求3所述的JTAG调试装置，其中，
    还包括第二与电路，其一输入端子接收所述使能信号，另一输入端子接收所述信号转换单元输出的被转换为所述JTAG端口信号的调试结果信号，所述第二与电路输出的信号传输至所述TAP控制器。
  8. 一种JTAG调试方法，用于调试芯片中的待调试单元，包括以下步骤：
    从JTAG端口接收的信号，并基于所接收的信号生成包含待调试单元地址以及调试指令的调试信号，所述调试信号是基于JTAG协议的JTAG端口信号；
    将所述调试信号从所述JTAG端口信号转换成能够对所述待调试单元的从端口进行访问的总线从端口信号；以及
    总线基于被转换为所述总线从端口信号的所述调试信号将所述调试指令传输给所述待调试单元地址所指示的所述待调试单元。
  9. 根据权利要求8所述的JTAG调试方法，其中，
    还将经由所述总线从所述待调试单元接收的信号从所述总线从端口信号转换成所述JTAG端口信号，并向所述JTAG端口输出。
  10. 根据权利要求8或9所述的JTAG调试方法，其中，
    在芯片上电时自动装载安全配置信息，并基于安全配置信息输出使能信号，以控制是否允许从所述JTAG端口访问所述待调试单元。
  11. 根据权利要求10所述的JTAG调试方法，其中，
    所述安全配置信息包括安全等级、密码以及芯片标识号。
  12. 根据权利要求11所述的JTAG调试方法，其中，
    在所述安全等级是低安全等级时，允许用户无限制地通过JTAG端口访问所述待调试单元；在所述安全等级是中安全等级时，允许用户在正确输入密码后通过所述JTAG端口访问所述待调试单元；在所述安全等级是高安全等级时，禁止用户通过所述JTAG端口访问所述待调试单元。
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