WO2018035993A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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WO2018035993A1
WO2018035993A1 PCT/CN2016/106033 CN2016106033W WO2018035993A1 WO 2018035993 A1 WO2018035993 A1 WO 2018035993A1 CN 2016106033 W CN2016106033 W CN 2016106033W WO 2018035993 A1 WO2018035993 A1 WO 2018035993A1
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Prior art keywords
layer
drain
contact hole
substrate
oxide semiconductor
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English (en)
French (fr)
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谢应涛
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/322,398 priority Critical patent/US20180210248A1/en
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Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • Oxide semiconductor TFTs have advantages such as high mobility and relatively large-scale production, and are gradually becoming a strong competitor for next-generation display technologies.
  • the current situation is that the threshold voltage of the oxide semiconductor TFT on the panel drifts, and the difference between the threshold voltages of the respective oxide semiconductor TFTs is large and uneven, which has a bad influence on the quality and effect of the liquid crystal display. .
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can adjust the difference between the threshold voltages of the plurality of oxide thin film transistors, and further reduce the drift of the threshold voltage of the oxide semiconductor TFT to achieve uniformity.
  • the display effect provides the technical basis.
  • the present invention adopts a technical solution to provide an array substrate, wherein the array substrate is provided with a plurality of oxide thin film transistors distributed in an array, and the array substrate comprises: a substrate;
  • a gate insulating layer covering the substrate and the gate layer
  • a source layer and a drain layer are respectively formed on the gate insulating layer at intervals, and partially cover the oxide semiconductor material layer, respectively, such that the source layer and the drain layer are respectively located in the oxide semiconductor Both sides of the material layer;
  • a passivation layer overlying the source layer, the drain layer, and the oxide semiconductor material layer, wherein the passivation layer is formed by annealing under radio frequency and in compressed air, Adjusting a difference between threshold voltages of the plurality of oxide thin film transistors;
  • a planarization layer overlying the passivation layer, wherein a contact hole penetrating the planarization layer is formed in the planarization layer, one end of the contact hole extending through the passivation layer and the drain layer Connection, said The material filled in the contact hole is a transparent electrode material;
  • a pixel electrode layer formed on the flat layer, the material of which is a transparent electrode material, the pixel electrode layer being connected to the other end of the contact hole to achieve between the drain layer and the pixel electrode layer Electrical connection.
  • the power of the radio frequency ranges from 400 W to 4000 W.
  • the power of the radio frequency is 600W, 1000W, and 1400W, respectively.
  • the temperature at the time of annealing is 200 to 400 °C.
  • a liquid crystal display panel comprising: a first substrate;
  • a gate insulating layer covering the substrate and the gate layer
  • a source layer and a drain layer are respectively formed on the gate insulating layer at intervals, and partially cover the oxide semiconductor material layer, respectively, such that the source layer and the drain layer are respectively located in the oxide semiconductor Both sides of the material layer;
  • a passivation layer overlying the source layer, the drain layer, and the oxide semiconductor material layer, wherein the passivation layer is formed by annealing under radio frequency and in compressed air, Adjusting a difference between threshold voltages of the plurality of oxide thin film transistors;
  • a planarization layer overlying the passivation layer, wherein a contact hole penetrating the planarization layer is formed in the planarization layer, one end of the contact hole extending through the passivation layer and the drain layer Connecting, the material filled in the contact hole is a transparent electrode material;
  • a pixel electrode layer formed on the flat layer, the material of which is a transparent electrode material, the pixel electrode layer being connected to the other end of the contact hole to achieve between the drain layer and the pixel electrode layer Electrical connection
  • the liquid crystal layer is interposed between the first substrate and the second substrate.
  • an array substrate wherein the array substrate is provided with a plurality of oxide thin film transistors distributed in an array, the array
  • the column substrate comprises: a substrate;
  • An oxide semiconductor material layer including a channel region, a source region, and a drain region, the oxide semiconductor material layer being formed on the buffer layer, wherein the source region and the drain region are respectively located Both ends of the channel region, the source region and the drain region are formed by doping the oxide semiconductor material;
  • a gate insulating layer overlying the channel region, wherein the gate insulating layer is formed by annealing under radio frequency and in compressed air to adjust the plurality of oxide thin film transistors The difference between the threshold voltages;
  • An insulating interconnect layer covering the buffer layer, the source region, the gate layer, and the drain region, and forming a first contact hole penetrating the interconnect layer in the interconnect layer And a second contact hole, one end of the first contact hole is connected to the source region, and one end of the second contact hole is connected to the drain region, wherein the first contact hole and the second contact hole
  • the material filled in is a transparent electrode material
  • a source layer and a drain layer respectively formed on the interconnect layer the material of which is a metal conductor material, wherein the source layer is connected to the other end of the first contact hole to achieve the An electrical connection between the source layer and the source region, the drain layer being connected to the other end of the second contact hole to achieve electrical connection between the drain layer and the drain region Sexual connection.
  • the power of the radio frequency ranges from 400 W to 4000 W.
  • the power of the radio frequency is 600W, 1000W, and 1400W, respectively.
  • the temperature at the time of annealing is 200 to 400 °C.
  • the invention has the beneficial effects that, different from the prior art, the present invention forms a passivation layer or a gate insulating layer after the formation of the oxide semiconductor material layer, under the irradiation of radio frequency, and annealing in compressed air. In this way, it is possible to adjust the difference between the threshold voltages of the oxide thin film transistors, and further provide a technical basis for reducing the drift of the threshold voltage of the oxide semiconductor TFT and achieving a uniform display effect.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic view showing a first part of a preparation process of the array substrate of FIG. 1 in practical application;
  • FIG. 3 is a schematic view showing a second part of a preparation process of the array substrate of FIG. 1 in practical application;
  • FIGS. 2 and 3 are schematic diagrams of a site of a test TFT device on a substrate obtained by the preparation flow of FIGS. 2 and 3;
  • Figure 5 is a current-voltage (IdVg) curve of the TFT device of Figure 4 at 600W;
  • IdVg current-voltage
  • Figure 7 is a current-voltage (IdVg) curve of the TFT device of Figure 4 at 1400 W;
  • FIG. 8 is a schematic structural view of another embodiment of an array substrate of the present invention.
  • FIG. 9 is a schematic view showing a first part of a preparation process of the array substrate of FIG. 8 in practical application;
  • FIG. 10 is a schematic view showing a second part of a preparation process of the array substrate of FIG. 8 in practical use.
  • FIG. 10 is a schematic view showing a second part of a preparation process of the array substrate of FIG. 8 in practical use.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present invention, wherein the array substrate is provided with a plurality of oxide thin film transistors distributed in an array, the array substrate comprising: a substrate 11 , a gate layer 12 , and a gate A pole insulating layer 13, an oxide semiconductor material layer 14, a source layer 15 and a drain layer 16, a passivation layer 17, a flat layer 18, and a pixel electrode layer 19.
  • the gate layer 12 is formed on the substrate 11.
  • the material of the gate layer 12 is a metallic conductor material.
  • a gate insulating layer 13 is overlaid on the substrate 11 and the gate layer 12.
  • the material of the gate insulating layer 13 may be a SiOx film, and the thickness may be less than 500 nm.
  • the oxide semiconductor material layer 14 is formed on the gate insulating layer 13 and directly above the gate layer 12; the material of the oxide semiconductor material layer 14 includes, but is not limited to, a-IGZO.
  • the source layer 15 and the drain layer 16 are formed on the gate insulating layer 13 at intervals, and partially cover the oxide semiconductor material layer 14, respectively, such that the source layer 15 and the drain layer 16 are respectively located on the oxide semiconductor material layer 14. On both sides.
  • the material of the source layer 15 and the drain layer 16 is a metal conductor material such as Mo, Cu or Mo/Cu alloy.
  • a passivation layer 17 is overlaid on the source layer 15, the drain layer 16, and the oxide semiconductor material layer 14, wherein the passivation layer 17 is formed by annealing under radio frequency irradiation and in compressed air to adjust a plurality of oxidations.
  • the power of the radio frequency can be adjusted according to actual needs, annealing in compressed air, annealing temperature and annealing time, etc., to adjust the difference between the threshold voltages of the plurality of oxide thin film transistors.
  • the flat layer 18 is covered on the passivation layer 17 , and a contact hole 181 penetrating the flat layer 18 is formed in the flat layer 18 .
  • One end 1811 of the contact hole 181 extends through the passivation layer 17 and is connected to the drain layer 16 .
  • the material filled in the contact hole 181 is a transparent electrode material.
  • the pixel electrode layer 19 is formed on the flat layer 18 and is made of a transparent electrode material.
  • the pixel electrode layer 19 is connected to the other end 1812 of the contact hole 181 to realize electrical connection between the drain layer 16 and the pixel electrode layer 19.
  • the power supply of the radio frequency ranges from 400W to 4000W. Further, the power of the radio frequency is 600W, 1000W, and 1400W, respectively.
  • the temperature at the time of annealing is 200 to 400 °C. Further, the temperature at the time of annealing was 350 °C.
  • the above array substrate can be prepared by the following preparation process, as shown in FIG. 2 and FIG. 3:
  • a passivation layer 17 by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), wherein the passivation layer 17 is formed by annealing under radio frequency irradiation and in compressed air.
  • PECVD plasma enhanced chemical vapor deposition
  • ITO Indium tin oxide
  • the above preparation process produces a 4.5-generation substrate.
  • the power supply of the radio frequency is maintained under the condition that the cavity pressure, spacing, and gas flow rate remain unchanged.
  • (RF power) 600W, 1000W, 1400W were respectively selected for deposition of SiOx film, and then the sample was subjected to hot air annealing at 350 ° C for 1 hour in compressed air.
  • the Eighteen TFT devices were tested on a 4.5-generation substrate. The test sites were as shown in Figure 4. Nine adjacent test locations were tested for two TFT devices at each adjacent location.
  • the current-voltage (IdVg) curves of the 18 TFT devices are shown in FIGS.
  • the threshold voltage (Vth) can be extracted by the IdVg curve of the series as shown in Table 1 below. It can be seen from Table 1 that the ⁇ Vth of the 1400W sample is 1.17V, the ⁇ Vth of the 1000W sample is 2.24V, and the ⁇ Vth of the 600W sample is 3.46V, so the regularity is that ⁇ Vth is significantly reduced as the RF power increases. If it is necessary to reduce the difference in threshold voltage between TFTs, RF power can be increased.
  • array substrate of the present invention is not limited to being prepared by the above process, and may be prepared by other processes, which is not limited herein.
  • the passivation layer is formed in the annealing under the radio frequency and in the compressed air. In this way, the difference between the threshold voltages of the oxide thin film transistors can be adjusted, and further In order to reduce the drift of the threshold voltage of the oxide semiconductor TFT, a technical basis is provided for achieving a uniform display effect.
  • the present invention further provides a liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer interposed between the first substrate and the second substrate, wherein
  • the substrate is any one of the above array substrates.
  • the above array substrate please refer to the above array substrate, which will not be described herein.
  • FIG. 8 is a schematic structural diagram of another embodiment of an array substrate according to the present invention.
  • the array substrate is provided with a plurality of oxide thin film transistors distributed in an array, the array substrate comprising: a substrate 21, an insulating buffer layer 22, and oxidation.
  • a semiconductor material layer (which includes a source region 23, a drain region 24, and a channel region 25), a gate insulating layer 26, a gate layer 27, an insulating interconnect layer 28, and a source layer 29 and a drain layer 30.
  • An insulating buffer layer 22 is overlaid on the substrate 21.
  • the material of the buffer layer may be SiOx.
  • the oxide semiconductor material layer includes a channel region 25, a source region 23, and a drain region 24, oxidized
  • a layer of semiconductor material is formed on the buffer layer 22, wherein the source region 23 and the drain region 24 are respectively located at both ends of the channel region 25, and the materials of the source region 23 and the drain region 24 pass through the oxide semiconductor material.
  • the doping process is formed; wherein the initial material of the source region 23 and the drain region 24 is an oxide semiconductor material, and the final material is that the oxide semiconductor material is doped to become a conductor material.
  • the basic principle of the oxide semiconductor material being turned into a conductor material after doping treatment may be: taking out oxygen atoms in the oxide semiconductor material, causing the oxygen atoms to react with other substances, thereby making the oxide
  • the semiconductor material becomes a conductor material by being trapped of oxygen atoms.
  • the manner of doping treatment includes, but is not limited to, plasma, UV illumination, metal oxidation, and the like.
  • the material of the interconnect layer 28 is SiNx
  • H2 can take oxygen atoms in the oxide semiconductor material and react, thereby turning the oxide semiconductor material into a conductor material.
  • the oxide semiconductor material includes, but is not limited to, a-IGZO.
  • a gate insulating layer 26 is overlaid on the channel region 25, wherein the gate insulating layer 26 is formed by annealing under radio frequency and in compressed air to adjust between threshold voltages of the plurality of oxide thin film transistors
  • the difference between the threshold voltages of the plurality of oxide thin film transistors can be adjusted according to actual needs, adjusting the power of the radio frequency, annealing in compressed air, adjusting the annealing temperature and annealing time, etc.
  • the material of the gate insulating layer 26 may be SiOx.
  • the gate layer 27 is overlaid on the gate insulating layer 26.
  • the material of the gate layer 27 is a metallic conductor material.
  • An insulating interconnect layer 28 is overlying the buffer layer 22, the source region 23, the gate layer 27, and the drain region 24, and a first contact hole 281 and a second contact hole penetrating through the interconnect layer 28 are formed in the interconnect layer 28, respectively.
  • one end 2811 of the first contact hole 281 is connected to the source region 23, and one end 2821 of the second contact hole 282 is connected to the drain region 24, wherein the material filled in the first contact hole 281 and the second contact hole 282 is transparent. Electrode material.
  • the source layer 29 and the drain layer 30 are respectively formed on the interconnect layer 28, and the material thereof is a metal conductor material, wherein the source layer 29 is connected to the other end 2812 of the first contact hole 281 to realize the source.
  • the electrical connection between the layer 29 and the source region 23, the drain layer 30 is connected to the other end 2822 of the second contact hole 282 to achieve an electrical connection between the drain layer 30 and the drain region 24.
  • the power supply of the radio frequency ranges from 400W to 4000W. Further, the power of the radio frequency is 600W, 1000W, and 1400W, respectively.
  • the temperature at the time of annealing is 200 to 400 °C. Further, the temperature at the time of annealing was 350 °C.
  • the above array substrate can be prepared by the following preparation process, as shown in FIG. 9 and FIG. 10:
  • the material of the source region 23 and the drain region 24 is also an initial material, that is, an oxide semiconductor material;
  • the gate insulating layer 26 is irradiated by radio frequency, and in compressed air Formed by annealing;
  • interconnect layer 28 depositing SiOx or SiNx as interconnect layer 28 (ILD) by PECVD and opening two contact holes 281, 282 to the conductive source region 23 and drain region 24 of the interconnect layer 28 by a standard photolithography process;
  • ITO is deposited and patterned by a standard photolithography process to form a pixel electrode at the drain electrode, thereby completing the array segment preparation.
  • the gate insulating layer is formed in the annealing under the radio frequency and in the compressed air, and in this way, the difference between the threshold voltages of the plurality of oxide thin film transistors can be adjusted. And further providing a technical basis for reducing the drift of the threshold voltage of the oxide semiconductor TFT and achieving a uniform display effect.
  • the present invention further provides a liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer interposed between the first substrate and the second substrate, wherein
  • the substrate is any one of the above array substrates, and the related content is described in the above array. The substrate is not described here.

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Abstract

一种阵列基板及液晶显示面板，该阵列基板包括：在氧化物半导体材料层（14,23,24,25）形成后，在射频照射下、并在压缩空气中进行退火形成钝化层（17）或栅极绝缘层（13,26）。通过上述方式，能够调节多个氧化物薄膜晶体管的阈值电压之间的差异，并进而为减少氧化物半导体TFT阈值电压的漂移，实现均匀的显示效果提供技术基础。

Description

阵列基板及液晶显示面板 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
氧化物半导体TFT(Oxide semiconductor TFT)具有高迁移率、较为廉价的大面积生产等优势，正逐渐成为下一代显示技术的有力竞争者。
但是，目前的情况是，面板上氧化物半导体TFT阈值电压发生漂移，各个氧化物半导体TFT阈值电压之间的差异很大，不均匀，这给液晶显示的质量和效果带来很不好的影响。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够调节多个氧化物薄膜晶体管的阈值电压之间的差异，并进而为减少氧化物半导体TFT阈值电压的漂移，实现均匀的显示效果提供技术基础。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，其中，所述阵列基板上设置有阵列分布的多个氧化物薄膜晶体管，所述阵列基板包括：基板；
栅极层，形成在所述基板上；
栅极绝缘层，覆盖在所述基板和所述栅极层上；
氧化物半导体材料层，形成在所述栅极绝缘层上，并位于所述栅极层的垂直正上方；
源极层和漏极层，分别间隔地形成在所述栅极绝缘层上，且分别部分覆盖所述氧化物半导体材料层，使得所述源极层和漏极层分别位于所述氧化物半导体材料层的两边；
钝化层，覆盖在所述源极层、所述漏极层以及所述氧化物半导体材料层上，其中，所述钝化层是在射频照射下、并在压缩空气中进行退火形成的，以调节所述多个氧化物薄膜晶体管的阈值电压之间的差值；
平坦层，覆盖在所述钝化层上，其在所述平坦层中形成贯穿所述平坦层的接触孔，所述接触孔的一端延伸并贯穿所述钝化层、与所述漏极层连接，所述 接触孔中填充的材料为透明电极材料；
像素电极层，形成在所述平坦层上，其材料为透明电极材料，所述像素电极层与所述接触孔的另一端连接，以实现所述漏极层与所述像素电极层之间的电性连接。
其中，所述射频的电源功率的范围为400W～4000W。
其中，所述射频的电源功率分别为600W、1000W以及1400W。
其中，退火时的温度为200～400℃。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示面板，包括：第一基板；
第二基板，与所述第一基板相对设置，其上设置有阵列分布的多个氧化物薄膜晶体管，其包括：
基板；
栅极层，形成在所述基板上；
栅极绝缘层，覆盖在所述基板和所述栅极层上；
氧化物半导体材料层，形成在所述栅极绝缘层上，并位于所述栅极层的垂直正上方；
源极层和漏极层，分别间隔地形成在所述栅极绝缘层上，且分别部分覆盖所述氧化物半导体材料层，使得所述源极层和漏极层分别位于所述氧化物半导体材料层的两边；
钝化层，覆盖在所述源极层、所述漏极层以及所述氧化物半导体材料层上，其中，所述钝化层是在射频照射下、并在压缩空气中进行退火形成的，以调节所述多个氧化物薄膜晶体管的阈值电压之间的差值；
平坦层，覆盖在所述钝化层上，其在所述平坦层中形成贯穿所述平坦层的接触孔，所述接触孔的一端延伸并贯穿所述钝化层、与所述漏极层连接，所述接触孔中填充的材料为透明电极材料；
像素电极层，形成在所述平坦层上，其材料为透明电极材料，所述像素电极层与所述接触孔的另一端连接，以实现所述漏极层与所述像素电极层之间的电性连接；
液晶层，夹设在所述第一基板和所述第二基板之间。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板，其中，所述阵列基板上设置有阵列分布的多个氧化物薄膜晶体管，所述阵 列基板包括：基板；
绝缘的缓冲层，覆盖在所述基板上；
氧化物半导体材料层，其包括沟道区域、源极区域和漏极区域，所述氧化物半导体材料层形成在所述缓冲层上，其中，所述源极区域和所述漏极区域分别位于所述沟道区域的两端，所述源极区域和所述漏极区域通过对所述氧化物半导体材料经过掺杂处理而形成；
栅极绝缘层，覆盖在所述沟道区域上，其中，所述栅极绝缘层在射频的照射下、并在压缩空气中进行退火而形成的，以调节所述多个氧化物薄膜晶体管的阈值电压之间的差值；
栅极层，覆盖在所述栅极绝缘层上；
绝缘的互联层，覆盖在所述缓冲层、所述源极区域、所述栅极层以及所述漏极区域上，且在所述互联层中分别形成贯穿所述互联层的第一接触孔和第二接触孔，所述第一接触孔的一端与所述源极区域连接，所述第二接触孔的一端与所述漏极区域连接，其中所述第一接触孔和第二接触孔中填充的材料为透明电极材料；
源极层和漏极层，其分别间隔形成在所述互联层上，其材料均为金属导体材料，其中，所述源极层与所述第一接触孔的另一端相连，以实现所述源极层与所述源极区域之间的电性连接，所述漏极层与所述第二接触孔的另一端相连，以实现所述漏极层与所述漏极区域之间的电性连接。
其中，所述射频的电源功率的范围为400W～4000W。
其中，所述射频的电源功率分别为600W、1000W以及1400W。
其中，退火时的温度为200～400℃。
本发明的有益效果是：区别于现有技术的情况，本发明在氧化物半导体材料层形成后，在射频的照射下、并在压缩空气中进行退火中形成钝化层或栅极绝缘层，通过这种方式，能够调节氧化物薄膜晶体管的阈值电压之间的差异，并进而为减少氧化物半导体TFT阈值电压的漂移，实现均匀的显示效果提供技术基础。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是图1的阵列基板在实际应用中一制备流程第一部分示意图；
图3是图1的阵列基板在实际应用中一制备流程第二部分示意图；
图4是通过图2和图3的制备流程获得的基板上测试TFT器件的位点示意图；
图5是图4的TFT器件在600W的电流电压(IdVg)曲线；
图6是图4的TFT器件在1000W的电流电压(IdVg)曲线；
图7是图4的TFT器件在1400W的电流电压(IdVg)曲线；
图8是本发明阵列基板另一实施方式的结构示意图；
图9是图8的阵列基板在实际应用中一制备流程第一部分示意图；
图10是图8的阵列基板在实际应用中一制备流程第二部分示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
参阅图1，图1是本发明阵列基板一实施方式的结构示意图，其中，该阵列基板上设置有阵列分布的多个氧化物薄膜晶体管，该阵列基板包括：基板11、栅极层12、栅极绝缘层13、氧化物半导体材料层14、源极层15和漏极层16、钝化层17、平坦层18以及像素电极层19。
栅极层12形成在基板11上。栅极层12的材料是金属导体材料。
栅极绝缘层13覆盖在基板11和栅极层12上。栅极绝缘层13的材料可以是SiOx薄膜，厚度可以在500nm一下。
氧化物半导体材料层14形成在栅极绝缘层13上，并位于栅极层12的垂直正上方；氧化物半导体材料层14的材料包括但不限于a-IGZO。
源极层15和漏极层16分别间隔地形成在栅极绝缘层13上，且分别部分覆盖氧化物半导体材料层14，使得源极层15和漏极层16分别位于氧化物半导体材料层14的两边。源极层15和漏极层16的材料是金属导体材料，例如：Mo、Cu或Mo/Cu合金等。
钝化层17覆盖在源极层15、漏极层16以及氧化物半导体材料层14上，其中，钝化层17在射频照射下、并在压缩空气中进行退火形成的，以调节多个氧化物薄膜晶体管的阈值电压之间的差异。在实际应用中，可以根据实际需要，调节射频的电源功率，在压缩空气中进行退火，调节退火温度和退火时间等，来调节多个氧化物薄膜晶体管的阈值电压之间的差异。
平坦层18覆盖在钝化层17上，其在平坦层18中形成贯穿平坦层18的接触孔181，接触孔181的一端1811延伸并贯穿钝化层17、与漏极层16连接， 接触孔181中填充的材料为透明电极材料。
像素电极层19形成在平坦层18上，其材料为透明电极材料，像素电极层19与接触孔181的另一端1812连接，以实现漏极层16与像素电极层19之间的电性连接。
其中，射频的电源功率的范围为400W～4000W。进一步地，射频的电源功率分别为600W、1000W以及1400W。
其中，退火时的温度为200～400℃。进一步地，退火时的温度为350℃。
在实际应用中，可以通过下面的制备流程来制备上述的阵列基板，如图2和图3所示：
(1)在基板11上，基于物理气相沉积(PVD)方法沉积金属栅电极膜层，并通过标准的光刻工艺对其进行图案化，获得栅极层12；
(2)在基板11和栅极层12上，基于化学气相沉积(CVD)方法沉积栅极绝缘层13(gate insulator)SiOx薄膜，厚度为500nm以下；
(3)在栅极绝缘层13上，基于PVD沉积氧化物半导体(如a-IGZO)薄膜，然后通过标准的光刻工艺，形成所需的a-IGZO图案，获得氧化物半导体材料层14；
(4)在栅极绝缘层13上，基于PVD沉积金属(如Mo、Cu或Mo/Cu)源漏电极膜层，并通过标准的光刻工艺对其进行图案化，获得源极层15和漏极层16；
(5)采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简写PECVD)沉积钝化层17(passivation layer)，其中，钝化层17在射频照射下并在压缩空气中进行退火而形成的；
(6)采用PECVD沉积SiOx等获得平坦层18，或者采用涂布(coating)方式沉积有机平坦层18，并通过标准的光刻工艺对平坦层18和钝化层17开接触孔181于漏极层16处；
(7)沉积氧化铟锡(ITO)并采用标准的光刻工艺形成图案，使其连接漏极层16处形成像素(pixel)电极层19，进而完成阵列基板的制备。
上述制备工艺制得4.5代基板，为了有效调节多个氧化物薄膜晶体管的阈值电压之间的差异，在腔体压力、间距(spacing)和气体流量均保持不变的情况下，射频的电源功率(RF power)分别选择600W、1000W、1400W进行沉积SiOx薄膜，接着将样品在压缩空气中以350℃进行热风式退火1个小时。在该 4.5代基板上测试18个TFT器件，测试的点位如图4所示，9个相邻的测试位置，每个相邻位置测试两个TFT器件。18个TFT器件的电流电压(IdVg)曲线如图5至图7所示，然后可通过该系列的IdVg曲线提取阈值电压(Vth)如下表1。从表1中可以看出1400W样品的ΔVth为1.17V，1000W样品的ΔVth为2.24V，而600W样品的ΔVth为3.46V，因此其规律性为ΔVth随着RF power的增加而明显减少。如果需要减少TFT之间阈值电压的差异，可以提高RF power。
表1 不同功率沉积条件下Vth分布表
Figure PCTCN2016106033-appb-000001
需要说明的是，本发明的阵列基板并不限于通过上述的工艺制备，还可以通过其它的工艺制备，在此不做限定。
本发明在氧化物半导体材料层形成后，在射频照射下、并在压缩空气中进行退火中形成钝化层，通过这种方式，能够调节氧化物薄膜晶体管的阈值电压之间的差异，并进而为减少氧化物半导体TFT阈值电压的漂移，实现均匀的显示效果提供技术基础。
本发明还提供一种液晶显示面板，该液晶显示面板包括：第一基板、与第一基板相对设置第二基板以及夹设在第一基板和第二基板之间的液晶层，其中，第二基板为上述阵列基板中的任意一种，相关内容的详细说明请参见上述阵列基板，在此不再赘叙。
参见图8，图8是本发明阵列基板另一实施方式的结构示意图，该阵列基板上设置有阵列分布的多个氧化物薄膜晶体管，该阵列基板包括：基板21、绝缘的缓冲层22、氧化物半导体材料层(其包括源极区域23、漏极区域24和沟道区域25)、栅极绝缘层26、栅极层27、绝缘的互联层28以及源极层29和漏极层30。
绝缘的缓冲层22覆盖在基板21上。缓冲层的材料可以是SiOx。
氧化物半导体材料层包括沟道区域25、源极区域23和漏极区域24，氧化 物半导体材料层形成在缓冲层22上，其中，源极区域23和漏极区域24分别位于沟道区域25的两端，源极区域23和漏极区域24的材料通过对氧化物半导体材料经过掺杂处理而形成的；其中，源极区域23和漏极区域24的初始材料是氧化物半导体材料，最终的材料是氧化物半导体材料经过掺杂处理后变成导体材料。在一实施方式中，氧化物半导体材料经过掺杂处理后变成导体材料的基本原理可以是：将氧化物半导体材料中的氧原子夺取出来，使氧原子与其他物质发生反应，从而使得氧化物半导体材料由于被夺取氧原子而变为导体材料。此处掺杂处理的方式包括但不限于：等离子体(plasma)、UV光照、金属氧化等方式。当然，如果互联层28的材料是SiNx，在沉积互联层28时，由于释放出氢气H2，H2可以夺取氧化物半导体材料中的氧原子，并发生反应，从而使氧化物半导体材料变成导体材料。其中，氧化物半导体材料包括但不限于a-IGZO。
栅极绝缘层26覆盖在沟道区域25上，其中，栅极绝缘层26在射频的照射下、并在压缩空气中进行退火而形成的，以调节多个氧化物薄膜晶体管的阈值电压之间的差值；在实际应用中，可以根据实际需要，调节射频的电源功率，在压缩空气中进行退火，调节退火温度和退火时间等，来调节多个氧化物薄膜晶体管的阈值电压之间的差异。栅极绝缘层26的材料可以是SiOx。
栅极层27覆盖在栅极绝缘层26上。栅极层27的材料是金属导体材料。
绝缘的互联层28覆盖在缓冲层22、源极区域23、栅极层27以及漏极区域24上，且在互联层28中分别形成贯穿互联层28的第一接触孔281和第二接触孔282，第一接触孔281的一端2811与源极区域23连接，第二接触孔282的一端2821与漏极区域24连接，其中第一接触孔281和第二接触孔282中填充的材料为透明电极材料。
源极层29和漏极层30，其分别间隔形成在互联层28上，其材料均为金属导体材料，其中，源极层29与第一接触孔281的另一端2812相连，以实现源极层29与源极区域23之间的电性连接，漏极层30与第二接触孔282的另一端2822相连，以实现漏极层30与漏极区域24之间的电性连接。
其中，射频的电源功率的范围为400W～4000W。进一步地，射频的电源功率分别为600W、1000W以及1400W。
其中，退火时的温度为200～400℃。进一步地，退火时的温度为350℃。
在实际应用中，可以通过下面的制备流程来制备上述的阵列基板，如图9和图10所示：
(1)在基板21上，基于CVD沉积SiOx作为缓冲层22(buffer layer)；
(2)在缓冲层22上，基于PVD沉积氧化物半导体(如a-IGZO)薄膜，形成氧化物半导体材料层，然后通过标准的光刻工艺，形成所需的a-IGZO图案，获得源极区域23、漏极区域24以及沟道区域25，此时，源极区域23、漏极区域24的材料还是初始材料，即氧化物半导体材料；
(3)基于CVD沉积栅极绝缘层26(gate insulator)薄膜，为了有效调节多个氧化物薄膜晶体管的阈值电压之间的差异，栅极绝缘层26在射频的照射下，且在压缩空气中进行退火而形成的；
(4)基于PVD沉积金属栅极层27，然后coating光阻(PR)形成图案，并通过干刻(dry etch)或者湿刻(Wet-etch)方法蚀刻未被光阻保护的金属层和绝缘层；
(5)对裸露的氧化物半导体材料进行诸如等离子体(plasma)、UV光照、金属氧化等方式实现氧化物半导体的掺杂，使其变为导体作为源极区域23和漏极区域24(如互联层ILD层为SiNx，此步骤可以省略)；
(6)采用PECVD沉积SiOx或SiNx作为互联层28(ILD)并通过标准的光刻工艺对互联层28开两个接触孔281、282于导电的源极区域23和漏极区域24处；
(7)基于PVD沉积金属薄膜并对其进行图案化，形成源漏电极图案，获得源极层29和漏极层30；
进一步地，还可以包括如下两个步骤：
(8)采用PECVD沉积SiOx平坦层或者采用coating方式沉积有机平坦层，并通过标准的光刻工艺对平坦层和钝化层开接触孔于漏电极处；
(9)沉积ITO并采用标准的光刻工艺形成图案，使其连接漏电极处形成像素电极，进而完成array段制备。
本发明在氧化物半导体材料层形成后，在射频照射下、并在压缩空气中进行退火中形成栅极绝缘层，通过这种方式，能够调节多个氧化物薄膜晶体管的阈值电压之间的差异，并进而为减少氧化物半导体TFT阈值电压的漂移，实现均匀的显示效果提供技术基础。
本发明还提供一种液晶显示面板，该液晶显示面板包括：第一基板、与第一基板相对设置第二基板以及夹设在第一基板和第二基板之间的液晶层，其中，第二基板为上述阵列基板中的任意一种，相关内容的详细说明请参见上述阵列 基板，在此不再赘叙。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (9)

  1. 一种阵列基板，其中，所述阵列基板上设置有阵列分布的多个氧化物薄膜晶体管，其中，所述阵列基板包括：
    基板；
    栅极层，形成在所述基板上；
    栅极绝缘层，覆盖在所述基板和所述栅极层上；
    氧化物半导体材料层，形成在所述栅极绝缘层上，并位于所述栅极层的垂直正上方；
    源极层和漏极层，分别间隔地形成在所述栅极绝缘层上，且分别部分覆盖所述氧化物半导体材料层，使得所述源极层和漏极层分别位于所述氧化物半导体材料层的两边；
    钝化层，覆盖在所述源极层、所述漏极层以及所述氧化物半导体材料层上，其中，所述钝化层是在射频照射下并在压缩空气中进行退火形成的，以调节所述多个氧化物薄膜晶体管的阈值电压之间的差值；
    平坦层，覆盖在所述钝化层上，其在所述平坦层中形成贯穿所述平坦层的接触孔，所述接触孔的一端延伸并贯穿所述钝化层、与所述漏极层连接，所述接触孔中填充的材料为透明电极材料；
    像素电极层，形成在所述平坦层上，其材料为透明电极材料，所述像素电极层与所述接触孔的另一端连接，以实现所述漏极层与所述像素电极层之间的电性连接。
  2. 根据权利要求1所述的阵列基板，其中，所述射频的电源功率的范围为400W～4000W。
  3. 根据权利要求2所述的阵列基板，其中，所述射频的电源功率分别为600W、1000W以及1400W。
  4. 根据权利要求1所述的阵列基板，其中，退火时的温度为200～400℃。
  5. 一种液晶显示面板，其中，包括：
    第一基板；
    第二基板，与所述第一基板相对设置，其上设置有阵列分布的多个氧化物薄膜晶体管，其包括：
    基板；
    栅极层，形成在所述基板上；
    栅极绝缘层，覆盖在所述基板和所述栅极层上；
    氧化物半导体材料层，形成在所述栅极绝缘层上，并位于所述栅极层的垂直正上方；
    源极层和漏极层，分别间隔地形成在所述栅极绝缘层上，且分别部分覆盖所述氧化物半导体材料层，使得所述源极层和漏极层分别位于所述氧化物半导体材料层的两边；
    钝化层，覆盖在所述源极层、所述漏极层以及所述氧化物半导体材料层上，其中，所述钝化层是在射频照射下并在压缩空气中进行退火形成的，以调节所述多个氧化物薄膜晶体管的阈值电压之间的差值；
    平坦层，覆盖在所述钝化层上，其在所述平坦层中形成贯穿所述平坦层的接触孔，所述接触孔的一端延伸并贯穿所述钝化层、与所述漏极层连接，所述接触孔中填充的材料为透明电极材料；
    像素电极层，形成在所述平坦层上，其材料为透明电极材料，所述像素电极层与所述接触孔的另一端连接，以实现所述漏极层与所述像素电极层之间的电性连接；
    液晶层，夹设在所述第一基板和所述第二基板之间。
  6. 一种阵列基板，其中，所述阵列基板上设置有阵列分布的多个氧化物薄膜晶体管，其中，所述阵列基板包括：
    基板；
    绝缘的缓冲层，覆盖在所述基板上；
    氧化物半导体材料层，其包括沟道区域、源极区域和漏极区域，所述氧化物半导体材料层形成在所述缓冲层上，其中，所述源极区域和所述漏极区域分别位于所述沟道区域的两端，所述源极区域和所述漏极区域通过对所述氧化物半导体材料经过掺杂处理而形成；
    栅极绝缘层，覆盖在所述沟道区域上，其中，所述栅极绝缘层在射频的照射下、并在压缩空气中进行退火而形成的，以调节所述多个氧化物薄膜晶体管的阈值电压之间的差值；
    栅极层，覆盖在所述栅极绝缘层上；
    绝缘的互联层，覆盖在所述缓冲层、所述源极区域、所述栅极层以及所述漏极区域上，且在所述互联层中分别形成贯穿所述互联层的第一接触孔和第二 接触孔，所述第一接触孔的一端与所述源极区域连接，所述第二接触孔的一端与所述漏极区域连接，其中所述第一接触孔和第二接触孔中填充的材料为透明电极材料；
    源极层和漏极层，其分别间隔形成在所述互联层上，其材料均为金属导体材料，其中，所述源极层与所述第一接触孔的另一端相连，以实现所述源极层与所述源极区域之间的电性连接，所述漏极层与所述第二接触孔的另一端相连，以实现所述漏极层与所述漏极区域之间的电性连接。
  7. 根据权利要求6所述的阵列基板，其中，所述射频的电源功率的范围为400W～4000W。
  8. 根据权利要求7所述的阵列基板，其中，所述射频的电源功率分别为600W、1000W以及1400W。
  9. 根据权利要求6所述的阵列基板，其中，退火时的温度为200～400℃。
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