WO2018035902A1 - 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板 - Google Patents

低温多晶硅阵列基板的制备方法、阵列基板以及显示面板 Download PDF

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WO2018035902A1
WO2018035902A1 PCT/CN2016/099215 CN2016099215W WO2018035902A1 WO 2018035902 A1 WO2018035902 A1 WO 2018035902A1 CN 2016099215 W CN2016099215 W CN 2016099215W WO 2018035902 A1 WO2018035902 A1 WO 2018035902A1
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layer
doped
amorphous silicon
thin film
array substrate
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French (fr)
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郝晓丹
殷婉婷
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/310,140 priority Critical patent/US10020382B1/en
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H10P14/3816—Pulsed laser beam

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a method for preparing a low temperature polysilicon array substrate, an array substrate, and a display panel.
  • LTPS Low temperature poly-silicon
  • the polysilicon layer is generally formed first, and then the channel doping, the N-type doping, and the P-type doping are performed, and the operation process is too complicated due to a large number of processes, and Each time a doping is performed, a mask must be passed, which increases the cost of the entire manufacturing process.
  • the technical problem to be solved by the present invention is to provide a method for preparing a low-temperature polysilicon array substrate, an array substrate and a display panel, which can effectively reduce the manufacturing process of the low-temperature polysilicon array substrate, reduce the investment of the manufacturing equipment, and further reduce the preparation cost.
  • a technical solution adopted by the present invention is to provide a method for preparing a low temperature polysilicon array substrate, and the preparation method includes:
  • the polysilicon layer is patterned.
  • the step of forming a doped amorphous silicon thin film layer on the buffer layer specifically includes:
  • a doped amorphous silicon thin film layer is formed on the buffer layer by chemical vapor deposition of a first mixed gas of SiH 4 , Ar, H 2 and a boron hydride or phosphorous hydrogen doped ionic gas. among them,
  • the step of dehydrogenating the amorphous silicon thin film layer by using a second mixed gas by means of meteorological deposition specifically includes:
  • the amorphous silicon thin film layer is dehydrogenated by chemical vapor deposition of a second mixed gas of phosphorus hydrogen or boron hydrogen.
  • the step of annealing the amorphous silicon film layer after dehydrogenation to diffuse the dopant ions to form the polysilicon layer specifically includes:
  • the doped ions are diffused by the excimer laser annealing of the amorphous silicon thin film layer after dehydrogenation to form a polysilicon layer.
  • the step of patterning the polysilicon layer specifically includes:
  • the photoresist is exposed and developed again, and the boron doped layer under the phosphor doped layer is etched to pattern the boron doped layer.
  • the step of disposing a substrate and forming a buffer layer on the substrate specifically includes:
  • SiO x layer is deposited on the SiN x layer, said SiN x layer, and the SiO x layer constituting the buffer layer.
  • the step of patterning the polysilicon layer further includes:
  • a surface of the source, the drain, and the interlayer insulating layer is covered with a flat layer, and an electrode is formed on a surface of the flat layer.
  • another technical solution adopted by the present invention is to provide an array substrate.
  • the polysilicon layer is formed by forming a doped amorphous silicon thin film layer on the buffer layer by means of meteorological deposition of a first mixed gas and doping an ion gas, and adopting a second mixed gas by meteorological deposition,
  • the amorphous silicon thin film layer is subjected to dehydrogenation, and an annealing treatment is performed to diffuse the dopant ions.
  • the amorphous silicon thin film layer is formed on the buffer layer by chemical vapor deposition of a first mixed gas of SiH 4 , Ar, H 2 and a boron hydride or phosphorous hydrogen doped ionic gas.
  • the amorphous silicon thin film layer is specifically dehydrogenated by chemical vapor deposition of a second mixed gas of phosphorus hydrogen or boron hydrogen.
  • the polysilicon layer is formed by diffusion of the doped ions by using an excimer laser annealing method on the amorphous silicon thin film layer after dehydrogenation.
  • the polysilicon layer further exposes and develops the photoresist by depositing a photoresist on the polysilicon layer through a mask using a mask having a mask and a half mask; and according to the processed a photoresist shape etching the phosphorus doped layer of the polysilicon layer to pattern the phosphor doped layer; exposing and developing the photoresist again to perform a boron doping layer under the phosphor doped layer Etching, patterning the boron doped layer to effect imaging of the polysilicon layer.
  • the array substrate further includes a light shielding layer formed on the substrate, wherein the buffer layer is formed by depositing a SiN x layer on the light shielding layer and depositing a SiO x layer on the SiN x layer.
  • the SiN x layer and the SiO x layer are formed.
  • the array substrate further includes a gate insulating layer deposited on the polysilicon layer, a gate formed on the gate insulating layer, and an interlayer deposited on a surface of the gate and the gate insulating layer An insulating layer, a source and a drain separated by a channel formed on the interlayer insulating layer, a surface flattening layer covering the surface of the source, the drain, and the interlayer insulating layer, and An electrode formed on the surface of the flat layer.
  • an array substrate display panel the display panel includes an array substrate, wherein the array substrate includes:
  • the polysilicon layer adopts a method of depositing a first mixed gas by means of meteorology and doping an ion gas, forming a doped amorphous silicon thin film layer on the buffer layer, and adopting a second mixed gas by meteorological deposition,
  • the amorphous silicon thin film layer is subjected to dehydrogenation, and an annealing treatment is performed to diffuse the dopant ions.
  • the amorphous silicon thin film layer is formed on the buffer layer by chemical vapor deposition of a first mixed gas of SiH 4 , Ar, H 2 and a boron hydride or phosphorous hydrogen doped ionic gas.
  • the amorphous silicon thin film layer is specifically dehydrogenated by chemical vapor deposition of a second mixed gas of phosphorus hydrogen or boron hydrogen.
  • the polysilicon layer is formed by diffusion of the doped ions by using an excimer laser annealing method on the amorphous silicon thin film layer after dehydrogenation.
  • the polysilicon layer further exposes and develops the photoresist by depositing a photoresist on the polysilicon layer through a mask using a mask having a mask and a half mask; and according to the processed a photoresist shape etching the phosphorus doped layer of the polysilicon layer to pattern the phosphor doped layer; exposing and developing the photoresist again to perform a boron doping layer under the phosphor doped layer Etching, patterning the boron doped layer to effect imaging of the polysilicon layer.
  • the array substrate further includes a light shielding layer formed on the substrate, wherein the buffer layer is formed by depositing a SiN x layer on the light shielding layer and depositing a SiO x layer on the SiN x layer.
  • the SiN x layer and the SiO x layer are formed.
  • the array substrate further includes a gate insulating layer deposited on the polysilicon layer, a gate formed on the gate insulating layer, and an interlayer deposited on a surface of the gate and the gate insulating layer An insulating layer, a source and a drain separated by a channel formed on the interlayer insulating layer, a surface flattening layer covering the surface of the source, the drain, and the interlayer insulating layer, and An electrode formed on the surface of the flat layer.
  • the present embodiment forms a buffer layer on the substrate, and forms a doped layer on the buffer layer by means of meteorological deposition of the first mixed gas and doping the ion gas.
  • An amorphous silicon thin film layer degassing the amorphous silicon thin film layer by means of meteorological deposition of a second mixed gas; annealing the amorphous silicon thin film layer after dehydrogenation to diffuse the dopant ions,
  • a polysilicon layer is formed and patterned into the polysilicon layer.
  • the doping is performed by simultaneously introducing the first mixed gas with a boron hydrogen or a phosphorus-hydrogen dopant ion gas.
  • the method of the amorphous silicon thin film layer not only simplifies the process of introducing the gas, saves time, and can reduce the number of masks, and also saves the doping equipment. Moreover, by doping with a gas, the doping can be made more uniform, and the electrical properties of the low-temperature polysilicon array substrate can be improved.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for preparing a low temperature polysilicon array substrate according to the present invention
  • FIG. 2A is a schematic structural view of a first embodiment of the low temperature polysilicon array substrate of FIG. 1;
  • FIG. 2B is a schematic view showing the mechanism of the second embodiment of the low temperature polysilicon array substrate of FIG. 1;
  • FIG. 2C is a schematic structural view of a third embodiment of the low temperature polysilicon array substrate of FIG. 1;
  • 2D is a schematic structural view of a fourth embodiment of the low temperature polysilicon array substrate of FIG. 1;
  • FIG. 2E is a schematic structural view of a fifth embodiment of the low temperature polysilicon array substrate of FIG. 1;
  • FIG. 3 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 4 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for preparing a low temperature polysilicon array substrate according to the present invention.
  • the manufacturing method of the embodiment includes the following steps:
  • a substrate 200 is disposed, and a buffer layer 202 is formed on the substrate 200.
  • the substrate 200 includes a glass substrate, and may be other substrates such as a quartz substrate in other embodiments, which is not limited herein.
  • first substrate 200 a first substrate 200, first light shielding layer 201 is formed on the first substrate 200, and then SiN x layer is deposited on the light shielding layer 2021, and then depositing a SiO x layer on the SiN x layer is 2022 2021, wherein the The SiN x layer 2021 and the SiO x layer 2022 constitute the buffer layer 202.
  • the above-mentioned light shielding layer 201, SiN x layer 2021, and SiO x layer 2022 can be realized by chemical vapor deposition CVD or physical vapor deposition of PVD.
  • 102 forming a doped amorphous silicon thin film layer on the buffer layer 202 by means of meteorological deposition of the first mixed gas and doping the ion gas.
  • a doped amorphous silicon thin film layer is formed on the buffer layer 202 by chemical vapor deposition of a first mixed gas of SiH 4 , Ar, H 2 , and a boron hydride or phosphorous hydrogen doped ionic gas.
  • a boron-hydrogen or phosphorous-hydrogen-doped ion gas is deposited while depositing the first mixed gas to form an amorphous silicon layer, wherein each of the different gases is introduced through different channels and then mixed, thereby buffering
  • An amorphous silicon film doped with boron or phosphorus ions is formed on the layer 202.
  • the order of first introducing a boron-hydrogen dopant ion gas or first introducing a phosphorus-hydrogen dopant ion gas is not limited.
  • the boron-hydrogen dopant ion gas is first introduced and then the phosphorus is introduced.
  • the hydrogen-doped ion gas is taken as an example.
  • the doped amorphous silicon thin film layer is formed by chemical vapor deposition. In other embodiments, the doped amorphous silicon thin film layer may also be formed by physical vapor deposition, which is not limited herein.
  • the method of simultaneously introducing the first mixed gas and the boron-hydrogen or phosphorus-hydrogen-doped ion gas into the doped amorphous silicon thin film layer can not only simplify the process of introducing the gas, but also save time and reduce the number of masks. Moreover, the doping equipment is also saved. Moreover, by doping with a gas, the doping can be made more uniform, and the electrical properties of the low-temperature polysilicon array substrate can be improved.
  • a second mixed gas of phosphorus hydrogen or boron hydrogen is deposited on the amorphous silicon film layer formed by the first mixed gas and the doped ion gas, and the amorphous silicon thin film layer is dehydrogenated.
  • a second mixed gas of phosphorus hydrogen or boron hydrogen is introduced by chemical vapor deposition.
  • the physical vapor deposition may also be implemented, which is not limited herein.
  • the amorphous silicon thin film layer after dehydrogenation is further annealed to diffuse the dopant ions.
  • a polysilicon layer 203 is formed.
  • the doped ions that is, boron ions and phosphorus ions
  • the doped ions are diffused by the excimer laser annealing of the amorphous silicon thin film layer after dehydrogenation to form a polysilicon layer 203.
  • a boron doped layer 2031 and a phosphorus doped layer 2032 are formed.
  • a photoresist is deposited on the polysilicon layer 203 by chemical deposition or by physical deposition to form a photoresist layer 204, and the photoresist layer 204 is exposed and developed.
  • 2B wherein, in this exposure process, only a mask is used, and the photoresist is exposed and developed by using a special mask 100 having both a mask and a half mask to obtain a predetermined shape as shown in FIG. 2C, wherein, as shown in FIG.
  • the portion 1011 of the mask 101 is a completely transparent mask, the portion of the light can be completely transmitted, and the portion 1012 is a half mask, and only part of the light is transmitted through the portion, 1013 Part of the mask, the light is completely impenetrable.
  • the specific shape of the mask 100 and the area occupied by each part may be set according to actual needs, and are not limited herein.
  • the phosphorus doped layer 2032 of the polysilicon layer 203 is etched according to the processed photoresist shape to pattern the phosphorus doped layer 2032. As shown in Figure 2D.
  • the photoresist layer 204 and the phosphorus doped layer 2032 are further exposed and developed, and the phosphorus doped layer 2032 and the boron doped layer 2031 are again etched, so that the phosphorus doped layer 2032 and the boron doped layer 2031 are patterned again. As shown in Figure 2E.
  • a gate insulating layer is further deposited on the patterned polysilicon layer, and a gate is formed on the gate insulating layer.
  • the gate insulating layer includes at least one of silicon nitride SiN x and amorphous silicon oxide SiO x . In other embodiments, other insulating materials may be used, which is not limited herein.
  • An interlayer insulating layer is then deposited on the surface of the gate electrode and the gate insulating layer, and a source and a drain separated by a channel are formed on the interlayer insulating layer.
  • a surface of the source, the drain, and the interlayer insulating layer is covered with a flat layer, and an electrode is formed on a surface of the flat layer.
  • the present embodiment forms a buffer layer on the substrate, and forms a doped amorphous silicon thin film layer on the buffer layer by means of meteorological deposition of the first mixed gas and doping ion gas; using meteorological deposition
  • the amorphous silicon thin film layer is dehydrogenated in a manner of a second mixed gas.
  • the amorphous silicon thin film layer after dehydrogenation is annealed to diffuse the dopant ions to form a polysilicon layer, and the polysilicon layer is patterned.
  • the process of introducing the gas can be simplified, the time is saved, and the time can be reduced.
  • the doping can be made more uniform, and the electrical properties of the low-temperature polysilicon array substrate can be improved.
  • FIG. 3 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • the array substrate of the present embodiment includes a substrate 301, and a buffer layer 302 and a polysilicon layer 303 which are sequentially formed on the substrate 300.
  • the polysilicon layer 303 is formed by forming a doped amorphous silicon thin film layer on the buffer layer 303 by using a first mixed gas and a doped ion gas by means of meteorological deposition, and adopting a second mixed gas method by meteorological deposition. Dehydrating the amorphous silicon thin film layer and annealing to form the dopant ions.
  • the substrate 300 includes a glass substrate, and may be another substrate such as a quartz substrate in other embodiments, which is not limited herein.
  • a light shielding layer 301 is formed on the substrate 300.
  • a buffer layer 302 is formed on the light shielding layer 301.
  • the buffer layer 302 is deposited first SiN x layer is 3021 on the light shielding layer, the SiO x layer 3022 and then deposited on the SiN x layer 3021 is composed of SiN x layer 3021 and the SiO x layer 3022 of.
  • the above-mentioned light shielding layer 301, SiN x layer 3021, and SiO x layer 3022 can be realized by chemical vapor deposition CVD or physical vapor deposition of PVD.
  • the polysilicon layer 303 is formed by first chemical vapor deposition of a first mixed gas of SiH 4 , Ar, H 2 , and a boron hydride or phosphorous hydrogen doped ionic gas.
  • a layer of doped amorphous silicon film is formed on layer 302. That is, depositing a boron-hydrogen or phosphorous-hydrogen doped ion gas while depositing the first mixed gas to form an amorphous silicon layer, wherein each of the different gases is deposited through different channels and then mixed, thereby being in the buffer layer
  • An amorphous silicon film doped with boron or phosphorus ions is formed on 302.
  • the amorphous silicon thin film layer is then dehydrogenated by chemical vapor deposition of a second mixed gas.
  • the first mixed gas and the amorphous silicon thin film layer formed by doping the ion gas are dehydrogenated by depositing a second mixed gas composed of phosphorus hydrogen or boron hydrogen.
  • the amorphous silicon thin film layer after dehydrogenation is annealed to diffuse the dopant ions to form a polysilicon layer 303.
  • the amorphous silicon thin film layer after dehydrogenation is subjected to excimer laser annealing to make the doped ions, ie, boron ions and Phosphorus ions are diffused to form a polysilicon layer 303.
  • the polysilicon layer After forming the polysilicon layer 303, in order to form a complete array substrate, the polysilicon layer needs to be patterned.
  • light is deposited on the polysilicon layer 303 by chemical deposition or by physical deposition. Resisting, forming a photoresist layer, and exposing and developing the photoresist layer. wherein, in this exposure process, only a photomask is used, and the light is used by using a special mask having both a mask and a half mask. Block exposure and development.
  • the specific shape of the mask and the area occupied by each part can also be set according to actual needs, which is not limited herein.
  • the phosphorus doped layer 3032 of the polysilicon layer 303 is etched according to the processed photoresist shape to pattern the phosphorus doped layer 3032.
  • the photoresist layer and the phosphorus doped layer 3032 are further exposed and developed, and the phosphorus doped layer 3032 and the boron doped layer 3031 are again etched, so that the phosphorus doped layer 3032 and the boron doped layer 3031 are patterned again.
  • the array substrate further includes a gate insulating layer 304 deposited on the polysilicon layer 303, and a gate electrode 305 on the gate insulating layer 304.
  • the array substrate further includes an interlayer insulating layer 306 overlying the gate insulating layer 304 and the gate 305.
  • the interlayer insulating layer 306 further includes a source 307 and a drain 308 separated by a channel.
  • a flat layer 309 is also covered on the surface of the source 307, the drain 308, and the interlayer insulating layer 306, and the surface of the flat layer 309 is further formed with an electrode 310.
  • the array substrate of the present embodiment can not only simplify the process of introducing gas by simultaneously introducing the first mixed gas and the boron hydrogen or phosphorus hydrogen-doped ion gas into the doped amorphous silicon thin film layer. This saves time and, in addition, reduces the number of masks and also saves doping equipment. Moreover, by doping with a gas, the doping can be made more uniform, and the electrical properties of the low-temperature polysilicon array substrate can be improved.
  • FIG. 4 is a schematic structural view of an embodiment of a display panel of the present invention.
  • the display panel of the present embodiment includes an array substrate 401 and a color filter substrate 402 disposed opposite to each other, and further includes The liquid crystal layer 403 between the array substrate 401 and the color filter substrate 402.
  • the array substrate 401 includes a substrate and a buffer layer and a polysilicon layer which are sequentially formed on the substrate.
  • the doped amorphous silicon thin film layer is formed on the buffer layer by means of meteorological deposition of the first mixed gas and the doped ion gas, and the amorphous silicon thin film is formed by means of meteorological deposition of a second mixed gas.
  • the layer is dehydrogenated and annealed to form the dopant ions.
  • the substrate includes a glass substrate.
  • the substrate may be another substrate, such as a quartz substrate, which is not limited herein.
  • a light shielding layer is formed on the substrate.
  • a buffer layer is formed on the light shielding layer.
  • the buffer layer is formed by depositing a SiN x layer on the light shielding layer and depositing a SiO x layer on the SiN x layer, followed by a SiN x layer and an SiO x layer.
  • the above-mentioned light shielding layer, SiN x layer and SiO x layer can be realized by chemical vapor deposition CVD or physical vapor deposition of PVD.
  • the polysilicon layer is formed by first introducing a first mixed gas of SiH 4 , Ar, H 2 and a boron hydride or phosphorous hydrogen on the buffer layer by chemical vapor deposition.
  • the ionic gas forms a doped amorphous silicon thin film layer. That is, a boron-hydrogen or phosphorous-hydrogen-doped ion gas is introduced while the first mixed gas is introduced to form an amorphous silicon layer, wherein each of the different gases is introduced through different channels and then mixed, thereby An amorphous silicon film doped with boron or phosphorus ions is formed on the buffer layer.
  • a second mixed gas is introduced into the amorphous silicon film layer by chemical vapor deposition, and the amorphous silicon thin film layer is dehydrogenated.
  • the amorphous silicon thin film layer is dehydrogenated by introducing a second mixed gas of phosphorus hydrogen or boron hydrogen onto the amorphous silicon film layer formed of the first mixed gas and the doped ion gas.
  • the amorphous silicon thin film layer after dehydrogenation is annealed to diffuse the dopant ions to form a polysilicon layer.
  • the amorphous silicon thin film layer after dehydrogenation is subjected to excimer laser annealing to make the doped ions, ie, boron ions and Phosphorus ions diffuse to form a polysilicon layer.
  • the polysilicon layer After forming the polysilicon layer, in order to form a complete array substrate, the polysilicon layer needs to be patterned.
  • the photoresist is deposited on the polysilicon layer by chemical deposition or by physical deposition. A photoresist layer is formed, and the photoresist layer is exposed and developed. Among them, this exposure process, only need to use a mask, through the use of both masks A special mask of the mold and half mask exposes and develops the photoresist.
  • the specific shape of the mask and the area occupied by each part may be set according to actual needs, and are not limited herein.
  • the phosphorus-doped layer of the polysilicon layer is etched according to the processed photoresist shape to pattern the phosphor-doped layer.
  • the photoresist layer and the phosphor-doped layer are further exposed and developed, and the phosphor-doped layer and the boron-doped layer are again etched to pattern the phosphor-doped layer and the boron-doped layer again.
  • the array substrate further includes a gate insulating layer deposited on the polysilicon layer, and a gate on the gate insulating layer.
  • the array substrate further includes an interlayer insulating layer covering the gate insulating layer and the gate, and the interlayer insulating layer further includes a source and a drain separated by a channel.
  • a flat layer is further covered on the surfaces of the source, the drain, and the interlayer insulating layer, and an electrode is further formed on the surface of the flat layer.
  • the array substrate of the present embodiment can not only simplify the process of introducing gas by simultaneously introducing the first mixed gas and the boron hydrogen or phosphorus hydrogen-doped ion gas into the doped amorphous silicon thin film layer. This saves time and, in addition, reduces the number of masks and also saves doping equipment. Moreover, by doping with a gas, the doping can be made more uniform, and the electrical properties of the low-temperature polysilicon array substrate can be improved.

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Abstract

公开了一种低温多晶硅阵列基板的制备方法，包括：设置一基板（200），并在基板（200）上形成缓冲层（202）；采用气象沉积第一混合气体以及掺杂离子气体的方式，在缓冲层（202）上形成掺杂的非晶硅薄膜层；采用气象沉积第二混合气体的方式，对非晶硅薄膜层进行去氢；对去氢后的非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层（203）；将多晶硅层（203）图案化。这种制备方法能够有效简化低温多晶硅阵列基板制造的工艺，减少制造设备的投入，降低制备成本。还公开了一种阵列基板和一种显示面板。

Description

低温多晶硅阵列基板的制备方法、阵列基板以及显示面板 【技术领域】
本发明涉及液晶显示领域，特别是涉及一种低温多晶硅阵列基板的制备方法、阵列基板以及显示面板。
【背景技术】
伴低温多晶硅技术LTPS(Low Temperature Poly-silicon)目前正迅速的发展，它的最大优势在于超薄、重量轻、低耗电，可以提供更艳丽的色彩和更清晰的影像。
在LTPS阵列基板的制作过程中，在进行参杂时，一般是先形成多晶硅层，然后再进行通道参杂、N型参杂以及P型掺杂，不仅操作过程由于制程多而过于复杂，而且，每进行一次参杂都必须经过一次光罩，提高了整个制作工艺的成本。
【发明内容】
本发明主要解决的技术问题是提供一种低温多晶硅阵列基板的制备方法、阵列基板以及显示面板，能够有效降低低温多晶硅阵列基板制造的工艺，较少了制造设备的投入，进一步降低了制备成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种低温多晶硅阵列基板的制备方法，所述制备方法包括：
设置一基板，并在所述基板上形成缓冲层；
采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层；
采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢；
对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层；
将所述多晶硅层图案化。
其中，所述采用气象沉积第一混合气体以及掺杂离子气体的方式，在所 述缓冲层上形成掺杂的非晶硅薄膜层的步骤具体包括：
通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层。其中，
所述采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢的步骤具体包括：
通过化学气相沉积磷氢或硼氢构成的第二混合气体的方式，对所述非晶硅薄膜层进行去氢。
其中，所述对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层的步骤具体包括：
对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子扩散，以形成多晶硅层。
其中，所述将所述多晶硅层图案化的步骤具体包括：
在所述多晶硅层上沉积光阻，通过一道光罩采用同时具有掩膜和半掩膜的掩模板对所述光阻进行曝光以及显影处理；
根据处理后的光阻形状对所述多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化；
再次对所述光阻进行曝光以及显影处理，对位于所述掺磷层下方的掺硼层进行刻蚀，使所述掺硼层图案化。
其中，所述设置一基板，并在所述基板上形成缓冲层的步骤具体包括：
设置所述第一基板，并在所述第一基板上形成遮光层；
在所述遮光层上沉积SiNx层；
在所述SiNx层上沉积SiOx层，其中，所述SiNx层以及所述SiOx层构成所述缓冲层。
其中，所述将所述多晶硅层图案化的步骤之后还包括：
在图案化后的多晶硅层上沉积栅极绝缘层，并在所述栅极绝缘层上形成栅极；
在所述栅极以及栅极绝缘层的表面沉积层间绝缘层，并在所述层间绝缘层上形成以一沟道分隔开的源极和漏极；
在所述源极、所述漏极以及层间绝缘层的表面覆盖平坦层，并在所述平坦层的表面形成电极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，
基板以及依次形成在所述基板上的缓冲层以及多晶硅层；
其中，所述多晶硅层是在采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层，采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢，以及退火处理使参杂离子扩散后形成的。
其中，所述非晶硅薄膜层具体通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在所述缓冲层上形成的。
其中，所述非晶硅薄膜层具体通过化学气相沉积磷氢或硼氢构成的第二混合气体的方式，进行去氢。
其中，所述多晶硅层具体由对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子扩散形成。
其中，所述多晶硅层还通过在所述多晶硅层上沉积光阻，通过一道光罩采用同时具有掩膜和半掩膜的掩模板对所述光阻进行曝光以及显影处理；并根据处理后的光阻形状对所述多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化；再次对所述光阻进行曝光以及显影处理，对位于所述掺磷层下方的掺硼层进行刻蚀，使所述掺硼层图案化，以实现所述多晶硅层的图像化。
其中，所述阵列基板还包括在所述基板上形成的遮光层，所述缓冲层具体通过在所述遮光层上沉积SiNx层，并在所述SiNx层上沉积SiOx层，以由所述SiNx层以及所述SiOx层构成的。
其中，所述阵列基板还包括在所述多晶硅层上沉积的栅极绝缘层、在所述栅极绝缘层上形成的栅极、在所述栅极以及栅极绝缘层的表面沉积的层间绝缘层、在所述层间绝缘层上形成的以一沟道分隔开的源极和漏极、在所述源极、所述漏极以及层间绝缘层的表面覆盖额平坦层、以及在所述平坦层的表面形成的电极。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种阵列基板显示面板，所述显示面板包括阵列基板，其中，所述阵列基板包括：
基板以及依次形成在所述基板上的缓冲层以及多晶硅层；
其中，所述多晶硅层是采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层，采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢，以及退火处理使参杂离子扩散后形成的。
其中，所述非晶硅薄膜层具体通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在所述缓冲层上形成的。
其中，所述非晶硅薄膜层具体通过化学气相沉积磷氢或硼氢构成的第二混合气体的方式，进行去氢。
其中，所述多晶硅层具体由对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子扩散形成。
其中，所述多晶硅层还通过在所述多晶硅层上沉积光阻，通过一道光罩采用同时具有掩膜和半掩膜的掩模板对所述光阻进行曝光以及显影处理；并根据处理后的光阻形状对所述多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化；再次对所述光阻进行曝光以及显影处理，对位于所述掺磷层下方的掺硼层进行刻蚀，使所述掺硼层图案化，以实现所述多晶硅层的图像化。
其中，所述阵列基板还包括在所述基板上形成的遮光层，所述缓冲层具体通过在所述遮光层上沉积SiNx层，并在所述SiNx层上沉积SiOx层，以由所述SiNx层以及所述SiOx层构成的。
其中，所述阵列基板还包括在所述多晶硅层上沉积的栅极绝缘层、在所述栅极绝缘层上形成的栅极、在所述栅极以及栅极绝缘层的表面沉积的层间绝缘层、在所述层间绝缘层上形成的以一沟道分隔开的源极和漏极、在所述源极、所述漏极以及层间绝缘层的表面覆盖额平坦层、以及在所述平坦层的表面形成的电极。
本发明的有益效果是：区别于现有技术的情况，本实施方式在基板上形成缓冲层，采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层；采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢；对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层，并对该多晶硅层图案化。上述方式中，通过将第一混合气体与硼氢或磷氢参杂离子气体同时通入形成掺杂 的非晶硅薄膜层的方式不仅能够简化通入气体的程序，节省时间，而且，能够减少光罩次数，而且，也节省了掺杂设备。且通过通入气体的方式进行掺杂，也能够使得参杂的更加均匀，改善低温多晶硅阵列基板的电性。
【附图说明】
图1是本发明低温多晶硅阵列基板的制备方法一实施方式的流程示意图；
图2A是图1低温多晶硅阵列基板第一具体实施方式的机构示意图；
图2B是图1低温多晶硅阵列基板第二具体实施方式的机构示意图；
图2C是图1低温多晶硅阵列基板第三具体实施方式的机构示意图；
图2D是图1低温多晶硅阵列基板第四具体实施方式的机构示意图；
图2E是图1低温多晶硅阵列基板第五具体实施方式的机构示意图；
图3是本发明阵列基板一实施方式的结构示意图；
图4是本发明显示面板一实施方式的结构示意图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
参阅图1，图1是本发明低温多晶硅阵列基板的制备方法一实施方式的流程示意图。同时参阅图2A～图2E对应的低温多晶硅阵列基板的结构示意图，本实施方式的制作方法包括以下步骤：
101：设置一基板200，并在所述基板200上形成缓冲层202。
其中，该基板200包括玻璃基板，在其他实施方式中还可以为其他基板如石英基板，在此不做限定。
具体地，首先设置第一基板200，先在第一基板200上形成遮光层201，然后在该遮光层上沉积SiNx层2021，再在SiNx层2021上沉积SiOx层2022， 其中，所述SiNx层2021以及所述SiOx层2022构成所述缓冲层202。
其中，上述的遮光层201、SiNx层2021以及SiOx层2022均可通过化学气相沉积CVD或物理气相沉积PVD的方式来实现。
102：采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层202上形成掺杂的非晶硅薄膜层。
具体地，采用化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在在缓冲层202上形成掺杂的非晶硅薄膜层。
即在沉积第一混合气体形成非晶硅层的同时沉积硼氢或磷氢参杂离子气体，其中，每一种不同的气体均通过不同的通道进行通入后再进行混合，从而在该缓冲层202上形成掺杂了硼或磷离子的非晶硅薄膜。在具体的实施方式中，先通入硼氢参杂离子气体或先通入磷氢参杂离子气体的顺序不做限定，本实施方式中以先通入硼氢参杂离子气体再通入磷氢参杂离子气体为例来说明。
在具体的实施方式中，通过化学气相沉积的方式形成掺杂的非晶硅薄膜层。在其他实施方式中，也可以通过物理气相沉积的方式形成掺杂的非晶硅薄膜层，在此不做限定。
上述将第一混合气体与硼氢或磷氢参杂离子气体同时通入形成掺杂的非晶硅薄膜层的方式不仅能够简化通入气体的程序，节省时间，而且，能够减少光罩次数，而且，也节省了掺杂设备。且通过通入气体的方式进行掺杂，也能够使得参杂的更加均匀，改善低温多晶硅阵列基板的电性。
103：采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢。
具体地，在第一混合气体以及掺杂离子气体形成的非晶硅膜层上沉积磷氢或硼氢构成的第二混合气体，对所述非晶硅薄膜层进行去氢。
在具体的实施方式中，通过化学气相沉积的方式通入磷氢或硼氢构成的第二混合气体。在其他实施方式中，也可以通过物理气相沉积的方式来实现，在此不做限定。
104：对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层203。
具体地，为了使去氢后的非晶硅薄膜层的晶格更加均匀化，还需进一步地对该对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层203。
在具体的实施方式中，对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子即硼离子和磷离子扩散，以形成多晶硅层203。如图2A所示，形成掺硼层2031以及掺磷层2032。
105：将所述多晶硅层图案化。
具体地，在形成多晶硅层203后，在该多晶硅层203上通过化学沉积的方式或通过物理沉积的方式沉积光阻，形成光阻层204，并对该光阻层204进行曝光以及显影处理如2B所示，其中，本次曝光过程，只需采用一道光罩，通过使用同时具有掩模和半掩模的特殊掩模板100对该光阻进行曝光和显影，使其得到预定的形状如图2C所示，其中，如图2B所示，掩模板101的1011部分为完全透光掩模，该部分光能够完全透过，1012部分为半掩模，该部分只有部分光能透过，1013部分为掩模，光完全不能透过。其中，该掩模板100的具体形状以及各部分所占的面积也可以根据实际需要来设定，在此不做限定。
再根据处理后的光阻形状对该多晶硅层203的掺磷层2032进行刻蚀，使所述掺磷层2032图案化。如图2D所示。
再次对光阻层204和掺磷层2032进一步进行曝光以及显影处理，并再次对掺磷层2032以及掺硼层2031进行刻蚀，使该掺磷层2032以及掺硼层2031再次被图案化，如图2E所示。
为了制备完整的低温多晶硅阵列基板，在对多晶硅层204完成图案化后，进一步地，在图案化后的多晶硅层上沉积栅极绝缘层，并在所述栅极绝缘层上形成栅极。
其中，所述栅极绝缘层包括氮化硅SiNx，非晶氧化硅SiOx中的至少一种，在其他实施方式中，也可以为其他绝缘物质，在此不做限定。
然后再在栅极以及栅极绝缘层的表面沉积层间绝缘层，并在所述层间绝缘层上形成以一沟道分隔开的源极和漏极。
在所述源极、所述漏极以及层间绝缘层的表面覆盖平坦层，并在所述平坦层的表面形成电极。
区别于现有技术，本实施方式在基板上形成缓冲层，采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层；采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢。对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层，并对该多晶硅层图案化。上述方式中，通过将第一混合气体与硼氢或磷氢参杂离子气体同时通入形成掺杂的非晶硅薄膜层的方式不仅能够简化通入气体的程序，节省时间，而且，能够减少光罩次数，而且，也节省了掺杂设备。且通过通入气体的方式进行掺杂，也能够使得参杂的更加均匀，改善低温多晶硅阵列基板的电性。
参阅图3，图3是本发明阵列基板一实施方式的结构示意图。如图3所示，本实施方式的阵列基板包括基板301以及依次形成在基板300上的缓冲层302以及多晶硅层303。
其中，所述多晶硅层303是在采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层303上形成掺杂的非晶硅薄膜层，采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢，以及退火处理使参杂离子扩散后形成的。
其中，该基板300包括玻璃基板，在其他实施方式中还可以为其他基板如石英基板，在此不做限定。该基板300上形成有遮光层301。缓冲层302形成在该遮光层301上。
在具体的实施方式中，该缓冲层302是先在该遮光层上沉积SiNx层3021，再在SiNx层3021上沉积SiOx层3022后，由SiNx层3021以及SiOx层3022所构成的。
其中，上述的遮光层301、SiNx层3021以及SiOx层3022均可通过化学气相沉积CVD或物理气相沉积PVD的方式来实现。
在具体的实施方式中，多晶硅层303是通过如下方式形成的：先通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在缓冲层302上形成掺杂的非晶硅薄膜层。即在沉积第一混合气体形成非晶硅层的同时沉积硼氢或磷氢参杂离子气体，其中，每一种不同的气体均通过不同的通道进行沉积后再进行混合，从而在该缓冲层302上形成掺杂了硼或磷离子的非晶硅薄膜。然后再通过化学气相沉积第二混 合气体的方式，对所述非晶硅薄膜层进行去氢。具体地，通过沉积磷氢或硼氢构成的第二混合气体对第一混合气体以及掺杂离子气体形成的非晶硅薄膜层进行去氢。最后再对对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层303。具体地，为了使去氢后的非晶硅薄膜层的晶格更加均匀化，对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子即硼离子和磷离子扩散，以形成多晶硅层303。
在在形成多晶硅层303后，为了形成完整的阵列基板，还需对该多晶硅层图案化，在具体的实施方式中，在该多晶硅层303上通过化学沉积的方式或通过物理沉积的方式沉积光阻，形成光阻层，并对该光阻层进行曝光以及显影处理.其中，本次曝光过程，只需采用一道光罩，通过使用同时具有掩模和半掩模的特殊掩模板对该光阻进行曝光和显影。其中，该掩模板的具体形状以及各部分所占的面积也可以根据实际需要来设定，在此不做限定.
再根据处理后的光阻形状对该多晶硅层303的掺磷层3032进行刻蚀，使所述掺磷层3032图案化。再次对光阻层和掺磷层3032进一步进行曝光以及显影处理，并再次对掺磷层3032以及掺硼层3031进行刻蚀，使该掺磷层3032以及掺硼层3031再次被图案化。
进一步地，如图3所示，该阵列基板还包括沉积在该多晶硅层303上的栅极绝缘层304，以及栅极绝缘层304上的栅极305。该阵列基板还包括覆盖在该栅极绝缘层304以及栅极305上的层间绝缘层306，该层间绝缘层306上还包括以一沟道分隔开的源极307和漏极308。在源极307、漏极308以及层间绝缘层306的表面上还覆盖有平坦层309，且该平坦层309的表面还形成有电极310。
区别于现有技术，本实施方式的阵列基板通过将第一混合气体与硼氢或磷氢参杂离子气体同时通入形成掺杂的非晶硅薄膜层的方式不仅能够简化通入气体的程序，节省时间，而且，能够减少光罩次数，而且，也节省了掺杂设备。且通过通入气体的方式进行掺杂，也能够使得参杂的更加均匀，改善低温多晶硅阵列基板的电性。
参阅图4，图4是本发明显示面板一实施方式的结构示意图。本实施方式的显示面板包括相对设置的阵列基板401、彩膜基板402，还包括设置在 该阵列基板401以及彩膜基板402之间的液晶层403。
阵列基板401包括：基板以及依次形成在所述基板上的缓冲层以及多晶硅层。其中，采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层，采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢，以及退火处理使参杂离子扩散后形成的。
其中，该基板包括玻璃基板，在其他实施方式中还可以为其他基板如石英基板，在此不做限定。该基板上形成有遮光层。缓冲层形成在该遮光层上。
在具体的实施方式中，该缓冲层是先在该遮光层上沉积SiNx层，再在SiNx层上沉积SiOx层后，由SiNx层以及SiOx层所构成的。
其中，上述的遮光层、SiNx层以及SiOx层均可通过化学气相沉积CVD或物理气相沉积PVD的方式来实现。
在具体的实施方式中，多晶硅层是通过如下方式形成的：先通过化学气相沉积的方式在缓冲层上通入SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体，形成掺杂的非晶硅薄膜层。即在通入第一混合气体形成非晶硅层的同时通入硼氢或磷氢参杂离子气体，其中，每一种不同的气体均通过不同的通道进行通入后再进行混合，从而在该缓冲层上形成掺杂了硼或磷离子的非晶硅薄膜。然后再通过化学气相沉积的方式在非晶硅膜层上通入第二混合气体，对所述非晶硅薄膜层进行去氢。具体地，在第一混合气体以及掺杂离子气体形成的非晶硅膜层上通入磷氢或硼氢构成的第二混合气体对非晶硅薄膜层进行去氢。最后再对对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层。具体地，为了使去氢后的非晶硅薄膜层的晶格更加均匀化，对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子即硼离子和磷离子扩散，以形成多晶硅层。
在在形成多晶硅层后，为了形成完整的阵列基板，还需对该多晶硅层图案化，在具体的实施方式中，在该多晶硅层上通过化学沉积的方式或通过物理沉积的方式沉积光阻，形成光阻层，并对该光阻层进行曝光以及显影处理。其中，本次曝光过程，只需采用一道光罩，通过使用同时具有掩 模和半掩模的特殊掩模板对该光阻进行曝光和显影。其中，该掩模板的具体形状以及各部分所占的面积也可以根据实际需要来设定，在此不做限定。
再根据处理后的光阻形状对该多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化。再次对光阻层和掺磷层进一步进行曝光以及显影处理，并再次对掺磷层以及掺硼层进行刻蚀，使该掺磷层以及掺硼层再次被图案化。
进一步地，该阵列基板还包括沉积在该多晶硅层上的栅极绝缘层，以及栅极绝缘层上的栅极。该阵列基板还包括覆盖在该栅极绝缘层以及栅极上的层间绝缘层，该层间绝缘层上还包括以一沟道分隔开的源极和漏极。在源极、漏极以及层间绝缘层的表面上还覆盖有平坦层，且该平坦层的表面还形成有电极。
区别于现有技术，本实施方式的阵列基板通过将第一混合气体与硼氢或磷氢参杂离子气体同时通入形成掺杂的非晶硅薄膜层的方式不仅能够简化通入气体的程序，节省时间，而且，能够减少光罩次数，而且，也节省了掺杂设备。且通过通入气体的方式进行掺杂，也能够使得参杂的更加均匀，改善低温多晶硅阵列基板的电性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板包括：
    基板以及依次形成在所述基板上的缓冲层以及多晶硅层；
    其中，所述多晶硅层是通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层，采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢，以及退火处理使参杂离子扩散后形成的；
    所述阵列基板还包括在所述多晶硅层上沉积的栅极绝缘层、在所述栅极绝缘层上形成的栅极、在所述栅极以及栅极绝缘层的表面沉积的层间绝缘层、在所述层间绝缘层上形成的以一沟道分隔开的源极和漏极、在所述源极、所述漏极以及层间绝缘层的表面覆盖额平坦层、以及在所述平坦层的表面形成的电极。
  2. 根据权利要求1所述的显示面板，其中，所述非晶硅薄膜层具体通过化学气相沉积磷氢或硼氢构成的第二混合气体的方式，进行去氢。
  3. 根据权利要求1所述的显示面板，其中，所述多晶硅层具体由对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子扩散形成。
  4. 根据权利要求1所述的显示面板，其中，所述多晶硅层还通过在所述多晶硅层上沉积光阻，通过一道光罩采用同时具有掩膜和半掩膜的掩模板对所述光阻进行曝光以及显影处理；并根据处理后的光阻形状对所述多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化；再次对所述光阻进行曝光以及显影处理，对位于所述掺磷层下方的掺硼层进行刻蚀，使所述掺硼层图案化，以实现所述多晶硅层的图像化。
  5. 根据权利要求1所述的显示面板，其中，所述阵列基板还包括在所述基板上形成的遮光层，所述缓冲层具体通过在所述遮光层上沉积SiNx层，并在所述SiNx层上沉积SiOx层，以由所述SiNx层以及所述SiOx层构成的。
  6. 一种低温多晶硅阵列基板的制备方法，其中，所述制备方法包括：
    设置一基板，并在所述基板上形成缓冲层；
    采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层；
    采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢；
    对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层；
    将所述多晶硅层图案化。
  7. 根据权利要求6所述的制备方法，其中，所述采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层的步骤具体包括：
    通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层。
  8. 根据权利要求7所述的制备方法，其中，所述采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢的步骤具体包括：
    通过化学气相沉积磷氢或硼氢构成的第二混合气体的方式，对所述非晶硅薄膜层进行去氢。
  9. 根据权利要求6所述的制备方法，其中，所述对去氢后的所述非晶硅薄膜层进行退火处理，使参杂离子扩散，以形成多晶硅层的步骤具体包括：
    对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子扩散，以形成多晶硅层。
  10. 根据权利要求6所述的制备方法，其中，所述将所述多晶硅层图案化的步骤具体包括：
    在所述多晶硅层上沉积光阻，通过一道光罩采用同时具有掩膜和半掩膜的掩模板对所述光阻进行曝光以及显影处理；
    根据处理后的光阻形状对所述多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化；
    再次对所述光阻进行曝光以及显影处理，对位于所述掺磷层下方的掺硼层进行刻蚀，使所述掺硼层图案化。
  11. 根据权利要求6所述的制备方法，其中，所述设置一基板，并在所述基板上形成缓冲层的步骤具体包括：
    设置所述第一基板，并在所述第一基板上形成遮光层；
    在所述遮光层上沉积SiNx层；
    在所述SiNx层上沉积SiOx层，其中，所述SiNx层以及所述SiOx层构成所述缓冲层。
  12. 根据权利要求6所述的制备方法，其中，所述将所述多晶硅层图案化的步骤之后还包括：
    在图案化后的多晶硅层上沉积栅极绝缘层，并在所述栅极绝缘层上形成栅极；
    在所述栅极以及栅极绝缘层的表面沉积层间绝缘层，并在所述层间绝缘层上形成以一沟道分隔开的源极和漏极；
    在所述源极、所述漏极以及层间绝缘层的表面覆盖平坦层，并在所述平坦层的表面形成电极。
  13. 一种阵列基板，其中，所述阵列基板包括；
    基板以及依次形成在所述基板上的缓冲层以及多晶硅层；
    其中，所述多晶硅层是在采用气象沉积第一混合气体以及掺杂离子气体的方式，在所述缓冲层上形成掺杂的非晶硅薄膜层，采用气象沉积第二混合气体的方式，对所述非晶硅薄膜层进行去氢，以及退火处理使参杂离子扩散后形成的。
  14. 根据权利要求13所述的阵列基板，其中，所述非晶硅薄膜层具体通过化学气相沉积SiH4、Ar、H2组成的第一混合气体以及硼氢或磷氢参杂离子气体的方式，在所述缓冲层上形成的。
  15. 根据权利要求14所述的阵列基板，其中，所述非晶硅薄膜层具体通过化学气相沉积磷氢或硼氢构成的第二混合气体的方式，进行去氢。
  16. 根据权利要求13所述的阵列基板，其中，所述多晶硅层具体由对去氢后的所述非晶硅薄膜层使用准分子镭射退火的方式使所述掺杂离子扩散形成。
  17. 根据权利要求13所述的阵列基板，其中，所述多晶硅层还通过在所述多晶硅层上沉积光阻，通过一道光罩采用同时具有掩膜和半掩膜的掩模板对所述光阻进行曝光以及显影处理；并根据处理后的光阻形状对所述多晶硅层的掺磷层进行刻蚀，使所述掺磷层图案化；再次对所述光阻进行曝光以及显影处理，对位于所述掺磷层下方的掺硼层进行刻蚀，使所述掺硼 层图案化，以实现所述多晶硅层的图像化。
  18. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括在所述基板上形成的遮光层，所述缓冲层具体通过在所述遮光层上沉积SiNx层，并在所述SiNx层上沉积SiOx层，以由所述SiNx层以及所述SiOx层构成的。
  19. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括在所述多晶硅层上沉积的栅极绝缘层、在所述栅极绝缘层上形成的栅极、在所述栅极以及栅极绝缘层的表面沉积的层间绝缘层、在所述层间绝缘层上形成的以一沟道分隔开的源极和漏极、在所述源极、所述漏极以及层间绝缘层的表面覆盖额平坦层、以及在所述平坦层的表面形成的电极。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108666218A (zh) * 2017-03-29 2018-10-16 京东方科技集团股份有限公司 薄膜晶体管和显示基板及其制作方法、显示装置
CN106960815B (zh) * 2017-05-05 2020-02-28 武汉华星光电技术有限公司 一种制作阵列基板的方法
CN108878537B (zh) 2017-05-12 2021-02-12 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示面板和显示装置
CN107505763A (zh) * 2017-09-25 2017-12-22 武汉华星光电技术有限公司 基板的制作方法、液晶面板的制作方法及液晶面板
CN108878539A (zh) * 2018-07-03 2018-11-23 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示面板
US11562903B2 (en) * 2019-01-17 2023-01-24 Ramesh kumar Harjivan Kakkad Method of fabricating thin, crystalline silicon film and thin film transistors
US11791159B2 (en) 2019-01-17 2023-10-17 Ramesh kumar Harjivan Kakkad Method of fabricating thin, crystalline silicon film and thin film transistors
CN111341794A (zh) * 2020-04-08 2020-06-26 武汉华星光电技术有限公司 显示面板、阵列基板及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540729A (zh) * 2003-04-25 2004-10-27 友达光电股份有限公司 低温多晶硅薄膜晶体管及其制造方法
CN101183643A (zh) * 2006-11-16 2008-05-21 索尼株式会社 薄膜半导体装置的制造方法
CN101409232A (zh) * 2007-10-12 2009-04-15 东京毅力科创株式会社 多晶硅膜的形成方法
CN104576399A (zh) * 2014-12-29 2015-04-29 昆山国显光电有限公司 一种薄膜晶体管及其制造方法
CN105140130A (zh) * 2015-09-29 2015-12-09 信利（惠州）智能显示有限公司 低温多晶硅薄膜晶体管及其制备方法
CN105304641A (zh) * 2015-09-24 2016-02-03 武汉华星光电技术有限公司 一种低温多晶硅tft阵列基板的制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540729A (zh) * 2003-04-25 2004-10-27 友达光电股份有限公司 低温多晶硅薄膜晶体管及其制造方法
CN101183643A (zh) * 2006-11-16 2008-05-21 索尼株式会社 薄膜半导体装置的制造方法
CN101409232A (zh) * 2007-10-12 2009-04-15 东京毅力科创株式会社 多晶硅膜的形成方法
CN104576399A (zh) * 2014-12-29 2015-04-29 昆山国显光电有限公司 一种薄膜晶体管及其制造方法
CN105304641A (zh) * 2015-09-24 2016-02-03 武汉华星光电技术有限公司 一种低温多晶硅tft阵列基板的制造方法
CN105140130A (zh) * 2015-09-29 2015-12-09 信利（惠州）智能显示有限公司 低温多晶硅薄膜晶体管及其制备方法

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