WO2018033374A1 - Schaltungsanordnung zur steuerung eines elektrischen verbrauchers - Google Patents
Schaltungsanordnung zur steuerung eines elektrischen verbrauchers Download PDFInfo
- Publication number
- WO2018033374A1 WO2018033374A1 PCT/EP2017/069260 EP2017069260W WO2018033374A1 WO 2018033374 A1 WO2018033374 A1 WO 2018033374A1 EP 2017069260 W EP2017069260 W EP 2017069260W WO 2018033374 A1 WO2018033374 A1 WO 2018033374A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit arrangement
- electrical load
- current
- threshold value
- clock divider
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
Definitions
- the invention relates to a circuit arrangement according to the preamble of claim 1, and a method according to the independent claim.
- the electrical load can be controlled such that a thermal overload of the electrical load is avoided.
- the invention relates to a circuit arrangement for controlling a
- the circuit arrangement comprises a forward-backward counter, and wherein the circuit arrangement is designed, depending on a count of the forward-backward Counter to generate a control signal for controlling the electrical load, in particular for switching off the electrical load.
- the circuit arrangement comprises a controllable clock divider circuit, by means of which the circuit arrangement is designed to specify a counting direction and a counting speed of the forward-backward counter in dependence on at least one an actual current and / or a nominal current of the electrical load characterizing size.
- An up-down counter is through a digital counter circuit
- the up-down counter is configured to be driven with a first and a second clock signal. If the first clock signal is active, the counter counts forward, if the second clock signal is active, the counter counts backwards. If none of the
- Said control signal for controlling the electrical load is preferably generated when the count of the forward-backward counter has reached or exceeded a predefinable overflow threshold.
- a count rate ("count frequency") of the up-down counter is defined by a time change of the count, which is generally characterized by a binary number. In a preferred embodiment, the count is changed by a value "one" with each clock step.
- the counting speed can be predetermined by the choice of a clock frequency and / or by the choice of a division factor characterizing the clock divider circuit.
- circuit arrangement to a control logic, which is adapted to the forward-backward counter in response to the at least one of the actual current and / or the rated current of the
- the electrical consumer can be any electrically operable
- Be device such as a solenoid, an electric motor, or the like.
- the electrical load can be switched by means of a semiconductor switch, in particular by means of a MOSFET (English: “metal oxide-semiconductor field-effect transistor”).
- MOSFET metal oxide-semiconductor field-effect transistor
- Circuit arrangement can be designed to take into account or simulate the thermal behavior of the electrical load and / or the semiconductor switch.
- the circuit arrangement is designed to take into account or emulate in particular the thermal behavior of the "weaker” or “more critical” element, for example of the MOSFET.
- the actual current of the electrical load can be determined for example by means of a comparatively low ohmic resistance, which is connected in an electrical supply line of the electrical load.
- a potential or a voltage can be detected at the resistor in proportion to the actual current.
- the potential or the voltage is the variable characterizing the actual current.
- the rated current is for example from a data sheet of the electrical
- the circuit arrangement is adapted to the counting direction and the counting speed of the up-down counter in response to at least one of the actual current and the rated current of the electric
- a difference can advantageously be formed as a function of the actual current and the nominal current, with a positive difference of the forward-backward counter counts forward and counts in negative difference of the forward-backward counter backwards. If the difference falls below a predefinable amount, the forward-backward counter (preferably) can be stopped, the count preserved.
- the said difference can for example be formed virtually by means of configuration of the clock divider circuit and therefore does not necessarily require an explicit subtraction of two currents or voltages.
- the circuit arrangement is designed to the
- the circuit arrangement performs at least approximately a (thermal) monitoring of the electrical load and / or a semiconductor switch controlling the electrical load according to the so-called "I 2 t principle".
- a square of the actual current (“I 2 ") characterizes a power consumed by the electrical load.
- the product of the square of the actual current over time (“l 2 t”) characterizes an energy absorbed by the electrical load, in particular a loss energy.
- the forward-backward counter allows, in particular, an integral formation over the said product "l 2 t" of the actual current or an integral formation over a difference of the products "l 2 t" of the actual current and of the
- circuit arrangement simulates, as it were, a thermal behavior of the electrical load or of the semiconductor switch.
- circuit arrangement is integrated
- the semiconductor integrated circuit executed or included in a semiconductor integrated circuit with.
- the semiconductor integrated circuit is, for example, an ASIC
- the invention has the advantage that an electrical consumer can be operated for a short time with a higher electrical power than the rated power. This concerns, for example, a start-up of the electrical load or a short-term peak load possible during operation. A possible thermal overload of the electrical consumer or the electrical
- the circuit arrangement can thanks to the controllable
- Clock divider circuit advantageously be realized using particularly simple digital switching elements.
- it is not necessary to explicitly square the variable characterizing the actual current, as will be explained in more detail below.
- the circuit arrangement is designed to at least one division factor of the controllable clock divider circuit in
- the counting speed (counting frequency) of the forward-backward counter can be preset in a particularly simple and cost-effective manner as a function of the actual current and / or the rated current.
- the division factor can be changed in steps by a factor of 2 in each case. This advantageously allows a particularly simple embodiment of the controllable clock divider circuit. Additionally or alternatively, it can be provided that the division factor is optionally variable by a factor of 2 or 4 or 8 or 16 or 32 or 64. The latter alternative may be advantageous, for example, if in one embodiment the clock divider circuit comprises only one clock divider by means of which the forward-backward counter can be clocked for both count directions.
- controllable clock divider circuit comprises a first and a second controllable clock divider, wherein the first controllable clock divider is adapted to the forward-backward counter for a
- Counting up counting and wherein the second controllable clock divider is adapted to clock the up-down counter for a count down.
- a control of the clock divider circuit can be particularly easily done, and a count speed of the forward-backward counter can be changed very flexible.
- the clock divider circuit comprises (only) a first clock divider, wherein the first clock divider is configured to clock the up-down counter at a clock input, and wherein the forward divider Reverse counter has at least one control input for a counting direction of the forward-backward counter, and wherein the forward-backward counter is adapted to count up or count down in response to the at least one control input or to hold a count.
- the count can be held by locking the one clock input of the up-down counter by means of a digital gate.
- the circuit arrangement is designed to compare the variable characterizing the actual current of the electrical load with a threshold value and to change the threshold value as a function of the comparison, and in particular also as a function of the threshold value itself.
- variable characterizing the actual current of the electrical load is a first potential, wherein the first potential is connected to a first input of a comparator, and wherein a second input of the comparator is connected to a second potential, and wherein the circuit arrangement is configured to change the second potential in dependence on the second potential itself and in dependence on an output signal of the comparator.
- the threshold value described above corresponds to the second potential or a voltage comparable thereto.
- the circuit arrangement is designed to predetermine the threshold value by selecting from a plurality of differently sized reference threshold values, wherein the circuit arrangement is further configured to then select a larger reference threshold relative to a current reference threshold value, if the actual current of the electrical load characterizing size greater than the threshold and then selecting a smaller reference threshold with respect to a current reference threshold if the magnitude characterizing the actual current of the electrical load is less than the threshold.
- a current value range for the variable characterizing the actual current of the electrical load can be determined.
- At least some, but preferably all, differently sized reference threshold values are continuous to one another at least approximately by a factor of approximately 42.
- this factor has a value between about 1, 3 and about 1, 6.
- this factor has a value between about 1, 2 and about 1, 7.
- this factor has a value between about 1, 1 and about 1, 9.
- the analog-to-digital conversion described above is thus preferably non-linear.
- Circuit arrangement can be advantageously realized using particularly simple digital switching elements.
- the circuit arrangement is designed to have at least one division factor of the controllable clock divider circuit as a function of a digital variable characterizing the threshold value
- the counting speed of the forward-backward counter can advantageously be predetermined by means of the division factor.
- circuitry is adapted to the
- the circuit arrangement is designed to switch off the electrical load (immediately) when the threshold value has reached a predefinable maximum reference threshold value.
- the electrical load and / or a semiconductor switch controlling the electrical load can advantageously be advantageously monitored and protected with respect to any overcurrent.
- the invention relates to a method for operating a
- Circuit arrangement for controlling an electrical load, wherein the circuit arrangement comprises a forward-backward counter, and wherein the
- Circuit arrangement in response to a count of the forward-backward counter, a control signal for controlling the electrical
- the circuit arrangement comprises a controllable
- Timing divider circuit by means of which the circuit arrangement specifies a counting direction and a counting speed of the forward-backward counter as a function of at least one variable that characterizes an actual current and / or a nominal current of the electrical load.
- Embodiment is the size characterizing the actual current a potential or a voltage.
- controllable comprises
- Clock divider circuit comprising a first and a second controllable clock divider, the method comprising at least one of the following steps:
- the first controllable clock divider clocks the up-down counter for
- the second controllable clock divider clocks the up-down counter for counting down
- the circuit arrangement outputs a division factor of the first and / or the second controllable clock divider in dependence on the at least one
- Characterizing size before, in particular, the division factor in stages by a factor of 2 is variable.
- the variable characterizing the actual current of the electrical load is given a threshold value compared, wherein depending on the comparison, and in particular also as a function of the threshold itself, the threshold value is changed.
- the threshold value is a potential or a
- the threshold value is predetermined by selection from a plurality of differently sized reference threshold values, wherein a reference threshold value greater than a current reference threshold value is selected if the variable characterizing the actual current of the electrical consumer is greater than the threshold value, and then selecting a smaller reference threshold with respect to a current reference threshold when the magnitude characterizing the actual current of the electrical load is less than the threshold.
- variable characterizing the actual current of the electrical load is a first potential, wherein the first potential is connected to a first input of a comparator, and wherein a second input of the comparator is connected to a second potential, and wherein the second potential is given in dependence on the second potential itself and an output signal of the comparator.
- the second potential is predetermined by selecting from a plurality of different sized reference potentials, wherein then a reference potential larger in relation to a current reference potential is selected, if the first potential is greater than the second potential, and then an in With respect to a current reference potential, smaller reference potential is selected when the first potential is less than the second potential.
- a digital variable is determined as a function of the threshold value or the second potential, and at least one division factor of the controllable clock divider circuit (or a first and a second clock divider of the clock divider circuit) is predetermined as a function of the digital variable.
- the digital size is determined by means of an analog-to-digital converter.
- Reference threshold greater reference threshold, if the
- Reference threshold smaller reference threshold, if the
- Delay times is performed to prevent uncontrolled oscillation of the threshold or the second potential.
- FIG. 1 shows an embodiment of a circuit arrangement for controlling an electrical load
- FIG. 2 shows a flowchart for a first method for operating the
- FIG. 3 shows a flow chart for a second method for operating the
- FIG. 1 shows a circuit arrangement 10 for controlling an electrical load 12, wherein the circuit arrangement 10 includes a forward-backward counter 14, and wherein the circuit arrangement 10 is adapted to a control signal depending on a count of the forward-backward counter 14 16 for controlling the electrical load 12, in particular for switching off the electrical load 12 to produce.
- the block represented in FIG. 1 by the reference numeral 12 has a semiconductor switch controlling the electrical load 12 and a low-resistance measuring resistor connected in series with it for the actual current.
- circuit arrangement 10 comprises a controllable
- Clock divider circuit 18 by means of which the circuit arrangement 10 is formed, a counting direction and a count speed of the forward-backward counter 14 in response to at least one of an actual current and / or a rated current of the electrical load 12th
- the circuit arrangement 10 is designed to predefine at least one division factor 24 of the controllable clock divider circuit 18 as a function of the at least one variable 20 or 22 characterizing the actual current and / or the rated current of the electrical load 12.
- the division factor 24 can be changed in steps by a factor of 2, in the present case from a factor of 1/1 to a factor of 1/64.
- the circuit arrangement 10 of Figure 1 includes the controllable
- Clock divider circuit 18 includes first and second controllable clock dividers 18a and 18b, wherein the first controllable clock divider 18a is adapted to clock the up-down counter 14 for up-counting, and wherein the second controllable clock divider 18b is adapted to forward-feed Reverse counter 14 to count down.
- a symbolic arrow 26 indicates a clock input of the up-down counter 14 for counting up
- a symbolic arrow 28 indicates a clock input of the up-down counter 14 for counting down.
- the circuit arrangement 10 comprises an (optional) prescaler 29, which is shown in FIG. 1 in an upper area.
- the prescaler 29 has eight divider stages, which enable a configurable pre-division of a clock input signal 31 in steps of 1/1, 1/2, 1/4 to 1/128.
- the thus pre-assigned clock input signal 31 is used as a clock signal 31 a for the first clock divider 18 a and as a clock signal 31 b for the second clock divider 18 b.
- a clock frequency of the clock signals 31 a and 31 b can be specified or configured.
- a configuration of the circuit arrangement 10 by means of a so-called "MSC bus" (Micro Second Bus).
- Horizontal dashed lines 33 below the prescaler 29 indicate that the clock division enabled by the prescaler 29 is configurable. In the present case, different clock frequencies can be predetermined for the clock signal 31 a and for the clock signal 31 b. By means of this configuration, the
- circuit 10 Operation of the circuit 10 is particularly well adapted to the operation of the clock divider 18a and 18b or particularly well to properties of the electrical load 12.
- the circuit arrangement 10 is designed to match the actual current of the electrical load 12
- Characterizing size 20 to be compared with a threshold value 30 and depending on the comparison, and in particular also as a function of the threshold value 30 itself, to change the threshold value 30.
- the circuit arrangement 10 is designed in this case, the
- Threshold 30 by selecting from a plurality of differently sized reference thresholds 30 ', wherein the circuit arrangement 10 is further adapted to then select a relation to a current reference threshold 30' larger reference threshold 30 ', when the actual current of the electrical load 12 characterizing size 20 is greater than the threshold value 30, and then select a reference threshold 30 'smaller in relation to a current reference threshold value 30', if the current 20 of the electrical load 12 characterizing size 20 is smaller than the threshold value 30.
- the circuit arrangement 10 of Figure 1 comprises a comparator 32 and a logic 34, which an output signal 32a of the comparator 32 is supplied.
- the current 20 characterizing the actual current is supplied to a non-inverting input of the comparator 32, and the threshold value 30 is supplied to an inverting input of the comparator 32.
- the size 20 and the threshold value 30 each correspond to an electrical potential or a voltage.
- Reference thresholds 30 ' are contiguous to one another at least approximately by a factor of approximately each time.
- the magnitude 20 characterizing the actual current and the reference threshold values 30 ' are each characterized by a voltage.
- the reference threshold values 30 ' are each characterized by a voltage.
- Reference Thresholds 30 continuously have values of 10mV (millivolts) / 15mV / 20mV / 30mV / 40mV / 60mV / 80mV / 1 10mV. For example, this is
- the circuit arrangement 10 of FIG. 1 is designed to predefine at least one division factor 24 of the controllable clock divider circuit 18 as a function of a digital variable 36 characterizing the threshold value 30. This is done by means of a control circuit 37.
- an arrow 38 indicates the respective one
- Dividing factors 1/64 to 1/1 in the drawing ascending from right to left associated reference thresholds 30 '. These have in the present example seven values 15mV / 20mV / 30mV / 40mV / 60mV / 80mV / 1 10mV.
- An eighth reference threshold value 30 'with the value 10 mV is characterized in the drawing to the right of the first clock divider 18a by an arrow and a mass symbol (in each case without reference numerals).
- an arrow 40 indicates the respective one
- Division factors 1/1 to 1/64 in the drawing from left to right increasing associated reference thresholds 30 ' have in the present example seven values 10mV / 15mV / 20mV / 30mV / 40mV / 60mV / 80mV.
- An eighth reference threshold value 30 'with the value 1 10mV is characterized in the drawing to the right of the second clock divider 18b by an arrow and a mass symbol (in each case without reference symbols).
- the drawn vertical arrow points to the nominal current of the electrical load 12 characterizing size 22 out.
- the size 22 is in the present example 30mV and is preferably the same for both clock dividers 18a and 18b. Compare to the above-described reference thresholds 30 ', which are assigned in ascending order along the arrows 38 and 40.
- the function of the control circuit 37 is illustrated by means of dashed lines and arrows.
- Dotted lines 37a and 37b which are drawn horizontally below the first and second clock divider 18a and 18b, respectively characterize a "multiplexer function" and a “tracking controller".
- seven downwardly directed arrows are shown at outputs of the first and second clock divider 18a and 18b, which can each be "contacted” by a circular symbol displaceable horizontally along the lines 37a and 37b.
- Counter 14 are connected for counting down.
- Respective binary values "1" and “0" shown above the horizontal arrows 38 and 40 represent an activation of the respective outputs of the first and second clock divider 18a and 18b which can be predetermined by means of a configuration.
- the binary value "1” means an activation, in which case the respective output, if it is contacted by the respective multiplexer function, transmits a clock signal divided according to the division factor 24 to the forward-backward counter 14.
- the binary value "0" means that no clock signal is transmitted to the forward-backward counter 14. This allows a comparatively flexible configuration of the clock dividers 18a and 18b.
- an up-counting, a down-counting or a holding state of the up-down counter 14 can be configured.
- a not desired for a particular output counting direction is per
- Counting direction is enabled by means of the specifiable binary value "1"
- the threshold value 30 is greater than the rated current
- Threshold 30 a division factor 24 correspondingly faster
- Said activation or deactivation of the outputs of the first and second clock divider 18a and 18b in conjunction with the associated reference threshold values 30 'and the multiplexer function ("tracking controller") is carried out, for example, according to the following rules: (1) The contacting (circle symbol) of the outputs is carried out for the first and second clock divider 18a and 18b in the example of FIG. 1 to exactly the same reference threshold values 30 '.
- the second output of the first clock divider 18a is contacted from the right, corresponding to a reference threshold value 30 'of 20 mV.
- the left third output of the second clock divider 18b is contacted, corresponding to a reference threshold value 30 'of likewise 20mV.
- the associated outputs of the first and second clock divider 18a and 18b are both deactivated, ie "0".
- the forward-backward counter 14 does not count but maintains its count.
- gate multiplexer circuits, programmable dividers, high-ohm control of outputs and the like
- the circuitry 10 includes only the first clock divider 18a, wherein the first clock divider 18a is configured to clock the up-down counter 14, and the forward-backward counter 14 has at least one control input for one Counting direction of the forward-backward counter 14, and wherein the forward-backward counter 14 is adapted to count up or count down in response to the at least one control input or a
- This embodiment is functionally equivalent to the embodiment of Figure 1, and allows the circuit structure if necessary to simplify. Activation of the multiplexer function described above may possibly be somewhat more complicated.
- the actual current of the electrical load 12 corresponds to the rated current, which is, for example, 2.5 amperes.
- the current 20 characterizing the actual current is thereby
- Threshold 30 is incremented using reference thresholds 30 'along the
- the threshold value 30 is now larger than the
- the threshold value 30 using the same speakerssschwelltone 30 'lowered by one level, in this case to a value of 20mV.
- the threshold value 30 is increased by one level using the same reference threshold values 30 ', ie (again) to a value of 30 mV. And so on.
- the threshold value 30 oscillates continuously between the two
- Reference thresholds 30 'of 20mV and 30mV In one embodiment of the
- Logic 34 is achieved by a predeterminable delay in logic 34, that a frequency of said oscillation, for example in the same
- Magnitude is how an expected rate of change of the actual current.
- the frequency of the oscillation is at least as great as the expected rate of change of the actual current.
- the digital quantity 36 corresponding to the oscillation is characterized alternately by the threshold values 30 of 20 mV and 30 mV. In an alternative embodiment, the digital quantity 36 is constantly characterized by the lower threshold 30 of 20mV. In an alternative Embodiment, digital size 36 is constant through the top
- Threshold 30 characterized by 30mV.
- Outputs with mutually equal threshold values 30 take place, in the example thus at 20 mV or 30 mV or alternately 20 mV and 30 mV. Accordingly, in the example for the first clock divider 18a, a division factor 24 of 1/32 or 1/16 or alternately 1/32 and 1/16 results. Accordingly, in the example for the second clock divider 18b, a division factor 24 of 1/4 or 1/8 or
- the up-down counter 14 counts down comparatively slowly (20mV) and the up-down counter 14, respectively keeps its current count (30mV), or the forward-backward counter 14 alternately counts backwards slowly and maintains its meter reading (20mV and 30mV).
- the contacting (circular symbol) of the first or second clock divider 18a and 18b by means of the multiplexer function only takes place when the associated output of the clock divider 18a or 18b is activated with a binary value "1". In this way, unnecessary selection operations on the respectively unnecessary clock divider 18a and 18b can be avoided, whereby the
- Arrow 22 characterizes. It is assumed in the present case that this current count is less than an overflow threshold of the forward-backward counter 14. Accordingly, the control signal 16 is inactive, and has, for example, a value "zero".
- the electrical load 12 can be controlled and operated by means of a drive signal 42 in a normal manner.
- control signal 16 and the drive signal 42 can be combined outside the electrical load 12 by means of a logic circuit or the like, so that the electrical load 12 or the electrical load 12
- triggering semiconductor switch is driven with the combined signal.
- the actual current of the electrical load 12 is smaller or is, for example, 1, 8 amps.
- the actual current characterizing size 20 is then
- the threshold 30 used in logic 34 oscillates between the two reference thresholds 30 'of 15mV and 20mV.
- the digital quantity 36 is accordingly characterized by a threshold value 30 of 15 mV or 20 mV or alternately by the threshold values 30 of 15 mV and 20 mV.
- the division factor 24 of the second clock divider 18b is 1/2 or 1/4 or alternately 1/2 and 1/4.
- the first clock divider 18a is inactive because of the binary values "0" configured for the threshold values 30 of 15mV and 20mV, respectively.
- the forward-backward counter 14 counts down continuously, either slowly (division factor 24 equal to 1/4) or medium-fast
- the control signal 16 is still inactive.
- the threshold value 30 and correspondingly the digital variable 36 at least approximately follow a time course of the Actual current characterizing size 20.
- the threshold value 30 runs the actual current of the electrical load 12 and the size 20, so to speak, "behind". In this case, the threshold value 30 generally oscillates in each case between two adjacent reference threshold values 30 '.
- the forward-backward counter 14 can now advance count, wherein a counting speed increases with increasing threshold value 30 disproportionately, in particular at least approximately quadratically.
- the control signal 16 becomes active, for example "one". Thereby, the electrical load 12 can be controlled and in particular switched off, whereby a possible thermal overload of the electrical load 12 and the semiconductor switch driving the electrical load 12 can be prevented.
- a thermal capacity and optionally other variables characterizing the electrical load 12 or the semiconductor switch, in particular thermal variables are characterized by corresponding parameters of the circuit arrangement 10. These parameters may include, for example, the characteristics of the prescaler 29 and the clock dividers 18a and 18b, as well as a maximum count range of the up-down counter 14 and a preset overflow threshold.
- the circuit arrangement 10 of Figure 1 allows at least approximately a (thermal) monitoring of the electrical load 12 according to the so-called "I 2 t principle".
- I 2 a square of the actual current
- the product of the square of the actual current characterizes with time (“l 2 t") an energy absorbed by the electrical load 12, in particular a loss energy.
- the forward-backward counter 14 in particular allows an integral formation over the said product "l 2 t".
- the reference threshold values 30 '- as described in FIG. 1 - are continuous with one another at least approximately by one factor at a time
- the circuit arrangement 10 can be advantageously realized using particularly simple digital switching elements.
- circuit arrangement 10 In a further embodiment, the circuit arrangement 10,
- logic 34 designed to monitor the electrical load 12 and / or a semiconductor switch controlling the electrical load 12 in addition to an excessively high actual current
- FIG. 2 shows, in addition to FIG. 1, a first flowchart for a
- Forward-reverse counter 14 includes, and wherein the circuit 10 in response to a count of the forward-backward counter 14, a control signal 16 for controlling the electrical load 12, in particular for switching off the electrical load 12, generates.
- the circuit arrangement 10 comprises a controllable clock divider circuit 18, by means of which the circuit arrangement 10 specifies a counting direction and a counting speed of the forward-backward counter 14 as a function of at least one an actual current and / or a nominal current of the electrical load 12 characterizing size 20, 22.
- the clock divider circuit 18 is configured according to the rated current of the electrical load 12.
- the (optional) prescaler 29 and the overflow threshold of the up-down counter 14 can be configured.
- the current 20 characterizing the actual current is determined.
- the method performed in block 1 10 is characterized by at least one of the following steps:
- the variable 20 characterizing the actual current of the electrical load 12 is compared with the threshold value 30, the threshold value 30 being changed as a function of the comparison, and in particular also as a function of the threshold value 30 itself.
- the threshold value 30 is predetermined by means of a selection from a plurality of differently sized reference threshold values 30 ', wherein a reference threshold value 30' greater than a current reference threshold value 30 'is selected if the variable 20 characterizing the actual current of the electrical load 12 is greater than the threshold value Threshold 30, and then a smaller reference threshold relative to a current reference threshold 30 '
- the method performed in block 120 is characterized by at least one of the following steps: the first controllable clock divider 18a clocks the up-down counter 14 for up-counting,
- the second controllable clock divider 18b clocks the up-down counter 14 for counting down
- the circuit arrangement 10 predetermines a division factor 24 of the first and / or the second controllable clock divider 18a or 18b as a function of the at least one variable 20, 22 characterizing the actual current and / or the rated current of the electrical load 12, in which case the division factor 24 gradually by a factor of 2 is variable.
- the binary values described above ensure that the forward
- Reverse counter 14 receives at most one clock signal from the clock dividers 18a and 18b.
- FIG. 3 shows a further embodiment of a method for operating the circuit arrangement 10 of FIG. 1. The following steps are carried out cyclically:
- step (f) Returning to step (a) or block 200 of the method.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020197007431A KR102307716B1 (ko) | 2016-08-17 | 2017-07-31 | 전기 부하의 제어를 위한 회로 장치 |
US16/325,620 US10958264B2 (en) | 2016-08-17 | 2017-07-31 | Circuit system for controlling an electrical consumer |
CN201780050274.3A CN109565273A (zh) | 2016-08-17 | 2017-07-31 | 用于控制耗电器的电路装置 |
AU2017312407A AU2017312407A1 (en) | 2016-08-17 | 2017-07-31 | Circuit arrangement for controlling an electrical consumer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102016215324.2 | 2016-08-17 | ||
DE102016215324.2A DE102016215324A1 (de) | 2016-08-17 | 2016-08-17 | Schaltungsanordnung zur Steuerung eines elektrischen Verbrauchers |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018033374A1 true WO2018033374A1 (de) | 2018-02-22 |
Family
ID=59683499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2017/069260 WO2018033374A1 (de) | 2016-08-17 | 2017-07-31 | Schaltungsanordnung zur steuerung eines elektrischen verbrauchers |
Country Status (6)
Country | Link |
---|---|
US (1) | US10958264B2 (de) |
KR (1) | KR102307716B1 (de) |
CN (1) | CN109565273A (de) |
AU (1) | AU2017312407A1 (de) |
DE (1) | DE102016215324A1 (de) |
WO (1) | WO2018033374A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017202191A1 (de) | 2017-02-13 | 2018-08-16 | Robert Bosch Gmbh | Schaltung und Verfahren zum Erkennen eines schleichenden Kurzschlusses bei Brückenschaltungen |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2244183A (en) * | 1990-05-16 | 1991-11-20 | Plessey Aerospace Limited | Control circuit for a solid state switching device |
WO2001045226A1 (en) * | 1999-12-17 | 2001-06-21 | Motorola Inc. | Overcurrent protection for the series fuse |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05184141A (ja) * | 1991-03-19 | 1993-07-23 | Canon Inc | 電源装置 |
TWI232017B (en) * | 1999-12-17 | 2005-05-01 | Motorola Inc | Overcurrent protection for the series fuse |
JP4161673B2 (ja) * | 2002-10-17 | 2008-10-08 | セイコーエプソン株式会社 | 電流検出回路 |
CN101566859B (zh) * | 2008-12-18 | 2011-06-22 | 昆山锐芯微电子有限公司 | 参考电压控制装置和方法、参考电压产生装置 |
CN204464953U (zh) * | 2015-01-13 | 2015-07-08 | 生迪光电科技股份有限公司 | 低温保护电路和电子装置 |
-
2016
- 2016-08-17 DE DE102016215324.2A patent/DE102016215324A1/de active Pending
-
2017
- 2017-07-31 WO PCT/EP2017/069260 patent/WO2018033374A1/de active Application Filing
- 2017-07-31 US US16/325,620 patent/US10958264B2/en active Active
- 2017-07-31 CN CN201780050274.3A patent/CN109565273A/zh active Pending
- 2017-07-31 KR KR1020197007431A patent/KR102307716B1/ko active IP Right Grant
- 2017-07-31 AU AU2017312407A patent/AU2017312407A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2244183A (en) * | 1990-05-16 | 1991-11-20 | Plessey Aerospace Limited | Control circuit for a solid state switching device |
WO2001045226A1 (en) * | 1999-12-17 | 2001-06-21 | Motorola Inc. | Overcurrent protection for the series fuse |
Also Published As
Publication number | Publication date |
---|---|
KR20190037331A (ko) | 2019-04-05 |
AU2017312407A1 (en) | 2019-04-11 |
DE102016215324A1 (de) | 2018-02-22 |
US20190190509A1 (en) | 2019-06-20 |
KR102307716B1 (ko) | 2021-10-01 |
US10958264B2 (en) | 2021-03-23 |
CN109565273A (zh) | 2019-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102017107517B4 (de) | Elektronische Schalt- und Schutzschaltung mit Aufweckfunktion | |
EP3161496B1 (de) | Verfahren zur erlangung eines hinweises, insbesondere eines anfangshinweises auf eine mögliche fehlerhafte lastbedingung eines mehrphasigen elektromotors | |
DE102017107520A1 (de) | Elektronische Schalt- und Schutzschaltung mit einem logarithmischen ADC | |
DE102017107521A1 (de) | Elektrische Schalt- und Schutzschaltung mit mehreren Betriebsarten | |
DE102017107523A1 (de) | Elektronische Schalt- und Schutzschaltung | |
DE3335220A1 (de) | Phasenregelschaltung fuer eine niederspannungslast | |
EP3417305B1 (de) | Batteriesensor, verfahren zum kalibrieren eines messwiderstands und verwendung | |
DE102007056956A1 (de) | Schaltung zur Regelung der Stromversorgung eines Verbrauchers und Verfahren zum Betrieb einer Schaltung | |
EP2850725B1 (de) | Verfahren zur regelung einer stromquelle, sowie stromquelle und prozessregler hierfür | |
DE102017107522A1 (de) | Elektronische Schalt- und Schutzschaltung mit Testbetriebsfunktion | |
EP3711162B1 (de) | Schutz eines in einem schaltbetrieb betriebenen feldeffekttransistors vor einem überlaststrom | |
DE102010044063A1 (de) | Nichtlinearer Regelkreis für DC/DC-Wandler | |
DE102014113443A1 (de) | Mehrphasen-Abwärtswandler mit einem dynamischen Phasenanschnitt | |
DE3346435A1 (de) | Schaltungsanordnung zum ein- und ausschalten sowie zum ueberwachen elektrischer verbraucher | |
DE102014218010A1 (de) | Vorrichtung und Verfahren zum Erzeugen eines Signals mit einem einstellbaren Tastverhältnis | |
EP3440753B1 (de) | Temperaturüberwachung | |
WO2018033374A1 (de) | Schaltungsanordnung zur steuerung eines elektrischen verbrauchers | |
DE102015113532A1 (de) | Stromsteuerschaltkreis | |
WO2016026629A1 (de) | Überwachung einer spule | |
EP1449000B1 (de) | Steuergerät | |
DE3325992A1 (de) | Schutzschaltung gegen kurzschluss der erregerwicklung fuer einen niederspannungssynchrongenerator mit einem spannungsregler, insbesondere zum einsatz bei kraftfahrzeugen | |
DE10331239A1 (de) | Überwachungselektronik für einen Elektromotor und Verfahren zur Überwachung eines Elektromotors | |
DE112017005583B4 (de) | Stromversorgungs-Steuervorrichtung für eine Funkenerosionsmaschine | |
DE102014212626B3 (de) | Verfahren zur Erlangung eines Hinweises, insbesondere eines Anfangshinweises auf eine mögliche fehlerhafte Lastbedingung eines mehrphasigen Elektromotors | |
EP1011190B1 (de) | Verfahren und Schaltungsanordnung zur Überwachung des Betriebszustandes einer Last |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17755071 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20197007431 Country of ref document: KR Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 2017312407 Country of ref document: AU Date of ref document: 20170731 Kind code of ref document: A |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17755071 Country of ref document: EP Kind code of ref document: A1 |