WO2018014684A1 - 一种测试方法和装置、设备、存储介质 - Google Patents

一种测试方法和装置、设备、存储介质 Download PDF

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Publication number
WO2018014684A1
WO2018014684A1 PCT/CN2017/088644 CN2017088644W WO2018014684A1 WO 2018014684 A1 WO2018014684 A1 WO 2018014684A1 CN 2017088644 W CN2017088644 W CN 2017088644W WO 2018014684 A1 WO2018014684 A1 WO 2018014684A1
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data
test
tdm
spi
read
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PCT/CN2017/088644
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English (en)
French (fr)
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卢春
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深圳市中兴微电子技术有限公司
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Publication of WO2018014684A1 publication Critical patent/WO2018014684A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Definitions

  • the present invention relates to the field of communications, and in particular, to a test method and apparatus, device, and storage medium.
  • SOC System-on-a-Chip
  • the embodiments of the present invention provide a testing method, device, device, and storage medium.
  • the testing of the ISI interface becomes efficient and reliable.
  • An embodiment of the present invention provides a testing method, where the testing method is applied to a testing device, where the testing device pre-downloads preset logic and a preset program, and establishes a connection with the test board, the method include:
  • ISI test mode includes: a serial peripheral interface SPI test mode and a time division multiplexing (TDM) test mode;
  • the TDM test mode is performed, and whether the TDM data is read and written correctly is tested;
  • the test problem of the test device is determined.
  • the testing device downloads preset logic and preset programs in advance, including:
  • the test device pre-downloads system integrated chip (SOC) logic, performs reset setting, and downloads the arm program through trace32.
  • SOC system integrated chip
  • test SPI data is read and written correctly, including:
  • the first data is any one of the first preset arrays
  • the SPI data read and write error is determined when the first data is different from the first output data.
  • test TDM data is read and written correctly, including:
  • test board Setting the test board to a TDM data loopback through an SPI interface
  • each of the data in the output array is an incremental data sequence, the data in the input array is the same preset data; n is a natural number greater than or equal to 3;
  • the first TDM data is TDM data that is sent back by the test board after sending the second data of the board to the test board;
  • the TDM data read and write error is determined.
  • the method includes:
  • the method After determining the TDM data read and write error, after determining the test problem of the test device, the method includes:
  • An embodiment of the present invention provides a testing device, where the testing device pre-downloads a preset logic and a preset program, and establishes a connection with a test board, where the device includes: a setting unit, a determining unit, and a testing unit, where
  • the setting unit is configured to set an ISI test mode, where the ISI test mode includes: an SPI test mode and a TDM test mode;
  • the determining unit is configured to determine whether to perform the SPI test mode
  • the test unit is configured to test whether the SPI data read and write is correct when determining to perform the SPI test mode; and further configured to: when it is determined that the SPI test mode is not performed, or when testing the SPI data to read and write correctly, Perform the TDM test mode to test whether the TDM data is read and written correctly;
  • the determining unit is further configured to determine a test problem of the test device when testing the TDM data read and write error.
  • test unit is further configured to download the system integrated chip SOC logic in advance, perform reset setting, and download the arm program through trace32.
  • the test unit includes: a write module, a read module, and a determination module, where
  • the writing module is configured to write input data in the first preset array to a register of the test board;
  • the reading module is configured to write a first data to the register, and read first output data of the register after writing the first data, where the first data is the first pre- Set any data in the array;
  • the determining module is configured to determine that the SPI data is correctly read and written when the first data is the same as the first output data, and is further configured to: when the first data is different from the first output data , determining the SPI data read and write error.
  • the testing unit includes: a setting module, a sending module, a reading module, and a determining module, where
  • the setting module is configured to set the test board to a TDM data loopback through an SPI interface; and further configured to set n output arrays and n input arrays, wherein the data in each of the output arrays is an incremental data sequence.
  • the data in the input array is the same preset data; n is a natural number greater than or equal to 3;
  • the sending module is configured to separately send data in the n output arrays to the test board;
  • the reading module is configured to read the TDM data sent by the test board, and the TDM data is replaced by the preset data and stored in the input array, wherein each of the output arrays is sent, and the sending interrupt is turned on;
  • the determining module is configured to determine that the TDM data is correctly read and written when the second data sent to the test board is the same as the first TDM data sent by the test board, where the second data is the Any one of the n output arrays, the first TDM data is TDM data sent back by the test board after the second data of the board is sent to the test board; and configured to be the second data When the first TDM data is different, the TDM data read and write error is determined.
  • test unit is further configured to determine a test problem when the test SPI data is read or written, download the arm program through trace32, and set the ISI test mode to re-test;
  • the test unit is further configured to determine a test problem when the TDM data is read or written, download the arm program through trace32, and set the ISI test mode to re-test.
  • the embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the test method provided by the embodiment of the present invention.
  • the embodiment of the invention provides a testing device, including:
  • a storage medium configured to store executable instructions
  • An embodiment of the present invention provides a testing method and apparatus, a device, and a storage medium.
  • the testing device pre-downloads preset logic and a preset program, and establishes a connection with the test board.
  • the method includes: setting an ISI test mode, the ISI test The mode includes: an SPI test mode and a TDM test mode; determining whether to perform the SPI test mode; when determining to perform the SPI test mode, testing whether the SPI data is read and written correctly; when determining that the SPI test mode is not performed, or when When the SPI data is correctly read and written, the TDM test mode is performed to test whether the TDM data is read and written correctly; when the TDM data read and write error is tested, the test problem of the test device is determined.
  • the testing method and device provided by the embodiments of the present invention enable the testing of the ISI interface to be efficient and reliable by setting the peripheral chip, and the improvement in the testing process and the testing method, saving manpower and material resources, improving work efficiency, and ensuring The reliability of the test.
  • FIG. 1 is a schematic flowchart 1 of a testing method according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a data flow of a test method according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart 2 of a testing method according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an SPI test data flow according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a TDM test data flow according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram 1 of a testing device according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram 2 of a testing apparatus according to an embodiment of the present invention.
  • the embodiment of the invention provides a testing method. As shown in FIG. 1 , the method may include:
  • Step 101 Download preset logic and preset program in advance, and establish a connection with the test board.
  • the test method provided by the embodiment of the present invention may be a Field Programmable Gate Array (FPGA) test method of an ISI interface in the SOC development process, and the execution body of the test method may be a test device, and the test device may be an FPGA.
  • the board, the FPGA board, acquires preset logic and preset programs to establish a connection with the test board.
  • FPGA Field Programmable Gate Array
  • FPGA appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of the custom circuit, but also overcomes the shortcomings of the limited number of original programmable device gates.
  • ASIC application-specific integrated circuits
  • ISI Integrated Serial Interface
  • SPI Serial Peripheral Interface
  • PCM Pulse Code Modulation interface in the SOC into a serial port.
  • ISI SLIC chip interaction converts the Serial Peripheral Interface (SPI) and the PCM Pulse Code Modulation interface in the SOC into a serial port.
  • the characteristics of the ISI interface are: internal connection standard PCM/SPI bus; support SPI maximum clock is 4 megahertz (MHz), support PCM clock highest bit 2.048M; support 3-pin interface Slic IC chip; no analog and storage cell Demand; the smallest area space.
  • Applications of the ISI interface include: Digital Subscriber Line (DSL), such as xDSL home gateways, Passive Optical Network (PON) home gateways, wireless loop terminals, and analog terminal adapters.
  • DSL Digital Subscriber Line
  • PON Passive Optical Network
  • the FPGA and the ISI interface of the SI3226x are interconnected.
  • the preset logic and preset programs are pre-downloaded to the FPGA board to establish a connection with the test board; that is, the SOC logic is first downloaded to the FPGA board, and the SI3226x is used.
  • the ISI interface of the test board is connected to the FPGA board, and the arm program of the SOC is loaded using the downloader trace32, and the arm program is downloaded to the Arm core of the FPGA.
  • the arm program of the Arm kernel reads and writes the configuration register of the SI3226x through the ISI interface.
  • TRACE32 is a simulation test tool developed by Lauterbach, Germany. TRACE32 as a truly integrated, versatile system simulator can be combined into a variety of solutions, can support network solutions, laboratory stand-alone solutions, off-site fiber solutions, etc. It has a fully modular, building block structure, can support joint testing work
  • the JTAG (Joint Test Action Group) interface and the Background Debugging Mode (BDM) interface and all CPUs provide powerful functions such as software analysis, port analysis, waveform analysis, and software testing.
  • JTAG Joint Test Action Group
  • BDM Background Debugging Mode
  • the test board used that is, the test chip is SI3226x
  • the chip uses the ISI to SPI port to set an internal register, and has a TDM data loopback function, and may also be other
  • the test chip for implementing the ISI to SPI port setting internal register and the self-contained TDM data loopback function is not limited in this embodiment of the present invention.
  • Step 102 Set an ISI test mode.
  • the ISI test mode includes: SPI test mode and time division multiplexing TDM test mode.
  • the Serial Peripheral Interface (SPI) bus system is a synchronous serial peripheral interface that allows the MCU to communicate serially with various peripherals to exchange information.
  • the SPI has three registers: control register SPCR, status register SPSR, and data register SPDR.
  • TDM is a time division multiplexing mode, which refers to a technique of transmitting a plurality of digitized data, voice and video signals on the same communication medium through cross-bit pulses in different channels or time slots.
  • Step 103 Determine whether to perform the SPI test mode.
  • Step 104 When it is determined that the SPI test mode is performed, it is tested whether the SPI data is read and written correctly.
  • the input data in the first preset array is written into the register of the test board one by one, each writes a first data to the register, and reads and writes the first data. Determining, by the first output data of the register, the first data is any one of the first preset arrays; when the first data is the same as the first output data, determining that the SPI data is read and written Correct; when the first data is different from the first output data, the SPI data read and write error is determined.
  • the trace32 loads the SOC arm program, and the arm program reads and writes the SI3226x configuration register through the ISI interface, and repeatedly reads and writes the register of the specific address to ensure that the SPI part of the ISI interface works normally.
  • the arm program sets the SI3226x directly through the SPI port of the FPGA's own peripherals.
  • the SPI bus needs to pass through the ISI port first, it needs The correct settings are made by adding an action that reads and writes timing.
  • Step 105 When it is determined that the SPI test mode is not performed, or when the SPI data is correctly read and written, the TDM test mode is performed to test whether the TDM data is read and written correctly.
  • the test board is set to a TDM data loopback through an SPI interface; n output arrays and n input arrays are set, and data in each of the output arrays is an incremental data sequence, the input array
  • the data in the data is the same preset data; n is a natural number greater than or equal to 3; respectively, the data in the n output arrays is sent to the test board, and the TDM data sent by the test board is read, the TDM data Substituting the preset data in the input array, wherein each time the output array is sent, a transmission interruption is turned on; when the second data sent to the test board is the same as receiving the first TDM data sent by the test board Determining that the TDM data is correctly read and written, wherein the second data is any one of the n output arrays, and the first TDM data is after sending the second data of the board to the test board.
  • the test board loops back the transmitted TDM data; when the second data is different from the first TDM data, determining the TDM data read
  • the setup register sets the TDM of the SI3226x to a data loopback. At this time, the TDM of the SI3226x resends the received data back to the SOC after receiving two frames of data.
  • the rm-side Arm program controls the TDM interface to send data through the ISI interface, and simultaneously reads the TDM data input by the ISI interface, and compares the input and output data.
  • the arm end TDM interface can directly receive the data sent by the test chip, and judge whether the arm ISI interface works normally by comparing the input and output data, wherein the arm end is FPGA side.
  • Step 106 When testing the TDM data read and write error, determine a test problem of the test device.
  • Trace32 downloads the arm program and sets the ISI test mode to retest.
  • the method may further include:
  • the test method provided by the embodiment of the present invention can determine the working state of the SPI by writing different values to the same register during the SPI test phase. Since the SI3226x with TDM self-loopback is used, the input can be simply compared at the arm end. The output data is used to achieve the purpose of testing the ISI interface.
  • the test method provided by the embodiment of the invention makes the test of the ISI interface become efficient and reliable by setting the peripheral chip, and the progress in the test flow and the test method is improved, the manpower and material resources are saved, the work efficiency is improved, and the test is guaranteed. Reliability.
  • An embodiment of the present invention provides a testing method. As shown in FIG. 3, the method may include:
  • Step 201 Download the SOC logic to the FPGA board.
  • Step 202 Perform reset setting, and download the arm program to the SOC through trace32.
  • the test method provided by the embodiment of the present invention is applied to the FPGA board.
  • the ISI interface of the FPGA and the SI3226x is interconnected, the SOC logic is downloaded to the FPGA board, the arm program is loaded by using the trace, and the arm program reads and writes the SI3226x through the ISI interface.
  • the arm program controls the TDM interface to send data through the ISI interface, simultaneously reads the TDM data input by the ISI interface, compares the input and output data, and obtains the test result.
  • Step 203 setting to an ISI test mode.
  • Step 204 Determine whether to perform an ISI test.
  • step 205 is performed; if not, it is determined that the ISI test is not performed, then step 206 is performed.
  • ISI tests include SPI test and TDM test.
  • Step 205 Test whether the SPI data is read and written correctly.
  • step 206 is performed; if the SPI data read and write error is tested, the positioning problem is determined, that is, the test problem is determined, the arm program is downloaded through trace32, and the ISI test mode is set to be re-tested.
  • the SPI test portion of the ISI interface test downloads the generated SOC logic to the target FPGA test board at the beginning of the test, as shown in FIG. 4, where the FPGA acts as a simulated SOC. Reset the FPGA system and download the arm program to the simulated SOC through trace32. Use the Universal Asynchronous Receiver/Transmitter (UART) serial port to control the program operation and set the program running mode to ISI test mode. Since the SPI port needs to be used to set the registers of the daughter board when testing the loopback, the SPI part of the ISI interface needs to be tested first.
  • UART Universal Asynchronous Receiver/Transmitter
  • the arm program writes a set of data incremented from 0x00 to 0xff one by one into the control register of the SI3226x. Each time a data is written, the value of the register is read immediately. If the read data and the written data are not written, The same, locate the problem and re-measure.
  • the data incremented from 0x00 to 0xff can be understood as hexadecimal data of 0 to 255.
  • the second method is to achieve the purpose of SPI to read and write SI3226x normally. It can be understood that the data is first written to the ISI interface, and then the data of the ISI interface is written to the SI3226x. When the data is read, the data of the SI3226x is first read to the ISI interface. Then read the data of the ISI interface to the SPI.
  • Step 206 Set the test board to a TDM data loopback through an SPI interface.
  • Step 207 Send a set of incremental data from the TDM port to the SI3226x.
  • Step 208 Read TDM data sent back by the SI3226x.
  • Step 209 Determine whether the data sent to the SI3226x is the same as the read TDM data.
  • test TDM data is correctly read and written, it ends; if the TDM data is read and written incorrectly, the positioning problem is determined, that is, the test problem is determined, and the arm program is downloaded through trace32, and the ISI test mode is set. Re-test.
  • the TSI test part of the ISI interface TDM as an important data transmission channel, is an important component of the ISI interface.
  • the arm program sets the SI3226x to TDM data loopback through the SPI interface, and the SI3226x will send the received TDM data directly, that is, to the FPGA.
  • three output arrays are set on the FPGA side, ie, the arm, initialized to an incrementing sequence of 0 to 0xff, and three input arrays, initialized to all 0xff.
  • the receiving port is opened, and the data of the transmitting end and the receiving end are compared each time the data is received. The same data means the test passed, if the data has errors, you need to locate the problem. Rewrite the program, and the SPI port at this time has been tested before, and can be skipped directly during the test TDM phase.
  • the incremental sequence of 0 to 0xff can be understood as a hexadecimal incremental data sequence of 0 to 255. All 0xffs in the input array are all set to 255.
  • the loopback data replaces the data 255 in the input array, and the loopback data can be stored in the input array, so that the output array can be compared with the data in the input array to determine whether the two are the same.
  • the data of the first frame is lost each time, and how much data is lost is related to the number of enabled slots.
  • the loopback data received by the TDM has a frame delay, and the delay of several bytes is also related to the enabled slot. Therefore, the transmission of multiple array data is usually used to avoid the first frame data loss. Error and error in loopback data delay.
  • the test method provided by the embodiment of the invention makes the test of the ISI interface become efficient and reliable by setting the peripheral chip, and the progress in the test flow and the test method is improved, the manpower and material resources are saved, the work efficiency is improved, and the test is guaranteed. Reliability.
  • the embodiment of the present invention provides a testing device 30.
  • each unit included in the testing device and each module included in each unit can be implemented by a processor in the testing device;
  • the function can of course also be implemented by logic circuits.
  • the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA). Wait.
  • the test device pre-downloads the preset logic and the preset program, and establishes a connection with the test board.
  • the device 30 includes: a setting unit 301, a determining unit 302, and a testing unit 303, where
  • the setting unit 301 is configured to set an integrated serial interface ISI test mode, where the ISI test mode includes: an SPI test mode and a TDM test mode;
  • the determining unit 302 is configured to determine whether to perform the SPI test mode
  • the testing unit 303 is configured to test whether the SPI data read and write is correct when determining to perform the SPI test mode; and further configured to: when it is determined that the SPI test mode is not performed, or when testing the SPI data to read and write correctly Performing the TDM test mode to test whether the TDM data is read and written correctly;
  • the determining unit 302 is further configured to determine a test problem of the test device when testing the TDM data read and write error.
  • testing unit 303 is further configured to download the system integrated chip SOC logic in advance, perform reset setting, and download the arm program through trace32.
  • the testing unit 303 includes: a writing module 3031, a reading module 3032, and a determining module 3033, where
  • the writing module 3031 is configured to write input data in the first preset array to a register of the test board;
  • the reading module 3032 is configured to write a first data to the register, and read first output data of the register after writing the first data, where the first data is the first Preset any one of the data in the array;
  • the determining module 3033 is configured to: when the first data is the same as the first output data, determine that the SPI data is correctly read and written; and further configured to: when the first data and the first output data are not At the same time, the SPI data read and write error is determined.
  • the testing unit 303 includes: a setting module 3034, a sending module 3035, a reading module 3032, and a determining module 3033, where
  • the setting module 3034 is configured to set the test board to a TDM data loopback through an SPI interface; and further configured to set n output arrays and n input arrays, wherein the data in each of the output arrays is an incremental data sequence.
  • the data in the input array is the same preset data; n is a natural number greater than or equal to 3;
  • the sending module 3035 is configured to separately send data in the n output arrays to the test board;
  • the reading module 3032 is configured to read TDM data sent by the test board, and the TDM data replaces the preset data in the input array, wherein each time the output array is sent, the sending interrupt is opened. ;
  • the determining module 3033 is configured to determine that the TDM data is correctly read and written when the second data sent to the test board is the same as the first TDM data sent by the test board, where the second data is Determining any one of the n output arrays, the first TDM data being TDM data sent back by the test board after sending the second data of the board to the test board; and configured to be the second When the data is different from the first TDM data, the TDM data read and write error is determined.
  • the testing unit 303 is further configured to: when testing the SPI data read and write error, determine the test problem, download the arm program through trace32, and set the ISI test mode to re-test;
  • the testing unit 303 is further configured to determine a test problem when the TDM data is read or written, download the arm program through trace32, and set the ISI test mode to re-test.
  • test apparatus provided by the embodiment of the present invention, reference may be made to the description of the test method of the first embodiment and the second embodiment, and details are not described herein again.
  • the test device provided by the embodiment of the invention makes the test of the ISI interface efficient and reliable by setting the peripheral chip, and has made progress in the test flow and the test method, saves manpower and material resources, improves work efficiency, and ensures the test. Reliability.
  • test method if the above test method is implemented in the form of a software function module and sold or used as a stand-alone product, it may also be stored in a computer readable storage medium.
  • technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • Embodiments of the present invention provide a computer storage medium in which computer executable instructions are stored, the computer executable instructions being used to execute the test method.
  • a test apparatus includes a storage medium configured to store executable instructions, a processor configured to execute stored executable instructions, and the executable instructions to execute the test method.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the present invention is directed to a method, apparatus (system), and computer program in accordance with an embodiment of the present invention
  • the flow chart and/or block diagram of the product is described. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the testing method and device provided by the embodiments of the present invention enable the testing of the ISI interface to be efficient and reliable by setting the peripheral chip, and the improvement in the testing process and the testing method, saving manpower and material resources, improving work efficiency, and ensuring The reliability of the test.

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Abstract

一种测试方法和装置、设备、存储介质，测试装置预先下载预设逻辑和预设程序，与测试板建立连接（101），所述方法包括：设置ISI测试模式（102），所述ISI测试模式包括：SPI测试模式和TDM测试模式；确定是否进行所述SPI测试模式（103）；当确定进行所述SPI测试模式时，测试SPI数据读写是否正确（104）；当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确（105）；当测试所述TDM数据读写错误时，确定所述测试装置的测试问题（106）。

Description

一种测试方法和装置、设备、存储介质
相关申请的交叉引用
本申请基于申请号为201610570095.X、申请日为2016年07月18日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本申请。
技术领域
本发明涉及通信领域，尤其涉及一种测试方法和装置、设备、存储介质。
背景技术
随着芯片集成度大幅提高，集成电路设计正快速地向系统集成芯片(SOC，System-on-a-Chip)上转变。SOC技术将多个系统功能映射到单个芯片上，在开发周期、系统功能和性能方面有着无可比拟的优点。然而，随着SOC集成接口的增加，对各个接口的测试访问也变得更加困难，进而也就为SOC的测试带来了更大的困难。
发明内容
为解决现有存在的技术问题，本发明实施例提供一种测试方法和装置、设备、存储介质，通过对外设芯片设置，使得ISI接口的测试变得高效、可靠。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种测试方法，所述测试方法应用于测试装置，所述测试装置预先下载预设逻辑和预设程序，与测试板建立连接，所述方法 包括：
设置集成串行接口(ISI)测试模式，所述ISI测试模式包括：串行外设接口SPI测试模式和时分复用(TDM)测试模式；
确定是否进行所述SPI测试模式；
当确定进行所述SPI测试模式时，测试SPI数据读写是否正确；
当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确；
当测试所述TDM数据读写错误时，确定所述测试装置的测试问题。
在其他的实施例中，所述测试装置预先下载预设逻辑和预设程序，包括：
所述测试装置预先下载系统集成芯片(SOC)逻辑，进行复位设置，通过trace32下载arm程序。
在其他的实施例中，所述测试SPI数据读写是否正确，包括：
将第一预设数组中的输入数据写入所述测试板的寄存器，每写入一个第一数据至所述寄存器，读取写入所述第一数据后所述寄存器的第一输出数据，所述第一数据为所述第一预设数组中的任意一个数据；
当所述第一数据与所述第一输出数据相同时，确定所述SPI数据读写正确；
当所述第一数据与所述第一输出数据不同时，确定所述SPI数据读写错误。
在其他的实施例中，所述测试TDM数据读写是否正确，包括：
通过SPI接口设置所述测试板为TDM数据回环；
设置n个输出数组和n个输入数组，每一个所述输出数组中的数据为递增的数据序列，所述输入数组中的数据为相同的预设数据；n为大于等于3的自然数；
分别发送所述n个输出数组中的数据至所述测试板，读取所述测试板发送的TDM数据，所述TDM数据替换所述预设数据存储于所述输入数组，其中，每发送一个所述输出数组，打开发送中断；
当发送至所述测试板第二数据与接收所述测试板发送的第一TDM数据相同，确定所述TDM数据读写正确，其中，所述第二数据为所述n个输出数组中的任意一个数据，所述第一TDM数据为发送所述板第二数据至所述测试板后所述测试板环回发送的TDM数据；
当所述第二数据与所述第一TDM数据不同时，确定所述TDM数据读写错误。
在其他的实施例中，在所述测试SPI数据读写是否正确之后，包括：
当测试所述SPI数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试；
在所述当测试所述TDM数据读写错误时，确定所述测试装置的测试问题之后，包括：
通过trace32下载arm程序，设置ISI测试模式重新进行测试。
本发明实施例提供一种测试装置，所述测试装置预先下载预设逻辑和预设程序，与测试板建立连接，所述装置包括：设置单元、确定单元、测试单元，其中，
所述设置单元，配置为设置ISI测试模式，所述ISI测试模式包括：SPI测试模式和TDM测试模式；
所述确定单元，配置为确定是否进行所述SPI测试模式；
所述测试单元，配置为当确定进行所述SPI测试模式时，测试SPI数据读写是否正确；还配置为当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确；
所述确定单元，还配置为当测试所述TDM数据读写错误时，确定所述测试装置的测试问题。
在其他的实施例中，所述测试单元，还配置为预先下载系统集成芯片SOC逻辑，进行复位设置，通过trace32下载arm程序。
在其他的实施例中，所述测试单元包括：写入模块、读取模块、确定模块，其中，
所述写入模块，配置为将第一预设数组中的输入数据写入所述测试板的寄存器；
所述读取模块，配置为每写入一个第一数据至所述寄存器，读取写入所述第一数据后所述寄存器的第一输出数据，所述第一数据为所述第一预设数组中的任意一个数据；
所述确定模块，配置为当所述第一数据与所述第一输出数据相同时，确定所述SPI数据读写正确；还配置为当所述第一数据与所述第一输出数据不同时，确定所述SPI数据读写错误。
在其他的实施例中，所述测试单元包括：设置模块、发送模块，读取模块、确定模块，其中，
所述设置模块，配置为通过SPI接口设置所述测试板为TDM数据回环；还配置为设置n个输出数组和n个输入数组，每一个所述输出数组中的数据为递增的数据序列，所述输入数组中的数据为相同的预设数据；n为大于等于3的自然数；
所述发送模块，配置为分别发送所述n个输出数组中的数据至所述测试板；
所述读取模块，配置为读取所述测试板发送的TDM数据，所述TDM数据替换所述预设数据存储于所述输入数组，其中，每发送一个所述输出数组，打开发送中断；
所述确定模块，配置为当发送至所述测试板第二数据与接收所述测试板发送的第一TDM数据相同，确定所述TDM数据读写正确，其中，所述第二数据为所述n个输出数组中的任意一个数据，所述第一TDM数据为发送所述板第二数据至所述测试板后所述测试板环回发送的TDM数据；还配置为当所述第二数据与所述第一TDM数据不同时，确定所述TDM数据读写错误。
在其他的实施例中，所述测试单元，还配置为当所述测试SPI数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试；
所述测试单元，还配置为当所述TDM数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试。
本发明实施例提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行本发明实施例提供的测试方法。
本发明实施例提供一种测试设备，包括：
存储介质，配置为存储可执行指令；
处理器，配置为执行存储的可执行指令，所述可执行指令用于执行本发明实施例提供的测试方法
本发明实施例提供了一种测试方法和装置、设备、存储介质，测试装置预先下载预设逻辑和预设程序，与测试板建立连接，所述方法包括：设置ISI测试模式，所述ISI测试模式包括：SPI测试模式和TDM测试模式；确定是否进行所述SPI测试模式；当确定进行所述SPI测试模式时，测试SPI数据读写是否正确；当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确；当测试所述TDM数据读写错误时，确定所述测试装置的测试问题。 本发明实施例提供的测试方法和装置，通过对外设芯片设置，使得ISI接口的测试变得高效、可靠，在测试流程、测试方法上取得了进步，节省了人力物力，提高了工作效率，保证了测试的可靠性。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本发明实施例提供的测试方法流程示意图一；
图2为本发明实施例提供的测试方法数据流程示例图；
图3为本发明实施例提供的测试方法流程示意图二；
图4为本发明实施例提供的SPI测试数据流程示例图；
图5为本发明实施例提供的TDM测试数据流程示例图；
图6为本发明实施例提供的测试装置结构示意图一；
图7为本发明实施例提供的测试装置结构示意图二。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例提供一种测试方法，如图1所示，该方法可以包括：
步骤101、预先下载预设逻辑和预设程序，与测试板建立连接。
本发明实施例提供的测试方法可以为SOC开发过程中ISI接口的现场可编程门阵列(FPGA，Field Programmable Gate Array)测试方法，该测试方法的执行主体可以为测试装置，该测试装置可以为FPGA板，即FPGA板获取预设逻辑和预设程序，与测试板建立连接。
其中，FPGA是作为专用集成电路(ASIC)领域中的一种半定制电路而出现的，既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。
ISI接口(Integrated Serial Interface)是一个集成串行接口，它将SOC中的串行外设接口(SPI，Serial Peripheral Interface)和脉冲编码调制(PCM Pulse Code Modulation)接口转化为一个串行口后与ISI SLIC芯片交互。
ISI接口的特性为：内部连接标准的PCM/SPI总线；支持SPI最高时钟为4兆赫兹(MHz)，支持PCM时钟最高位2.048M；支持3-pin接口的Slic IC芯片；没有模拟和存储cell需求；最小的面积空间。ISI接口的应用包括：数字用户线路(DSL，Digital Subscriber Line)例如xDSL家用闸道器、无源光纤网络(PON，Passive Optical Network)家用闸道器、无线回路端子和模拟终端适配器。
如图2所示，FPGA和SI3226x的ISI接口互联，在测试开始时，预先下载预设逻辑和预设程序至FPGA板，与测试板建立连接；即先下载SOC逻辑到FPGA板子上，将SI3226x测试板的ISI接口连接FPGA板，使用下载器trace32加载SOC的arm程序，将arm程序下载到FPGA的Arm内核，Arm内核的arm程序通过ISI接口读写SI3226x的配置寄存器。
TRACE32是由德国Lauterbach公司研制开发的一款仿真测试工具。TRACE32作为一种真正集成化、通用性系统仿真器可以组合成多种方案，可以支持网络方案、实验室单机方案、异地光纤方案等，它具有全模块化、积木式结构、可支持联合测试工作组(JTAG，Joint Test Action Group)接口及背景调试模式(BDM，Background Debugging Mode)接口和所有CPU，能够提供软件分析、端口分析、波形分析以及软件测试等强大功能。
本发明实施例中，使用的测试板，即测试芯片为SI3226x，该芯片使用ISI转SPI口设置内部寄存器，自带TDM数据回环功能，还可以是其它可 以实现ISI转SPI口设置内部寄存器及自带TDM数据回环功能的测试芯片，本发明实施例对此不做限定。
步骤102、设置ISI测试模式。
其中，ISI测试模式包括：SPI测试模式和时分复用TDM测试模式。
串行外设接口(SPI，Serial Peripheral Interface)总线系统是一种同步串行外设接口，它可以使MCU与各种外围设备以串行方式进行通信以交换信息。SPI有三个寄存器分别为：控制寄存器SPCR，状态寄存器SPSR，数据寄存器SPDR。
TDM是时分复用模式，时分复用是指一种通过不同信道或时隙中的交叉位脉冲，同时在同一个通信媒体上传输多个数字化数据、语音和视频信号等的技术。
步骤103、确定是否进行SPI测试模式。
步骤104、当确定进行所述SPI测试模式时，测试SPI数据读写是否正确。
在其他的实施例中，将第一预设数组中的输入数据逐个写入所述测试板的寄存器，每写入一个第一数据至所述寄存器，读取写入所述第一数据后所述寄存器的第一输出数据，所述第一数据为所述第一预设数组中的任意一个数据；当所述第一数据与所述第一输出数据相同时，确定所述SPI数据读写正确；当所述第一数据与所述第一输出数据不同时，确定所述SPI数据读写错误。
在其他的实施例中，trace32加载SOC的arm程序，arm程序通过ISI接口读写SI3226x的配置寄存器，对特定地址的寄存器反复读写，保证ISI接口的SPI部分工作正常。
在其他的实施例中，arm程序直接通过FPGA自身外设的SPI口对SI3226x进行设置。在设置过程中，由于SPI总线需要先通过ISI口，需要 通过增加一个读写时序的动作来完成正确的设置。
步骤105、当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行TDM测试模式，测试TDM数据读写是否正确。
在其他的实施例中，通过SPI接口设置所述测试板为TDM数据回环；设置n个输出数组和n个输入数组，每一个所述输出数组中的数据为递增的数据序列，所述输入数组中的数据为相同的预设数据；n为大于等于3的自然数；分别发送所述n个输出数组中的数据至所述测试板，读取所述测试板发送的TDM数据，所述TDM数据替换所述预设数据存储于所述输入数组，其中，每发送一个所述输出数组，打开发送中断；当发送至所述测试板第二数据与接收所述测试板发送的第一TDM数据相同，确定所述TDM数据读写正确，其中，所述第二数据为所述n个输出数组中的任意一个数据，所述第一TDM数据为发送所述板第二数据至所述测试板后所述测试板环回发送的TDM数据；当所述第二数据与所述第一TDM数据不同时，确定所述TDM数据读写错误。
在其他的实施例中，arm程序测试ISI接口的SPI部分工作正常后，设置寄存器将SI3226x的TDM设置为数据回环。此时SI3226x的TDM在接受到数据两帧之后将接收到的数据重新送回SOC。SOC端的Arm程序控制TDM接口通过ISI接口发送数据，同时读取ISI接口输入的TDM数据，对输入输出数据进行比较。
arm程序设置完TDM回环的测试芯片写入TMD数据后，arm端的TDM接口能直接收到测试芯片发出的数据，通过对输入输出数据进行比较判断arm端的ISI接口是否工作正常，其中，arm端即FPGA端。
步骤106、当测试所述TDM数据读写错误时，确定测试装置的测试问题。
在其他的实施例中，当TDM数据读写错误时，确定测试问题，通过 trace32下载arm程序，设置ISI测试模式重新进行测试。
在其他的实施例中，在步骤104之后，所述方法还可以包括：
当SPI数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试。
本发明实施例提供的测试方法，在SPI测试阶段可以通过对同一个寄存器写入读取不同的值来判断SPI的工作状态，由于采用带有TDM自回环的SI3226x，可以在arm端简单对比输入输出的数据来达到测试ISI接口的目的。
本发明实施例提供的测试方法，通过对外设芯片设置，使得ISI接口的测试变得高效、可靠，在测试流程、测试方法上取得了进步，节省了人力物力，提高了工作效率，保证了测试的可靠性。
本发明实施例提供一种测试方法，如图3所示，该方法可以包括：
步骤201、下载SOC逻辑到FPGA板。
步骤202、进行复位设置，通过trace32下载arm程序到SOC。
本发明实施例提供的测试方法应用于FPGA板，如图2所示，FPGA和SI3226x的ISI接口互联，下载SOC逻辑到FPGA板子上，使用trace加载arm程序，arm程序通过ISI接口读写SI3226x的寄存器，将SI3226x的TDM设置为数据回环。arm程序控制TDM接口通过ISI接口发送数据，同时读取ISI接口输入的TDM数据，对输入输出数据进行比较，得出测试结果。
步骤203、设置为ISI测试模式。
步骤204、确定是否进行ISI测试。
若是，即确定进行ISI测试，则执行步骤205；若否，即确定不进行ISI测试，则执行步骤206。
其中，ISI测试包括SPI测试和TDM测试。
步骤205、测试SPI数据读写是否正确。
若测试SPI数据读写正确，则执行步骤206；若测试SPI数据读写错误，则定位问题，即确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试。
在其他的实施例中，ISI接口测试的SPI测试部分，在测试开始时，下载已经生成的SOC逻辑到目标FPGA测试板上，如图4所示，此时的FPGA即作为一片模拟的SOC，复位FPGA系统并通过trace32下载arm程序到该模拟的SOC，使用通用异步收发传输器(UART，Universal Asynchronous Receiver/Transmitter)串口控制程序运行，设置程序运行模式为ISI测试模式。由于在测试回环的时候需要先使用SPI口设置子板的寄存器，需要先测试ISI接口的SPI部分。
如图4所示，arm程序将一组从0x00到0xff递增的数据逐个写入SI3226x的控制寄存器，每写入一个数据紧接着读出该寄存器的值，如果读出的数据和写入的不一样，则定位问题，并重新测量。其中，0x00到0xff递增的数据可以理解为0～255的16进制数据。
在写入读取数据的过程中，由于SPI的数据先经过了ISI接口的转发，单次读写只能把时序送到ISI接口，无法直接送到SI3226x，因此，在这里通过连续读写两次的方法来达到SPI正常读写SI3226x的目的，可以理解为，先将数据写入ISI接口，再将ISI接口的数据写入SI3226x，读取数据时，先将SI3226x的数据读取到ISI接口，再将ISI接口的数据读取到SPI。
步骤206、通过SPI接口设置所述测试板为TDM数据回环。
步骤207、将一组递增的数据从TDM口发送到SI3226x。
步骤208、读取SI3226x发回的TDM数据。
步骤209、确定发送到SI3226x的数据与读取的TDM数据是否相同。
若测试TDM数据读写正确，则结束；若测试TDM数据读写错误，则定位问题，即确定测试问题，通过trace32下载arm程序，设置ISI测试模 式重新进行测试。
如图5所示，ISI接口TDM测试部分，TDM作为重要的数据传输通道，是ISI接口重要组成。在SPI接口测试完成后，arm程序通过SPI接口设置SI3226x为TDM数据回环，SI3226x将会把接收到的TDM数据直接发送出，即发送给FPGA。
在其他的实施例中，在FPGA端，即arm端设置3个输出数组，初始化为0到0xff的递增序列，3个输入数组，初始化为全0xff。设置TDM轮流发送3个输出数组里的数据，打开发送中断，每次使用不同的发送数组。同时打开接收端口，每次接收到数据后就对发送端和接收端的数据进行比较。数据一样则表示测试通过，如果数据有错误，则需要定位问题。重新写程序，而此时的SPI口由于之前已经测过，在测试TDM阶段就可以直接跳过。
其中，0到0xff的递增序列可以理解为0～255的16进制递增数据序列，输入数组中的全0xff为，输入数组中的数据全部设为255，当接收到SI3226x的环回数据，将该环回数据替换输入数组中的数据255，即可将该环回数据存储在输入数组中，从而可以输出数组和输入数组中的数据进行比较，确定两者是否相同。
需要说明的是，在TDM测试的数据比较阶段，由于TDM数据帧传输的特性，每次测试第一帧的数据是丢失的，丢失多少个数据和使能slot数目相关。同时由于使能数据回环，TDM接收到的回环数据有一帧的延迟，延迟几个字节也和使能的slot有关，因此，通常通过多个数组数据的传输测试，来避免第一帧数据丢失的误差及回环数据延迟的误差。
本发明实施例提供的测试方法，通过对外设芯片设置，使得ISI接口的测试变得高效、可靠，在测试流程、测试方法上取得了进步，节省了人力物力，提高了工作效率，保证了测试的可靠性。
本发明实施例提供一种测试装置30，如图6所示，该测试装置所包括的各单元、各单元所包括的各模块都可以通过测试设备中处理器来实现；其中处理器所实现的功能当然还可以通过逻辑电路来实现，在实施的过程中，处理器可以为中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)或现场可编程门阵列(FPGA)等。
所述测试装置预先下载预设逻辑和预设程序，与测试板建立连接，所述装置30包括：设置单元301、确定单元302、测试单元303，其中，
所述设置单元301，配置为设置集成串行接口ISI测试模式，所述ISI测试模式包括：SPI测试模式和TDM测试模式；
所述确定单元302，配置为确定是否进行所述SPI测试模式；
所述测试单元303，配置为当确定进行所述SPI测试模式时，测试SPI数据读写是否正确；还配置为当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确；
所述确定单元302，还配置为当测试所述TDM数据读写错误时，确定所述测试装置的测试问题。
在其他的实施例中，所述测试单元303，还配置为预先下载系统集成芯片SOC逻辑，进行复位设置，通过trace32下载arm程序。
在其他的实施例中，如图7所示，所述测试单元303包括：写入模块3031、读取模块3032、确定模块3033，其中，
所述写入模块3031，配置为将第一预设数组中的输入数据写入所述测试板的寄存器；
所述读取模块3032，配置为每写入一个第一数据至所述寄存器，读取写入所述第一数据后所述寄存器的第一输出数据，所述第一数据为所述第一预设数组中的任意一个数据；
所述确定模块3033，配置为当所述第一数据与所述第一输出数据相同时，确定所述SPI数据读写正确；还配置为当所述第一数据与所述第一输出数据不同时，确定所述SPI数据读写错误。
在其他的实施例中，如图7所示，所述测试单元303包括：设置模块3034、发送模块3035，读取模块3032、确定模块3033，其中，
所述设置模块3034，配置为通过SPI接口设置所述测试板为TDM数据回环；还配置为设置n个输出数组和n个输入数组，每一个所述输出数组中的数据为递增的数据序列，所述输入数组中的数据为相同的预设数据；n为大于等于3的自然数；
所述发送模块3035，配置为分别发送所述n个输出数组中的数据至所述测试板；
所述读取模块3032，配置为读取所述测试板发送的TDM数据，所述TDM数据替换所述预设数据存储于所述输入数组，其中，每发送一个所述输出数组，打开发送中断；
所述确定模块3033，配置为当发送至所述测试板第二数据与接收所述测试板发送的第一TDM数据相同，确定所述TDM数据读写正确，其中，所述第二数据为所述n个输出数组中的任意一个数据，所述第一TDM数据为发送所述板第二数据至所述测试板后所述测试板环回发送的TDM数据；还配置为当所述第二数据与所述第一TDM数据不同时，确定所述TDM数据读写错误。
在其他的实施例中，所述测试单元303，还配置为当测试所述SPI数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试；
所述测试单元303，还配置为当所述TDM数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试。
本发明实施例提供的测试装置的理解可以参考实施例一和实施例二的测试方法的说明，本发明实施例在此不再赘述。
本发明实施例提供的测试装置，通过对外设芯片设置，使得ISI接口的测试变得高效、可靠，在测试流程、测试方法上取得了进步，节省了人力物力，提高了工作效率，保证了测试的可靠性。
本发明实施例中，如果以软件功能模块的形式实现上述的测试方法，并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read Only Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
本发明实施例提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行所述的测试方法。
本发明实施例一种测试设备，包括：存储介质，配置为存储可执行指令；处理器，配置为执行存储的可执行指令，所述可执行指令用于执行所述的测试方法。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序 产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例提供的测试方法和装置，通过对外设芯片设置，使得ISI接口的测试变得高效、可靠，在测试流程、测试方法上取得了进步，节省了人力物力，提高了工作效率，保证了测试的可靠性。

Claims (12)

  1. 一种测试方法，所述测试方法应用于测试装置，所述测试装置预先下载预设逻辑和预设程序，与测试板建立连接，所述方法包括：
    设置集成串行接口ISI测试模式，所述ISI测试模式包括：串行外设接口SPI测试模式和时分复用TDM测试模式；
    确定是否进行所述SPI测试模式；
    当确定进行所述SPI测试模式时，测试SPI数据读写是否正确；
    当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确；
    当测试所述TDM数据读写错误时，确定所述测试装置的测试问题。
  2. 根据权利要求1所述的方法，其中，所述测试装置预先下载预设逻辑和预设程序，包括：
    所述测试装置预先下载系统集成芯片SOC逻辑，进行复位设置，通过trace32下载arm程序。
  3. 根据权利要求1所述的方法，其中，所述测试SPI数据读写是否正确，包括：
    将第一预设数组中的输入数据写入所述测试板的寄存器，每写入一个第一数据至所述寄存器，读取写入所述第一数据后所述寄存器的第一输出数据，所述第一数据为所述第一预设数组中的任意一个数据；
    当所述第一数据与所述第一输出数据相同时，确定所述SPI数据读写正确；
    当所述第一数据与所述第一输出数据不同时，确定所述SPI数据读写错误。
  4. 根据权利要求1所述的方法，其中，所述测试TDM数据读写是否正确，包括：
    通过SPI接口设置所述测试板为TDM数据回环；
    设置n个输出数组和n个输入数组，每一个所述输出数组中的数据为递增的数据序列，所述输入数组中的数据为相同的预设数据；n为大于等于3的自然数；
    分别发送所述n个输出数组中的数据至所述测试板，读取所述测试板发送的TDM数据，所述TDM数据替换所述预设数据存储于所述输入数组，其中，每发送一个所述输出数组，打开发送中断；
    当发送至所述测试板第二数据与接收所述测试板发送的第一TDM数据相同，确定所述TDM数据读写正确，其中，所述第二数据为所述n个输出数组中的任意一个数据，所述第一TDM数据为发送所述板第二数据至所述测试板后所述测试板环回发送的TDM数据；
    当所述第二数据与所述第一TDM数据不同时，确定所述TDM数据读写错误。
  5. 根据权利要求1所述的方法，其中，在所述测试SPI数据读写是否正确之后，包括：
    当测试所述SPI数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试；
    在所述当测试所述TDM数据读写错误时，确定所述测试装置的测试问题之后，包括：
    通过trace32下载arm程序，设置ISI测试模式重新进行测试。
  6. 一种测试装置，所述测试装置预先下载预设逻辑和预设程序，与测试板建立连接，所述装置包括：设置单元、确定单元、测试单元，其中，
    所述设置单元，配置为设置ISI测试模式，所述ISI测试模式包括：SPI测试模式和TDM测试模式；
    所述确定单元，配置为确定是否进行所述SPI测试模式；
    所述测试单元，配置为当确定进行所述SPI测试模式时，测试SPI数据读写是否正确；还配置为当确定不进行所述SPI测试模式，或者当测试所述SPI数据读写正确时，进行所述TDM测试模式，测试TDM数据读写是否正确；
    所述确定单元，还配置为当测试所述TDM数据读写错误时，确定所述测试装置的测试问题。
  7. 根据权利要求6所述的装置，其中，所述测试单元，还配置为预先下载系统集成芯片SOC逻辑，进行复位设置，通过trace32下载arm程序。
  8. 根据权利要求6所述的装置，其中，所述测试单元包括：写入模块、读取模块、确定模块，其中，
    所述写入模块，配置为将第一预设数组中的输入数据写入所述测试板的寄存器；
    所述读取模块，配置为每写入一个第一数据至所述寄存器，读取写入所述第一数据后所述寄存器的第一输出数据，所述第一数据为所述第一预设数组中的任意一个数据；
    所述确定模块，配置为当所述第一数据与所述第一输出数据相同时，确定所述SPI数据读写正确；还配置为当所述第一数据与所述第一输出数据不同时，确定所述SPI数据读写错误。
  9. 根据权利要求6所述的装置，其中，所述测试单元包括：设置模块、发送模块，读取模块和确定模块，其中，
    所述设置模块，配置为通过SPI接口设置所述测试板为TDM数据回环；还配置为设置n个输出数组和n个输入数组，每一个所述输出数组中的数据为递增的数据序列，所述输入数组中的数据为相同的预设数据； n为大于等于3的自然数；
    所述发送模块，配置为分别发送所述n个输出数组中的数据至所述测试板；
    所述读取模块，配置为读取所述测试板发送的TDM数据，所述TDM数据替换所述预设数据存储于所述输入数组，其中，每发送一个所述输出数组，打开发送中断；
    所述确定模块，配置为当发送至所述测试板第二数据与接收所述测试板发送的第一TDM数据相同，确定所述TDM数据读写正确，其中，所述第二数据为所述n个输出数组中的任意一个数据，所述第一TDM数据为发送所述板第二数据至所述测试板后所述测试板环回发送的TDM数据；还配置为当所述第二数据与所述第一TDM数据不同时，确定所述TDM数据读写错误。
  10. 根据权利要求6所述的装置，其中，所述测试单元，还配置为当所述测试SPI数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试；
    所述测试单元，还配置为当所述TDM数据读写错误时，确定测试问题，通过trace32下载arm程序，设置ISI测试模式重新进行测试。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求1至5任一项所述的测试方法。
  12. 一种测试设备，包括：
    存储介质，配置为存储可执行指令；
    处理器，配置为执行存储的可执行指令，所述可执行指令用于执行权利要求1至5任一项所述的测试方法。
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