WO2018014385A1 - 薄膜晶体管及其制作方法 - Google Patents

薄膜晶体管及其制作方法 Download PDF

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WO2018014385A1
WO2018014385A1 PCT/CN2016/094682 CN2016094682W WO2018014385A1 WO 2018014385 A1 WO2018014385 A1 WO 2018014385A1 CN 2016094682 W CN2016094682 W CN 2016094682W WO 2018014385 A1 WO2018014385 A1 WO 2018014385A1
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active layer
source
forming
thin film
layer
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French (fr)
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刘洋
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/128,202 priority Critical patent/US10312376B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention belongs to the field of semiconductor technology, and in particular to a thin film transistor capable of realizing a shorter channel and a method of fabricating the same.
  • Metal oxide semiconductor thin film transistors are considered to be key technologies in next-generation flat panel displays due to their good device performance and low process cost.
  • the channel in the metal oxide semiconductor thin film transistor is required to have a larger aspect ratio, and the aspect ratio of the channel determines the functional characteristics of the metal oxide semiconductor thin film transistor.
  • the width W of the track is constant, shortening the length L of the channel enables the MOS transistor to have a larger aspect ratio W/L, thereby having a larger on-state current.
  • the length L of the channel is directly limited by the photolithography process, so that it is more difficult to realize the short channel.
  • the present invention provides a thin film transistor including: a substrate; a gate on the substrate; a gate insulating layer covering the substrate and the gate, a gate insulating layer covering a portion of the protrusion of the gate to form a convex portion, the gate insulating layer covering a portion of the substrate not protruding to form a flat portion; and respectively on the convex portion a first active layer and a second active layer at both ends of the raised portion, the first active layer and the second active layer extending along the sidewall of the raised portion to the flat a first source in contact with the first active layer, and a second source in contact with the second active layer, the first source and the second source being connected to each other; a passivation layer covering the first active layer, the second active layer, the first source, the second source, and the gate insulating layer; in the passivation layer Exposing a first via of the first active layer, and exposing a second pass of the second active layer in the pass
  • first source is located on the first active layer extending onto the flat portion
  • second source is located on the second active layer extending onto the flat portion
  • the first via and the second via expose the first active layer and the second active layer on the raised portion, respectively.
  • first source is located on the first active layer on the convex portion
  • second source is located on the second active layer on the convex portion
  • first via and the second via expose the first active layer and the second active layer that extend to the flat portion, respectively.
  • first source is located between the flat portion and the first active layer extending to the flat portion
  • second source is located at the flat portion and extends to the flat portion
  • first via and the second via expose the first active layer and the second active layer on the raised portion, respectively.
  • the cross-sectional shape of the gate electrode has a trapezoidal shape
  • the cross-sectional shape of the convex portion has a trapezoidal shape
  • sidewalls of the convex portion are inclined.
  • a middle portion of the gate is convex, and a cross-sectional shape of the middle portion of the gate is a trapezoidal shape, and a cross-sectional shape of the convex portion has a trapezoidal shape, and a sidewall of the convex portion is inclined.
  • the present invention also provides a method of fabricating a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer covering the substrate and the gate; wherein the gate insulating layer covers the a portion of the gate is convex to form a convex portion, the portion of the gate insulating layer covering the substrate is not convex to form a flat portion; and the convex portion is respectively formed on the convex portion a first active layer and a second active layer; wherein the first active layer and the second active layer extend along a sidewall of the raised portion onto the flat portion;
  • the first active layer contacts the first source, and is formed with the second source a second source contacted by the source layer; wherein the first source and the second source are connected to each other; forming the first active layer, the second active layer, and the first source a passivation layer of the second source and the gate insulating layer; forming a first via exposing the first active layer in the passivation layer, and in the passiva
  • the forming method of the first source and the second source includes: forming the first source on the first active layer extending onto the flat portion, and extending to Forming the second source on the second active layer on the flat portion; forming a first via and the second via: forming an exposed in the passivation layer a first via hole of the first active layer on the raised portion, and a second via hole exposing the second active layer on the raised portion is formed in the passivation layer.
  • the forming method of the first source and the second source includes: forming the first source on the first active layer on the convex portion, and in the convex Forming the second source on the second active layer on the top; forming the first via and the second via: forming an exposed extension in the passivation layer to a first via of the first active layer on the flat portion, and a second via hole exposing a second active layer extending to the flat portion is formed in the passivation layer.
  • the forming method of the first source and the second source includes: forming the first source between the flat portion and the first active layer extending to the flat portion Forming the second source between the flat portion and the second active layer extending to the flat portion; forming method of the first via and the second via The method includes: forming a first via hole exposing a first active layer on the convex portion in the passivation layer, and forming a exposed portion on the convex portion in the passivation layer a second via of the second active layer.
  • the present invention produces a thin film transistor having a vertical structure, Thereby ensuring that the length of the channel is determined by the length of the sidewall of the gate; compared to the thin film transistor of the prior art, wherein the channel length is controlled by a photolithography process, the length of the channel in the thin film transistor of the present invention is not Due to the influence of the photolithography process, a short channel can be realized, and the resulting short-channel thin film transistor has a larger aspect ratio and thus a larger on-state current.
  • 1a to 1g are flowcharts of a method of fabricating a thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a thin film transistor according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a thin film transistor according to still another embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a thin film transistor according to still another embodiment of the present invention.
  • FIG. 1a through 1g illustrate a fabrication flow diagram of a thin film transistor in accordance with an embodiment of the present invention.
  • a gate electrode 2 is formed on a substrate 1.
  • the cross-sectional shape of the gate electrode 2 has a trapezoidal shape, but the present invention is not limited thereto.
  • the middle portion of the gate electrode 2 is convex, that is, the intermediate portion of the gate electrode 2 has a step difference from both ends thereof, and the cross-sectional shape of the intermediate portion of the gate electrode 2 has a trapezoidal shape.
  • the gate electrode 2 may be made of a metal material such as Al, Mo, Cu, or Ag.
  • a gate insulating layer 3 covering the substrate 1 and the gate 2 is formed.
  • the gate insulating layer 3 covers a portion of the protrusion of the gate electrode 2 to form the convex portion 31, and the portion of the gate insulating layer 3 directly covering the substrate 1 is not convex to form the flat portion 32.
  • both sides of the boss portion 31 are flat portions 32.
  • the gate insulating layer 3 may be made of an insulating material such as SiN x , SiO x , Al 2 O 3 or the like.
  • a first active layer 4a and a second active layer 4b respectively located at both ends of the convex portion 31 are formed on the convex portion 31, and the first active layer 4a is along the left side of the convex portion 31
  • the wall extends to the flat portion 32 on the left side of the boss portion 31, and the second active layer 4b extends along the right side wall of the boss portion 31 to the flat portion 32 on the right side of the boss portion 31. Since the grid 2 has a trapezoidal shape, the boss portion 31 also has a trapezoidal shape.
  • first active layer 4a and the second active layer 4b may be made of a ZnO-based material, an In 2 O 3 -based material, a SnO 2 -based material, or other metal oxide semiconductor material.
  • a first source 5a is formed on the flat portion 32 extending to the left of the boss portion 31, and a second source 5b is formed on the flat portion 32 extending to the right side of the boss portion 31.
  • the first source 5a and the second source 5b are connected to each other.
  • the first source 5a and the second source 5b are integrally formed and have a semi-circular shape such as a ring shape or a U-shape as a whole; thus, a single wire and an integrated first source 5a and second source may be passed through a wire 5b is connected to ensure stability of voltage applied to the first source 5a and the second source 5b.
  • a first source 5a is formed on the first active layer 4a on the boss 31, and a second active layer 4b is located on the boss 31.
  • a second source 5b is formed thereon, and the first source 5a and the second source 5b are connected to each other.
  • the first source 5a is formed on the flat portion 32 on the left side of the boss portion 31, and the second source is formed on the flat portion 32 on the right side of the boss portion 31. Extreme 5b. Then, the convex portions 31 are respectively formed at the opposite ends of the convex portion 31.
  • the first active layer 4a and the second active layer 4b, the first active layer 4a extends along the left side wall of the convex portion 31 to the first source 5a, and the second active layer 4b along the convex
  • the right side wall of the rising portion 31 extends onto the second source 5b.
  • a passivation layer 6 covering the first active layer 4a, the second active layer 4b, the first source 5a, the second source 5b, and the gate insulating layer 3 is formed.
  • the passivation layer 6 may be made of an insulating material such as SiN x , SiO x , Al 2 O 3 or the like.
  • a first via hole 6a exposing the first active layer 4a on the bump portion 31 is formed in the passivation layer 6, and the exposed bump portion 31 is formed in the passivation layer 6.
  • the second via 6b of the second active layer 4b is also applicable to the embodiment shown in FIG. 4, as shown in FIG.
  • a first via hole 6a exposing the first active layer 4a extending to the flat portion 32 located on the left side of the convex portion 31 is formed in the passivation layer 6
  • a second via hole 6b exposing the second active layer 4b extending to the flat portion 32 on the right side of the convex portion 31 is formed in the passivation layer 6.
  • a drain electrode 7 is formed on the passivation layer 6, and the drain electrode 7 passes through the first via hole 6a and the second via hole 6b and the first active layer 4a and the second portion on the convex portion 31, respectively.
  • the source layer 4b is in contact.
  • the distance between the contact plane of the drain electrode 7 and the first active layer 4a on the convex portion 31 and the contact plane of the first source layer 5a with the first active layer 4a on the flat portion 32 is equal to the convex portion.
  • the height of 31 the distance between the contact plane of the drain 7 and the second active layer 4b on the boss 31 and the contact plane of the second source 5b with the second active layer 4b on the flat portion 32 is equal to the bump The height of the portion 31.
  • the drain electrode 7 may be made of a transparent metal oxide semiconductor conductive material such as ITO or IZO. It should be noted that in the present embodiment, the drain 7 and the pixel electrode are simultaneously formed using the same material.
  • a drain electrode 7 is formed on the passivation layer 6, and the drain electrode 7 passes through the first via hole 6a and the second via hole 6b and the first portion on the flat portion 32, respectively.
  • the active layer 4a is in contact with the second active layer 4b.
  • the channel between the drain 7 and the first source 5a or the second source 5b is first by the left side wall or the right side wall of the convex portion 31.
  • the source layer 4a or the second active layer 4b is configured such that the length of the channel is determined by the length of the left side wall or the right side wall of the convex portion 31, and the length of the left side wall or the right side wall of the convex portion 31 is determined by the grid
  • the length of the left side wall or the right side wall of the pole 2 ie, the height of the gate 2 is determined, so the length of the channel is determined by the length of the left side wall or the right side wall of the gate 2, thereby passing through the control gate 2
  • the length of the left or right side wall controls the length of the channel.
  • the length of the left side wall or the right side wall of the control gate 2 is short, and the length of the channel can be made short.
  • a short-channel thin film transistor is realized, so that the fabricated thin film transistor has a larger aspect ratio and a larger on-state current.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管，其包括：在基板（1）上的栅极（2）、栅极绝缘层（3）、设置于栅极绝缘层（3）的凸起部（31）的两端的第一有源层（4a）和第二有源层（4b）、分别与第一有源层（4a）和第二有源层（4b）接触的第一源极（5a）和第二源极（5b）、钝化层（6）、钝化层（6）中的第一过孔（6a）和第二过孔（6b）、在所述钝化层（6）上且分别通过第一过孔（6a）和第二过孔（6b）与第一有源层（4a）和第二有源层（4b）接触的漏极（7），漏极（7）与第一有源层（4a）的接触平面与第一源极（5a）与第一有源层（4a）的接触平面之间的距离等于凸起部（31）的高度，漏极（7）与第二有源层（4b）的接触平面与第二源极（5b）与第二有源层（4b）的接触平面之间的距离等于凸起部（31）的高度。

Description

薄膜晶体管及其制作方法 技术领域
本发明属于半导体技术领域，具体地讲，涉及一种能够实现较短沟道的薄膜晶体管及其制作方法。
背景技术
金属氧化物半导体薄膜晶体管以其良好的器件性能，较低的工艺成本，被认为是下一代平板显示中的关键技术。然而，随着显示器性能的提高，要求金属氧化物半导体薄膜晶体管中的沟道具有更大的宽长比，而沟道的宽长比决定了该金属氧化物半导体薄膜晶体管的功能特性，在沟道的宽度W一定的条件下，缩短沟道的长度L能够使该金属氧化物半导体薄膜晶体管具有更大的宽长比W/L，从而具有更大的开态电流。
然而，传统的金属氧化物半导体薄膜晶体管在制作过程中，沟道的长度L直接受光刻工艺的限制，因此实现短沟道有较大的难度。
发明内容
为了解决上述现有技术存在的问题，本发明提供了一种薄膜晶体管，其包括：基板；在所述基板上的栅极；覆盖所述基板和所述栅极的栅极绝缘层，所述栅极绝缘层覆盖所述栅极的部分凸起，以形成凸起部，所述栅极绝缘层覆盖所述基板的部分未凸起，以形成平坦部；在所述凸起部上且分别位于所述凸起部两端的第一有源层和第二有源层，所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上；与所述第一有源层接触的第一源极，以及与所述第二有源层接触的第二源极，所述第一源极与所述第二源极彼此连接；覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层；在所述钝化层中且暴露所述第一有源层的第一过孔，以及在所述钝化层中且暴露所述第二有源层的第二过 孔；在所述钝化层上且分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极，所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度，所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度。
进一步地，所述第一源极位于延伸至所述平坦部上的所述第一有源层上，所述第二源极位于延伸至所述平坦部上的所述第二有源层上；所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露。
进一步地，所述第一源极位于在所述凸起部上的所述第一有源层上，所述第二源极位于在所述凸起部上的所述第二有源层上；所述第一过孔和所述第二过孔分别将延伸至所述平坦部上的第一有源层和第二有源层暴露。
进一步地，所述第一源极位于所述平坦部与延伸至所述平坦部上的所述第一有源层之间，所述第二源极位于所述平坦部与延伸至所述平坦部上的所述第二有源层之间；所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露。
进一步地，所述栅极的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
进一步地，所述栅极的中间部分凸起，且所述栅极的中间部分的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
本发明还提供了一种薄膜晶体管的制作方法，其包括：在基板上形成栅极；形成覆盖所述基板和所述栅极的栅极绝缘层；其中，所述栅极绝缘层覆盖所述栅极的部分凸起，以形成凸起部，所述栅极绝缘层覆盖所述基板的部分未凸起，以形成平坦部；在所述凸起部上形成分别位于所述凸起部两端的第一有源层和第二有源层；其中，所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上；形成与所述第一有源层接触的第一源极，且形成与所述第二有 源层接触的第二源极；其中，所述第一源极与所述第二源极彼此连接；形成覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层；在所述钝化层中形成暴露所述第一有源层的第一过孔，且在所述钝化层中形成暴露所述第二有源层的第二过孔；在所述钝化层上形成分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极；其中，所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度，所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度。
进一步地，所述第一源极和所述第二源极的形成方法包括：在延伸至所述平坦部上的所述第一有源层上形成所述第一源极，且在延伸至所述平坦部上的所述第二有源层上形成所述第二源极；所述第一过孔和所述第二过孔的形成方法包括：在所述钝化层中形成暴露出位于所述凸起部上的第一有源层的第一过孔，且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔。
进一步地，所述第一源极和所述第二源极的形成方法包括：在所述凸起部上的所述第一有源层上形成所述第一源极，且在所述凸起部上的所述第二有源层上形成所述第二源极；所述第一过孔和所述第二过孔的形成方法包括：在所述钝化层中形成暴露出延伸至所述平坦部上的第一有源层的第一过孔，且在所述钝化层中形成暴露出延伸至所述平坦部上的第二有源层的第二过孔。
进一步地，所述第一源极和所述第二源极的形成方法包括：在所述平坦部与延伸至所述平坦部上的所述第一有源层之间形成所述第一源极，且在所述平坦部与延伸至所述平坦部上的所述第二有源层之间形成所述第二源极；所述第一过孔和所述第二过孔的形成方法包括：在所述钝化层中形成暴露出位于所述凸起部上的第一有源层的第一过孔，且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔。
本发明的有益效果：本发明通过制作具有垂直结构的薄膜晶体管， 从而保证了其中沟道的长度由栅极的侧壁长度所决定；相比现有技术中的薄膜晶体管其中的沟道长度由光刻工艺所控制，本发明的薄膜晶体管中沟道的长度不受光刻工艺的影响，可以实现短沟道，从而得到的短沟道的薄膜晶体管具有更大的宽长比，进而具有更大的开态电流。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1a至图1g是根据本发明的实施例的薄膜晶体管的制作方法的流程图；
图2是根据本发明的另一实施例的薄膜晶体管的结构示意图；
图3是根据本发明的又一实施例的薄膜晶体管的结构示意图；
图4是根据本发明的又一实施例的薄膜晶体管的结构示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚元件，可以夸大元件的形状和尺寸，并且相同的标号将始终被用于表示相同或相似的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
图1a至图1g示出了根据本发明的实施例的薄膜晶体管的制作流程图。
首先，参照图1a，在基板1上形成栅极2。这里，栅极2的截面形状呈梯形状，但本发明并不限制于此。例如，作为本发明的另一实 施方式，如图2所示，栅极2的中间部分凸起，即栅极2的中间部分与其两端具有台阶差，并且栅极2的中间部分的截面形状呈梯形状。
此外，栅极2可以由Al、Mo、Cu、Ag等金属材料制成。
接着，参照图1b，形成覆盖基板1和栅极2的栅极绝缘层3。这里，栅极绝缘层3覆盖栅极2的部分凸起，以形成凸起部31，而栅极绝缘层3直接覆盖基板1的部分未凸起，以形成平坦部32。一般而言，凸起部31的两侧均为平坦部32。
此外，栅极绝缘层3可以由SiNx、SiOx、Al2O3等绝缘材料制成。
接着，参照图1c，在凸起部31上形成分别位于凸起部31两端的第一有源层4a和第二有源层4b，第一有源层4a沿着凸起部31的左侧壁延伸至位于凸起部31左侧的平坦部32上，而第二有源层4b沿着凸起部31的右侧壁延伸至位于凸起部31右侧的平坦部32上。由于栅极2呈梯形状，对应地，凸起部31亦呈梯形状。
进一步地，第一有源层4a和第二有源层4b之间具有间隔，从而暴露出凸起部31。此外，第一有源层4a和第二有源层4b可以由ZnO基材料、In2O3基材料、SnO2基材料或者其他金属氧化物半导体材料制成。
接着，参照图1d，在延伸至位于凸起部31左侧的平坦部32上形成第一源极5a，且在延伸至位于凸起部31右侧的平坦部32上形成第二源极5b，第一源极5a和第二源极5b彼此连接。例如，第一源极5a和第二源极5b一体形成，并整体呈环状或U字型等半包围形状；这样，可通过一根导线与一体的第一源极5a和第二源极5b相连，以保证对第一源极5a和第二源极5b施加电压的稳定性。
作为本发明的另一实施方式，参照图3，在位于凸起部31上的第一有源层4a上形成第一源极5a，且在位于凸起部31上的第二有源层4b上形成第二源极5b，第一源极5a和第二源极5b彼此连接。
作为本发明的另一实施方式，请参照图4，在凸起部31左侧的平坦部32上形成第一源极5a，且在凸起部31右侧的平坦部32上形成第二源极5b。接着，在凸起部31上形成分别位于凸起部31两端 的第一有源层4a和第二有源层4b，第一有源层4a沿着凸起部31的左侧壁延伸至第一源极5a上，而第二有源层4b沿着凸起部31的右侧壁延伸至第二源极5b上。
接着，参照图1e，形成覆盖第一有源层4a、第二有源层4b、第一源极5a、第二源极5b和栅极绝缘层3的钝化层6。
此外，钝化层6可以由SiNx、SiOx、Al2O3等绝缘材料制成。
接着，参照图1f，在钝化层6中形成暴露出凸起部31上的第一有源层4a的第一过孔6a，且在钝化层6中形成暴露出凸起部31上的第二有源层4b的第二过孔6b。需要说明的是，图1f所示的第一过孔6a和第二过孔6b的形成位置也适用于图4所示的实施例，具体如图4所示。
作为本发明的另一实施例，参照图3，在钝化层6中形成暴露出延伸至位于凸起部31左侧的平坦部32上的第一有源层4a的第一过孔6a，且在钝化层6中形成暴露出延伸至位于凸起部31右侧的平坦部32上的第二有源层4b的第二过孔6b。
最后，参照图1g，在钝化层6上形成漏极7，漏极7分别通过第一过孔6a和第二过孔6b与凸起部31上的第一有源层4a和第二有源层4b接触。这样，漏极7与凸起部31上的第一有源层4a的接触平面与第一源极5a与平坦部32上的第一有源层4a的接触平面之间的距离等于凸起部31的高度，漏极7与凸起部31上第二有源层4b的接触平面与第二源极5b与平坦部32上的第二有源层4b的接触平面之间的距离等于凸起部31的高度。
需要说明的是，图1所示的漏极7的形成位置也适用于图4所示的实施例，具体如图4所示。
此外，漏极7可以由ITO、IZO等透明金属氧化物半导体导电材料制成。需要说明的是，在本实施例中，利用同种材料同时制成漏极7和像素电极。
作为本发明的另一实施方式，参照图3，在钝化层6上形成漏极7，漏极7分别通过第一过孔6a和第二过孔6b与平坦部32上的第一 有源层4a和第二有源层4b接触。
如此，当本实施例的薄膜晶体管在使用时，漏极7与第一源极5a或第二源极5b之间的沟道由凸起部31左侧壁或者右侧壁上的第一有源层4a或第二有源层4b构成，即沟道的长度由凸起部31左侧壁或者右侧壁的长度决定，而凸起部31左侧壁或者右侧壁的长度是由栅极2的左侧壁或者右侧壁的长度(即栅极2的高度)决定，因此沟道的长度由栅极2的左侧壁或者右侧壁的长度决定，从而通过控制栅极2的左侧壁或者右侧壁的长度来控制沟道的长度。这样，控制栅极2的左侧壁或者右侧壁的长度短，就能够使沟道的长度短。
综上所述，根据本发明的实施例，实现了短沟道的薄膜晶体管，从而使制作得到的薄膜晶体管具有更大的宽长比，具有更大的开态电流。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (16)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    在所述基板上的栅极；
    覆盖所述基板和所述栅极的栅极绝缘层，所述栅极绝缘层覆盖所述栅极的部分凸起，以形成凸起部，所述栅极绝缘层覆盖所述基板的部分未凸起，以形成平坦部；
    在所述凸起部上且分别位于所述凸起部两端的第一有源层和第二有源层，所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上；
    与所述第一有源层接触的第一源极，以及与所述第二有源层接触的第二源极，所述第一源极与所述第二源极彼此连接；
    覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层；
    在所述钝化层中且暴露所述第一有源层的第一过孔，以及在所述钝化层中且暴露所述第二有源层的第二过孔；
    在所述钝化层上且分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极，所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度，所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一源极位于延伸至所述平坦部上的所述第一有源层上，所述第二源极位于延伸至所述平坦部上的所述第二有源层上；所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第一源极位于在所述凸起部上的所述第一有源层上，所述第二源极位于在所述凸 起部上的所述第二有源层上；所述第一过孔和所述第二过孔分别将延伸至所述平坦部上的第一有源层和第二有源层暴露。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述第一源极位于所述平坦部与延伸至所述平坦部上的所述第一有源层之间，所述第二源极位于所述平坦部与延伸至所述平坦部上的所述第二有源层之间；所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述栅极的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  6. 根据权利要求2所述的薄膜晶体管，其中，所述栅极的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  7. 根据权利要求3所述的薄膜晶体管，其中，所述栅极的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  8. 根据权利要求4所述的薄膜晶体管，其中，所述栅极的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  9. 根据权利要求1所述的薄膜晶体管，其中，所述栅极的中间部分凸起，且所述栅极的中间部分的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  10. 根据权利要求2所述的薄膜晶体管，其中，所述栅极的中间部分凸起，且所述栅极的中间部分的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  11. 根据权利要求3所述的薄膜晶体管，其中，所述栅极的中间部分凸起，且所述栅极的中间部分的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  12. 根据权利要求4所述的薄膜晶体管，其中，所述栅极的中间部分凸起，且所述栅极的中间部分的截面形状呈梯形状，所述凸起部的截面形状呈梯形状，所述凸起部的侧壁倾斜。
  13. 一种薄膜晶体管的制作方法，其中，包括：
    在基板上形成栅极；
    形成覆盖所述基板和所述栅极的栅极绝缘层；其中，所述栅极绝缘层覆盖所述栅极的部分凸起，以形成凸起部，所述栅极绝缘层覆盖所述基板的部分未凸起，以形成平坦部；
    在所述凸起部上形成分别位于所述凸起部两端的第一有源层和第二有源层；其中，所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上；
    形成与所述第一有源层接触的第一源极，且形成与所述第二有源层接触的第二源极；其中，所述第一源极与所述第二源极彼此连接；
    形成覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层；
    在所述钝化层中形成暴露所述第一有源层的第一过孔，且在所述钝化层中形成暴露所述第二有源层的第二过孔；
    在所述钝化层上形成分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极；其中，所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度，所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度。
  14. 根据权利要求13所述的薄膜晶体管的制作方法，其中，所述第一源极和所述第二源极的形成方法包括：在延伸至所述平坦部上的所述第一有源层上形成所述第一源极，且在延伸至所述平坦部上的所述第二有源层上形成所述第二源极；
    所述第一过孔和所述第二过孔的形成方法包括：在所述钝化层中 形成暴露出位于所述凸起部上的第一有源层的第一过孔，且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔。
  15. 根据权利要求13所述的薄膜晶体管的制作方法，其中，所述第一源极和所述第二源极的形成方法包括：在所述凸起部上的所述第一有源层上形成所述第一源极，且在所述凸起部上的所述第二有源层上形成所述第二源极；
    所述第一过孔和所述第二过孔的形成方法包括：在所述钝化层中形成暴露出延伸至所述平坦部上的第一有源层的第一过孔，且在所述钝化层中形成暴露出延伸至所述平坦部上的第二有源层的第二过孔。
  16. 根据权利要求13所述的薄膜晶体管的制作方法，其中，所述第一源极和所述第二源极的形成方法包括：在所述平坦部与延伸至所述平坦部上的所述第一有源层之间形成所述第一源极，且在所述平坦部与延伸至所述平坦部上的所述第二有源层之间形成所述第二源极；
    所述第一过孔和所述第二过孔的形成方法包括：在所述钝化层中形成暴露出位于所述凸起部上的第一有源层的第一过孔，且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔。
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