WO2018006779A1 - 一种基于二维半导体的电子器件及其制造方法 - Google Patents

一种基于二维半导体的电子器件及其制造方法 Download PDF

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WO2018006779A1
WO2018006779A1 PCT/CN2017/091509 CN2017091509W WO2018006779A1 WO 2018006779 A1 WO2018006779 A1 WO 2018006779A1 CN 2017091509 W CN2017091509 W CN 2017091509W WO 2018006779 A1 WO2018006779 A1 WO 2018006779A1
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doping
region
dimensional semiconductor
gate
electrode
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PCT/CN2017/091509
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English (en)
French (fr)
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杨雯
张日清
夏禹
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华为技术有限公司
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Priority to EP17823591.7A priority Critical patent/EP3467877A4/en
Publication of WO2018006779A1 publication Critical patent/WO2018006779A1/zh
Priority to US16/239,401 priority patent/US11088032B2/en

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Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to an electronic device based on a two-dimensional semiconductor and a method of fabricating the same.
  • two-dimensional semiconductor materials can effectively prevent the occurrence of short channel effects in small-sized devices.
  • the variety of two-dimensional semiconductor materials can also provide a variety of options for devices with different requirements. Therefore, two-dimensional semiconductor materials are considered to be important materials in future integrated circuits that are expected to continue Moore's Law.
  • TMDs transition metal dichalcogenides
  • Se 2 Se 3 tris(Se 2 Se 3 )
  • black phosphorus etc.
  • proper doping can not only be realized according to the requirements of the device.
  • the traditional semiconductor doping method - ion implantation has not been applied to two-dimensional semiconductor materials.
  • substitutional doping It is common practice to introduce impurities during the growth of a two-dimensional semiconductor so that the impurity atoms exist in the form of some atoms in the two-dimensional semiconductor in the crystal lattice of the two-dimensional semiconductor. For example, by replacing a part of molybdenum atoms with germanium atoms, a germanium atom is doped in molybdenum disulfide.
  • the substitutional doping has a stable doping effect, but causes a large amount of damage to the lattice of the two-dimensional semiconductor, resulting in a decrease in electrical properties such as field effect mobility of the two-dimensional semiconductor.
  • the second method of doping in the prior art is surface charge transfer, which adsorbs specific gas, liquid molecules or solid thin films on the surface of the two-dimensional semiconductor, and realizes the transfer of two-dimensional semiconductors by charge transfer between the adsorbed molecules and the two-dimensional semiconductor.
  • Doping For example, p-type doping of WSe 2 can be achieved by charge transfer between nitrogen dioxide (NO 2 ) and tungsten disilicide (WSe 2 ), which can be achieved by cesium carbonate (Cs 2 CO 3 ) and molybdenum disulfide ( The charge transfer between MoS 2 ) achieves n-type doping of MoS 2 .
  • the doping method based on surface charge transfer is susceptible to the surrounding environment, resulting in an unstable doping effect.
  • the third method of doping in the prior art is to treat the two-dimensional semiconductor by plasma to achieve the effect of doping the two-dimensional semiconductor.
  • p-type doping of MoS 2 can be achieved by treating MoS 2 with a sulfur hexafluoride (SF 6 ) plasma.
  • SF 6 sulfur hexafluoride
  • the plasma doping process has a damaging effect on the chemical bonds of the two-dimensional semiconductor surface, and thus has a negative impact on the electrical properties of the electronic device.
  • Embodiments of the present invention provide an electronic device based on a two-dimensional semiconductor and a method of fabricating the same.
  • an electronic device based on a two-dimensional semiconductor comprising:
  • the doping effect is n-type doping or p-type doping;
  • the two-dimensional semiconductor layer is over the insulating dielectric layer, and at least a portion of the two-dimensional semiconductor layer is located in the doped region or the filled region Above.
  • the electronic device is a field effect transistor, the field effect transistor further comprising a heavily doped silicon layer and a gate region, wherein the heavily doped silicon layer is located in the insulation Below the dielectric layer; the first electrode is a source, the second electrode is a drain, the gate region includes a gate dielectric and a gate electrode, and the gate dielectric is over the channel region, the gate An electrode is located above the gate dielectric.
  • the gate region above the channel region is also commonly referred to as the top gate.
  • the field effect transistor is a CMOS field effect transistor;
  • the channel region includes a first channel region and a second channel region
  • the source includes a first source and a second source, the drain includes a first drain and a second drain, and the gate region includes a first gate region and a second gate region, the doping The region includes a first doped region and a second doped region;
  • the doping type of the first doping region is n-type doping
  • the first channel region is located above the first doping region
  • the first source and the first drain are located at the first
  • the first gate region includes a first gate dielectric and a first gate electrode, the first gate dielectric is over the first channel region, and the first gate electrode is located at Above the first gate dielectric; this portion constitutes an nFET.
  • the doping type of the second doping region is p-type doping
  • the second channel region is above the second doping region
  • the second source and the second drain are located at the On both sides of the two-channel region
  • the second gate region includes a second gate dielectric and a second gate electrode
  • the second gate dielectric is over the second channel region
  • the second gate electrode is located at Above the second gate dielectric. This part constitutes a pFET.
  • the transistor is a gate-controlled PN junction, and the two-dimensional semiconductor exhibits n-type conductivity characteristics on the insulating dielectric layer.
  • the doping type of the doping region is p-type doping, the area of the doping region is smaller than the area of the channel region; or the two-dimensional semiconductor exhibits p-type conductivity characteristics on the insulating dielectric layer.
  • the doping type of the doping region is n-type doping, and the area of the doping region is smaller than the area of the channel region.
  • the electronic device is a thin film transistor
  • the first electrode is a source
  • the second electrode is a drain
  • the thin film transistor further includes a gate electrode and an insulation a substrate, the gate electrode being over the insulating substrate, the insulating dielectric layer being over the gate electrode.
  • a method of fabricating a two-dimensional semiconductor-based electronic device comprising:
  • the material of the insulating medium being SiO 2 or a high-k dielectric
  • the doping region containing a dopant having a doping effect on the two-dimensional semiconductor layer Filling a region filled with a solid material having a doping effect on the two-dimensional semiconductor; transferring a two-dimensional semiconductor layer onto the insulating dielectric layer; according to the device size and the area of the doped region
  • the semiconductor is etched to form a channel region; a first electrode and a second electrode are formed on both sides of the etched two-dimensional semiconductor.
  • the electronic device is a field effect transistor
  • the insulating dielectric layer further comprises: forming the insulating layer on the heavily doped silicon layer a dielectric layer; after forming the first electrode and the second electrode on both sides of the etched two-dimensional semiconductor, further comprising: forming a gate dielectric over the channel region; forming a gate electrode on the gate dielectric
  • the first electrode is a source and the second electrode is a drain.
  • the transistor in conjunction with the first possible implementation of the second aspect, in a second implementation manner, is a gate-controlled PN junction, and the two-dimensional semiconductor exhibits n-type conductivity characteristics on the insulating dielectric layer.
  • the doping type of the doping region is p-type doping, the area of the doping region is smaller than the area of the channel region; or the two-dimensional semiconductor exhibits p-type conductivity characteristics on the insulating dielectric layer.
  • the doping type of the doping region is n-type doping, and the area of the doping region is smaller than the area of the channel region.
  • the electronic device is a thin film transistor, and before the insulating dielectric layer forms a doped region or a filled region, the method further includes:
  • a gate electrode is formed on the insulating substrate, and the insulating dielectric layer is formed on the gate electrode.
  • the doping effect is n-type doping
  • the doping source of the dopant includes the following At least one of: an amino group-containing plasma, a gas and a chemical reagent, a gas containing sodium, potassium, and chloride ions and a solution (such as a DCE solution), a PEI solution, a PTSA solution, a BV solution, a NADH solution, and a PVA solution.
  • the doping effect is p-type doping
  • the doping source of the dopant includes the following At least one of: a plasma or gas containing O and F, a Br 2 , I 2 or AuCl 3 solution, a solution containing Pt, Ag, Au, Pd or Sc metal nanoparticles, a F 4 TCNQ solution, a TCNQ solution, wherein
  • the plasma containing oxygen and fluorine SF 6 plasma, CHF 3 plasma, CF 4 plasma, O 2 plasma, and the gas containing oxygen and fluorine includes ozone and NO 2 .
  • the method for forming a filling region on the insulating dielectric layer includes:
  • the insulating dielectric layer is etched to obtain a trench in which a solid material having a doping effect on the two-dimensional semiconductor is filled to form the filled region.
  • the doping effect is n-type doping
  • the solid material is Cs 2 CO 3 ; or the doping effect For p-doping, the solid material is MoO 3 .
  • the two-dimensional semiconductor material is any one of the following: MoS 2, MoSe 2, MoTe 2, WS 2, WSe 2, WTe 2, GeS 2, GeSe 2, GeTe 2 , SnS 2 , SnSe 2 , SnTe 2 , SnO, PbS 2 , PbSe 2 , PbTe 2 , GaS, GaSe, GaTe, InS, InSe, InTe, Bi 2 Se 3 , graphene, black phosphorus, arsenene, decene , terpenes, tinnes and silenes.
  • the high-k dielectric comprises any one of the following: Al 2 O 3 , WO 3 , Ta 2 O 5 , HfO 2 , ZnO 2 , TiO 2 , CaO, ZrO 2 , La 2 O 3 , BaO, MgO, HfSiO x , ZrSiO x , HfLaO x , HfZrO x , HfAlO x , LaAlO x , Y 2 O 3 , SrO, Si 3 N 4 .
  • the number of layers of the two-dimensional semiconductor is 1-10 layers.
  • the insulating dielectric layer is a uniform dielectric film.
  • the present invention only needs to form a uniform dielectric film by a conventional method, and the insulating dielectric layer is not required to have a special structure, the process is simple, and the manufacturing cost is low.
  • a doping region of a two-dimensional semiconductor is doped or a solid material is partially filled in a medium surrounding the semiconductor to form a filling region, and a doping region or a filling region is used to perform a doping effect on a two-dimensional semiconductor characteristic to realize a two-dimensional semiconductor.
  • the doping of the two-dimensional semiconductor in the embodiment of the present invention is not a direct processing of the two-dimensional semiconductor, so that the damage caused by the doping process to the two-dimensional semiconductor and the degradation of the device performance caused thereby can be effectively improved, and the device after doping is improved. Performance stability.
  • FIG. 1 is a flow chart of manufacturing a two-dimensional semiconductor-based electronic device according to an embodiment of the present invention
  • FIG. 2 is a schematic side view showing a structure of manufacturing a two-dimensional semiconductor-based electronic device according to an embodiment of the present invention
  • FIG. 3 is a schematic side view of a CMOS field effect transistor manufacturing process according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a method of fabricating a CMOS field effect transistor according to an embodiment of the present invention
  • FIG. 5 is a flowchart of a method of fabricating a gate-controlled P-N junction according to an embodiment of the present invention
  • FIG. 6 is a schematic side view showing a manufacturing method of a gate-controlled P-N junction according to an embodiment of the present invention
  • FIG. 7 is a flow chart showing still another manufacturing method of a gate-controlled P-N junction according to an embodiment of the present invention.
  • FIG. 8 is a side elevational view showing still another manufacturing method of a gate-controlled P-N junction according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of still another MOSFET for manufacturing a two-dimensional semiconductor according to an embodiment of the present invention.
  • FIG. 10 is a side view of still another MOSFET for manufacturing a two-dimensional semiconductor according to an embodiment of the present invention.
  • FIG. 11 is a flow chart of manufacturing a thin film transistor according to an embodiment of the present invention.
  • FIG. 12 is a side view showing the structure of a thin film transistor according to an embodiment of the present invention.
  • Embodiments of the present invention provide a two-dimensional semiconductor-based electronic device including various types of transistors.
  • the basic structure of the two-dimensional semiconductor-related electronic device shown in FIG. 2(D) includes an insulating dielectric layer 202, a channel region 204, a first electrode 205, and a second electrode 206.
  • the channel region 204 is above the insulating dielectric layer 202, and the first electrode 205 and the second electrode 206 are located on both sides of the channel region 204.
  • the electronic device is a field effect transistor, the first electrode 205 and the second electrode 206 are respectively the source and the drain of the device.
  • the material of the insulating dielectric layer is SiO 2 or a high-k dielectric, and the channel region 204 is a two-dimensional semiconductor layer.
  • the insulating dielectric layer is provided with a doping region 203 containing a dopant having a doping effect on the two-dimensional semiconductor layer. If the method of doping the insulating dielectric layer is not employed, the doping effect solid material may be filled in the insulating dielectric layer to form the filling region 203.
  • the high-k dielectric may be any of the following: Al 2 O 3 , WO 3 , Ta 2 O 5 , HfO 2 , ZnO 2 , TiO 2 , CaO, ZrO 2 , La 2 O 3 , BaO, MgO, HfSiO x ZrSiO x , HfLaO x , HfZrO x , HfAlO x , LaAlO x , Y 2 O 3 , SrO, Si 3 N 4 .
  • the dopants vary depending on the device type and performance requirements.
  • the insulating medium layer can be formed by a conventional method, and a uniform dielectric film can be formed without using a special structure.
  • the dielectric layer in which the channel region 204 (the two-dimensional semiconductor layer) is located may have a large area or a portion of the region doped or filled.
  • the device may further include a bottom gate 201 and/or a top gate 207, which is indicated by a broken line in Fig. 2(E).
  • a plurality of devices such as field effect transistors
  • doped regions or filled regions
  • the doping effect in the embodiment of the present invention may be n-type doping or p-type doping, depending on the device type and performance requirements.
  • the doping region may be provided with dopants, such as molecules, ions or functional groups having a doping effect on the two-dimensional semiconductor.
  • a method of manufacturing the electronic device shown in FIG. 2(D) includes the following steps:
  • the dopant source includes, but is not limited to, at least one of the following: sodium (Na) ions, potassium (K) ions, plasmas containing amino groups, gases and chemical reagents, containing chlorine (Cl) ions Solution (such as DCE solution), PEI solution, PTSA solution, BV solution, NADH solution, PVA solution, and the like.
  • the dopant source includes, but is not limited to, at least one of the following: SF 6 plasma, CHF 3 plasma, CF 4 plasma, O 2 plasma, ozone, NO 2 , etc. containing oxygen (O And fluorine (F) plasma and gas, Br 2 , I 2 , AuCl 3 solution, containing platinum (Pt), silver (Ag), gold (Au), palladium (Pd), bismuth (Sc) and other metal nanoparticles A solution of particles, F 4 TCNQ solution, or TCNQ solution.
  • the two-dimensional semiconductor is etched according to the device size and the area of the doped region to form a channel region, as shown in FIG. 2(C).
  • step S11 If the electronic device has a bottom gate, it includes before step S11:
  • an insulating dielectric layer 202 is formed over the bottom gate 201. As shown in FIG. 2(E), the bottom gate 201 is indicated by a dashed box.
  • step S14 the method further includes:
  • a top gate 207 is formed over the channel region (two-dimensional semiconductor layer) 204. As shown in FIG. 2(E), the top gate 207 is indicated by a dashed box.
  • the top gate generally includes a gate dielectric and a gate electrode.
  • a gate dielectric (not shown) is typically formed over the channel region 204, and then a gate electrode (not shown) is formed over the gate dielectric.
  • the thickness of a two-layer semiconductor material of a single layer or a few layers is only at the atomic level, so the influence of the surrounding medium environment and manufacturing process on the characteristics of the two-dimensional semiconductor material is much greater than that of the conventional semiconductor.
  • MoS 2 the bulk material MoS 2 generally exhibits n-type semiconductor characteristics, but as the thickness of MoS 2 is reduced (the number of layers is reduced), the influence of the environment on the characteristics of MoS 2 is gradually increased.
  • the thickness of MoS 2 is lowered to a certain extent, bipolar conductivity can be exhibited under the induction of a specific environment such as PMMA.
  • the embodiment of the present invention utilizes the medium and the two-dimensional by changing the medium environment around the two-dimensional semiconductor (for example, doping or regional filling of the medium in which the two-dimensional semiconductor is located).
  • the two-dimensional semiconductor-based electronic device of the embodiment of the present invention does not directly dope the two-dimensional semiconductor itself, and can effectively reduce the damage caused by the doping process to the two-dimensional semiconductor and the device performance degradation caused thereby. Stability of device performance.
  • Common two-dimensional semiconductor materials MoS 2, MoSe 2, MoTe 2, WS 2, WSe 2, WTe 2, GeS 2, GeSe 2, GeTe 2, SnS 2, SnSe 2, SnTe 2, SnO, PbS 2, PbSe 2 , PbTe 2 , GaS, GaSe, GaTe, InS, InSe, InTe, graphene, black phosphorus, arsenene, antimonene and germanene, stannene (stanene), silicene, and the like.
  • the fabrication of a two-dimensional semiconductor-based CMOS device is achieved by doping a substrate medium (insulating dielectric layer) in which the two-dimensional semiconductor is placed.
  • the doping of the substrate medium in this embodiment is embodied in two aspects: 1. Controlling the carrier concentration in the two-dimensional semiconductor channel to achieve control of different conductivity types and device threshold voltages; The concentration of carriers in the source, drain, and extension regions to reduce the contact resistance of the channel with the source and drain electrodes.
  • the CMOS field effect transistor includes a two-dimensional semiconductor-based n-type field effect transistor (2D nFET) and a p-type field effect transistor (2D pFET).
  • the process of fabricating a CMOS field effect transistor includes:
  • the substrate may include a heavily doped silicon layer 301 and an insulating dielectric layer 302 over the heavily doped silicon layer.
  • the heavily doped silicon layer 301 is used as a back electrode, and can be grounded when the device is in operation, or a corresponding voltage can be applied as needed.
  • the material of the insulating dielectric layer 302 may be silicon dioxide (SiO 2 ) or a high-k dielectric.
  • the insulating substrate (in this example, the insulating layer 302) in the region where the 2D nFET is located is first n-type doped to form an n-type doping region 303, as shown in FIG. 3(B).
  • Doping sources include, but are not limited to, sodium ions, potassium ions, plasmas containing amino groups, gases and chemical reagents, solutions containing chloride ions (such as DCE solution), PEI solutions, PTSA solutions, BV solutions, NADH solutions, PVA solutions, etc. .
  • the doping concentration is closely related to the type of two-dimensional semiconductor (original carrier concentration and type), thickness (number of layers), and requirements for 2D nFET threshold voltage.
  • the two-dimensional semiconductor of this embodiment is exemplified by tungsten selenide (WSe 2 ).
  • n-type doping region 304 to reduce the contact resistance between the two-dimensional semiconductor and the source and the drain, as shown in FIG. (C) is shown.
  • the area of the heavily n-doped region 304 may be slightly larger than the actual source and drain contact areas.
  • the doping source may be a plasma containing oxygen (O) or fluorine (F), a gas such as SF 6 plasma, CHF 3 plasma, CF 4 plasma, O 2 plasma, ozone, NO 2 , etc.).
  • the doping source may further include a Br 2 , I 2 , AuCl 3 solution, a solution containing metal nanoparticles such as platinum (Pt), silver (Ag), gold (Au), palladium (Pd), strontium (Sc), and F 4 .
  • the doping concentration is closely related to the type of two-dimensional semiconductor (original carrier concentration and type), thickness (number of layers), and requirements for 2D pFET threshold voltage. There must be a certain interval between the n-doped region 303 domain and the p-doped region 305 for isolation purposes.
  • the defects may be repaired by an annealing process.
  • the two-dimensional semiconductor can be a single layer or a few layers (1-10 layers).
  • the two-dimensional semiconductor is etched by a plasma etching process to obtain channel regions 3071 and 3072, and the channels of different devices are isolated, as shown in FIG. 3(G). Shown.
  • etching can be performed using O 2 plasma.
  • the type of plasma used in the etching process can be selected according to actual conditions.
  • a CMOS field effect transistor according to Embodiment 1 of the present invention includes:
  • the heavily doped silicon layer 301, the insulating dielectric layer 302, the first channel region 3071, the second channel region 3072, the first source 3081, the first drain 3091, the second source 3082, and the second drain 3092 The first gate dielectric 3101, the second gate dielectric 3102, the first gate electrode 3111, and the second gate electrode 3112.
  • the material of the insulating dielectric layer 302 is SiO 2 or a high-k dielectric.
  • the insulating dielectric layer 302 is provided with a first doping region 303 and a second doping region 305.
  • the first channel region 3071 and the second channel region 3072 are two-dimensional. Semiconductor layer.
  • the area of the first doping region 303 is larger than the first channel region 3071, and the area of the second doping region 305 is larger than the second channel region 3072.
  • the first channel region 3071 and the second channel region 3072 are isolated from each other.
  • the doping type of the first doping region 303 is n-type doping
  • the first channel region 3071 is located above the first doping region 303
  • the first source electrode 3081 and the first drain electrode 3091 are located in the first channel region 3071.
  • the first gate region includes a first gate dielectric 3101 and a first gate electrode 3111
  • the first gate dielectric 3101 is located above the first channel region 3071
  • the first gate electrode 3111 is located at the Above the first gate dielectric 3101.
  • the first doping region 303, the first channel region 3071, the first source electrode 3081, the first drain electrode 3091, the first gate dielectric 3101, and the first gate electrode 3111 constitute an nFET.
  • the doping type of the second doping region 305 is p-type doping
  • the second channel region 3072 is located above the second doping region 305
  • the second source region 3082 and the second drain region 3092 are located in the second channel region 3072.
  • the second gate region includes a second gate dielectric 3102 and a second gate electrode 3112.
  • the second gate dielectric 3102 is located above the second channel region 3072
  • the second gate electrode 3112 is located above the second gate dielectric 3102.
  • the second doping region 305, the second channel region 3072, the second source 3082, the second drain 3092, the second gate dielectric 3102, and the second gate electrode 3112 constitute a pFET.
  • nFET and pFET are also two complementary transistors on the left and right sides of the substrate, nFET and pFET, each having a channel region, a source and a drain, and a top gate (gate dielectric and gate electrode). There are doped regions below the entire channel region.
  • Gate-controlled PN junction fabrication based on two-dimensional semiconductors is achieved by doping the substrate insulating dielectric.
  • the two-dimensional semiconductor of the present embodiment is described by taking MoS 2 as an example, but the methods and application scenarios involved are equally applicable to other two-dimensional semiconductor materials.
  • the manufacturing process of the gate-controlled PN junction is shown in Figure 5 and includes the following steps:
  • step S51 preparation and cleaning of the substrate, as shown in Fig. 6(A), is the same as step S41 in the first embodiment.
  • the insulating dielectric layer in this example is exemplified by Al 2 O 3 .
  • step S52 performing p-type doping on the insulating dielectric layer of the p-type region of the P-N junction, as shown in FIG. 6(B).
  • the use of the p-type dopant source is the same as step S44 and step S45 in the first embodiment.
  • step S52 in the present embodiment should be changed to a regional n-type doping to form.
  • the homogenous PN junction, the use of the n-type dopant source is the same as step S42 and step S43 in the first embodiment.
  • the etching process is performed on the MoS 2 to obtain a channel region, as shown in FIG. 6(C).
  • the gate-controlled P-N junction manufactured by the present embodiment includes:
  • the material of the insulating dielectric layer 602 is SiO 2 or a high-k dielectric, and the channel region 604 is a two-dimensional semiconductor layer;
  • the insulating dielectric layer 602 is provided with a doping region 603 containing a dopant having a doping effect on the two-dimensional semiconductor layer 604. If a two-dimensional semiconductor material is used, the n-type conductive property is displayed on the insulating dielectric layer 602. Then, the doping type of the doping region 603 is p-type doping; if the two-dimensional semiconductor material used exhibits p-type conductivity on the insulating dielectric layer 602, the doping type of the doping region 603 is n-type doping.
  • a two-dimensional semiconductor layer (channel region) 604 is disposed over the insulating dielectric layer 602, a portion of the two-dimensional semiconductor layer is over the doped region 603, and an area of the doped region 603 is smaller than an area of the channel region 604.
  • the first electrode 605 and the second electrode 606 are located on both sides of the channel region 604 as a source and a drain of the gate-controlled PN junction, the gate dielectric 607 is located above the channel region 604, and the gate electrode 608 is located in the gate dielectric 607. Above.
  • This embodiment realizes gate-controlled PN junction fabrication based on a two-dimensional semiconductor (taking MoS 2 as an example) by replacing a partial substrate medium.
  • the replacement of the local medium as used herein refers to filling a local region of the insulating dielectric layer with other solid materials having a doping effect on the two-dimensional semiconductor.
  • the process of fabricating a gated PN junction includes:
  • the insulating dielectric layer in this example is exemplified by Al 2 O 3 .
  • the etched trench should be filled with an induced two-dimensional semiconductor display n-type.
  • a material with conductive properties In this case, Cs 2 CO 3 is used for filling; for other two-dimensional semiconductor materials, the material filled in the trench may be different and should be selected according to the actual situation.
  • the gate-controlled P-N junction fabricated by the present embodiment includes:
  • the material of the insulating dielectric layer 802 is SiO 2 or a high-k dielectric, and the channel region 804 is a two-dimensional semiconductor layer;
  • the insulating dielectric layer 802 is provided with a filling region 803 filled with a solid material having a doping effect on the two-dimensional semiconductor layer 804, and if the two-dimensional semiconductor material used exhibits n-type conductivity characteristics on the insulating dielectric layer 802, the filling is performed.
  • the doping effect of the region 803 on the two-dimensional semiconductor is p-type doping; if the two-dimensional semiconductor material used exhibits p-type conductivity on the insulating dielectric layer 802, the doping effect of the filling region 803 on the two-dimensional semiconductor is n Type doping.
  • a two-dimensional semiconductor layer 804 is located above the insulating dielectric layer 802. A portion of the two-dimensional semiconductor layer is above the doped region 803. The area of the doped region 803 is smaller than the area of the channel region 804.
  • the first electrode 805 and the second electrode 806 are located on both sides of the channel region 804 as a source and a drain of the gate-controlled PN junction, the gate dielectric 807 is located above the channel region 804, and the gate electrode 808 is located in the gate dielectric 807. Above.
  • This embodiment reduces the contact resistance of the metal/two-dimensional semiconductor (still taking MoS 2 as an example) in the MOSFET by replacing the partial substrate medium.
  • the replacement of the local medium as used herein refers to filling a local region of the insulating dielectric layer with other solid materials having a doping effect on the two-dimensional semiconductor.
  • the manufacturing process of MOSFE includes:
  • the insulating medium in this example is exemplified by Al 2 O 3 .
  • the trench is filled with a material which can increase the electron concentration, such as Cs 2 CO 3 or the like.
  • a material which can increase the hole concentration is filled in the trench.
  • the MOSFET manufactured by this embodiment includes:
  • the material of the insulating dielectric layer 1002 is SiO 2 or a high-k dielectric, and the channel region 1005 is a two-dimensional semiconductor layer;
  • the insulating dielectric layer 1002 is provided with a first filling region 1003 and a second filling region 1004, respectively filled with a solid material having a doping effect on the two-dimensional semiconductor layer 1005.
  • the two-dimensional semiconductor layer 1005 is located above the insulating dielectric layer 1002, and a portion of the two-dimensional semiconductor layer is located above the doping region 1003.
  • the area of the doping region 1003 is smaller than the area of the channel region 1005.
  • the first electrode 1006 and the second electrode 1007 are located on both sides of the channel region 1005.
  • the gate dielectric 1008 is located above the channel region 1005, and the gate electrode 1009 is located above the gate dielectric 1008.
  • the trench is filled with a material which can increase the electron concentration.
  • the trench is filled with a material which can increase the hole concentration.
  • a method of manufacturing a two-dimensional semiconductor-based thin film transistor includes:
  • the substrate material is an insulating material including glass, quartz, sapphire, ceramic, plastic, PI, PET, and the like.
  • a glass substrate is taken as an example, and the substrate and the embodiment herein are as an example. One to four are different.
  • the bottom gate electrode may be a metal material such as gold (Au), titanium (Ti), nickel (Ni), platinum (Pt), or the like, or may be ITO. This embodiment takes ITO as an example.
  • the gate dielectric material may be SiO 2 or a high-k material such as Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 or La 2 O 3 .
  • HfO 2 is taken as an example.
  • the thin film transistor manufactured in this embodiment is as shown in FIG. 12(F) and includes:
  • the insulating dielectric layer is provided with a first doping region 1204 and a second doping region 1205, respectively, under the contact regions of the first electrode 1207 and the second electrode 1208.
  • the first electrode 1207 and the second electrode 1208 are used as a source and a drain.
  • the bottom gate electrode 1202 is located above the substrate 1201, the insulating dielectric layer 1203 is located above the bottom gate electrode 1202, the channel region 1206 is located above the insulating dielectric layer 1203, and the first electrode 1207 and the second electrode 1208 are located in the channel region 1206. On both sides.
  • the thin film transistor has a bottom gate electrode and no top gate.
  • the channel region 1206 is a two-dimensional semiconductor layer, and the first doping region 1204 and the second doping region 1205 contain a dopant having a doping effect on the two-dimensional semiconductor.
  • the doping effect is n-type doping; for a p-type thin film transistor, the doping effect is p-type doping.
  • the above describes the doping of the two-dimensional semiconductor material by differently doping or partially filling different solid material mediums in the dielectric layer where the two-dimensional semiconductor layer is located in different application scenarios.
  • the manufacturing process, the actual application scenario is not limited to this.
  • the methods involved in the above embodiments may also be used in combination, as in the first embodiment, the metal/two-dimensional semiconductor contact resistance may be reduced by regional doping of the insulating medium in which the source and drain contact regions are located, and
  • the partial medium filling method employed in the fourth embodiment has a similar effect.
  • the present invention can greatly reduce the damage of doping to two-dimensional semiconductor materials and reduce the doping process. Defect density introduced in two-dimensional semiconductor materials.
  • the embodiment of the present invention does not bring similar problems in reliability to the device, and the performance of the device after doping can be kept relatively stable.
  • the present invention can effectively reduce the increase of leakage current between the source and the drain of the device and the reduction of the switching ratio.

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Abstract

本发明实施例采用对二维半导体周围介质的掺杂或者在半导体周围介质局部填充固体材料形成填充区，利用掺杂区或填充区对二维半导体特性的掺杂效应来实现基于二维半导体的电子器件。本发明实施例对二维半导体的掺杂不是对二维半导体的直接处理，因此能够有效地降低掺杂过程对二维半导体造成的损伤及由此带来的器件性能退化，提升掺杂后器件性能的稳定性。

Description

一种基于二维半导体的电子器件及其制造方法 技术领域
本发明涉及电子技术领域，特别涉及一种基于二维半导体的电子器件及其制造方法。
背景技术
新材料、新结构及新技术的应用，如应力硅、高k栅介质、金属栅、鳍栅场效应晶体管(fin field effect transistor，简称FinFET)和超薄沟道场效应晶体管(ultra-thin body field effect transistor，简称UTB FET)等的应用，使得晶体管在尺寸不断缩小的同时还可以实现性能的不断提升。然而随着晶体管尺寸的继续缩小，尤其是在10nm以下的尺寸，现有技术或许已经无法解决器件尺寸的缩小所带来的器件性能退化的问题。二维半导体材料的出现为器件尺寸的缩小带来了新的希望。单层或少数层的二维半导体材料拥有原子级的厚度，作为沟道区材料使用时能够大幅增强栅对沟道的控制力。并且，相比传统半导体材料，二维半导体材料在小尺寸器件中能够有效防止短沟道效应的发生。二维半导体材料的多样性也可以为有不同要求的器件提供多种选择。因此，二维半导体材料被认为是未来集成电路中有望延续摩尔定律的重要材料。
对于二维半导体材料而言，如过渡金属硫族化合物(transition metal dichalcogenides，简称TMDs)、三硒化二铋(Bi2Se3)、黑磷等，适当的掺杂不仅能够根据器件的要求实现载流子浓度和类型的调控，而且能够有效降低与金属之间的接触电阻。然而由于单层及少数层的二维半导体本身的厚度很小(单层MoS2的厚度仅为
Figure PCTCN2017091509-appb-000001
)，传统的半导体掺杂方法——离子注入已不适用于二维半导体材料。
现有技术的掺杂方法之一是替位式掺杂。通常做法是在二维半导体的生长过程中引入杂质，使杂质原子以替代二维半导体中某些原子的形式存在于二维半导体的晶格当中。例如，用铌原子替代部分钼原子，实现二硫化钼中掺杂铌原子。替位式掺杂具有稳定的掺杂效果，但会为二维半导体的晶格带来大量损伤，导致二维半导体的场效应迁移率等电学性能的下降。
现有技术的掺杂方法之二是表面电荷转移，在二维半导体表面吸附一些特定的气体、液体分子或固体薄膜，通过吸附的分子与二维半导体之间的电荷转移实现对二维半导体的掺杂。例如，可以通过二氧化氮(NO2)与二硒化钨(WSe2)之间的电荷转移实现对WSe2的p型掺杂，可以通过碳酸铯(Cs2CO3)与二硫化钼(MoS2)之间的电荷转移实现对MoS2的n型掺杂。然而，基于表面电荷转移的掺杂方法容易受到周围环境的影响，导致掺杂效果不稳定。例如，使用NO2对WSe2掺杂后，表面吸附的NO2在空气中难以保持稳定，因此会导致掺杂后器件性能的不稳定。而MoS2表面覆盖的Cs2CO3薄膜在对MoS2沟道有掺杂效应的同时，也会为器件源、漏之间的漏电流提供通道，导致器件漏电流的增加和开关比的减小。
现有技术的掺杂方法之三是采用等离子体对二维半导体进行处理，实现对二维半导体掺杂的效果。例如，采用六氟化硫(SF6)等离子体对MoS2进行处理，可以实现对MoS2的p型掺杂。但是等离子体掺杂的过程对二维半导体表面的化学键有损伤作用，因此会对电子器件的电学性能产生负面影响。
因此需要进一步探索新的掺杂方法，在实现对二维半导体中载流子浓度和类型有效调控的同时，降低或消除掺杂对二维半导体电学性能方面的负面影响。
发明内容
本发明实施例提供了基于二维半导体的电子器件及其制造方法。
第一方面，提供了一种基于二维半导体的电子器件，所述电子器件包括：
绝缘介质层、沟道区、第一电极、第二电极，所述绝缘介质的材料为SiO2或高k介质，所述沟道区为二维半导体层；所述绝缘介质层设置有掺杂区或填充区，所述掺杂区含有对所述二维半导体层具有掺杂效应的掺杂剂，所述填充区填充有对所述二维半导体层具有掺杂效应的固体材料，所述掺杂效应为n型掺杂或p型掺杂；所述二维半导体层位于所述绝缘介质层之上，且所述二维半导体层的至少一部分位于所述掺杂区或所述填充区之上。
结合第一方面，在第一种可实现方式中，所述电子器件为场效应晶体管，所述场效应晶体管还包括重掺杂硅层和栅区，所述重掺杂硅层位于所述绝缘介质层之下；所述第一电极为源极，所述第二电极为漏极，所述栅区包括栅介质和栅电极，所述栅介质位于所述沟道区之上，所述栅电极位于所述栅介质之上。位于沟道区上方的栅区通常也叫做顶栅。
结合第一方面的第一种可能的实现方式，在第二种可实现方式中，所述场效应晶体管为CMOS场效应晶体管；所述沟道区包括第一沟道区和第二沟道区，所述源极包括第一源极和第二源极，所述漏极包括第一漏极和第二漏极，所述栅区包括第一栅区和第二栅区，所述掺杂区包括第一掺杂区和第二掺杂区；
所述第一掺杂区的掺杂类型为n型掺杂，所述第一沟道区位于所述第一掺杂区之上，所述第一源极和第一漏极位于所述第一沟道区的两侧，所述第一栅区包括第一栅介质和第一栅电极，所述第一栅介质位于所述第一沟道区之上，所述第一栅电极位于所述第一栅介质之上；这部分构成nFET。
所述第二掺杂区的掺杂类型为p型掺杂，所述第二沟道区位于所述第二掺杂区之上，所述第二源极和第二漏极位于所述第二沟道区的两侧，所述第二栅区包括第二栅介质和第二栅电极，所述第二栅介质位于所述第二沟道区之上，所述第二栅电极位于所述第二栅介质之上。这部分构成pFET。
结合第一方面的第一种可能的实现方式，在第三种可实现方式中，所述晶体管为栅控P-N结，所述二维半导体在所述绝缘介质层上显示n型导电特性，所述掺杂区的掺杂类型为p型掺杂，所述掺杂区的面积小于所述沟道区的面积；或所述二维半导体在所述绝缘介质层上显示p型导电特性，所述掺杂区的掺杂类型为n型掺杂，所述掺杂区的面积小于所述沟道区的面积。
结合第一方面，在第四种可实现方式中，所述电子器件为薄膜晶体管，所述第一电极为源极，所述第二电极为漏极，所述薄膜晶体管还包括栅电极和绝缘衬底，所述栅电极位于所述绝缘衬底之上，所述绝缘介质层位于所述栅电极之上。
第二方面，提供一种制造基于二维半导体的电子器件的方法，包括：
在绝缘介质层形成掺杂区或填充区，所述绝缘介质的材料为SiO2或高k介质，所述掺杂区含有对所述二维半导体层具有掺杂效应的掺杂剂，所述填充区填充有对所述二维半导体具有掺杂效应的固体材料；将二维半导体层转移至所述绝缘介质层之上；根据所述器件尺寸及所述掺杂区的面积对所述二维半导体进行刻蚀，形成沟道区；在所述刻蚀后的二维半导体两侧形成第一电极和第二电极。
结合第二方面，在第一种可能的实现方式中，所述电子器件为场效应晶体管，在绝缘介质层形成掺杂区或填充区之前还包括：在重掺杂硅层上形成所述绝缘介质层；在所述刻蚀后的二维半导体两侧形成所述第一电极和第二电极之后还包括：在所述沟道区之上形成栅介质；在所述栅介质上形成栅电极；所述第一电极为源极，所述第二电极为漏极。
结合第二方面的第一种可能的实现方式，在第二种可实现方式中，所述晶体管为栅控P-N结，所述二维半导体在所述绝缘介质层上显示n型导电特性，所述掺杂区的掺杂类型为p型掺杂，所述掺杂区的面积小于所述沟道区的面积；或所述二维半导体在所述绝缘介质层上显示p型导电特性，所述掺杂区的掺杂类型为n型掺杂，所述掺杂区的面积小于所述沟道区的面积。
结合第二方面，在第三种可能的实现方式中，所述电子器件为薄膜晶体管，在绝缘介质层形成掺杂区或填充区之前还包括：
在绝缘衬底上形成栅电极，在所述栅电极上形成所述绝缘介质层。
结合第二方面或第二方面的任意一种可能的实现方式，在第四种可能的实现方式中，所述掺杂效应为n型掺杂，所述掺杂剂的掺杂源包括以下中的至少一种：含有氨基的等离子体、气体和化学试剂，含有钠离子、钾离子、氯离子的气体和溶液(如DCE溶液)，PEI溶液，PTSA溶液，BV溶液，NADH溶液和PVA溶液。
结合第二方面或第二方面的任意一种可能的实现方式，在第五种可能的实现方式中，所述掺杂效应为p型掺杂，所述掺杂剂的掺杂源包括以下中的至少一种：含有O和F的等离子体或气体，Br2、I2或AuCl3溶液，含有Pt、Ag、Au、Pd或Sc金属纳米颗粒的溶液，F4TCNQ溶液，TCNQ溶液，其中所述含有氧和氟的等离子体：SF6等离子体、CHF3等离子体、CF4等离子体、O2等离子体，所述含有氧和氟的气体包括臭氧、NO2。
结合第二方面或第二方面的任意一种可能的实现方式，在第六种可能的实现方式中，在所述绝缘介质层上形成填充区的方法包括：
对所述绝缘介质层进行刻蚀得到沟槽，在所述沟槽中填充对所述二维半导体具有掺杂效应的固体材料以形成所述填充区。
结合第二方面的第六种可能的实现方式，在第七种可能的实现方式中，所述掺杂效应为n型掺杂，所述固体材料为Cs2CO3；或所述掺杂效应为p掺杂，所述固体材料为MoO3。
以上任意方面或任意可能的实现方式中，所述二维半导体材料为以下中的任意一种：MoS2、MoSe2、MoTe2、WS2、WSe2、WTe2、GeS2、GeSe2、GeTe2、SnS2、SnSe2、SnTe2、SnO、PbS2、PbSe2、PbTe2、GaS、GaSe、GaTe、InS、InSe、InTe、Bi2Se3、石墨烯、黑磷、砷烯、锑烯、锗烯、锡烯和硅烯。
以上任意方面或任意可能的实现方式中，所述高k介质包括以下中的任意一种：Al2O3、WO3、Ta2O5、HfO2、ZnO2、TiO2、CaO、ZrO2、La2O3、BaO、MgO、HfSiOx、ZrSiOx、HfLaOx、HfZrOx、HfAlOx、LaAlOx、Y2O3、SrO、Si3N4。
以上任意方面或任意可能的实现方式中，所述二维半导体的层数为1-10层。
以上任意方面或任意可能的实现方式中，所述绝缘介质层为均匀的介质薄膜。对于绝缘介质层的制造，本发明只需要采用常规的方法形成均匀的介质薄膜，不需要绝缘介质层具有特殊的结构，工艺简单，制造成本低。
本发明实施例采用对二维半导体周围介质的掺杂或者在半导体周围介质局部填充固体材料形成填充区，利用掺杂区或填充区对二维半导体特性的掺杂效应来实现基于二维半导体 的电子器件。本发明实施例对二维半导体的掺杂不是对二维半导体的直接处理，因此能够有效地降低掺杂过程对二维半导体造成的损伤及由此带来的器件性能退化，提升掺杂后器件性能的稳定性。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1是本发明实施例提供的一种制造基于二维半导体的电子器件的流程图；
图2是本发明实施例提供的一种制造基于二维半导体的电子器件的侧视结构示意图；
图3是本发明实施例提供的CMOS场效应晶体管制造过程对应的侧视结构示意图；
图4是本发明实施例提供的CMOS场效应晶体管的制造方法的流程图；
图5是本发明实施例提供的栅控P-N结的制造方法的流程图；
图6是本发明实施例提供的栅控P-N结的制造方法的侧视结构示意图；
图7是本发明实施例栅控P-N结的又一种制造方法的流程图；
图8是本发明实施例栅控P-N结的又一种制造方法的侧视结构示意图；
图9是本发明实施例提供的又一种制造基于二维半导体的MOSFET的流程图；
图10是本发明实施例提供的又一种制造基于二维半导体的MOSFET的侧视
结构示意图；
图11是本发明实施例提供的制造薄膜晶体管的流程图；
图12是本发明实施例提供的制造薄膜晶体管的侧视结构示意图
在以上各结构示意图中，构成器件的各部分在图中的比例不代表其实际比例。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
首先对本申请中可能用到的缩略语、化学式进行定义，如表1所示。
表1缩略语/化学式的中英文说明
Figure PCTCN2017091509-appb-000002
Figure PCTCN2017091509-appb-000003
Figure PCTCN2017091509-appb-000004
Figure PCTCN2017091509-appb-000005
本发明实施例提供一种基于二维半导体的电子器件，包括各种类型的晶体管。图2(D)展示的与二维半导体相关的电子器件的基本结构，包括：绝缘介质层202、沟道区204、第一电极205、第二电极206。沟道区204位于绝缘介质层202之上，第一电极205和第二电极206位于沟道区204的两侧。若电子器件为场效应晶体管，第一电极205和第二电极206分别为作为器件的源极和漏极。
绝缘介质层的材料为SiO2或高k介质，沟道区204为二维半导体层。绝缘介质层设置有掺杂区203，掺杂区203含有对二维半导体层具有掺杂效应的掺杂剂。如果不采用对绝缘介质层进行掺杂的方法，也可以在绝缘介质层填充对所述二维半导体具有掺杂效应固体材料，形成填充区203。
高k介质可以为以下中的任意一种：Al2O3、WO3、Ta2O5、HfO2、ZnO2、TiO2、CaO、ZrO2、La2O3、BaO、MgO、HfSiOx、ZrSiOx、HfLaOx、HfZrOx、HfAlOx、LaAlOx、Y2O3、SrO、Si3N4。掺杂剂则根据器件类型和性能要求不同而不同。这里所说的绝缘介质层，采用传统的方法形成的均匀的介质薄膜即可，不需要采用特殊的结构。
二维半导体层的至少一部分位于掺杂区(或填充区)203之上。根据器件类型的不同，沟道区204(二维半导体层)所在的绝缘介质层可能有大面积或部分区域的掺杂或填充。
根据器件类型的不同，在上述基本结构之上，器件可能还包括底栅201和/或顶栅207，在图2(E)以虚线表示。若同一个基底上包括有多个器件(如场效应晶体管)，则相应的会有多个掺杂区(或填充区)、沟道区、第一电极和第二电极。本发明实施例所说的掺杂效应可以为n型掺杂或p型掺杂，具体根据器件类型和性能的要求决定。通过对二维半导体所在的绝缘介质层的直接掺杂，可以使得掺杂区内含有掺杂剂，这些掺杂剂包括对二维半导体有掺杂效应的分子、离子或官能团等。
参见图1，制造图2(D)所示的电子器件的方法包括以下步骤：
S11、在绝缘介质层202形成掺杂区(或填充区)203，如图2(A)所示。如果是掺杂的话，用传统的掺杂方法即可。如果是n型掺杂，掺杂源包括但不限于以下中的至少一种：钠(Na)离子，钾(K)离子，含有氨基的等离子体、气体和化学试剂，含有氯(Cl)离子的溶液(如DCE溶液)，PEI溶液，PTSA溶液，BV溶液，NADH溶液，PVA溶液等。如果是p型掺杂，掺杂源包括但不限于以下中的至少一种：SF6等离子体、CHF3等离子体、CF4等离 子体、O2等离子体、臭氧、NO2等含有氧(O)和氟(F)的等离子体和气体，Br2、I2、AuCl3溶液，含有铂(Pt)、银(Ag)、金(Au)、钯(Pd)、钪(Sc)等金属纳米颗粒的溶液，F4TCNQ溶液，或TCNQ溶液。
S12、将二维半导体层204转移至包含有掺杂区或填充区的绝缘介质层之上，如图2(B)所示。
S13、根据所述器件尺寸及所述掺杂区的面积对所述二维半导体进行刻蚀，形成沟道区，如图2(C)所示。
S14、在所述刻蚀后的二维半导体两侧形成第一电极205和第二电极206，如图2(D)所示。
若电子器件带有底栅，则在步骤S11之前包括：
S10、在底栅201之上形成绝缘介质层202，如图2(E)所示，底栅201以虚线框表示。
若电子器件带有顶栅，则在步骤S14之后还包括：
S15、在沟道区(二维半导体层)204上方形成顶栅207，如图2(E)所示，顶栅207以虚线框表示。顶栅一般包括栅介质和栅电极，通常先在沟道区204上方形成栅介质(图中未示出)，然后再栅介质上形成栅电极(图中未示出)。
单层或少数层(通常指2-10层左右)二维半导体材料的厚度仅在原子级，因此周围介质环境及制造工艺对二维半导体材料特性的影响要远大于对传统半导体的影响。以MoS2为例，体材料的MoS2通常表现n型半导体特性，但随着MoS2厚度的减薄(层数的减小)，环境对MoS2特性的影响逐渐增大。当MoS2厚度降低到一定程度后，在特定的环境(如PMMA等)诱导下可表现出双极型的导电特性。再比如，少数层黑磷在SiO2衬底上表现为P型(空穴)主导的导电特性，但在黑磷表面覆盖Cs2CO3后，少数层黑磷逐渐表现出N型(电子)主导的导电特性。针对二维半导体对其周围介质环境敏感的特点，本发明实施例通过改变二维半导体周围的介质环境(例如对二维半导体所在的介质进行掺杂或进行区域性填充)，利用介质与二维半导体界面对二维半导体特性的调制作用来实现对二维半导体的掺杂效应。本发明实施例的基于二维半导体的电子器件，没有对二维半导体本身直接进行掺杂处理，能够有效地降低掺杂过程对二维半导体造成的损伤及由此带来的器件性能退化，提升器件性能的稳定性。
常见的二维半导体材料有：MoS2、MoSe2、MoTe2、WS2、WSe2、WTe2、GeS2、GeSe2、GeTe2、SnS2、SnSe2、SnTe2、SnO、PbS2、PbSe2、PbTe2、GaS、GaSe、GaTe、InS、InSe、InTe、石墨烯(graphene)、黑磷(black phosphorus)、砷烯(arsenene)、锑烯(antimonene)和锗烯(germanene)、锡烯(stanene)、硅烯(silicene)等。
下面介绍各种应用场景中的具体实施例。
实施例一
通过对二维半导体所在衬底介质(绝缘介质层)的掺杂实现基于二维半导体的CMOS器件的制造。对衬底介质的掺杂在本实施例中的作用体现在两方面：1、调控二维半导体沟道中的载流子浓度，以实现对不同的导电类型和器件阈值电压的控制；2、调控源、漏及其延伸区域中载流子的浓度，以降低沟道与源、漏电极的接触电阻。
以制造基于二维半导体CMOS场效应晶体管为例，CMOS场效应晶体管包括基于二维半导体的n型场效应晶体管(2D nFET)和p型场效应晶体管(2D pFET)。如图4所示，制造CMOS场效应晶体管的过程包括：
S41、准备衬底并对衬底进行清洗，如图3(A)所示，衬底可以包括重掺杂硅层301和位于重掺杂硅层上面的绝缘介质层302。其中重掺杂硅层301作为背电极使用，在器件工作时可以接地，也可以根据需要施加相应的电压。绝缘介质层302的材料可以为二氧化硅(SiO2)或高k介质。
S42、为了制造2D nFET，首先对2D nFET所在区域的绝缘衬底(在本例中指绝缘层302)进行n型掺杂，形成n型掺杂区域303，如图3(B)所示。掺杂源包括但不限于钠离子，钾离子，含有氨基的等离子体、气体和化学试剂，含有氯离子的溶液(如DCE溶液)，PEI溶液，PTSA溶液，BV溶液，NADH溶液，PVA溶液等。掺杂浓度与二维半导体的种类(原本的载流子浓度及类型)、厚度(层数)以及对2D nFET阈值电压的要求密切相关。本实施例的二维半导体以硒化钨(WSe2)为例。
S43、对2D nFET的源极、漏极所在的区域进行重n型掺杂，形成重n型掺杂区域304，以降低二维半导体和源极、漏极之间的接触电阻，如图3(C)所示。重n型掺杂区域304的面积可以略大于实际源、漏的接触面积。
S44、对2D pFET所在区域的绝缘衬底进行p型掺杂，形成p型掺杂区305，如图3(D)所示。掺杂源可以是含氧(O)或含氟(F)的等离子体、气体，如SF6等离子体、CHF3等离子体、CF4等离子体、O2等离子体、臭氧、NO2等)。掺杂源还可以包括Br2、I2、AuCl3溶液，含有铂(Pt)、银(Ag)、金(Au)、钯(Pd)、钪(Sc)等金属纳米颗粒的溶液，F4TCNQ溶液，TCNQ溶液。同样的，掺杂浓度与二维半导体的种类(原本的载流子浓度及类型)、厚度(层数)以及对2D pFET阈值电压的要求密切相关。n型掺杂区303域和p型掺杂区域305之间要有一定的间隔以达到隔离的目的。
S45、对2D pFET源、漏电极所在的区域进行重p型掺杂，以降低二维半导体和源、漏金属之间的接触电阻，形成重p型掺杂区域306，如图3(E)所示。重p型掺杂区域306的面积要略大于实际2D pFET源、漏的接触面积。
S46、可选的，如在上述S41-S45步的掺杂过程中为衬底引入了缺陷，可通过退火工艺对缺陷进行修复。
S47、将二维半导体层307转移至上述经过掺杂的绝缘介质层表面，如图3(F)所示。二维半导体可以是单层或少数层的(1-10层)。
S48、根据器件尺寸的要求和掺杂区域的面积，采用等离子体刻蚀工艺对二维半导体进行刻蚀，得到沟道区3071和3072，并隔离不同器件的沟道，如图3(G)所示。对于过渡金属硫族化合物(TMDs)和石墨烯，可采用O2等离子体进行刻蚀。对其他二维半导体，可根据实际情况选择刻蚀工艺中采用的等离子体类型。
S49、经过光刻、金属淀积以及栅介质淀积等工艺步骤形成2D nFET和pFET的源极(3081和3082)、漏极(3091和3092)，顶栅的栅介质(3101和3102)及栅电极(3111和3112)。最终形成的器件结构如图3(H)所示，左侧是nFET，右侧是pFET。在图3(H)中以nFET和pFET的栅电极与源、漏电极采用相同的金属材料为例，在实际情况中也可采用不同金属材料。
本发明实施例一提供的CMOS场效应晶体管，如图3(G)和图3(H)所示，包括：
重掺杂硅层301，绝缘介质层302、第一沟道区3071、第二沟道区3072、第一源极3081、第一漏极3091，第二源极3082、第二漏极3092、第一栅介质3101、第二栅介质3102、第一栅电极3111、第二栅电极3112。绝缘介质层302的材料为SiO2或高k介质，绝缘介质层302 设置有第一掺杂区303、第二掺杂区305，第一沟道区3071和第二沟道区3072为二维半导体层。第一掺杂区303的面积大于第一沟道区3071，第二掺杂区305的面积大于第二沟道区3072，第一沟道区3071和第二沟道区3072相互隔离。
第一掺杂区303的掺杂类型为n型掺杂，第一沟道区3071位于第一掺杂区303之上，第一源极3081和第一漏极3091位于第一沟道区3071的两侧，第一栅区包括第一栅介质3101和第一栅电极3111，所述第一栅介质3101位于所述第一沟道区3071之上，所述第一栅电极3111位于所述第一栅介质3101之上。第一掺杂区303、第一沟道区3071、第一源极3081、第一漏极3091、第一栅介质3101和第一栅电极3111构成了nFET。
第二掺杂区305的掺杂类型为p型掺杂，第二沟道区3072位于第二掺杂区305之上，第二源极3082和第二漏极3092位于第二沟道区3072的两侧，第二栅区包括第二栅介质3102和第二栅电极3112，第二栅介质3102位于第二沟道区3072之上，第二栅电极3112位于第二栅介质3102之上。第二掺杂区305、第二沟道区3072、第二源极3082、第二漏极3092、第二栅介质3102和第二栅电极3112构成了pFET。
与图2(D)所示结构的区别在于，在图2(D)所示的结构的基础之上，绝缘介质层下方有重掺杂硅，通常作为背电极(背栅)使用。另外还有在衬底上左右两个互补的晶体管，nFET和pFET，各自有沟道区、源极和漏极、顶栅(栅介质和栅电极)。整个沟道区下方均有掺杂区域。
实施例二
通过对衬底绝缘介质的掺杂实现基于二维半导体的栅控P-N结制造。本实施例的二维半导体以MoS2为例进行阐述，但所涉及的方法和应用场景对其它二维半导体材料同样适用。栅控P-N结的制造过程如图5所示，包括以下步骤：
S51、衬底的准备及清洗，如图6(A)所示，同实施例一中的步骤S41。本例中的绝缘介质层以Al2O3为例。
S52、对P-N结的p型区域所在绝缘介质层进行p型掺杂，如图6(B)所示。p型掺杂源的使用同实施例一中步骤S44和步骤S45。
S53、由于MoS2在Al2O3衬底上显示n型半导体导电特性，此处省略了对P-N结的n型区域所在绝缘介质衬底的n型掺杂过程。但对于其他在Al2O3衬底上显示双极型导电特性的二维半导体(如WSe2、黑磷等)，或者需要n型掺杂来调节二维半导体中载流子浓度的情况，此处需要增加对P-N结的n型区域所在绝缘介质层进行n型掺杂，掺杂源的使用同实施例一中的步骤S42和步骤S43。与实施例一不同的是，n型掺杂区与p型掺杂区之间无间隔，两区域应密切相连且界面清晰，以保证P-N结具有良好的电学特性。
类似地，对于在绝缘衬底表面原本显示p型半导体特性的二维材料(如SnO等)，应把本实施例中步骤S52的区域性p型掺杂变为区域性n型掺杂以形成同质P-N结，n型掺杂源的使用同实施例一中的步骤S42和步骤S43。
S54、将单层或少数层的MoS2转移至上述Al2O3介质层表面。
S55、根据掺杂区域的面积及对器件尺寸的要求，采用刻蚀工艺对MoS2进行刻蚀得到沟道区，如图6(C)所示。
S56、通过光刻、金属淀积、剥离(lift-off)工艺以及介质生长工艺等完成栅控P-N结的 源极、漏极，顶栅的栅介质和栅电极，如图6(D)和图6(E)所示。
如图6(E)所示，通过本实施例制造的栅控P-N结，包括:
重掺杂硅层601、绝缘介质层602、沟道区604、第一电极605、第二电极606、栅介质607、栅电极608。绝缘介质层602的材料为SiO2或高k介质，沟道区604为二维半导体层；
绝缘介质层602设置有掺杂区603，掺杂区603含有对二维半导体层604具有掺杂效应的掺杂剂，若采用的二维半导体材料在绝缘介质层602上显示n型导电特性，则掺杂区603的掺杂类型为p型掺杂；若采用的二维半导体材料在绝缘介质层602上显示p型导电特性，则掺杂区603的掺杂类型为n型掺杂。
二维半导体层(沟道区)604位于所述绝缘介质层602之上，二维半导体层的一部分位于掺杂区603之上，掺杂区603的面积小于所述沟道区604的面积
第一电极605和第二电极606位于所述沟道区604的两侧，作为栅控P-N结的源极和漏极，栅介质607位于沟道区604之上，栅电极608位于栅介质607之上。
实施例三
本实施例通过更换局部衬底介质实现基于二维半导体(以MoS2为例)的栅控P-N结制造。这里所说的更换局部介质是指对绝缘介质层的局部区域填充其他对二维半导体具有掺杂效应的固体材料。如图7所示，制造栅控P-N结的过程包括：
S71、衬底的准备及清洗，如图8(A)所示。本例中的绝缘介质层以Al2O3为例。
S72、通过光刻工艺定义出P-N结的p型区域并刻蚀掉相应位置的绝缘介质层(Al2O3)，形成沟槽，如图8(B)所示。
S73、在沟槽中填入诱导MoS2显示p型导电特性的材料，形成填充区，如图8(C)所示，该材料在本实施例中为MoO3。实际应用中，还可以采用PMMA、O含量比较高的高k介质等。对于其它二维半导体，沟槽中所需要填入的材料可能会有所不同，应根据实际情况进行选择。
对于在Al2O3、SiO2以及其它高k介质表面显示p型导电特性的二维半导体材料(如黑磷等)，应在刻蚀好的沟槽中填入诱导二维半导体显示n型导电特性的材料。本例中采用Cs2CO3进行填充；对于其它二维半导体材料，沟槽中所填充的材料可能会有所不同，应根据实际情况进行选择。
S74、将单层或少数层的MoS2转移至上述衬底表面。
S75、根据上述填充区域的面积及对器件尺寸的要求，采用刻蚀工艺对MoS2进行刻蚀得到器件的沟道区，如图8(D)所示。
S76、通过光刻、金属淀积、剥离工艺(lift-off)以及介质生长工艺等形成栅控P-N结的源极、漏极，顶栅的栅介质和栅电极，如图8(E)和图8(F)所示。
如图8(F)所示，通过本实施例制造的栅控P-N结，包括:
重掺杂硅层801、绝缘介质层802、沟道区804、第一电极805、第二电极806、栅介质807、栅电极808。绝缘介质层802的材料为SiO2或高k介质，沟道区804为二维半导体层；
绝缘介质层802设置有填充区803，填充区803填充有对二维半导体层804具有掺杂效应的固体材料，若采用的二维半导体材料在绝缘介质层802上显示n型导电特性，则填充区803对二维半导体的掺杂效应为p型掺杂；若采用的二维半导体材料在绝缘介质层802上显示p型导电特性，则填充区803对二维半导体的的掺杂效应为n型掺杂。
二维半导体层804位于所述绝缘介质层802之上，二维半导体层的一部分位于掺杂区803之上，掺杂区803的面积小于所述沟道区804的面积
第一电极805和第二电极806位于所述沟道区804的两侧，作为栅控P-N结的源极和漏极，栅介质807位于沟道区804之上，栅电极808位于栅介质807之上。
实施例四
本实施例通过更换局部衬底介质减小MOSFET中金属/二维半导体(仍然以MoS2为例)的接触电阻。这里所说的更换局部介质是指对绝缘介质层的局部区域填充其它对二维半导体具有掺杂效应的固体材料。如图9所示，MOSFE的制造过程包括：
S91、衬底的准备及清洗，如图10(A)所示。本例中的绝缘介质以Al2O3为例。
S92、通过光刻工艺定义出器件中的金属/二维半导体接触区，并采用刻蚀工艺刻蚀掉相应位置的Al2O3，形成沟槽，如图10(B)所示。
S93、在沟槽中填入对二维半导体有掺杂效应的材料，形成填充区，如图10(C)所示。对于在Al2O3上显示n型二维半导体材料，如本例中的MoS2以及WS2等，沟槽中填入可以增大电子浓度的材料，例如Cs2CO3等。对于在Al2O3上显示p型的二维半导体材料(如黑磷、SnO等)，沟槽中填入可以增大空穴浓度的材料，如MoO3等。
S94、将单层或少数层的MoS2转移至上述绝缘介质层的表面。
S95、并根据掺杂位置和对器件尺寸的要求，对MoS2的进行刻蚀得到沟道区，如图10(D)所示。
S96、经过光刻、金属淀积、剥离工艺以及栅介质淀积工艺等步骤形成器件的源、漏电极、顶栅栅介质及栅电极，如图10(E)和图10(F)所示。
如图10(F)所示，通过本实施例制造的MOSFET，包括:
重掺杂硅层1001、绝缘介质层1002、沟道区1005、第一电极1006、第二电极1007、栅介质1008、栅电极1009。绝缘介质层1002的材料为SiO2或高k介质，沟道区1005为二维半导体层；
绝缘介质层1002设置有第一填充区1003和第二填充区1004，分别填充有对二维半导体层1005具有掺杂效应的固体材料。
二维半导体层1005位于所述绝缘介质层1002之上，二维半导体层的一部分位于掺杂区1003之上，掺杂区1003的面积小于所述沟道区1005的面积
第一电极1006和第二电极1007位于所述沟道区1005的两侧，作为MOSFET的源极和漏极，栅介质1008位于沟道区1005之上，栅电极1009位于栅介质1008之上。
对于在绝缘介质层上显示n型导电特性的二维半导体材料，沟槽中填入可以增大电子浓度的材料。对于在绝缘介质层上显示p型导电特性的二维半导体材料，沟槽中填入可以增大空穴浓度的材料。
实施例五
本实施例通过对二维半导体薄膜晶体管的源、漏接触所在区域的绝缘介质层进行掺杂以降低薄膜晶体管的源、漏接触电阻。本实施例的薄膜晶体管，是通过底栅来控制薄膜晶体管的工作的。如图11所示，基于二维半导体的薄膜晶体管的制造方法包括：
S111、衬底的准备及清洗，如图12(A)所示。所述衬底材料为绝缘材料，包括玻璃、石英、蓝宝石、陶瓷、塑料、PI、PET等。本实施例中以玻璃衬底为例，这里的衬底与实施例 一至四有所不同。
S112、经过光刻、薄膜淀积等工艺在衬底表面形成薄膜晶体管的底栅电极，如图12(B)所示。底栅电极可以为金属材料，如金(Au)、钛(Ti)、镍(Ni)、铂(Pt)等，也可以是ITO。本实施例以ITO为例。
S113、在底栅电极表面淀积栅介质材料，相当于本发明实施例所说的绝缘介质层，如图12(C)所示。栅介质材料可以是SiO2，也可以是Al2O3、HfO2、ZrO2、TiO2、La2O3等高k材料。本实施例中以HfO2为例。
S114、对薄膜晶体管的源极、漏极接触所在区域的绝缘介质层进行掺杂以降低薄膜晶体管的源极、漏极接触电阻，如图12(D)所示。对于n型薄膜晶体管，应进行n型掺；对于p型薄膜晶体管，应进行p型掺杂。掺杂所使用的掺杂源种类与实施例一相同。本实施例中的二维半导体以WS2为例，因此应对源、漏所在区域的介质进行n型掺杂。
S115、将单层或少数层WS2转移至上述绝缘介质层的表面。
S116、对二维半导体进行刻蚀得到薄膜晶体管的沟道区，如图12(E)所示。
S117、制作源、漏电极，形成薄膜晶体管，如图12(F)所示。
本实施例制造的薄膜晶体管如图12(F)所示，包括：
衬底1201、底栅电极1202、绝缘介质层(底栅介质)1203、沟道区1206、第一电极1207、第二电极1208。绝缘介质层设置有第一掺杂区1204和第二掺杂区1205，分别位于第一电极1207和第二电极1208的接触区下方。第一电极1207和第二电极1208作为源极、漏极使用。底栅电极1202位于衬底1201之上，绝缘介质层1203位于底栅电极1202之上，沟道区1206位于绝缘介质层1203之上，第一电极1207和第二电极1208位于沟道区1206的两侧。与前面的实施例不同的是，薄膜晶体管有底栅电极，无顶栅。沟道区1206为二维半导体层，第一掺杂区1204和第二掺杂区1205含有对二维半导体具有掺杂效应的掺杂剂。对于n型薄膜晶体管，掺杂效应为n型掺杂；对于p型薄膜晶体管，掺杂效应为p型掺杂。
以上通过五个不同的实施例分别展示了在不同的应用场景中通过对二维半导体层所在的绝缘介质层进行区域性掺杂或者局部填充不同的固体材料介质，实现对二维半导体材料掺杂的制造过程，实际的应用场景不限于此。另外，以上实施例中涉及到的方法也可以结合使用，如实施例一中通过对源、漏接触区所在绝缘介质的区域性重掺杂可以达到降低金属/二维半导体接触电阻的目的，与实施例四采用的局部介质填充方法具有相似的效果。
本发明通过对二维半导体所在的绝缘介质层进行区域性掺杂或者局部填充不同的固体材料介质，实现对二维半导体材料掺杂具有以下有益效果：
1)相比金属原子的替位式掺杂、等离子体掺杂以及传统的离子注入等掺杂方法，本发明能够很大程度地减小掺杂对二维半导体材料的损伤，降低掺杂过程在二维半导体材料中引入的缺陷密度。
2)与使用气态离子进行表面电荷转移的掺杂方法相比，本发明实施例不会为器件带来可靠性方面的类似问题，掺杂后器件的性能可以保持相对稳定。
3)与在二维半导体材料表面增加覆盖层以实现掺杂的方法相比，本发明能够有效降低器件源、漏之间漏电流的增加和开关比的减小。
4)方便实现区域性掺杂以及器件阈值电压的调节。
以上所述仅为本发明的较佳实施例，并不用以限制本发明。

Claims (17)

  1. 一种基于二维半导体的电子器件，其特征在于，包括：绝缘介质层、沟道区、第一电极、第二电极，所述绝缘介质的材料为SiO2或高k介质，所述沟道区为二维半导体层；
    所述绝缘介质层设置有掺杂区或填充区，所述掺杂区含有对所述二维半导体层具有掺杂效应的掺杂剂，所述填充区填充有对所述二维半导体层具有掺杂效应的固体材料，所述掺杂效应为n型掺杂或p型掺杂；
    所述二维半导体层位于所述绝缘介质层之上，且所述二维半导体层的至少一部分位于所述掺杂区或所述填充区之上；
    所述第一电极和第二电极位于所述沟道区的两侧。
  2. 根据权利要求1任意一项所述的电子器件，其特征在于，所述电子器件为场效应晶体管，所述场效应晶体管还包括重掺杂硅层和栅区，所述重掺杂硅层位于所述绝缘介质层之下；
    所述第一电极为源极，所述第二电极为漏极，所述栅区包括栅介质和栅电极，所述栅介质位于所述沟道区之上，所述栅电极位于所述栅介质之上。
  3. 根据权利要求2所述的电子器件，其特征在于，所述晶体管为CMOS场效应晶体管；
    所述沟道区包括第一沟道区和第二沟道区，所述源极包括第一源极和第二源极，所述漏极包括第一漏极和第二漏极，所述栅区包括第一栅区和第二栅区，所述掺杂区包括第一掺杂区和第二掺杂区；
    所述第一掺杂区的掺杂类型为n型掺杂，所述第一沟道区位于所述第一掺杂区之上，所述第一源极和第一漏极位于所述第一沟道区的两侧，所述第一栅区包括第一栅介质和第一栅电极，所述第一栅介质位于所述第一沟道区之上，所述第一栅电极位于所述第一栅介质之上；
    所述第二掺杂区的掺杂类型为p型掺杂，所述第二沟道区位于所述第二掺杂区之上，所述第二源极和第二漏极位于所述第二沟道区的两侧，所述第二栅区包括第二栅介质和第二栅电极，所述第二栅介质位于所述第二沟道区之上，所述第二栅电极位于所述第二栅介质之上。
  4. 根据权利要求2所述的电子器件，其特征在于，所述晶体管为栅控P-N结，
    所述二维半导体在所述绝缘介质层上显示n型导电特性，所述掺杂区的掺杂类型为p型掺杂，所述掺杂区的面积小于所述沟道区的面积；或
    所述二维半导体在所述绝缘介质层上显示p型导电特性，所述掺杂区的掺杂类型为n型掺杂，所述掺杂区的面积小于所述沟道区的面积。
  5. 根据权利要求1的电子器件，其特征在于，所述电子器件为薄膜晶体管，所述第一电极为源极，所述第二电极为漏极，所述薄膜晶体管还包括栅电极和绝缘衬底，所述栅电极位于所述绝缘衬底之上，所述绝缘介质层位于所述栅电极之上。
  6. 根据权利要求1-5任意一项所述的电子器件，其特征在于，所述二维半导体材料为以下中的任意一种：MoS2、MoSe2、MoTe2、WS2、WSe2、WTe2、GeS2、GeSe2、GeTe2、 SnS2、SnSe2、SnTe2、SnO、PbS2、PbSe2、PbTe2、GaS、GaSe、GaTe、InS、InSe、InTe、Bi2Se3、石墨烯、黑磷、砷烯、锑烯、锗烯、锡烯和硅烯。
  7. 根据权利要求1-6任意一项所述的电子器件，其特征在于，所述高k介质包括以下中的任意一种：Al2O3、WO3、Ta2O5、HfO2、ZnO2、TiO2、CaO、ZrO2、La2O3、BaO、MgO、HfSiOx、ZrSiOx、HfLaOx、HfZrOx、HfAlOx、LaAlOx、Y2O3、SrO、Si3N4。
  8. 根据权利要求1-7任意一项所述的电子器件，其特征在于，所述二维半导体的层数为1-10层。
  9. 根据权利要求1-8任意一项所述的电子器件，其特征在于，所述绝缘介质层为均匀的介质薄膜。
  10. 一种制造基于二维半导体的电子器件的方法，其特征在于，所述方法包括：
    在绝缘介质层形成掺杂区或填充区，所述绝缘介质的材料为SiO2或高k介质，所述掺杂区含有对所述二维半导体层具有掺杂效应的掺杂剂，所述填充区填充有对所述二维半导体具有掺杂效应的固体材料；
    将二维半导体层转移至所述绝缘介质层之上；
    根据所述器件尺寸及所述掺杂区的面积对所述二维半导体进行刻蚀，形成沟道区；
    在所述刻蚀后的二维半导体两侧形成第一电极和第二电极。
  11. 根据权利要求10所述的方法，其特征在于，所述电子器件为场效应晶体管，在绝缘介质层形成掺杂区或填充区之前还包括：
    在重掺杂硅层上形成所述绝缘介质层；
    在所述刻蚀后的二维半导体两侧形成所述第一电极和第二电极之后还包括：
    在所述沟道区之上形成栅介质；
    在所述栅介质上形成栅电极；
    所述第一电极为源极，所述第二电极为漏极。
  12. 根据权利要求11所述的方法，其特征在于，所述场效应晶体管为栅控P-N结，
    所述二维半导体在所述绝缘介质层上显示n型导电特性，所述掺杂区的掺杂类型为p型掺杂，所述掺杂区的面积小于所述沟道区的面积；或
    所述二维半导体在所述绝缘介质层上显示p型导电特性，所述掺杂区的掺杂类型为n型掺杂，所述掺杂区的面积小于所述沟道区的面积。
  13. 根据权利要求10所述的方法，其特征在于，所述电子器件为薄膜晶体管，在绝缘介质层形成掺杂区或填充区之前还包括：
    在绝缘衬底上形成栅电极；
    在所述栅电极上形成所述绝缘介质层，所述绝缘介质层为均匀的介质薄膜。
  14. 根据权利要求10-13任意一项所述的方法，其特征在于，所述掺杂效应为n型掺杂，所述掺杂剂的掺杂源包括以下中的至少一种：含有氨基的等离子体、气体和化学试剂，含有钠离子、钾离子、氯离子的气体和溶液，聚乙烯亚胺PEI溶液，对甲苯磺酸PTSA溶液，苄基紫精BV溶液，烟酰胺腺嘌呤二核苷酸NADH溶液和聚乙烯醇PVA溶液。
  15. 根据权利要求10-13任意一项所述的方法，其特征在于，所述掺杂效应为p型掺杂，所述掺杂剂的掺杂源包括以下中的至少一种：含有氧和氟的等离子体或气体，Br2、I2或AuCl3溶液，含有Pt、Ag、Au、Pd或Sc金属纳米颗粒的溶液，2,3,5,6-四氟-7,7’,8,8’- 四氰二甲基对苯醌F4TCNQ溶液，7,7,8,8-四氰基对苯二醌二甲烷TCNQ溶液,其中，所述含有氧和氟的等离子体：SF6等离子体、CHF3等离子体、CF4等离子体、O2等离子体，所述含有氧和氟的气体包括臭氧、NO2。
  16. 根据权利要求10-13任意一项所述的方法，其特征在于，在所述绝缘介质层上形成填充区的方法包括：
    对所述绝缘介质层进行刻蚀得到沟槽，
    在所述沟槽中填充对所述二维半导体具有掺杂效应的固体材料以形成所述填充区。
  17. 根据权利要求16所述的器件，其特征在于，所述掺杂效应为n型掺杂，所述固体材料为Cs2CO3；或
    所述掺杂效应为p掺杂，所述固体材料为MoO3。。
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CN106129112B (zh) 2019-04-26
TW201813087A (zh) 2018-04-01
CN110299405B (zh) 2021-05-04

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