WO2018006442A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2018006442A1
WO2018006442A1 PCT/CN2016/090654 CN2016090654W WO2018006442A1 WO 2018006442 A1 WO2018006442 A1 WO 2018006442A1 CN 2016090654 W CN2016090654 W CN 2016090654W WO 2018006442 A1 WO2018006442 A1 WO 2018006442A1
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Prior art keywords
pixel electrode
layer
array substrate
electrode layer
intermediate layer
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Ceased
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PCT/CN2016/090654
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English (en)
French (fr)
Inventor
周志超
周佑联
武岳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/117,444 priority Critical patent/US20180203308A1/en
Publication of WO2018006442A1 publication Critical patent/WO2018006442A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • the current display has been rapidly developed, and can be classified into a liquid crystal display, a plasma display, an organic electroluminescence display, etc. according to its display principle.
  • the vertical alignment (VA) display mode has been welcomed by the market because of its good viewing angle.
  • the VA display mode adopts multi-domain design, and currently the multi-domain design has two modes: Is a PVA mode in which the crack of the pixel electrode forms a lateral electric field; rather, the protrusion in the pixel unit causes the liquid crystal molecules to form a multi-domain arrangement of the MVA mode, whereas in both modes, the liquid crystal display has dark lines or poor display. problem.
  • the present invention provides an array substrate including: a substrate; a patterned intermediate layer disposed on the substrate; and an unpatterned pixel electrode layer disposed on the patterned intermediate layer, the pixel
  • the electrode layer forms a recessed region and a convex region corresponding to the patterned intermediate layer
  • the patterned intermediate layer is a trench structure or a strip structure, and is a fishbone pattern
  • the patterned intermediate layer is an active layer.
  • the trench structure includes a recess and a protrusion, and the pixel electrode layer forms a recessed area corresponding to the recess, and the pixel electrode layer forms a convex area corresponding to the protrusion.
  • the strip structure includes a slit between the strip and the strip, the pixel electrode layer forms a convex area corresponding to the strip, and the pixel electrode layer forms a concave area corresponding to the slit.
  • the present invention provides an array substrate including: a substrate; a patterned intermediate layer disposed on the substrate; and an unpatterned pixel electrode layer disposed on the patterned intermediate layer, the pixel The electrode layer forms a recessed region and a raised region corresponding to the patterned intermediate layer.
  • the patterned intermediate layer is a groove structure or a strip structure.
  • the trench structure includes a recess and a protrusion, and the pixel electrode layer forms a recessed area corresponding to the recess, and the pixel electrode layer forms a convex area corresponding to the protrusion.
  • the strip structure includes a slit between the strip and the strip, the pixel electrode layer forms a convex area corresponding to the strip, and the pixel electrode layer forms a concave area corresponding to the slit.
  • the patterned intermediate layer is a fishbone pattern.
  • the patterned intermediate layer is an active layer.
  • a passivation layer is disposed between the active layer and the pixel electrode layer.
  • the material of the active layer is amorphous silicon or indium gallium zinc oxide.
  • the present invention further provides a display panel, the display panel comprising an array substrate, the array substrate comprising: a substrate; a patterned intermediate layer disposed on the substrate; and a dummy disposed on the patterned intermediate layer A patterned pixel electrode layer, the pixel electrode layer corresponding to the patterned intermediate layer forming a recessed region and a raised region.
  • the patterned intermediate layer is a groove structure or a strip structure.
  • the trench structure includes a recess and a protrusion, and the pixel electrode layer forms a recessed area corresponding to the recess, and the pixel electrode layer forms a convex area corresponding to the protrusion.
  • the strip structure includes a slit between the strip and the strip, the pixel electrode layer forms a convex area corresponding to the strip, and the pixel electrode layer forms a concave area corresponding to the slit.
  • the patterned intermediate layer is a fishbone pattern.
  • the patterned intermediate layer is an active layer.
  • a passivation layer is disposed between the active layer and the pixel electrode layer.
  • the material of the active layer is amorphous silicon or indium gallium zinc oxide.
  • the display panel further includes a color filter substrate disposed corresponding to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the array substrate of the present invention comprises: a substrate, a patterned intermediate layer disposed on the substrate, and an unpatterned pixel electrode layer disposed on the patterned intermediate layer, wherein the pixel electrode layer forms a recessed region corresponding to the patterned intermediate layer and Protruding area.
  • the pixel electrode layer in the array substrate of the present invention is a non-patterned, that is, a block-shaped pixel electrode layer, and there is no slit, and the display panel using the array substrate does not have problems of dark lines, poor display brightness, and contrast.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of a second embodiment of the array substrate of the present invention.
  • FIG. 3 is a plan view of a pixel electrode layer of a second embodiment of the array substrate shown in FIG. 2;
  • FIG. 4 is a flow chart showing the fabrication of the second embodiment of the array substrate shown in FIG. 2;
  • FIG. 5 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate according to the present invention.
  • the array substrate 100 of the present embodiment includes a substrate 11 , an intermediate layer 12 , and a pixel electrode layer 13 .
  • the intermediate layer 12 is a patterned intermediate layer 12, that is, the process of forming the intermediate layer 12 includes an etching process capable of patterning.
  • the unpatterned pixel electrode layer 13 is formed on the intermediate layer 12, and the pixel electrode layer 13 forms a convex region 131 and a recessed region 132 corresponding to the patterned intermediate layer 12.
  • the patterned intermediate layer 12 may be a strip structure (as in FIG. 1(A)) or a trench structure (as in FIG. 1(B)).
  • the intermediate layer 12 of the strip structure includes a slit 122 formed between the strip 121 and the strip 121, that is, the intermediate layer 12 at the slit 122 is completely removed in the etching process.
  • the corresponding strips 121 on the pixel electrode layer 13 form a convex region 131, and a recessed region 132 is formed corresponding to the slit 122.
  • the intermediate layer 12 of the trench structure then includes protrusions 121 and recesses 122, and a thinner intermediate layer 12 remains at the recesses 122, i.e., in the etching process, only the intermediate layer 12 at the recess 122 is partially removed. .
  • the corresponding protrusions 121 on the pixel electrode layer 13 form a convex region 131
  • the corresponding recess 122 forms a recessed region 132.
  • the pixel electrode layer 13 is formed thereon with a bulk electrode having the convex regions 131 and the recess regions 132, ensuring the liquid crystal in the display panel using the array substrate 100 It can be flipped, and the display panel will not appear dark.
  • another layer may be disposed between the intermediate layer 12 and the pixel electrode layer 13.
  • the pixel electrode layer 13 may be deposited directly on the intermediate layer 12 or may not be directly deposited on the intermediate layer 12.
  • the array substrate of the present embodiment includes a substrate, a patterned intermediate layer disposed on the substrate, and an unpatterned pixel electrode layer disposed on the patterned intermediate layer, wherein the pixel electrode layer forms a recessed region corresponding to the patterned intermediate layer and Protruding area.
  • the pixel electrode layer is unpatterned, that is, a block-shaped pixel electrode layer, and there is no slit.
  • the display panel using the array substrate does not have problems of dark lines, poor display brightness, and poor contrast.
  • the array substrate 200 of the present embodiment includes a glass substrate 21, and a gate electrode 22 and a gate insulating layer 23 sequentially formed on the glass substrate 21.
  • the active layer 24 is a patterned intermediate layer in the present invention, and the pixel electrode layer 28 is disposed above the active layer 24, and the protruding layer 281 and the recessed region 282 are formed corresponding to the active layer 24, in the embodiment.
  • the active layer 24 is a strip structure, and may of course also be a trench structure.
  • the patterned active layer 24 is a fishbone pattern.
  • the convex region 281 and the recessed region 282 of the corresponding pixel electrode layer 28 also constitute the texture of the fishbone pattern.
  • FIG. 3 is a plan view of the pixel electrode layer of the second embodiment of the array substrate shown in FIG. 2.
  • FIG. 4 is a flow chart of the second embodiment of the array substrate shown in FIG. 2 , and the manufacturing process includes the following steps.
  • a gate electrode 22 is formed on the glass substrate 21 by a physical vapor deposition and a wet etching process, and then the gate insulating layer 23 is formed by a chemical vapor deposition and a dry etching process.
  • a patterned active layer 24 is formed on the gate insulating layer 23, and the active layer 24 is formed mainly on a corresponding display region of the array substrate such that the pixel electrode layer 28 corresponding to the patterned active layer 24 has a convex shape.
  • the region 281 and the recessed region 282, the patterned active layer 24 is a fishbone pattern of a strip structure, and the material forming the active layer 24 may be amorphous silicon or indium gallium zinc oxide (IGZO).
  • the barrier layer 25 is formed by a chemical vapor deposition and a dry etching process, and the barrier layer 25 is an etch barrier layer 25, which serves as a barrier in the subsequent etching process to avoid The formed active layer 24 is again etched. Since the subsequently formed source/drain 26 needs to be electrically connected to the active layer 24, two openings are also formed on the barrier layer 25 to respectively contact the source and drain contacts with the active layer 24.
  • S404 forming a source/drain on the barrier layer, wherein the source/drain are electrically connected to the active layer through an opening of the barrier layer.
  • the source and the drain are the same metal, and thus are formed simultaneously in this step S404. Specifically, a metal layer is first physically vapor deposited, and then the metal layer is patterned by a wet etching process to form a source. Pole and drain. When the metal layer is deposited, since the barrier layer 25 has an opening, the metal layer may be deposited in the opening to achieve electrical connection with the active layer 24.
  • a passivation layer 27 is further formed. Since the subsequently formed pixel electrode layer 28 needs to be electrically connected to the drain, an opening is also formed on the passivation layer 27, so that the pixel is formed. The electrode layer 28 can be in contact with the drain through the opening.
  • the passivation layer is formed by a chemical vapor deposition and a dry etching process.
  • S406 forming a pixel electrode layer, wherein the pixel electrode layer is electrically connected to the drain through an opening of the passivation layer.
  • the pixel electrode layer 28 is made of indium tin oxide (ITO) by physical vapor deposition, and ITO can be deposited in the opening of the passivation layer 27 to achieve electrical connection with the drain.
  • ITO indium tin oxide
  • the barrier layer 25, the passivation layer 27, and the pixel electrode layer 28 formed thereon have a convex region and a recessed region, and for the pixel electrode layer 28, Corresponding to the strip of the active layer 24, it forms a convex region 281 corresponding to the slit of the active layer 24, which is formed with a recessed region 282.
  • the pixel electrode layer 28 formed in this embodiment is a block-shaped pixel electrode layer having a convex region 281 and a recessed region 282, and there is no slit. Therefore, the display panel using the array substrate 200 does not appear dark and display. Problems with poor brightness and contrast.
  • FIG. 5 is a schematic structural diagram of an embodiment of a display panel according to the present invention.
  • the display panel 500 includes an array substrate 51 , a color filter substrate 52 , and a liquid crystal layer 53 .
  • the liquid crystal layer 53 is located between the array substrate 51 and the color filter substrate 52.
  • the array substrate 51 in the display panel 500 of the present embodiment is similar to the above-described array substrate 200, and details are not described herein.
  • the liquid crystal layer 53 of the present embodiment can be effectively flipped between the array substrate 51 and the color filter substrate 52, and the display panel 500 does not have problems of dark lines, display brightness, and contrast.

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板及显示面板，其中阵列基板包括基板（11）；设置在基板（11）上的图案化的中间层（12）；以及设置在图案化的中间层（12）上的无图案化的像素电极层（13），像素电极层（13）对应图案化的中间层（12）形成凹陷区（132）和凸出区（131），阵列基板可以有效的改善暗纹的问题。

Description

一种阵列基板及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及显示面板。
【背景技术】
当前显示器的发展迅速，按照其显示原理可分为液晶显示器、等离子显示器、有机电致发光显示器等。
在液晶显示器的各种显示模式中，垂直排列（VA）显示模式因具有良好的视角而受到市场欢迎，一般来说VA显示模式采用多畴设计，而当前实现多畴设计有两种模式：一是像素电极的裂缝形成侧向电场的PVA模式；而是像素单元中的凸起使得液晶分子形成多畴排列的MVA模式，然而在两种模式中，液晶显示器都存在暗纹或显示不佳的问题。
【发明内容】
本发明的目的在于提供一种阵列基板及显示面板，以解决使用现有阵列基板的显示面板上出现暗纹的问题。
为解决上述问题，本发明提出一种阵列基板，该阵列基板包括：基板；设置在基板上的图案化的中间层；以及设置在图案化的中间层上的无图案化的像素电极层，像素电极层对应图案化的中间层形成凹陷区和凸出区，图案化的中间层为沟槽结构或条状结构，并为鱼骨状图案，且图案化的中间层为有源层。
其中，沟槽结构包括凹槽和凸起，像素电极层对应凹槽形成凹陷区，像素电极层对应凸起形成凸出区。
其中，条状结构包括条块和条块之间的狭缝，像素电极层对应条块形成凸出区，像素电极层对应狭缝形成凹陷区。为解决上述问题，本发明提出一种阵列基板，该阵列基板包括：基板；设置在基板上的图案化的中间层；以及设置在图案化的中间层上的无图案化的像素电极层，像素电极层对应图案化的中间层形成凹陷区和凸出区。
其中，图案化的中间层为沟槽结构或条状结构。
其中，沟槽结构包括凹槽和凸起，像素电极层对应凹槽形成凹陷区，像素电极层对应凸起形成凸出区。
其中，条状结构包括条块和条块之间的狭缝，像素电极层对应条块形成凸出区，像素电极层对应狭缝形成凹陷区。
其中，图案化的中间层为鱼骨状图案。
其中，图案化的中间层为有源层。
其中，有源层与像素电极层之间设置有钝化层。
其中，有源层的材料为非晶硅或铟镓锌氧化物。
为解决上述技术问题，本发明还提出一种显示面板，该显示面板包括阵列基板，阵列基板包括：基板；设置在基板上的图案化的中间层；以及设置在图案化的中间层上的无图案化的像素电极层，像素电极层对应图案化的中间层形成凹陷区和凸出区。
其中，图案化的中间层为沟槽结构或条状结构。
其中，沟槽结构包括凹槽和凸起，像素电极层对应凹槽形成凹陷区，像素电极层对应凸起形成凸出区。
其中，条状结构包括条块和条块之间的狭缝，像素电极层对应条块形成凸出区，像素电极层对应狭缝形成凹陷区。
其中，图案化的中间层为鱼骨状图案。
其中，图案化的中间层为有源层。
其中，有源层与像素电极层之间设置有钝化层。
其中，有源层的材料为非晶硅或铟镓锌氧化物。
其中，显示面板进一步包括对应阵列基板设置的彩色滤光片基板，以及设置在阵列基板和彩色滤光片基板之间的液晶层。
本发明阵列基板包括：基板，设置在基板上的图案化的中间层，以及设置在图案化的中间层上的无图案化的像素电极层，像素电极层对应图案化的中间层形成凹陷区和凸出区。本发明阵列基板中的像素电极层为无图案化的，即块状像素电极层，不存在狭缝，使用该阵列基板的显示面板不会出现暗纹、显示亮度和对比度不佳的问题。
【附图说明】
图1是本发明阵列基板第一实施方式的结构示意图；
图2是本发明阵列基板第二实施方式的结构示意图；
图3是图2所示阵列基板第二实施方式像素电极层的俯视图；
图4是图2所示阵列基板第二实施方式的制作流程图；
图5是本发明显示面板一实施方式的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对发明所提供的一种阵列基板及显示面板做进一步详细描述。
参阅图1，图1是本发明阵列基板第一实施方式的结构示意图，本实施方式阵列基板100包括基板11、中间层12、像素电极层13。
中间层12为图案化的中间层12，即形成中间层12的过程包括能够实现图案化的刻蚀工艺。无图案化的像素电极层13则形成在中间层12上，像素电极层13对应图案化的中间层12形成凸出区131和凹陷区132。
具体来说图案化的中间层12可以为条状结构（如图1（A））或沟槽结构（如图1（B））。
条状结构的中间层12包括条块121和条块121之间形成的狭缝122，即在刻蚀工艺中，将狭缝122处的中间层12完全去除。对于此类中间层12，像素电极层13上对应条块121形成凸出区131，对应于狭缝122形成凹陷区132。
沟槽结构的中间层12则包括凸起121和凹槽122，凹槽122处还保留有较薄的中间层12，即在刻蚀工艺中，只是将凹槽122处的中间层12部分去除。对于该类中间层12，像素电极层13上对应凸起121形成凸出区131，对应凹槽122形成凹陷区132。
无论是对于条状结构或沟槽结构的中间层12，像素电极层13均在其上形成具有凸出区131和凹陷区132的块状电极，保证使用该阵列基板100的显示面板中的液晶均能发生翻转，显示面板不会出现暗纹。
具体到应用中，中间层12与像素电极层13之间还可以设置别的层，像素电极层13可以直接沉积在中间层12上，也可以不直接沉积在中间层12上。
本实施方式阵列基板包括基板，设置在基板上的图案化的中间层，以及设置在图案化的中间层上的无图案化的像素电极层，像素电极层对应图案化的中间层形成凹陷区和凸出区。其中像素电极层为无图案化的，即为块状像素电极层，不存在狭缝，使用该阵列基板的显示面板不会出现暗纹、显示亮度和对比度不佳的问题。
请参阅图2，图2是本发明阵列基板第二实施方式的结构示意图，本实施方式阵列基板200包括玻璃基板21，以及在玻璃基板21上依次形成的栅极22、栅极绝缘层23、有源层24、阻挡层25、源/漏极26、钝化层27和像素电极层28。
其中，有源层24为本发明中图案化的中间层，像素电极层28设置在有源层24上方，对应于有源层24形成有凸出区281和凹陷区282，本实施方式中的有源层24为条状结构，当然也可为沟槽结构，具体来说图案化的有源层24为鱼骨状图案。相应的像素电极层28的凸出区281和凹陷区282也构成鱼骨状图案的纹路，可参阅图3，图3是图2所示阵列基板第二实施方式像素电极层的俯视图。
对于本实施方式阵列基板200，其制造过程可参阅图4，图4是图2所示阵列基板第二实施方式的制作流程图，该制造过程包括以下步骤。
S401：在玻璃基板上形成栅极和栅极绝缘层。
采用物理气相沉积及湿法刻蚀工艺在玻璃基板21上形成栅极22，然后采用化学气相沉积及干法刻蚀工艺形成栅极绝缘层23。
S402：栅极绝缘层上形成图案化的有源层。
在栅极绝缘层23上形成图案化的有源层24，主要是在阵列基板对应的显示区域形成该有源层24，以使得对应该图案化有源层24的像素电极层28具有凸出区281和凹陷区282，该图案化的有源层24为条状结构的鱼骨状图案，形成有源层24的材料可以为非晶硅或铟镓锌氧化物（IGZO）。
S403：形成具有开口的阻挡层。
在形成图案化的有源层24后，采用化学气相沉积及干法刻蚀工艺形成阻挡层25，该阻挡层25为刻蚀阻挡层25，即在后续刻蚀工艺中起到阻挡作用，避免已形成的有源层24又被刻蚀。由于后续形成的源/漏极26需要与有源层24电性连接，因此在阻挡层25上还形成两开口，以分别供源极和漏极与有源层24接触。
S404：阻挡层上形成源/漏极，源/漏极均通过阻挡层的开口与有源层电性连接。
源极和漏极为同一种金属，因此在本步骤S404中同时形成，具体来说，首先采用物理气相沉积一金属层，然后通过湿法刻蚀工艺对该金属层进行图案化处理，以形成源极和漏极。在沉积金属层时，由于阻挡层25上具有开口，因此金属层可沉积于开口中，以实现与有源层24的电性连接。
S405：形成具有开口的钝化层。
为延缓金属的源/漏极26的氧化，继续形成一钝化层27，由于后续形成的像素电极层28需要与漏极电性连接，因此在钝化层27上还形成一开口，使得像素电极层28能够通过该开口与漏极接触。具体来说钝化层的形成采用化学气相沉积和干法刻蚀工艺。
S406：形成像素电极层，像素电极层通过钝化层的开口与漏极电性连接。
本实施方式中像素电极层28由铟锡氧化物（ITO）采用物理气相沉积法制得，ITO能够沉积于钝化层27的开口中，实现与漏极的电性连接。
由于本实施方式中形成的有源层24为条状结构，因此形成在其上方的阻挡层25、钝化层27以及像素电极层28均有凸出区和凹陷区，对于像素电极层28，对应于有源层24的条块，其形成凸出区281，对应于有源层24的狭缝，其形成有凹陷区282。
本实施方式中所形成的像素电极层28为具有凸出区281和凹陷区282的块状像素电极层，不存在狭缝，因此，使用该阵列基板200的显示面板不会出现暗纹、显示亮度和对比度不佳的问题。
请参阅图5，图5是本发明显示面板一实施方式的结构示意图，本实施方式显示面板500包括阵列基板51、彩色滤光片基板52以及液晶层53。
液晶层53位于阵列基板51和彩色滤光片基板52之间，本实施方式显示面板500中的阵列基板51与上述阵列基板200类似，具体不再赘述。
本实施方式的液晶层53在阵列基板51和彩色滤光片基板52之间均能得到有效翻转，显示面板500不会出现暗纹、显示亮度和对比度不佳的问题。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    设置在所述基板上的图案化的中间层；
    以及设置在所述图案化的中间层上的无图案化的像素电极层，所述像素电极层对应所述图案化的中间层形成凹陷区和凸出区；
    所述图案化的中间层为沟槽结构或条状结构，且为鱼骨状图案；
    所述图案化的中间层为有源层。
  2. 根据权利要求1所述的阵列基板，其中，所述沟槽结构包括凹槽和凸起，所述像素电极层对应所述凹槽形成所述凹陷区，所述像素电极层对应所述凸起形成所述凸出区。
  3. 根据权利要求1所述的阵列基板，其中，所述条状结构包括条块和条块之间的狭缝，所述像素电极层对应所述条块形成所述凸出区，所述像素电极层对应所述狭缝形成所述凹陷区。
  4. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    设置在所述基板上的图案化的中间层；
    以及设置在所述图案化的中间层上的无图案化的像素电极层，所述像素电极层对应所述图案化的中间层形成凹陷区和凸出区。
  5. 根据权利要求4所述的阵列基板，其中，所述图案化的中间层为沟槽结构或条状结构。
  6. 根据权利要求5所述的阵列基板，其中，所述沟槽结构包括凹槽和凸起，所述像素电极层对应所述凹槽形成所述凹陷区，所述像素电极层对应所述凸起形成所述凸出区。
  7. 根据权利要求5所述的阵列基板，其中，所述条状结构包括条块和条块之间的狭缝，所述像素电极层对应所述条块形成所述凸出区，所述像素电极层对应所述狭缝形成所述凹陷区。
  8. 根据权利要求5所述的阵列基板，其中，所述图案化的中间层为鱼骨状图案。
  9. 根据权利要求4所述的阵列基板，其中，所述图案化的中间层为有源层。
  10. 根据权利要求9所述的阵列基板，其中，所述有源层与所述像素电极层之间设置有钝化层。
  11. 根据权利要求9所述的阵列基板，其中，所述有源层的材料为非晶硅或铟镓锌氧化物。
  12. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括：
    基板；
    设置在所述基板上的图案化的中间层；
    以及设置在所述图案化的中间层上的无图案化的像素电极层，所述像素电极层对应所述图案化的中间层形成凹陷区和凸出区。
  13. 根据权利要求12所述的显示面板，其中，所述图案化的中间层为沟槽结构或条状结构。
  14. 根据权利要求13所述的显示面板，其中，所述沟槽结构包括凹槽和凸起，所述像素电极层对应所述凹槽形成所述凹陷区，所述像素电极层对应所述凸起形成所述凸出区。
  15. 根据权利要求13所述的显示面板，其中，所述条状结构包括条块和条块之间的狭缝，所述像素电极层对应所述条块形成所述凸出区，所述像素电极层对应所述狭缝形成所述凹陷区。
  16. 根据权利要求13所述的显示面板，其中，所述图案化的中间层为鱼骨状图案。
  17. 根据权利要求12所述的显示面板，其中，所述图案化的中间层为有源层。
  18. 根据权利要求17所述的显示面板，其中，所述有源层与所述像素电极层之间设置有钝化层。
  19. 根据权利要求17所述的显示面板，其中，所述有源层的材料为非晶硅或铟镓锌氧化物。
  20. 根据权利要求12所述的显示面板，其中，所述显示面板进一步包括对应所述阵列基板设置的彩色滤光片基板，以及设置在所述阵列基板和所述彩色滤光片基板之间的液晶层。
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