WO2018004276A1 - Chip component and manufacturing method therefor - Google Patents

Chip component and manufacturing method therefor Download PDF

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Publication number
WO2018004276A1
WO2018004276A1 PCT/KR2017/006909 KR2017006909W WO2018004276A1 WO 2018004276 A1 WO2018004276 A1 WO 2018004276A1 KR 2017006909 W KR2017006909 W KR 2017006909W WO 2018004276 A1 WO2018004276 A1 WO 2018004276A1
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WO
WIPO (PCT)
Prior art keywords
laminate
chip component
surface modification
modification member
oxide
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Application number
PCT/KR2017/006909
Other languages
French (fr)
Korean (ko)
Inventor
백정철
이정훈
김정채
김주성
Original Assignee
주식회사 모다이노칩
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 모다이노칩 filed Critical 주식회사 모다이노칩
Priority to CN201780040170.4A priority Critical patent/CN109478465B/en
Publication of WO2018004276A1 publication Critical patent/WO2018004276A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G29/00Compounds of bismuth
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G45/00Compounds of manganese
    • C01G45/02Oxides; Hydroxides
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G51/00Compounds of cobalt
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G51/00Compounds of cobalt
    • C01G51/40Cobaltates
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G9/00Compounds of zinc
    • C01G9/02Oxides; Hydroxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/14Protection against electric or thermal overload
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F2017/0093Common mode choke coil

Definitions

  • the present invention relates to a chip component and a method for manufacturing the same, and more particularly, to a chip component capable of controlling the shape of an external electrode and a manufacturing method thereof.
  • a plurality of chip components are used to suppress noise of various frequencies of the portable electronic device and to suppress noise between internal circuits.
  • chip beads, a common mode filter, and the like which remove noise of different frequency bands, are used.
  • an ESD protection element such as a varistor, a suppressor, or the like is required to protect the electronic device from high voltage such as ESD applied to the electronic device from the outside.
  • ESD protection element such as a varistor, a suppressor, or the like is required to protect the electronic device from high voltage such as ESD applied to the electronic device from the outside.
  • at least two or more layers having different characteristics may be stacked to fabricate the chip components. For example, noise filters and ESD protection devices are stacked on one chip to implement chip components.
  • the chip component is formed with an external electrode on the outside of the laminate in which a predetermined structure is formed therein, and is connected to the internal circuit of the electronic device through the external electrode.
  • the external electrode may be formed by a plating process.
  • the chip component may be soldered and mounted on a PCB substrate of an electronic device.
  • an external electrode is formed by a plating process.
  • the surface of a laminated body has a nonuniform resistance state, and when a plating process is performed in this state, the nonuniformity of plating layer growth will generate
  • the present invention provides a chip component and a method of manufacturing the same that facilitate the shape control of an external electrode.
  • the present invention provides a chip component and a method of manufacturing the same, the surface of which is easily modified to control the shape of the external electrode.
  • Chip component is a laminate; And a surface modification member formed on at least one region of the laminate, wherein the surface modification member is formed to expose at least a portion of the surface of the laminate.
  • the laminate In the laminate, a plurality of sheets are stacked, and a layer of material different from the sheets is formed in the laminate.
  • the heterogeneous material layer includes a conductive pattern and an overvoltage protection material layer having a predetermined shape.
  • the surface modification member is distributed in an area of 5% to 90% of the surface area of the laminate.
  • the surface modification member includes at least one of an oxide in a crystalline state and an amorphous state.
  • the oxide is Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca (CO 3 ) 2 , Ca (NO 3 ) 2 , CaCO 3 .
  • the oxide is at least partially embedded in the surface of the laminate.
  • the oxide is aggregated or connected in at least one region of particles having at least one size.
  • the average size of the oxide particles is 0.1 ⁇ m to 10 ⁇ m.
  • the second surface modification member is formed on at least one sheet constituting the laminate.
  • a chip component includes a laminate in which a plurality of sheets are stacked; A heterogeneous material layer formed inside the laminate and formed of a material different from that of the sheet; And an external electrode formed on at least one side of the laminate, wherein the laminate has at least one surface having two or more components.
  • a surface modification member formed on at least one side of the laminate to expose at least a portion of the laminate surface.
  • the surface modification member includes an oxide.
  • the oxide is formed to a thickness of 0.01% to 10% of the laminate thickness.
  • a method of manufacturing a chip component comprising: providing a plurality of chip components; Forming a surface modification member on at least one surface of the plurality of chip components, wherein the surface modification member is formed such that at least a portion of the surface of the chip component is exposed.
  • the surface modification member is formed by injecting and rotating the plurality of chip components and oxide powder into a container.
  • a plurality of mediators are further added together with the plurality of chip components and the oxide powder.
  • the plurality of mediators consist of the chip component and the oxide powder and a heterogeneous material.
  • the plurality of mediators have a total volume greater than the total volume of the oxide powder and less than the total volume of the plurality of laminates.
  • Chip components according to the embodiments of the present invention can form a surface modification member on the surface of the laminate, thereby controlling the shape of the external electrode. That is, by forming a surface modification member on the surface of the laminate to modify the surface of the laminate, it is possible to prevent the spreading and spreading of the external electrode formed by plating, thereby easily controlling the shape of the external electrode. .
  • the present invention can prevent the penetration of moisture into the laminate by forming a surface modification member, thereby improving the life and reliability of the chip component.
  • FIG. 1 is a perspective view of a chip component according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic view of the surface of a chip component according to an embodiment of the present disclosure.
  • 3 to 5 is an exploded perspective view of a chip component according to embodiments of the present invention.
  • FIG. 6 is a flowchart illustrating a method of manufacturing a chip component according to an embodiment of the present disclosure.
  • 10 and 11 are schematic views showing the shape of the surface modification member and the surface of the laminate according to the size of the media and without the media.
  • FIG. 1 is a perspective view of a chip component according to an exemplary embodiment
  • FIG. 2 is a schematic surface view of the chip component.
  • a chip component may include a laminate 1000 in which a plurality of sheets are stacked, and a surface modification member 2000 formed on at least one surface of the laminate 1000. And an external electrode 3000 formed on at least one surface of the laminate 1000.
  • the laminate 1000 has a predetermined length and width, respectively, in one direction (for example, the X direction) and the other direction (for example, the Y direction) orthogonal thereto, and in the vertical direction (for example, the Z direction). It may be provided in a substantially hexahedral shape having a height of. That is, when the forming direction of the external electrode 3000 is the X direction, that is, the length, the direction orthogonal to the horizontal direction may be the Y direction, and the vertical direction may be the Z direction, that is, the thickness.
  • the length in the X direction may be greater than or equal to, for example, the width in the Y direction and the height in the Z direction, and the width in the Y direction may be the same as or different from the height in the Z direction. If the width (Y direction) and the height (Z direction) are different, the width may be larger or smaller than the height.
  • the ratio of length, width and height may be 1-5: 1: 0.5-2. That is, the length may be about 1 to 5 times greater than the width, and the height may be 0.5 to 2 times greater than the width.
  • the laminate 1000 may be formed by stacking a plurality of substantially plate-shaped sheets having a predetermined size. That is, the sheet may be provided in a substantially rectangular plate shape having a predetermined length and width in the X and Y directions and having a predetermined thickness in the Z direction. A plurality of such sheets may be stacked to form a substantially hexahedral stack 1000.
  • the plurality of sheets constituting the laminate 1000 may include at least one of dielectric material powder such as MLCC, BaTiO 3 , BaCO 3 , TiO 2 , Nd 2 O 3 , Bi 2 O 3 , Zn0, and Al 2 O 3 . It may be formed of a material containing. Accordingly, the sheets may each have a predetermined dielectric constant, for example, 5 to 20000, preferably 7 to 5000, and more preferably 200 to 3000. In addition, the plurality of sheets may be made of a varistor material. For example, the sheet may be formed by adding additives such as Bi 2 O 3 , Pr 6 O 11 , CoO, MnO, and the like to the ZnO powder.
  • dielectric material powder such as MLCC, BaTiO 3 , BaCO 3 , TiO 2 , Nd 2 O 3 , Bi 2 O 3 , Zn0, and Al 2 O 3 . It may be formed of a material containing. Accordingly, the sheets may each have a pre
  • the plurality of sheets may be nonmagnetic sheets or magnetic sheets. That is, it may be a nonmagnetic sheet formed of a material as described above and having a predetermined dielectric constant, or may be a magnetic sheet further comprising a magnetic material. Of course, at least one of the plurality of sheets may be formed of a magnetic sheet or a nonmagnetic sheet according to the use of the chip component. In addition, the plurality of sheets may be formed of a mixture of metal powder and polymer. As described above, the plurality of sheets may be formed of various materials according to the purpose of the chip component. In addition, the plurality of sheets may all be formed with the same thickness, and at least one may be formed thicker or thinner than the others.
  • various structures may be formed in the plurality of sheets in the laminate 1000. That is, various types of conductive patterns may be formed in the laminate 1000, and an ESD protection material may be formed. In other words, at least one heterogeneous material layer having a different component from the sheet of the laminate 1000 may be formed in the laminate 1000. For example, a spiral coil pattern and a hole filled with a conductive material may be selectively formed in the plurality of sheets in the stack 1000, and thus an inductor or a noise filter may be implemented. In addition, a structure for protecting a high voltage such as a varistor or an ESD protection unit may be implemented in the stack 1000.
  • a plurality of inner electrodes may be formed on the plurality of sheets in the stack 1000 so as to be alternately connected to the external electrodes 3000, and thus capacitors formed by two adjacent inner electrodes and a sheet therebetween may be formed.
  • a substrate having a coil pattern formed on at least one surface may be provided in the stack 1000, and a sheet made of metal powder and a polymer may be stacked thereon to form a power inductor.
  • One of the inductor, the noise filter, the capacitor, the power inductor, the varistor, and the ESD protection unit may be implemented in the stack 1000, or at least two or more of them may be implemented in combination.
  • the laminate 1000 may further include a lower cover layer (not shown) and an upper cover layer (not shown) formed on the lowermost layer and the uppermost layer.
  • the lowermost sheet may serve as the lower cover layer
  • the uppermost sheet may serve as the upper cover layer.
  • the lower and upper cover layers may be provided by stacking a plurality of magnetic sheets, and may have the same thickness.
  • a nonmagnetic sheet for example, a glass sheet, may be further formed on the outermost portion of the lower and upper cover layers formed of the magnetic sheet, that is, the lower and upper surfaces.
  • the lower and upper cover layers may be thicker than the sheets therein.
  • the surface modification member 2000 may be formed on at least one surface of the laminate 1000.
  • the surface modification member 2000 may be formed by, for example, distributing an oxide on the surface of the laminate 1000 before forming the external electrode 3000.
  • the oxide may be dispersed and distributed on the surface of the laminate 1000 in a crystalline state or an amorphous state.
  • the surface modification member 2000 may be distributed on the surface of the stack 1000 before the plating process when the external electrode 3000 is formed by the plating process. That is, the surface modification member 2000 may be distributed before forming a part of the external electrode 3000 in the printing process, or may be distributed before the plating process after the printing process.
  • the plating process may be performed after the surface modification member 2000 is distributed. In this case, at least a portion of the surface modification member 2000 distributed on the surface may be melted.
  • the surface modification member 2000 may be evenly distributed on the surface of the stack 1000 with at least a portion having the same size as shown in FIG. 2A, and as shown in FIG. 2B. Likewise, at least some may be irregularly distributed in different sizes.
  • a recess may be formed on at least part of the surface of the laminate 1000. That is, the surface modification member 2000 may be formed to form a convex portion, and at least a portion of the region where the surface modification member 2000 is not formed may be recessed to form a recess. In this case, at least a portion of the surface modification member 2000 may be formed deeper than the surface of the laminate 1000.
  • the surface modification member 2000 may be formed with a predetermined thickness to be embedded at a predetermined depth of the laminate 1000 and the remaining thickness higher than the surface of the laminate 1000.
  • the thickness of the laminate 1000 may be 1/20 to 1 of the average diameter of the oxide particles.
  • the oxide particles may be all embedded in the stack 1000 as illustrated in FIG. 2D, and at least some may be embedded.
  • the oxide particles may be formed only on the surface of the laminate 1000 as shown in FIG. Therefore, the oxide particles may be formed in a hemispherical shape on the surface of the laminate 1000, or may be formed in a spherical shape.
  • the surface modification member 2000 may be partially distributed on the surface of the laminate 1000 as described above, or may be distributed in a film form on at least one region. That is, as illustrated in FIGS. 2A to 2D, the oxide particles may be distributed in the form of islands on the surface of the laminate 1000 to form the surface modification member 2000. That is, oxides in a crystalline state or an amorphous state may be distributed in an island form on the surface of the laminate 1000, and thus at least a portion of the surface of the laminate 1000 may be exposed. In addition, as illustrated in FIG. 2E, at least two or more surface modification members 2000 may be connected to each other to form an oxide, and at least a portion of the oxide may be formed in an island shape.
  • At least two or more oxide particles may be aggregated or adjacent oxide particles may be connected to form a film.
  • the oxide is present in the form of particles or when two or more particles are aggregated or connected, at least a part of the surface of the laminate 1000 is exposed to the outside by the surface modifying member 2000.
  • the total area of the surface modification member 2000 may be, for example, 5% to 90% of the total area of the surface of the laminate 1000.
  • Plating bleeding of the surface of the laminate 1000 may be controlled according to the area of the surface modifying member 2000.
  • the conductive pattern and the external electrode (the inside of the laminate 1000) may be controlled. 3000) can be difficult to contact. That is, when the surface modification member 2000 is formed to be less than 5% of the surface area of the laminate 1000, it is difficult to control the plating bleeding phenomenon.
  • the electrode 3000 may not be in contact. Therefore, the surface modification member 2000 may control the plating bleeding phenomenon and may be formed in an area that can be in contact with the conductive pattern inside the laminate 1000 and the external electrode 3000.
  • the surface modification member 2000 may be formed of 10% to 90% of the surface area of the laminate 1000, preferably 30% to 70% of the surface area, more preferably 40% to It can be formed with an area of 50%.
  • the surface area of the laminate 1000 may be one surface area, or may be the six surface areas of the laminate 1000 forming a hexahedron.
  • the surface modification member 2000 may be formed to a thickness of 10% or less of the thickness of the laminate 1000. That is, the surface modification member 2000 may be formed to a thickness of 0.01% to 10% of the thickness of the laminate 1000.
  • the surface modification member 2000 may be present in a size of 0.1 ⁇ m to 50 ⁇ m, and thus the surface modification member 2000 may be formed to a thickness of 0.1 ⁇ m to 50 ⁇ m from the surface of the laminate 1000. have. That is, the surface modification member 2000 may be formed to have a thickness of 0.1 ⁇ m to 50 ⁇ m from the surface of the laminate 1000 except for a region that is less than the surface of the laminate 1000. Therefore, when the thickness of the laminated body 1000 is embedded, the surface modification member 2000 may have a thickness greater than 0.1 ⁇ m to 50 ⁇ m.
  • the surface modification member 2000 When the surface modification member 2000 is formed to a thickness less than 0.01% of the thickness of the laminate 1000, it is difficult to control the plating bleeding phenomenon, and when the surface modified member 2000 is formed to a thickness exceeding 10% of the thickness of the laminate 1000, the laminate The conductive pattern inside the 1000 and the external electrode 3000 may not contact each other. That is, the surface modification member 2000 may have various thicknesses according to the material properties (conductivity, semiconductivity, insulation, magnetic material, etc.) of the laminate 1000, and various thicknesses depending on the size, distribution amount, and aggregation of the oxide powder. It can have
  • the surface modification member 2000 is formed on the surface of the stack 1000, and thus, the surface of the stack 1000 may include at least two regions having different components. That is, different components may be detected in the region where the surface modification member 2000 is formed and the region where the surface modification member 2000 is not formed.
  • the region in which the surface modification member 2000 is formed may have a component according to the surface modification member 2000, that is, an oxide
  • the region in which the surface modification member 2000 is not formed may be a component according to the laminate 1000, that is, a component of the sheet. May exist.
  • the surface of the laminate 1000 may be provided with a roughness to be modified.
  • the plating process can be performed uniformly, and thus the shape of the external electrode 3000 can be controlled. That is, the surface of the laminate 1000 may have a resistance of at least one region different from that of another region. If the plating process is performed in a state where the resistance is uneven, growth unevenness of the plating layer may occur. In order to solve this problem, the surface of the laminate 1000 may be modified by dispersing oxides in a particulate state or a molten state on the surface of the laminate 1000 to form a surface modification member 2000, thereby increasing the growth of the plating layer. Can be controlled.
  • the oxide in the particulate state or in the molten state to make the surface resistance of the laminate 1000 uniform is, for example, Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al At least one of 2 O 3 , MnO, H 2 BO 3 , Ca (CO 3 ) 2 , Ca (NO 3 ) 2 , and CaCO 3 may be used.
  • the surface modification member 2000 may also be formed on at least one sheet in the laminate 1000. That is, the conductive patterns of various shapes on the sheet may be formed by a plating process, and the shape of the conductive patterns may be controlled by forming the surface modification member 2000.
  • the external electrodes 3100, 3200; 3000 are provided on two opposite sides of the stack 1000 to be selectively connected to a conductive pattern formed in the stack 1000. That is, one external electrode 3000 may be formed on each of two side surfaces facing each other, for example, the first and second sides, or two or more external electrodes may be formed as shown in FIG. 1. In addition, at least one external electrode may be further formed on at least one of the third and fourth sides orthogonal to the first and second sides.
  • the external electrode 3000 may be formed of at least one layer.
  • the external electrode 3000 may be formed of a metal layer such as Ag, and at least one plating layer may be formed on the metal layer.
  • the external electrode 3000 may be formed by stacking a copper layer, a Ni plating layer, and a Sn or Sn / Ag plating layer.
  • the external electrode 3000 may be formed by mixing, for example, glass frit having a multi-component glass frit containing 0.5% to 20% of Bi 2 O 3 or SiO 2 as a main component.
  • the mixture of the glass frit and the metal powder may be prepared in a paste form and applied to two surfaces of the laminate 1000.
  • the adhesion between the external electrode 3000 and the laminate 1000 may be improved, and the contact reaction between the conductive pattern inside the laminate 1000 and the external electrode 3000 may be improved. Can be improved.
  • At least one plating layer may be formed on the upper portion thereof, thereby forming the external electrode 3000. That is, the metal layer including the glass and at least one plating layer formed thereon may be formed to form the external electrode 3000.
  • the external electrode 3000 may sequentially form a Ni plating layer and a Sn plating layer through electrolytic or electroless plating after forming a layer including glass frit and Ag and Cu.
  • the Sn plating layer may be formed to the same or thicker thickness than the Ni plating layer.
  • the external electrode 3000 may be formed of only at least one plating layer.
  • the external electrode 3000 may be formed by forming at least one layer of the plating layer using at least one plating process without applying the paste. Meanwhile, the external electrode 3000 may be formed to have a thickness of 2 ⁇ m to 100 ⁇ m, the Ni plating layer may be formed to have a thickness of 1 ⁇ m to 10 ⁇ m, and the Sn or Sn / Ag plating layer may have a thickness of 2 ⁇ m to 10 ⁇ m. Can be formed.
  • FIGS. 3 to 5 are exploded perspective views of the laminate 1000 according to an exemplary embodiment, and are exploded perspective views of a noise filter including a spiral coil pattern.
  • the stack 1000 may include various chip components such as a capacitor, a varistor, an inductor, and a power inductor.
  • the following embodiment describes an example of a common mode noise filter.
  • a plurality of sheets 110 to 150 may be stacked, and at least one coil pattern 310 to 340 may be formed on at least one selected sheet 120 to 150, respectively.
  • at least two coil patterns 310 to 340 may be connected in a vertical direction through holes 351, 352, 361, and 362 in which conductive materials are embedded.
  • the first coil pattern 310 may be connected to the third coil pattern 330 through holes 351 and 352 in which the conductive material is embedded, and the second coil pattern 320 may be filled with the conductive material. It may be connected to the fourth coil pattern 340 through the holes 361 and 362.
  • lead electrodes 410 to 440 drawn outward from each coil pattern 310 to 340 may be formed to be connected to the external electrode.
  • an upper cover layer 1100 and a lower cover layer 1200 may be formed at an upper portion of the uppermost sheet 110 and a lower portion of the lowermost sheet 150, respectively.
  • the upper and lower cover layers 1100 and 1200 may be formed thicker than the thickness of each of the sheets 110 to 150.
  • an ESD protection unit may be further formed in the stack 1000. That is, the common mode noise filter and the ESD protection unit may be stacked to form a composite device.
  • the laminate 1000 connects the plurality of sheets 110 to 180, the coil patterns 310 to 340 and the coil patterns 310 to 340 respectively formed on the selected at least one sheet 120 to 150, respectively. Holes 351, 352, 361, and 362 formed by filling a conductive material, the lead electrodes 410 through 440 drawn out from the coil patterns 310 through 340, and connected to external electrodes, and the selected sheet 170.
  • the second discharge electrode 520 may be formed on the selected sheet 180 to be connected to the ESD protection layers 531 to 534.
  • the first discharge electrodes 511 to 514 are connected to an external electrode together with the plurality of lead electrodes 410 to 440, and the second discharge electrode 520 is connected to a separate external electrode.
  • a sheet 160 may be provided therebetween to separate the common mode noise filter unit and the ESD protection unit.
  • At least one capacitor electrode 610 may be further formed in the stack 1000. That is, the capacitor electrode 610 may be provided with a sheet 190 between the two coil patterns 320 and 330, may be formed on the sheet 190, and may be drawn out from the capacitor electrode 610. 610 may be formed. In addition, holes 190 and 363 in which the conductive material is embedded may be formed in the sheet 190 to connect the upper and lower coil patterns. Capacitors having a predetermined capacitance may be formed between the capacitor electrodes 610 and upper and lower coil patterns 320 and 330 with the sheets 130 and 190 interposed therebetween.
  • the chip component according to the exemplary embodiment may control the shape of the external electrode 3000 by forming the surface modification member 2000 on the surface of the laminate 1000. That is, by forming the surface modification member 2000 on the surface of the laminate 1000 to modify the surface of the laminate 1000, the spreading and spreading of the external electrode 3000 formed by plating may be prevented, Accordingly, the shape of the external electrode 3000 can be easily controlled.
  • the present invention can form a surface modification member 2000 having a different component from that of the laminate 1000 on the surface of the laminate 1000, thereby preventing the penetration of moisture into the laminate 1000, thereby preventing the It can improve the service life and reliability. Moisture resistance can be confirmed by measuring a leakage current after maintaining a chip component for a predetermined time in a high temperature and high humidity environment.
  • FIG. 8 is a flowchart illustrating a method of manufacturing a chip component according to an embodiment of the present disclosure.
  • a plurality of substantially rectangular sheets having a predetermined thickness are provided (S110).
  • the plurality of sheets may be larger than the size of the chip component. That is, after forming a some electrically conductive pattern etc. on a some sheet, it can cut to the magnitude
  • the plurality of sheets may be nonmagnetic sheets or magnetic sheets having a predetermined dielectric constant. That is, at least one of the plurality of sheets may be a nonmagnetic sheet or a magnetic sheet.
  • the plurality of sheets may be formed of a varistor material having a predetermined breakdown voltage.
  • a conductive pattern having a predetermined shape is formed on at least one sheet (S120).
  • a plurality of insulating patterns may be formed on the conductive pattern.
  • the conductive pattern may be formed in a quadrangle having a predetermined area, or may be formed in a spiral shape from the center area to the outside.
  • the conductive pattern may be formed by a screen printing method using a conductive material such as Ag, Pt, Ni, Sn, Cu, or may be formed by a plating method.
  • the surface modification member 2000 may be formed on at least one surface of the sheet before the conductive pattern is formed by the plating method.
  • the surface modification member 2000 may be formed on the surface of the sheet to modify the surface of the sheet.
  • an ESD protection member for blocking a high voltage such as an ESD may be formed on the at least one sheet.
  • the ESD protection member may be formed between two conductive patterns spaced apart in the vertical or horizontal direction.
  • the ESD protection member may be formed to fill a gap formed to penetrate the sheet, or may be formed to partially overlap them between two conductive patterns spaced apart on the sheet.
  • the ESD protection member may be a gap provided between the two conductive patterns. That is, without forming a separate material between the two conductive patterns spaced apart in the vertical or horizontal direction, it may be used as an ESD protection member by maintaining a gap therebetween.
  • a plurality of sheets on which the conductive pattern and / or the ESD protection member are formed are stacked, cut and baked to form the laminate 1000 (S130). Accordingly, an inductor or a common mode noise filter in which a plurality of spiral coils are formed may be formed, or a capacitor may be formed in which two conductive patterns form capacitance between sheets. In addition, an ESD protection unit may be formed. By stacking the plurality of sheets to form the stack 1000, chip components having various uses may be formed according to the shape of the conductive pattern, the presence or absence of an ESD protection unit, the material of the sheet, and the like.
  • the surface modification member 2000 is formed on the surface of the laminate 1000 (S140).
  • the surface modification member 2000 may be formed by dispersing an oxide on the surface of the laminate 1000, for example, Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3, MnO, H 2 BO 3, Ca (CO 3) 2, Ca (NO 3) 2, may be used at least one of CaCO 3.
  • the oxide and the laminate 1000 are introduced into a cylinder having a predetermined space therein, and the cylinder is then moved in the horizontal direction and / or the vertical direction. By rotating, the oxide may be dispersed on the surface of the laminate 1000.
  • the barrel may be formed in a substantially cylindrical.
  • the surface modification member 2000 may be formed by performing the process at least once.
  • the amount, size, and thickness of the surface of the stack 1000 of the surface modification member 2000 may vary depending on the amount of oxide, the amount of the stack 1000, a process time, and the like. That is, the amount of the oxide and the processing time increases, the distribution amount of the surface modifying member 2000, that is, the surface area, size and thickness may increase, and as the amount of the laminate 1000 increases, the amount of distribution of the surface modifying member 2000 increases. That is, the surface area, size and thickness can be reduced.
  • the quantity of the laminated body 1000 is 20000-60000, and 2g-15g of oxides can be thrown in, and the oxide of 0 micrometer-10 micrometers thickness can be distributed on the surface of the laminated body 1000, and one laminated body ( The oxide may be applied in an amount of 50 ⁇ g to 200 ⁇ g per 1000).
  • the rotational speed may be, for example, 50 to 100 rpm, and the volume of the cylinder may be 500 to 1000 cc.
  • the process time may be 30 minutes to 2 hours.
  • the oxide when 60000 laminates 1000 having a surface area of 9.92 mm 2 are put in a predetermined cylinder together with 4 g of oxide, and then rotated for a predetermined time, the oxide is formed to a thickness of 0 ⁇ m to 4 ⁇ m, and 6.7 per surface area. About ⁇ g / mm 2 is formed to distribute oxides in an amount of about 67 ⁇ g per chip. The surface photograph at this time is shown in FIG. Further, when 60000 laminates 1000 having a surface area of 9.92 mm 2 were put in a predetermined cylinder together with 8 g of oxide, and then rotated for a predetermined time, the oxide was formed to a thickness of 1 ⁇ m to 6 ⁇ m and 13.4 ⁇ g / surface area.
  • the surface of the laminate 1000 may be pickled.
  • the pickling process is a preliminary step for modifying the surface of the stack 1000 to weakly treat the stack 1000 to form uniform pores on the surface of the stack 1000.
  • the surface modification member 2000 may further facilitate the formation of the laminate 1000.
  • a plurality of mediators may be further added together with the oxides, and the mediators may be added to uniformly distribute the oxides. In other words, when the medium is not added, the oxides may increase in agglomeration with each other if the media are unevenly distributed, but when the medium is added, the oxides may be uniformly distributed and the amount of aggregates may be reduced.
  • the medium may use a material different from that of the laminate 1000 and the surface modifying member 2000, for example, stainless steel, ceramic, or the like.
  • the medium may use a variety of forms, such as spherical, hexahedral.
  • the plurality of media may use a volume whose total volume is larger than the total volume of the oxide powder and smaller than the total volume of the stack 1000, for example, the total volume of the medium is 10% of the total volume of the stack 1000. To 90% may be used.
  • the size and spacing of the oxide dispersed in the stack 1000 can be adjusted according to the size of the mediator.
  • 10 (a) and 11 (a) are schematic cross-sectional views and planar photographs for explaining the distribution shape of the surface modifying member when no medium is used, and as shown, the surface modifying member 2000 is laminated.
  • the amount of aggregation or connection may be increased to form a film in at least one region.
  • the surface modification member 2000 may be formed on the surface of the laminate 1000 in FIGS. 10A and 10B. It is distributed more regularly than the case shown in (a) of 11, and the amount of aggregation or connection is reduced.
  • a medium having a large size as shown in FIGS.
  • the surface modification member 2000 is regularly distributed on the surface of the laminate 1000, and It is formed on the surface of the laminate 1000 in a larger size than in the case of using the small medium shown in (b) and (b) of FIG.
  • the oxide adhering to the surface of the stack 1000 is compacted so that the oxide can be attached to a predetermined depth from the surface of the stack 1000.
  • the laminated body 1000 in which the surface modification member 2000 was formed can be surface-polished as needed (S150).
  • a part of the surface modification member 2000 may be polished according to the surface polishing, thereby allowing the surface modification member 2000 to be formed in an island shape.
  • the polishing process can be carried out by a wet polishing or a dry polishing process.
  • wet polishing a plurality of laminates 1000 in which the surface modification member 2000 is formed, pure water, and an abrasive are introduced into a cylinder having a predetermined internal space, and then polished at a rotational speed of 50 to 100 rpm.
  • the polishing may be performed at a rotational speed of 100 to 200 rpm. That is, dry polishing can be performed at high speed without adding pure water.
  • the abrasive may be alumina.
  • the polishing time may vary depending on the laminate 1000, the amount of pure water and abrasives, the roughness of the abrasive, the polishing rate, etc., and the low speed and wet polishing may be performed for 30 minutes or more, and the high speed and dry polishing may be performed for 1 hour or less. Can be.
  • wet grinding can be performed for 30 minutes or more and 24 hours or less
  • dry polishing can be performed for 1 hour or more and 24 hours or less.
  • 12 and 13 are photographs of the surface of the laminate after wet polishing and dry polishing, (a) before each polishing, (b) after one hour polishing, (c) after four hours polishing, and (d) 6 After time polishing, (e) shows photographs after 24 hours polishing, respectively.
  • the polishing process may control the size and distribution of the surface modification member 2000 of the laminate 1000.
  • FIG. 14 and 15 are photographs of the external electrode shape of the chip component according to the present invention in which the surface modification member is formed and the external electrode shape of the chip component according to the conventional example in which the surface modification member is not formed.
  • the present invention in which the surface modification member is formed as shown in (a) of FIG. 14 has an insulating property of the surface of the laminate 1000 as compared with the prior art which does not form the surface modification member as shown in (b) of FIG. It is possible to further prevent the plating bleeding to control the shape of the external electrode.
  • the present invention in which the surface modification member is formed as shown in FIG. 15A shows surface roughness through surface modification as compared with the prior art in which the surface modification member is not formed as shown in FIG. 15B. The spreading phenomenon can be prevented during plating.
  • the plurality of chip parts having the surface modification member according to the present invention and the plurality of chip parts without the surface modification member according to the related art are maintained at 85 ° C. and 85% humidity. After maintaining for 12 hours at 5V voltage was applied to check the leakage current. At this time, the leakage current (cross IL) between the data line and the ground line and the leakage current between the data lines (IL) were measured, and when a current of 10 nA or more flowed, it was determined as defective.
  • Table 1 shows the results of moisture resistance according to the present invention and the conventional example.
  • the present invention can improve the moisture resistance of the chip component by forming the surface modification member, thereby improving the life and reliability of the chip component.

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Abstract

The present invention provides a chip component and a manufacturing method therefor, the chip component comprising a laminate, and a surface modified member formed on at least one region of the laminate, wherein the surface modified member exposes at least a portion of the surface of the laminate.

Description

칩 부품 및 그 제조 방법Chip component and its manufacturing method
본 발명은 칩 부품 및 그 제조 방법에 관한 것으로, 특히 외부 전극의 형상을 제어할 수 있는 칩 부품 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component and a method for manufacturing the same, and more particularly, to a chip component capable of controlling the shape of an external electrode and a manufacturing method thereof.
최근들어, 휴대용 전자 기기, 예컨데 스마트폰 등의 다기능화에 따라 다양한 주파수 대역이 사용되고 있다. 즉, 하나의 스마트폰 내에서 무선 LAN(wireless LAN), 블루투스(bluetooth), GPS 등 다른 주파수 대역을 이용하는 복수의 기능을 채용하게 되었다. 또한, 전자 기기의 고집적화에 따라 한정된 공간에서의 내부 회로 밀도가 높아지게 되고, 그에 따라 내부 회로 사이에 노이즈 간섭이 필연적으로 발생하게 된다.Recently, various frequency bands have been used in accordance with the multifunctionalization of portable electronic devices, for example, smart phones. That is, a plurality of functions using different frequency bands, such as wireless LAN, Bluetooth, and GPS, are adopted in one smartphone. In addition, due to the high integration of electronic devices, the internal circuit density in a limited space is increased, and noise interference between the internal circuits is inevitably generated.
이렇게 휴대용 전자 기기의 다양한 주파수의 노이즈를 억제하고, 내부 회로 사이의 노이즈를 억제하기 위해 복수의 칩 부품이 이용되고 있다. 예를 들어, 각각 서로 다른 주파수 대역의 노이즈를 제거하는 칩 비드, 공통 모드 필터(common mode filter) 등이 이용되고 있다.Thus, a plurality of chip components are used to suppress noise of various frequencies of the portable electronic device and to suppress noise between internal circuits. For example, chip beads, a common mode filter, and the like, which remove noise of different frequency bands, are used.
또한, 외부로부터 전자기기로 인가되는 ESD 등의 고전압으로부터 전자기기를 방호하기 위해 배리스터, 서프레서, 등의 ESD 보호 소자가 필요하다. 그리고, 이들 칩 부품이 차지하는 면적을 줄이기 위해 서로 다른 특성을 갖는 적어도 둘 이상을 적층하여 칩 부품을 제작할 수 있다. 예를 들어, 노이즈 필터와 ESD 보호 소자를 하나의 칩 내에 적층하여 칩 부품을 구현한다.In addition, an ESD protection element such as a varistor, a suppressor, or the like is required to protect the electronic device from high voltage such as ESD applied to the electronic device from the outside. In order to reduce the area occupied by these chip components, at least two or more layers having different characteristics may be stacked to fabricate the chip components. For example, noise filters and ESD protection devices are stacked on one chip to implement chip components.
이러한 칩 부품은 내부에 소정의 구조물이 형성된 적층체의 외부에 외부 전극이 형성되고, 외부 전극을 통해 전자기기의 내부 회로와 연결된다. 이때, 외부 전극은 도금 공정으로 형성할 수 있다. 즉, 칩 부품은 전자기기의 PCB 기판 상에 납땜되어 실장될 수 있는데, 솔더링 특성을 향상시키기 위해 외부 전극을 도금 공정으로 형성한다.The chip component is formed with an external electrode on the outside of the laminate in which a predetermined structure is formed therein, and is connected to the internal circuit of the electronic device through the external electrode. In this case, the external electrode may be formed by a plating process. In other words, the chip component may be soldered and mounted on a PCB substrate of an electronic device. In order to improve soldering characteristics, an external electrode is formed by a plating process.
그런데, 적층체의 표면은 불균일한 저항 상태를 갖게 되고, 이 상태에서 도금 공정을 실시하면 도금층 성장의 불균일이 발생된다. 즉, 도금층의 번짐 현상이 발생되고, 그에 따라 외부 전극이 원하지 않는 형상으로 형성된다.By the way, the surface of a laminated body has a nonuniform resistance state, and when a plating process is performed in this state, the nonuniformity of plating layer growth will generate | occur | produce. That is, a bleeding phenomenon of the plating layer occurs, whereby the external electrode is formed into an unwanted shape.
이러한 도금 번짐 현상을 방지하기 위해 적층체 표면에 글래스 등을 코팅하는 것이 알려져 있다. 즉, 글래스를 이용하여 적층체 표면에 코팅층을 형성한다. 그러나, 표면 코팅층은 적층체 형성 후 적층체 표면에 글래스 성분을 코팅하는 것으로 적층체와 완벽한 결합성을 얻지 못하며, 코팅층으로 인해 적층체 내부의 도체와 외부 전극이 연결되지 못하는 등의 문제가 발생될 수 있다.It is known to coat glass or the like on the laminate surface in order to prevent such plating bleeding phenomenon. That is, a coating layer is formed on the laminated body surface using glass. However, the surface coating layer does not obtain a perfect bond with the laminate by coating a glass component on the surface of the laminate after the laminate is formed, and the coating layer may cause problems such as the connection between the conductor and the external electrode inside the laminate. Can be.
(선행기술문헌)(Prior art document)
한국등록특허 제10-0876206호Korea Patent Registration No. 10-0876206
한국공개특허 제2002-0045782호Korean Laid-Open Patent No. 2002-0045782
본 발명은 외부 전극의 형상 제어가 용이한 칩 부품 및 그 제조 방법을 제공한다.The present invention provides a chip component and a method of manufacturing the same that facilitate the shape control of an external electrode.
본 발명은 표면을 개질시켜 외부 전극의 형상 제어가 용이한 칩 부품 및 그 제조 방법을 제공한다.The present invention provides a chip component and a method of manufacturing the same, the surface of which is easily modified to control the shape of the external electrode.
본 발명의 일 양태에 따른 칩 부품은 적층체; 및 상기 적층체의 적어도 일 영역에 형성된 표면 개질 부재를 포함하고, 상기 표면 개질 부재는 상기 적층체 표면의 적어도 일부를 노출시키도록 형성된다.Chip component according to an aspect of the present invention is a laminate; And a surface modification member formed on at least one region of the laminate, wherein the surface modification member is formed to expose at least a portion of the surface of the laminate.
상기 적층체는 복수의 시트가 적층되고, 상기 적층체 내에 상기 시트와는 이종의 물질층이 형성된다.In the laminate, a plurality of sheets are stacked, and a layer of material different from the sheets is formed in the laminate.
상기 이종의 물질층은 소정 형상의 도전 패턴 및 과전압 방호 물질층을 포함한다.The heterogeneous material layer includes a conductive pattern and an overvoltage protection material layer having a predetermined shape.
상기 표면 개질 부재는 상기 적층체의 표면적의 5% 내지 90%의 면적으로 분포된다.The surface modification member is distributed in an area of 5% to 90% of the surface area of the laminate.
상기 표면 개질 부재는 결정 상태 및 비결정 상태의 산화물 중 적어도 하나를 포함한다.The surface modification member includes at least one of an oxide in a crystalline state and an amorphous state.
상기 산화물은 Bi2O3, BO2, B2O3, ZnO, Co3O4, SiO2, Al2O3, MnO, H2BO3, Ca(CO3)2, Ca(NO3)2, CaCO3 중 적어도 하나를 포함한다.The oxide is Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca (CO 3 ) 2 , Ca (NO 3 ) 2 , CaCO 3 .
상기 산화물은 적어도 일부가 상기 적층체의 표면 내측으로 박힌다.The oxide is at least partially embedded in the surface of the laminate.
상기 산화물은 적어도 하나 이상의 크기를 갖는 입자가 적어도 일 영역에서 응집 또는 연결된다.The oxide is aggregated or connected in at least one region of particles having at least one size.
상기 산화물 입자의 평균 크기는 0.1㎛ 내지 10㎛이다.The average size of the oxide particles is 0.1 μm to 10 μm.
상기 적층체 표면의 적어도 일부에 형성된 오목부를 더 포함한다.It further includes a recess formed in at least a portion of the surface of the laminate.
상기 적층체 내부에 형성된 제 2 표면 개질 부재를 더 포함한다.It further comprises a second surface modification member formed inside the laminate.
상기 제 2 표면 개질 부재는 상기 적층체를 이루는 적어도 하나의 시트에 형성된다.The second surface modification member is formed on at least one sheet constituting the laminate.
본 발명의 다른 양태에 따른 칩 부품은 복수의 시트가 적층된 적층체; 상기 적층체 내부에 형성되며 상기 시트와는 다른 물질로 형성된 이종 물질층; 및 상기 적층체의 적어도 일 면에 형성된 외부 전극을 포함하고, 상기 적층체는 적어도 일 표면이 둘 이상의 성분을 갖는다.According to another aspect of the present invention, a chip component includes a laminate in which a plurality of sheets are stacked; A heterogeneous material layer formed inside the laminate and formed of a material different from that of the sheet; And an external electrode formed on at least one side of the laminate, wherein the laminate has at least one surface having two or more components.
상기 적층체의 적어도 일 면에 상기 적층체 표면의 적어도 일부를 노출시키도록 형성된 표면 개질 부재를 포함한다.And a surface modification member formed on at least one side of the laminate to expose at least a portion of the laminate surface.
상기 표면 개질 부재는 산화물을 포함한다.The surface modification member includes an oxide.
상기 산화물은 상기 적층체 두께의 0.01% 내지 10%의 두께로 형성된다.The oxide is formed to a thickness of 0.01% to 10% of the laminate thickness.
본 발명의 또다른 양태에 따른 칩 부품의 제조 방법은 복수의 칩 부품을 마련하는 과정; 상기 복수의 칩 부품의 적어도 일면에 표면 개질 부재를 형성하는 과정을 포함하고, 상기 표면 개질 부재는 상기 칩 부품 표면의 적어도 일부가 노출되도록 형성한다.According to still another aspect of the present invention, there is provided a method of manufacturing a chip component, the method comprising: providing a plurality of chip components; Forming a surface modification member on at least one surface of the plurality of chip components, wherein the surface modification member is formed such that at least a portion of the surface of the chip component is exposed.
상기 표면 개질 부재는 상기 복수의 칩 부품과 산화물 분말을 용기 내에 투입하고 회전하여 형성한다.The surface modification member is formed by injecting and rotating the plurality of chip components and oxide powder into a container.
상기 복수의 칩 부품 및 상기 산화물 분말과 함께 복수의 매개물을 더 투입한다.A plurality of mediators are further added together with the plurality of chip components and the oxide powder.
상기 복수의 매개물은 상기 칩 부품 및 상기 산화물 분말과 이종의 물질로 이루어진다.The plurality of mediators consist of the chip component and the oxide powder and a heterogeneous material.
상기 복수의 매개물은 총 부피가 상기 산화물 분말의 총 부피보다 크고 상기 복수의 적층체의 총 부피보다 작다.The plurality of mediators have a total volume greater than the total volume of the oxide powder and less than the total volume of the plurality of laminates.
상기 표면 개질 부재를 형성하기 전 산세 처리하는 과정과, 상기 표면 개질 부재를 형성한 후 상기 칩 부품을 표면 연마하는 과정의 적어도 하나를 더 포함한다.At least one of a process of pickling before forming the surface modification member, and a process of surface polishing the chip component after forming the surface modification member.
본 발명의 실시 예들에 따른 칩 부품은 적층체의 표면에 표면 개질 부재를 형성하고, 그에 따라 외부 전극의 형상을 제어할 수 있다. 즉, 적층체의 표면에 표면 개질 부재를 형성하여 적층체의 표면을 개질함으로써 도금으로 형성되는 외부 전극의 번짐 및 퍼짐 현상을 방지할 수 있고, 그에 따라 외부 전극의 형상을 용이하게 제어할 수 있다.Chip components according to the embodiments of the present invention can form a surface modification member on the surface of the laminate, thereby controlling the shape of the external electrode. That is, by forming a surface modification member on the surface of the laminate to modify the surface of the laminate, it is possible to prevent the spreading and spreading of the external electrode formed by plating, thereby easily controlling the shape of the external electrode. .
또한, 본 발명은 표면 개질 부재를 형성함으로써 적층체로의 수분 침투를 방지할 수 있고, 그에 따라 칩 부품의 수명 및 신뢰성을 향상시킬 수 있다.In addition, the present invention can prevent the penetration of moisture into the laminate by forming a surface modification member, thereby improving the life and reliability of the chip component.
도 1은 본 발명의 일 실시 예에 따른 칩 부품의 사시도.1 is a perspective view of a chip component according to an embodiment of the present disclosure.
도 2는 본 발명의 일 실시 예에 따른 칩 부품의 표면 개략도.2 is a schematic view of the surface of a chip component according to an embodiment of the present disclosure.
도 3 내지 도 5는 본 발명의 실시 예들에 따른 칩 부품의 분해 사시도.3 to 5 is an exploded perspective view of a chip component according to embodiments of the present invention.
도 6은 본 발명의 일 실시 예에 따른 칩 부품의 제조 방법을 설명하기 위한 공정 흐름도.6 is a flowchart illustrating a method of manufacturing a chip component according to an embodiment of the present disclosure.
도 7 내지 도 9는 산화물의 투입량에 따른 적층체 표면 사진.7 to 9 is a photograph of the laminate surface according to the dosage of the oxide.
도 10 및 도 11은 매개물을 이용하지 않은 경우와 매개물의 크기에 따른 표면 개질 부재의 형상을 도시한 개략도 및 적층체 표면 사진.10 and 11 are schematic views showing the shape of the surface modification member and the surface of the laminate according to the size of the media and without the media.
도 12 및 도 13은 습식 연마와 건식 연마 후의 적층체 표면 사진.12 and 13 are photographs of the laminate surface after wet polishing and dry polishing.
도 14 및 도 15는 표면 개질 부재를 형성한 본 발명과 표면 개질 부재를 형성하지 않은 종래 예에 따른 칩 부품의 외부 전극의 사진.14 and 15 are photographs of the external electrode of the chip component according to the present invention in which the surface modification member is formed and the conventional example without the surface modification member.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면에서 여러 층 및 각 영역을 명확하게 표현하기 위하여 두께를 확대하여 표현하였으며 도면상에서 동일 부호는 동일한 요소를 지칭하도록 하였다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements.
도 1은 본 발명의 일 실시 예에 따른 칩 부품의 사시도이고, 도 2는 칩 부품의 표면 개략도이다.1 is a perspective view of a chip component according to an exemplary embodiment, and FIG. 2 is a schematic surface view of the chip component.
도 1 및 도 2를 참조하면, 본 발명의 일 실시 예에 따른 칩 부품은 복수의 시트가 적층된 적층체(1000)와, 적층체(1000)의 적어도 일 표면에 형성된 표면 개질 부재(2000)와, 적층체(1000)의 적어도 일 면에 형성된 외부 전극(3000)을 포함할 수 있다.1 and 2, a chip component according to an exemplary embodiment may include a laminate 1000 in which a plurality of sheets are stacked, and a surface modification member 2000 formed on at least one surface of the laminate 1000. And an external electrode 3000 formed on at least one surface of the laminate 1000.
적층체Laminate
적층체(1000)는 일 방향(예를 들어 X 방향) 및 이와 직교하는 타 방향(예를 들어 Y 방향)으로 각각 소정의 길이 및 폭을 각각 갖고, 수직 방향(예를 들어 Z 방향)으로 소정의 높이를 갖는 대략 육면체 형상으로 마련될 수 있다. 즉, 외부 전극(3000)의 형성 방향을 X 방향, 즉 길이라 할 때, 이와 수평 방향으로 직교하는 방향을 Y 방향을 폭으로 하고, 수직 방향을 Z 방향, 즉 두께로 할 수 있다. 여기서, X 방향으로의 길이는 예를 들어 Y 방향으로의 폭 및 Z 방향으로의 높이보다 크거나 같고, Y 방향으로의 폭은 Z 방향으로의 높이와 같거나 다를 수 있다. 폭(Y 방향)과 높이(Z 방향)가 다를 경우 폭은 높이보다 크거나 작을 수 있다. 예를 들어, 길이, 폭 및 높이의 비는 1∼5:1:0.5∼2일 수 있다. 즉, 폭을 기준으로 길이가 폭보다 1배 내지 5배 정도 클 수 있고, 높이는 폭보다 0.5배 내지 2배일 수 있다. 그러나, 이러한 X, Y 및 Z 방향의 크기는 하나의 예로서 칩 부품이 연결되는 전자기기의 내부 구조, 칩 부품의 형상, 칩 부품의 기능 등에 따라 다양하게 변형 가능하다. 이러한 적층체(1000)는 소정 크기를 갖는 대략 판 형상의 시트가 복수 적층되어 형성될 수 있다. 즉, 시트는 X 방향 및 Y 방향으로 소정의 길이 및 폭을 갖고, Z 방향으로 소정의 두께를 갖는 대략 사각형의 판 형상으로 마련될 수 있다. 이러한 시트가 복수 적층되어 대략 육면체의 적층체(1000)를 형성할 수 있다. 적층체(1000)를 이루는 복수의 시트는 예를 들어 MLCC 등의 유전체 재료 분말, BaTiO3, BaCO3, TiO2, Nd2O3, Bi2O3, Zn0, Al2O3 중의 하나 이상을 포함하는 물질로 형성될 수 있다. 따라서, 시트는 재질에 따라 각각 소정의 유전율, 예를 들어 5∼20000, 바람직하게는 7∼5000, 더욱 바람직하게는 200∼3000의 유전율을 가질 수 있다. 또한, 복수의 시트는 배리스터 물질로 이루어질 수도 있는데, 예를 들어 ZnO 분말에 Bi2O3, Pr6O11, CoO, MnO 등의 첨가제를 첨가하여 시트를 형성할 수도 있다. 그리고, 복수의 시트는 비자성 시트일 수도 있고, 자성 시트일 수도 있다. 즉, 상기한 바와 같은 물질로 형성되어 소정의 유전율을 가지는 비자성 시트일 수 있고, 자성 물질이 더 포함된 자성 시트일 수 있다. 물론, 복수의 시트는 칩 부품의 용도에 맞게 적어도 하나가 자성 시트 또는 비자성 시트로 형성될 수 있다. 그리고, 복수의 시트는 금속 분말과 폴리머의 혼합물로 형성될 수도 있다. 상기한 바와 같이 복수의 시트는 칩 부품의 용도 등에 따라 다양한 물질로 형성될 수 있다. 또한, 복수의 시트는 모두 동일 두께로 형성될 수 있고, 적어도 어느 하나가 다른 것들에 비해 두껍거나 얇게 형성될 수 있다. The laminate 1000 has a predetermined length and width, respectively, in one direction (for example, the X direction) and the other direction (for example, the Y direction) orthogonal thereto, and in the vertical direction (for example, the Z direction). It may be provided in a substantially hexahedral shape having a height of. That is, when the forming direction of the external electrode 3000 is the X direction, that is, the length, the direction orthogonal to the horizontal direction may be the Y direction, and the vertical direction may be the Z direction, that is, the thickness. Here, the length in the X direction may be greater than or equal to, for example, the width in the Y direction and the height in the Z direction, and the width in the Y direction may be the same as or different from the height in the Z direction. If the width (Y direction) and the height (Z direction) are different, the width may be larger or smaller than the height. For example, the ratio of length, width and height may be 1-5: 1: 0.5-2. That is, the length may be about 1 to 5 times greater than the width, and the height may be 0.5 to 2 times greater than the width. However, the size of the X, Y and Z directions can be variously modified according to the internal structure of the electronic device to which the chip component is connected, the shape of the chip component, the function of the chip component, and the like. The laminate 1000 may be formed by stacking a plurality of substantially plate-shaped sheets having a predetermined size. That is, the sheet may be provided in a substantially rectangular plate shape having a predetermined length and width in the X and Y directions and having a predetermined thickness in the Z direction. A plurality of such sheets may be stacked to form a substantially hexahedral stack 1000. The plurality of sheets constituting the laminate 1000 may include at least one of dielectric material powder such as MLCC, BaTiO 3 , BaCO 3 , TiO 2 , Nd 2 O 3 , Bi 2 O 3 , Zn0, and Al 2 O 3 . It may be formed of a material containing. Accordingly, the sheets may each have a predetermined dielectric constant, for example, 5 to 20000, preferably 7 to 5000, and more preferably 200 to 3000. In addition, the plurality of sheets may be made of a varistor material. For example, the sheet may be formed by adding additives such as Bi 2 O 3 , Pr 6 O 11 , CoO, MnO, and the like to the ZnO powder. The plurality of sheets may be nonmagnetic sheets or magnetic sheets. That is, it may be a nonmagnetic sheet formed of a material as described above and having a predetermined dielectric constant, or may be a magnetic sheet further comprising a magnetic material. Of course, at least one of the plurality of sheets may be formed of a magnetic sheet or a nonmagnetic sheet according to the use of the chip component. In addition, the plurality of sheets may be formed of a mixture of metal powder and polymer. As described above, the plurality of sheets may be formed of various materials according to the purpose of the chip component. In addition, the plurality of sheets may all be formed with the same thickness, and at least one may be formed thicker or thinner than the others.
한편, 적층체(1000) 내의 복수의 시트에는 다양한 구조가 형성될 수 있다. 즉, 적층체(1000) 내에는 다양한 형태의 도전 패턴이 형성될 수 있고, ESD 보호 물질 등이 형성될 수 있다. 다시 말하면, 적층체(1000) 내에는 적층체(1000)를 이루는 시트와는 다른 성분을 갖는 이종의 물질층이 적어도 하나 이상 형성될 수 있다. 예를 들어, 적층체(1000) 내의 복수의 시트에는 스파이럴 형태의 코일 패턴, 전도성 물질이 매립된 홀이 선택적으로 형성될 수 있고, 그에 따라 인덕터 또는 노이즈 필터가 구현될 수 있다. 또한, 적층체(1000)에는 배리스터, ESD 보호부 등의 고전압을 방호하기 위한 구조가 구현될 수 있다. 또한, 적층체(1000) 내의 복수의 시트에는 외부 전극(3000)과 각각 교대로 연결되도록 복수의 내부 전극이 형성될 수 있고, 그에 따라 인접한 두 내부 전극과 그 사이의 시트에 의한 캐패시터가 형성될 수 있다. 그리고, 적층체(1000) 내에는 적어도 일 면에 코일 패턴이 형성된 기판이 마련되고 그 상부에 금속 분말 및 폴리머로 이루어진 시트가 적층되어 파워 인덕터가 형성될 수 있다. 이러한 인덕터, 노이즈 필터, 캐패시터, 파워 인덕터, 배리스터, ESD 보호부는 적층체(1000) 내에 하나 구현될 수도 있고, 적어도 둘 이상이 복합되어 구현될 수도 있다. 한편, 적층체(1000)는 최하층 및 최상층에 형성된 하부 커버층(미도시) 및 상부 커버층(미도시)을 더 포함할 수 있다. 물론, 최하층의 시트가 하부 커버층으로 기능하고 최상층의 시트가 상부 커버층으로 기능할 수도 있다. 하부 및 상부 커버층은 자성체 시트가 복수 적층되어 마련될 수 있으며, 동일 두께로 형성될 수 있다. 여기서, 자성체 시트로 이루어진 하부 및 상부 커버층의 최외곽, 즉 하부 및 상부 표면에 비자성 시트, 예를 들어 유리질의 시트가 더 형성될 수 있다. 또한, 하부 및 상부 커버층은 내부의 시트들보다 두꺼울 수 있다.Meanwhile, various structures may be formed in the plurality of sheets in the laminate 1000. That is, various types of conductive patterns may be formed in the laminate 1000, and an ESD protection material may be formed. In other words, at least one heterogeneous material layer having a different component from the sheet of the laminate 1000 may be formed in the laminate 1000. For example, a spiral coil pattern and a hole filled with a conductive material may be selectively formed in the plurality of sheets in the stack 1000, and thus an inductor or a noise filter may be implemented. In addition, a structure for protecting a high voltage such as a varistor or an ESD protection unit may be implemented in the stack 1000. In addition, a plurality of inner electrodes may be formed on the plurality of sheets in the stack 1000 so as to be alternately connected to the external electrodes 3000, and thus capacitors formed by two adjacent inner electrodes and a sheet therebetween may be formed. Can be. In addition, a substrate having a coil pattern formed on at least one surface may be provided in the stack 1000, and a sheet made of metal powder and a polymer may be stacked thereon to form a power inductor. One of the inductor, the noise filter, the capacitor, the power inductor, the varistor, and the ESD protection unit may be implemented in the stack 1000, or at least two or more of them may be implemented in combination. The laminate 1000 may further include a lower cover layer (not shown) and an upper cover layer (not shown) formed on the lowermost layer and the uppermost layer. Of course, the lowermost sheet may serve as the lower cover layer and the uppermost sheet may serve as the upper cover layer. The lower and upper cover layers may be provided by stacking a plurality of magnetic sheets, and may have the same thickness. Here, a nonmagnetic sheet, for example, a glass sheet, may be further formed on the outermost portion of the lower and upper cover layers formed of the magnetic sheet, that is, the lower and upper surfaces. In addition, the lower and upper cover layers may be thicker than the sheets therein.
표면 개질 부재Surface modification
표면 개질 부재(2000)는 적층체(1000)의 적어도 일 표면에 형성될 수 있다. 이러한 표면 개질 부재(2000)는 외부 전극(3000)을 형성하기 이전에 적층체(1000)의 표면에 예를 들어 산화물을 분포시켜 형성할 수 있다. 여기서, 산화물은 결정 상태 또는 비결정 상태로 적층체(1000)의 표면에 분산되어 분포될 수 있다. 표면 개질 부재(2000)는 도금 공정으로 외부 전극(3000)을 형성할 때 도금 공정 이전에 적층체(1000) 표면에 분포될 수 있다. 즉, 표면 개질 부재(2000)는 외부 전극(3000)의 일부를 인쇄 공정으로 형성하기 이전에 분포시킬 수도 있고, 인쇄 공정 후 도금 공정을 실시하기 이전에 분포시킬 수도 있다. 물론, 인쇄 공정을 실시하지 않는 경우 표면 개질 부재(2000)를 분포시킨 후 도금 공정을 실시할 수 있다. 이때, 표면에 분포된 표면 개질 부재(2000)는 적어도 일부가 용융될 수 있다.The surface modification member 2000 may be formed on at least one surface of the laminate 1000. The surface modification member 2000 may be formed by, for example, distributing an oxide on the surface of the laminate 1000 before forming the external electrode 3000. Here, the oxide may be dispersed and distributed on the surface of the laminate 1000 in a crystalline state or an amorphous state. The surface modification member 2000 may be distributed on the surface of the stack 1000 before the plating process when the external electrode 3000 is formed by the plating process. That is, the surface modification member 2000 may be distributed before forming a part of the external electrode 3000 in the printing process, or may be distributed before the plating process after the printing process. Of course, when the printing process is not performed, the plating process may be performed after the surface modification member 2000 is distributed. In this case, at least a portion of the surface modification member 2000 distributed on the surface may be melted.
한편, 표면 개질 부재(2000)는 도 2의 (a)에 도시된 바와 같이 적어도 일부가 동일한 크기로 적층체(1000)의 표면에 고르게 분포될 수 있고, 도 2의 (b)에 도시된 바와 같이 적어도 일부가 서로 다른 크기로 불규칙하게 분포될 수도 있다. 또한, 도 2의 (c)에 도시된 바와 같이 적층체(1000)의 적어도 일부 표면에는 오목부가 형성될 수도 있다. 즉, 표면 개질 부재(2000)가 형성되어 볼록부가 형성되고 표면 개질 부재(2000)가 형성되지 않은 영역의 적어도 일부가 패여 오목부가 형성될 수도 있다. 이때, 표면 개질 부재(2000)는 적어도 일부가 적층체(1000)의 표면보다 깊이 형성될 수 있다. 즉, 표면 개질 부재(2000)는 소정 두께가 적층체(1000)의 소정 깊이로 박히고 나머지 두께가 적층체(1000)의 표면보다 높게 형성될 수 있다. 이때, 적층체(1000)에 박히는 두께는 산화물 입자의 평균 직경의 1/20 내지 1일 수 있다. 즉, 산화물 입자는 도 2(d)에 도시된 바와 같이 적층체(1000) 내부로 모두 함입될 수 있고, 적어도 일부가 함입될 수 있다. 물론, 산화물 입자는 도 2(d)에 도시된 바와 같이 적층체(1000)의 표면에만 형성될 수 있다. 따라서, 산화물 입자는 적층체(1000)의 표면에서 반구형으로 형성될 수도 있고, 구 형태로 형성될 수도 있다. 또한, 표면 개질 부재(2000)는 상기한 바와 같이 적층체(1000)의 표면에 부분적으로 분포될 수도 있으며, 적어도 일 영역에 막 형태로 분포될 수도 있다. 즉, 도 2(a) 내지 도 2(d)에 도시된 바와 같이 산화물 입자가 적층체(1000)의 표면에 섬(island) 형태로 분포되어 표면 개질 부재(2000)가 형성될 수 있다. 즉, 적층체(1000) 표면에 결정 상태 또는 비결정 상태의 산화물이 서로 이격되어 섬 형태로 분포될 수 있고, 그에 따라 적층체(1000) 표면의 적어도 일부가 노출될 수 있다. 또한, 산화물은 도 2(e)에 도시된 바와 같이 표면 개질 부재(2000)는 적어도 둘 이상이 연결되어 적어도 일 영역에는 막으로 형성되고, 적어도 일부에는 섬 형태로 형성될 수 있다. 즉, 적어도 둘 이상의 산화물 입자가 응집되거나 인접한 산화물 입자가 연결되어 막 형태를 이룰 수 있다. 그러나, 산화물이 입자 상태로 존재하거나, 둘 이상의 입자가 응집되거나 연결된 경우에도 적층체(1000) 표면의 적어도 일부는 표면 개질 부재(2000)에 의해 외부로 노출된다. Meanwhile, the surface modification member 2000 may be evenly distributed on the surface of the stack 1000 with at least a portion having the same size as shown in FIG. 2A, and as shown in FIG. 2B. Likewise, at least some may be irregularly distributed in different sizes. In addition, as shown in FIG. 2C, a recess may be formed on at least part of the surface of the laminate 1000. That is, the surface modification member 2000 may be formed to form a convex portion, and at least a portion of the region where the surface modification member 2000 is not formed may be recessed to form a recess. In this case, at least a portion of the surface modification member 2000 may be formed deeper than the surface of the laminate 1000. That is, the surface modification member 2000 may be formed with a predetermined thickness to be embedded at a predetermined depth of the laminate 1000 and the remaining thickness higher than the surface of the laminate 1000. In this case, the thickness of the laminate 1000 may be 1/20 to 1 of the average diameter of the oxide particles. That is, the oxide particles may be all embedded in the stack 1000 as illustrated in FIG. 2D, and at least some may be embedded. Of course, the oxide particles may be formed only on the surface of the laminate 1000 as shown in FIG. Therefore, the oxide particles may be formed in a hemispherical shape on the surface of the laminate 1000, or may be formed in a spherical shape. In addition, the surface modification member 2000 may be partially distributed on the surface of the laminate 1000 as described above, or may be distributed in a film form on at least one region. That is, as illustrated in FIGS. 2A to 2D, the oxide particles may be distributed in the form of islands on the surface of the laminate 1000 to form the surface modification member 2000. That is, oxides in a crystalline state or an amorphous state may be distributed in an island form on the surface of the laminate 1000, and thus at least a portion of the surface of the laminate 1000 may be exposed. In addition, as illustrated in FIG. 2E, at least two or more surface modification members 2000 may be connected to each other to form an oxide, and at least a portion of the oxide may be formed in an island shape. That is, at least two or more oxide particles may be aggregated or adjacent oxide particles may be connected to form a film. However, even when the oxide is present in the form of particles or when two or more particles are aggregated or connected, at least a part of the surface of the laminate 1000 is exposed to the outside by the surface modifying member 2000.
이때, 표면 개질 부재(2000)의 총 면적은 적층체(1000) 표면 전체 면적의 예를 들어 5% 내지 90%일 수 있다. 표면 개질 부재(2000)의 면적에 따라 적층체(1000) 표면의 도금 번짐 현상이 제어될 수 있지만, 표면 개질 부재(2000)가 너무 많이 형성되면 적층체(1000) 내부의 도전 패턴과 외부 전극(3000)의 접촉이 어려울 수 있다. 즉, 표면 개질 부재(2000)가 적층체(1000) 표면적의 5% 미만으로 형성될 경우 도금 번짐 현상의 제어가 어렵고, 90%를 초과하여 형성될 경우 적층체(1000) 내부의 도전 패턴과 외부 전극(3000)이 접촉되지 않을 수 있다. 따라서, 표면 개질 부재(2000)는 도금 번짐 현상을 제어할 수 있고 적층체(1000) 내부의 도전 패턴과 외부 전극(3000)의 접촉될 수 있는 정도의 면적으로 형성하는 것이 바람직하다. 이를 위해 표면 개질 부재(2000)는 적층체(1000) 표면적의 10% 내지 90%로 형성될 수 있고, 바람직하게는 30% 내지 70%의 면적으로 형성될 수 있으며, 더욱 바람직하게는 40% 내지 50%의 면적으로 형성될 수 있다. 이때, 적층체(1000)의 표면적은 일 면의 표면적일 수도 있고, 육면체를 이루는 적층체(1000)의 여섯면의 표면적일 수도 있다. 한편, 표면 개질 부재(2000)는 적층체(1000) 두께의 10% 이하의 두께로 형성될 수 있다. 즉, 표면 개질 부재(2000)는 적층체(1000) 두께의 0.01% 내지 10%의 두께로 형성될 수 있다. 예를 들어, 표면 개질 부재(2000)는 0.1㎛∼50㎛의 크기로 존재할 수 있는데, 그에 따라 표면 개질 부재(2000)는 적층체(1000) 표면으로부터 0.1㎛∼50㎛의 두께로 형성될 수 있다. 즉, 표면 개질 부재(2000)는 적층체(1000)의 표면보다 박힌 영역을 제외하고 적층체(1000) 표면으로부터 0.1㎛∼50㎛의 두께로 형성될 수 있다. 따라서, 적층체(1000) 내측으로 박힌 두께를 포함하면 표면 개질 부재(2000)는 0.1㎛∼50㎛보다 두꺼운 두께를 가질 수 있다. 표면 개질 부재(2000)가 적층체(1000) 두께의 0.01% 미만의 두께로 형성될 경우 도금 번짐 현상의 제어가 어렵고, 적층체(1000) 두께의 10%를 초과하는 두께로 형성될 경우 적층체(1000) 내부의 도전 패턴과 외부 전극(3000)이 접촉되지 않을 수 있다. 즉, 표면 개질 부재(2000)는 적층체(1000)의 재료 특성(전도성, 반도성, 절연성, 자성체 등)에 따라 다양한 두께를 가질 수 있고, 산화물 분말의 크기, 분포량, 응집 여부에 따라 다양한 두께를 가질 수 있다.In this case, the total area of the surface modification member 2000 may be, for example, 5% to 90% of the total area of the surface of the laminate 1000. Plating bleeding of the surface of the laminate 1000 may be controlled according to the area of the surface modifying member 2000. However, when too much surface modifying member 2000 is formed, the conductive pattern and the external electrode (the inside of the laminate 1000) may be controlled. 3000) can be difficult to contact. That is, when the surface modification member 2000 is formed to be less than 5% of the surface area of the laminate 1000, it is difficult to control the plating bleeding phenomenon. The electrode 3000 may not be in contact. Therefore, the surface modification member 2000 may control the plating bleeding phenomenon and may be formed in an area that can be in contact with the conductive pattern inside the laminate 1000 and the external electrode 3000. To this end, the surface modification member 2000 may be formed of 10% to 90% of the surface area of the laminate 1000, preferably 30% to 70% of the surface area, more preferably 40% to It can be formed with an area of 50%. In this case, the surface area of the laminate 1000 may be one surface area, or may be the six surface areas of the laminate 1000 forming a hexahedron. Meanwhile, the surface modification member 2000 may be formed to a thickness of 10% or less of the thickness of the laminate 1000. That is, the surface modification member 2000 may be formed to a thickness of 0.01% to 10% of the thickness of the laminate 1000. For example, the surface modification member 2000 may be present in a size of 0.1 μm to 50 μm, and thus the surface modification member 2000 may be formed to a thickness of 0.1 μm to 50 μm from the surface of the laminate 1000. have. That is, the surface modification member 2000 may be formed to have a thickness of 0.1 μm to 50 μm from the surface of the laminate 1000 except for a region that is less than the surface of the laminate 1000. Therefore, when the thickness of the laminated body 1000 is embedded, the surface modification member 2000 may have a thickness greater than 0.1 μm to 50 μm. When the surface modification member 2000 is formed to a thickness less than 0.01% of the thickness of the laminate 1000, it is difficult to control the plating bleeding phenomenon, and when the surface modified member 2000 is formed to a thickness exceeding 10% of the thickness of the laminate 1000, the laminate The conductive pattern inside the 1000 and the external electrode 3000 may not contact each other. That is, the surface modification member 2000 may have various thicknesses according to the material properties (conductivity, semiconductivity, insulation, magnetic material, etc.) of the laminate 1000, and various thicknesses depending on the size, distribution amount, and aggregation of the oxide powder. It can have
이렇게 적층체(1000)의 표면에 표면 개질 부재(2000)가 형성됨으로써 적층체(1000)의 표면은 성분이 다른 적어도 두 영역이 존재할 수 있다. 즉, 표면 개질 부재(2000)가 형성된 영역과 형성되지 않은 영역은 서로 다른 성분이 검출될 수 있다. 예를 들어, 표면 개질 부재(2000)가 형성된 영역은 표면 개질 부재(2000)에 따른 성분, 즉 산화물이 존재할 수 있고, 형성되지 않은 영역은 적층체(1000)에 따른 성분, 즉 시트의 성분이 존재할 수 있다. 이렇게 도금 공정 이전에 적층체(1000)의 표면에 표면 개질 부재(2000)를 분포시킴으로써 적층체(1000) 표면에 거칠기를 부여하여 개질시킬 수 있다. 따라서, 도금 공정이 균일하게 실시될 수 있고, 그에 따라 외부 전극(3000)의 형상을 제어할 수 있다. 즉, 적층체(1000)의 표면은 적어도 일 영역의 저항이 다른 영역의 저항과 다를 수 있는데, 저항이 불균일한 상태에서 도금 공정을 실시하면 도금층의 성장 불균일이 발생된다. 이러한 문제를 해결하기 위해 적층체(1000)의 표면에 입자 상태 또는 용융 상태의 산화물을 분산시켜 표면 개질 부재(2000)를 형성함으로써 적층체(1000)의 표면을 개질시킬 수 있고, 도금층의 성장을 제어할 수 있다. As such, the surface modification member 2000 is formed on the surface of the stack 1000, and thus, the surface of the stack 1000 may include at least two regions having different components. That is, different components may be detected in the region where the surface modification member 2000 is formed and the region where the surface modification member 2000 is not formed. For example, the region in which the surface modification member 2000 is formed may have a component according to the surface modification member 2000, that is, an oxide, and the region in which the surface modification member 2000 is not formed may be a component according to the laminate 1000, that is, a component of the sheet. May exist. Thus, by distributing the surface modification member 2000 on the surface of the laminate 1000 before the plating process, the surface of the laminate 1000 may be provided with a roughness to be modified. Therefore, the plating process can be performed uniformly, and thus the shape of the external electrode 3000 can be controlled. That is, the surface of the laminate 1000 may have a resistance of at least one region different from that of another region. If the plating process is performed in a state where the resistance is uneven, growth unevenness of the plating layer may occur. In order to solve this problem, the surface of the laminate 1000 may be modified by dispersing oxides in a particulate state or a molten state on the surface of the laminate 1000 to form a surface modification member 2000, thereby increasing the growth of the plating layer. Can be controlled.
여기서, 적층체(1000)의 표면 저항을 균일하게 하기 위한 입자 상태 또는 용융 상태의 산화물은 예를 들어 Bi2O3, BO2, B2O3, ZnO, Co3O4, SiO2, Al2O3, MnO, H2BO3, Ca(CO3)2, Ca(NO3)2, CaCO3 중 적어도 하나 이상을 이용할 수 있다. 한편, 표면 개질 부재(2000)는 적층체(1000) 내의 적어도 하나의 시트 상에도 형성될 수 있다. 즉, 시트 상의 다양한 형상의 도전 패턴은 도금 공정으로 형성할 수도 있는데, 표면 개질 부재(2000)를 형성함으로써 도전 패턴의 형상을 제어할 수 있다.Here, the oxide in the particulate state or in the molten state to make the surface resistance of the laminate 1000 uniform is, for example, Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al At least one of 2 O 3 , MnO, H 2 BO 3 , Ca (CO 3 ) 2 , Ca (NO 3 ) 2 , and CaCO 3 may be used. Meanwhile, the surface modification member 2000 may also be formed on at least one sheet in the laminate 1000. That is, the conductive patterns of various shapes on the sheet may be formed by a plating process, and the shape of the conductive patterns may be controlled by forming the surface modification member 2000.
외부 전극External electrode
외부 전극(3100, 3200; 3000)는 적층체(1000)의 서로 대향되는 두 측면에 마련되어 적층체(1000) 내부에 형성된 도전 패턴과 선택적으로 연결된다. 즉, 외부 전극(3000)은 서로 대향되는 두 측면, 예를 들어 제 1 및 제 2 측면에 각각 하나씩 형성될 수도 있고, 도 1에 도시된 바와 같이 두개 이상씩 형성될 수도 있다. 또한, 제 1 및 제 2 측면과 직교하는 제 3 및 제 4 측면의 적어도 하나에 적어도 하나의 외부 전극이 더 형성될 수도 있다. 이러한 외부 전극(3000)은 적어도 하나의 층으로 형성될 수 있다. 외부 전극(3000)은 Ag 등의 금속층으로 형성될 수 있고, 금속층 상에 적어도 하나의 도금층이 형성될 수도 있다. 예를 들어, 외부 전극(3000)은 구리층, Ni 도금층 및 Sn 또는 Sn/Ag 도금층이 적층 형성될 수도 있다. 또한, 외부 전극(3000)은 예를 들어 0.5%∼20%의 Bi2O3 또는 SiO2를 주성분으로 하는 다성분계의 글래스 프릿(Glass frit)을 금속 분말과 혼합하여 형성할 수 있다. 이때, 글래스 프릿과 금속 분말의 혼합물은 페이스트 형태로 제조되어 적층체(1000)의 두면에 도포될 수 있다. 이렇게 외부 전극(3000)에 글래스 프릿이 포함됨으로써 외부 전극(3000)과 적층체(1000)의 밀착력을 향상시킬 수 있고, 적층체(1000) 내부의 도전 패턴과 외부 전극(3000)의 콘택 반응을 향상시킬 수 있다. 또한, 글래스가 포함된 도전성 페이스트가 도포된 후 그 상부에 적어도 하나의 도금층이 형성되어 외부 전극(3000)이 형성될 수 있다. 즉, 글래스가 포함된 금속층과, 그 상부에 적어도 하나의 도금층이 형성되어 외부 전극(3000)이 형성될 수 있다. 예를 들어, 외부 전극(3000)은 글래스 프릿과 Ag 및 Cu의 적어도 하나가 포함된 층을 형성한 후 전해 또는 무전해 도금을 통하여 Ni 도금층 및 Sn 도금층 순차적으로 형성할 수 있다. 이때, Sn 도금층은 Ni 도금층과 같거나 두꺼운 두께로 형성될 수 있다. 물론, 외부 전극(3000)은 적어도 하나의 도금층만으로 형성될 수도 있다. 즉, 페이스트를 도포하지 않고 적어도 1회의 도금 공정을 이용하여 적어도 일층의 도금층을 형성하여 외부 전극(3000)을 형성할 수도 있다. 한편, 외부 전극(3000)은 2㎛∼100㎛의 두께로 형성될 수 있으며, Ni 도금층이 1㎛∼10㎛의 두께로 형성되고, Sn 또는 Sn/Ag 도금층은 2㎛∼10㎛의 두께로 형성될 수 있다.The external electrodes 3100, 3200; 3000 are provided on two opposite sides of the stack 1000 to be selectively connected to a conductive pattern formed in the stack 1000. That is, one external electrode 3000 may be formed on each of two side surfaces facing each other, for example, the first and second sides, or two or more external electrodes may be formed as shown in FIG. 1. In addition, at least one external electrode may be further formed on at least one of the third and fourth sides orthogonal to the first and second sides. The external electrode 3000 may be formed of at least one layer. The external electrode 3000 may be formed of a metal layer such as Ag, and at least one plating layer may be formed on the metal layer. For example, the external electrode 3000 may be formed by stacking a copper layer, a Ni plating layer, and a Sn or Sn / Ag plating layer. In addition, the external electrode 3000 may be formed by mixing, for example, glass frit having a multi-component glass frit containing 0.5% to 20% of Bi 2 O 3 or SiO 2 as a main component. In this case, the mixture of the glass frit and the metal powder may be prepared in a paste form and applied to two surfaces of the laminate 1000. As the glass frit is included in the external electrode 3000, the adhesion between the external electrode 3000 and the laminate 1000 may be improved, and the contact reaction between the conductive pattern inside the laminate 1000 and the external electrode 3000 may be improved. Can be improved. In addition, after the conductive paste including glass is applied, at least one plating layer may be formed on the upper portion thereof, thereby forming the external electrode 3000. That is, the metal layer including the glass and at least one plating layer formed thereon may be formed to form the external electrode 3000. For example, the external electrode 3000 may sequentially form a Ni plating layer and a Sn plating layer through electrolytic or electroless plating after forming a layer including glass frit and Ag and Cu. In this case, the Sn plating layer may be formed to the same or thicker thickness than the Ni plating layer. Of course, the external electrode 3000 may be formed of only at least one plating layer. That is, the external electrode 3000 may be formed by forming at least one layer of the plating layer using at least one plating process without applying the paste. Meanwhile, the external electrode 3000 may be formed to have a thickness of 2 μm to 100 μm, the Ni plating layer may be formed to have a thickness of 1 μm to 10 μm, and the Sn or Sn / Ag plating layer may have a thickness of 2 μm to 10 μm. Can be formed.
적층체 내부의 구조 예Example of the structure inside the laminate
한편, 적층체(1000) 내의 일 실시 예에 따른 구조가 도 3 내지 도 5에 도시되어 있다. 도 3 내지 도 5는 본 발명의 일 실시 예에 따른 적층체(1000)의 분해 사시도로서, 스파이럴 형상의 코일 패턴을 포함하는 노이즈 필터의 분해 사시도이다. 상기한 바와 같이 적층체(1000)는 내부에 캐패시터, 배리스터, 인덕터, 파워 인덕터 등 다양한 칩 부품이 구현될 수 있는데, 하기 실시 예는 공통 모드 노이즈 필터의 예를 설명한다.Meanwhile, a structure according to one embodiment in the stack 1000 is illustrated in FIGS. 3 to 5. 3 to 5 are exploded perspective views of the laminate 1000 according to an exemplary embodiment, and are exploded perspective views of a noise filter including a spiral coil pattern. As described above, the stack 1000 may include various chip components such as a capacitor, a varistor, an inductor, and a power inductor. The following embodiment describes an example of a common mode noise filter.
도 3을 참조하면, 적층체(1000)는 복수의 시트(110 내지 150)가 적층되고, 선택된 적어도 하나의 시트(120 내지 150) 상에 적어도 하나의 코일 패턴(310 내지 340)이 각각 형성될 수 있다. 또한, 코일 패턴(310 내지 340)이 복수 형성되는 경우 적어도 두 코일 패턴(310 내지 340)이 전도성 물질이 매립된 홀(351, 352, 361, 362)을 통해 수직 방향으로 연결될 수 있다. 예를 들어, 제 1 코일 패턴(310)은 전도성 물질이 매립된 홀들(351, 352)를 통해 제 3 코일 패턴(330)과 연결될 수 있고, 제 2 코일 패턴(320)은 전도성 물질이 매립된 홀들(361, 362)을 통해 제 4 코일 패턴(340)과 연결될 수 있다. 그리고, 각 코일 패턴(310 내지 340)으로부터 외측으로 인출되는 인출 전극(410 내지 440)이 형성되어 외부 전극과 연결될 수 있다. 한편, 최상측 시트(110)의 상부 및 최하측 시트(150)의 하부에는 각각 상부 커버층(1100) 및 하부 커버층(1200)이 형성될 수 있다. 상부 및 하부 커버층(1100, 1200)은 시트(110 내지 150) 각각의 두께보다 두껍게 형성될 수 있다.Referring to FIG. 3, in the stack 1000, a plurality of sheets 110 to 150 may be stacked, and at least one coil pattern 310 to 340 may be formed on at least one selected sheet 120 to 150, respectively. Can be. In addition, when a plurality of coil patterns 310 to 340 are formed, at least two coil patterns 310 to 340 may be connected in a vertical direction through holes 351, 352, 361, and 362 in which conductive materials are embedded. For example, the first coil pattern 310 may be connected to the third coil pattern 330 through holes 351 and 352 in which the conductive material is embedded, and the second coil pattern 320 may be filled with the conductive material. It may be connected to the fourth coil pattern 340 through the holes 361 and 362. In addition, lead electrodes 410 to 440 drawn outward from each coil pattern 310 to 340 may be formed to be connected to the external electrode. Meanwhile, an upper cover layer 1100 and a lower cover layer 1200 may be formed at an upper portion of the uppermost sheet 110 and a lower portion of the lowermost sheet 150, respectively. The upper and lower cover layers 1100 and 1200 may be formed thicker than the thickness of each of the sheets 110 to 150.
도 4에 도시된 바와 같이, 적층체(1000) 내에는 ESD 보호부가 더 형성될 수 있다. 즉, 공통 모드 노이즈 필터와 ESD 보호부가 적층되어 복합 소자를 이룰 수 있다. 이러한 적층체(1000)는 복수의 시트(110 내지 180)와, 선택된 적어도 하나 이상의 시트(120 내지 150) 상에 각각 형성된 코일 패턴(310 내지 340)과, 코일 패턴(310 내지 340)을 각각 연결시키기 위해 전도성 물질이 매립되어 형성된 홀(351, 352, 361, 362)과, 코일 패턴(310 내지 340)로부터 인출되어 외부 전극과 연결되는 인출 전극(410 내지 440)과, 선택된 시트(170) 상에 형성된 복수의 제 1 방전 전극(511, 512, 513, 514)과, 제 1 방전 전극(511 내지 514)의 말단에 형성된 홀 내에 매립된 ESD 보호층(531, 532, 533, 534)과, 선택된 시트(180) 상에 형성되어 ESD 보호층(531 내지 534)와 연결되는 제 2 방전 전극(520)을 포함할 수 있다. 이때, 제 1 방전 전극(511 내지 514)은 복수의 인출 전극(410 내지 440)과 함께 외부 전극과 연결되고, 제 2 방전 전극(520)은 별도의 외부 전극과 연결된다. 한편, 공통 모드 노이즈 필터부와 ESD 보호부를 분리하기 위해 이들 사이에 시트(160)가 마련될 수 있다.As shown in FIG. 4, an ESD protection unit may be further formed in the stack 1000. That is, the common mode noise filter and the ESD protection unit may be stacked to form a composite device. The laminate 1000 connects the plurality of sheets 110 to 180, the coil patterns 310 to 340 and the coil patterns 310 to 340 respectively formed on the selected at least one sheet 120 to 150, respectively. Holes 351, 352, 361, and 362 formed by filling a conductive material, the lead electrodes 410 through 440 drawn out from the coil patterns 310 through 340, and connected to external electrodes, and the selected sheet 170. A plurality of first discharge electrodes 511, 512, 513, and 514 formed in the plurality of electrodes; an ESD protection layer 531, 532, 533, and 534 embedded in holes formed at ends of the first discharge electrodes 511 to 514; The second discharge electrode 520 may be formed on the selected sheet 180 to be connected to the ESD protection layers 531 to 534. In this case, the first discharge electrodes 511 to 514 are connected to an external electrode together with the plurality of lead electrodes 410 to 440, and the second discharge electrode 520 is connected to a separate external electrode. Meanwhile, a sheet 160 may be provided therebetween to separate the common mode noise filter unit and the ESD protection unit.
도 5에 도시된 바와 같이, 적층체(1000) 내에는 적어도 하나의 캐패시터 전극(610)이 더 형성될 수 있다. 즉, 캐패시터 전극(610)은 두 코일 패턴(320, 330) 사이에 시트(190)가 마련되고, 시트(190) 상에 형성될 수 있고, 캐패시터 전극(610)으로부터 외측으로 인출되는 인출 전극(610)이 형성될 수 있다. 또한, 시트(190)에는 전도성 물질이 매립된 홀(353, 363)이 형성되어 상하 코일 패턴을 연결시킬 수 있다. 캐패시터 전극(610)과 그 상측 및 하측의 코일 패턴(320, 330) 사이에는 시트(130, 190)를 사이에 두고 소정의 정전용량을 갖는 캐패시터가 형성될 수 있다.As shown in FIG. 5, at least one capacitor electrode 610 may be further formed in the stack 1000. That is, the capacitor electrode 610 may be provided with a sheet 190 between the two coil patterns 320 and 330, may be formed on the sheet 190, and may be drawn out from the capacitor electrode 610. 610 may be formed. In addition, holes 190 and 363 in which the conductive material is embedded may be formed in the sheet 190 to connect the upper and lower coil patterns. Capacitors having a predetermined capacitance may be formed between the capacitor electrodes 610 and upper and lower coil patterns 320 and 330 with the sheets 130 and 190 interposed therebetween.
상기한 바와 같이 본 발명의 일 실시 예에 따른 칩 부품은 적층체(1000)의 표면에 표면 개질 부재(2000)를 형성함으로써 외부 전극(3000)의 형상을 제어할 수 있다. 즉, 적층체(1000)의 표면에 표면 개질 부재(2000)를 형성하여 적층체(1000)의 표면을 개질함으로써 도금으로 형성되는 외부 전극(3000)의 번짐 및 퍼짐 현상을 방지할 수 있고, 그에 따라 외부 전극(3000)의 형상을 용이하게 제어할 수 있다. 또한, 본 발명은 적층체(1000)의 표면에 적층체(1000)와는 다른 성분의 표면 개질 부재(2000)를 형성함으로써 적층체(1000)로의 수분 침투를 방지할 수 있고, 그에 따라 칩 부품의 수명 및 신뢰성을 향상시킬 수 있다. 내습성은 고온다습한 환경에서 칩 부품을 소정 시간 유지시킨 후 누설 전류를 측정함으로써 확인할 수 있다. As described above, the chip component according to the exemplary embodiment may control the shape of the external electrode 3000 by forming the surface modification member 2000 on the surface of the laminate 1000. That is, by forming the surface modification member 2000 on the surface of the laminate 1000 to modify the surface of the laminate 1000, the spreading and spreading of the external electrode 3000 formed by plating may be prevented, Accordingly, the shape of the external electrode 3000 can be easily controlled. In addition, the present invention can form a surface modification member 2000 having a different component from that of the laminate 1000 on the surface of the laminate 1000, thereby preventing the penetration of moisture into the laminate 1000, thereby preventing the It can improve the service life and reliability. Moisture resistance can be confirmed by measuring a leakage current after maintaining a chip component for a predetermined time in a high temperature and high humidity environment.
칩 부품의 제조 방법Manufacturing method of chip parts
본 발명의 일 실시 예에 따른 칩 부품의 제조 방법을 도 8을 이용하여 설명하면 다음과 같다. 도 6은 본 발명의 일 실시 예에 따른 칩 부품의 제조 방법을 설명하기 위한 공정 순서도이다. Hereinafter, a method of manufacturing a chip component according to an exemplary embodiment of the present invention will be described with reference to FIG. 8. 6 is a flowchart illustrating a method of manufacturing a chip component according to an embodiment of the present disclosure.
먼저, 소정 두께를 갖는 대략 사각 형태의 시트를 복수 마련한다(S110). 이때, 복수의 시트는 칩 부품의 크기보다 클 수 있다. 즉, 복수의 시트 상에 복수의 도전 패턴 등을 형성한 후 칩 부품의 크기로 절단할 수 있다. 또한, 복수의 시트는 소정의 유전율을 갖는 비자성 시트 또는 자성 시트일 수 있다. 즉, 복수의 시트는 적어도 하나가 비자성 시트 또는 자성 시트일 수 있다. 물론, 복수의 시트는 소정의 항복 전압을 갖는 배리스터 물질로 형성될 수도 있다. First, a plurality of substantially rectangular sheets having a predetermined thickness are provided (S110). In this case, the plurality of sheets may be larger than the size of the chip component. That is, after forming a some electrically conductive pattern etc. on a some sheet, it can cut to the magnitude | size of a chip component. In addition, the plurality of sheets may be nonmagnetic sheets or magnetic sheets having a predetermined dielectric constant. That is, at least one of the plurality of sheets may be a nonmagnetic sheet or a magnetic sheet. Of course, the plurality of sheets may be formed of a varistor material having a predetermined breakdown voltage.
이어서, 적어도 하나의 시트 상에 소정 형상의 도전 패턴 등을 형성한다(S120). 이때, 도전 패턴 상에 복수의 절연 패턴을 형성할 수 있다. 도전 패턴은 소정의 면적을 갖는 사각형으로 형성될 수도 있고, 중심 영역에서 외측으로 스파이럴 형태로 형성될 수도 있다. 또한, 도전 패턴은 Ag, Pt, Ni, Sn, Cu 등의 도전 물질을 이용하여 스크린 프린팅 방법으로 형성할 수도 있고, 도금 방법으로 형성할 수도 있다. 이때, 도전 패턴을 도금 방법으로 형성하기 이전에 시트의 적어도 일면 상에 표면 개질 부재(2000)를 형성할 수 있다. 즉, 도금 형상을 제어하기 위해 시트의 표면에 표면 개질 부재(2000)를 형성하여 시트의 표면을 개질시킬 수 있다. 또한, 적어도 하나의 시트 상에는 ESD 등의 고전압을 차단하기 위한 ESD 보호 부재를 형성할 수 있다. ESD 보호 부재는 수직 또는 수평 방향으로 이격된 두 도전 패턴 사이에 형성될 수 있다. 예를 들어, ESD 보호 부재는 시트를 관통하도록 형성된 공극을 매립하도록 형성될 수도 있고, 시트 상에 이격된 두 도전 패턴 사이에 이들과 일부 중첩되도록 형성될 수도 있다. 또한, ESD 보호 부재는 두 도전 패턴 사이에 마련된 공극일 수도 있다. 즉, 수직 또는 수평 방향으로 이격된 두 도전 패턴 사이에 별도의 물질을 형성하지 않고 이들 사이에 공극을 유지하여 ESD 보호 부재로 이용할 수도 있다. Subsequently, a conductive pattern having a predetermined shape is formed on at least one sheet (S120). In this case, a plurality of insulating patterns may be formed on the conductive pattern. The conductive pattern may be formed in a quadrangle having a predetermined area, or may be formed in a spiral shape from the center area to the outside. In addition, the conductive pattern may be formed by a screen printing method using a conductive material such as Ag, Pt, Ni, Sn, Cu, or may be formed by a plating method. In this case, the surface modification member 2000 may be formed on at least one surface of the sheet before the conductive pattern is formed by the plating method. That is, in order to control the plating shape, the surface modification member 2000 may be formed on the surface of the sheet to modify the surface of the sheet. In addition, an ESD protection member for blocking a high voltage such as an ESD may be formed on the at least one sheet. The ESD protection member may be formed between two conductive patterns spaced apart in the vertical or horizontal direction. For example, the ESD protection member may be formed to fill a gap formed to penetrate the sheet, or may be formed to partially overlap them between two conductive patterns spaced apart on the sheet. In addition, the ESD protection member may be a gap provided between the two conductive patterns. That is, without forming a separate material between the two conductive patterns spaced apart in the vertical or horizontal direction, it may be used as an ESD protection member by maintaining a gap therebetween.
이어서, 도전 패턴 및/또는 ESD 보호 부재가 형성된 복수의 시트를 적층하고 절단 및 소성하여 적층체(1000)를 형성한다(S130). 이에 따라, 복수의 스파이럴 형태의 코일이 형성된 인덕터 또는 공통 모드 노이즈 필터가 형성되거나, 시트를 사이에 두고 두 도전 패턴이 캐패시턴스를 형성하는 캐패시터가 형성될 수 있다. 또한, ESD 보호부가 형성될 수도 있다. 이렇게 복수의 시트를 적층하여 적층체(1000)를 형성함으로써 도전 패턴의 형상, ESD 보호부의 유무, 시트의 재질 등에 따라 다양한 용도의 칩 부품이 형성될 수 있다.Subsequently, a plurality of sheets on which the conductive pattern and / or the ESD protection member are formed are stacked, cut and baked to form the laminate 1000 (S130). Accordingly, an inductor or a common mode noise filter in which a plurality of spiral coils are formed may be formed, or a capacitor may be formed in which two conductive patterns form capacitance between sheets. In addition, an ESD protection unit may be formed. By stacking the plurality of sheets to form the stack 1000, chip components having various uses may be formed according to the shape of the conductive pattern, the presence or absence of an ESD protection unit, the material of the sheet, and the like.
이어서, 적층체(1000)의 표면에 표면 개질 부재(2000)를 형성한다(S140). 표면 개질 부재(2000)는 적층체(1000) 표면에 산화물을 분포시켜 형성할 수 있는데, 예를 들어 Bi2O3, BO2, B2O3, ZnO, Co3O4, SiO2, Al2O3, MnO, H2BO3, Ca(CO3)2, Ca(NO3)2, CaCO3 중 적어도 하나를 이용할 수 있다. 또한, 표면 개질 부재(2000)를 적층체(1000) 표면에 형성하기 위해 상기 산화물과 적층체(1000)를 내부에 소정의 공간이 형성된 통 내에 투입한 후 통을 좌우 방향 및/또는 상하 방향으로 회전시켜 산화물을 적층체(1000) 표면에 분산시킬 수 있다. 즉, 밀링하여 형성할 수 있다. 이때, 통은 대략 원통형으로 이루어질 수 있다. 또한, 이러한 공정을 적어도 1회 실시하여 표면 개질 부재(2000)를 형성할 수 있다. 표면 개질 부재(2000)의 적층체(1000) 표면의 분포량, 크기 및 두께 등은 산화물의 투입량, 적층체(1000)의 투입량, 공정 시간 등에 따라 달라질 수 있다. 즉, 산화물의 투입량 및 공정 시간이 증가할수록 표면 개질 부재(2000)의 분포량, 즉 표면적, 크기 및 두께가 증가할 수 있고, 적층체(1000)의 투입량이 증가할수록 표면 개질 부재(2000)의 분포량, 즉 표면적, 크기 및 두께가 감소할 수 있다. 예를 들어, 적층체(1000)의 수량을 20000∼60000으로 하고 산화물을 2g∼15g 투입함으로써 적층체(1000) 표면에 0㎛∼10㎛ 두께의 산화물을 분포시킬 수 있고, 하나의 적층체(1000) 당 50㎍∼200㎍ 양으로 산화물을 도포시킬 수 있다. 이때, 회전 속도를 예를 들어 50∼100rpm으로 하고, 통의 부피는 500∼1000cc일 수 있다. 또한, 공정 시간은 30분 내지 2시간 일 수 있다. 실시 예로서, 9.92㎟의 표면적을 갖는 60000개의 적층체(1000)를 4g의 산화물과 함께 소정의 통 내에 투입한 후 소정 시간 회전시키면 산화물은 0㎛∼4㎛의 두께로 형성되며, 표면적당 6.7㎍/㎟ 정도 형성되어 칩당 67㎍ 정도의 양으로 산화물이 분포된다. 이때의 표면 사진을 도 7에 도시하였다. 또한, 9.92㎟의 표면적을 갖는 60000개의 적층체(1000)를 8g의 산화물과 함께 소정의 통 내에 투입한 후 소정 시간 회전시키면 산화물은 1㎛∼6㎛의 두께로 형성되며, 표면적당 13.4㎍/㎟ 정도 형성되어 칩당 133㎍ 정도의 양으로 산화물이 분포된다. 이때의 표면 사진을 도 8에 도시하였다. 그리고, 9.92㎟의 표면적을 갖는 60000개의 적층체(1000)를 11g의 산화물과 함께 소정의 통 내에 투입한 후 소정 시간 회전시키면 산화물은 2㎛∼10㎛의 두께로 형성되며, 표면적당 18.5㎍/㎟ 정도 형성되어 칩당 183㎍ 정도의 양으로 산화물이 분포된다. 이때의 표면 사진을 도 9에 도시하였다.Next, the surface modification member 2000 is formed on the surface of the laminate 1000 (S140). The surface modification member 2000 may be formed by dispersing an oxide on the surface of the laminate 1000, for example, Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3, MnO, H 2 BO 3, Ca (CO 3) 2, Ca (NO 3) 2, may be used at least one of CaCO 3. In addition, in order to form the surface modification member 2000 on the surface of the laminate 1000, the oxide and the laminate 1000 are introduced into a cylinder having a predetermined space therein, and the cylinder is then moved in the horizontal direction and / or the vertical direction. By rotating, the oxide may be dispersed on the surface of the laminate 1000. That is, it can form by milling. At this time, the barrel may be formed in a substantially cylindrical. In addition, the surface modification member 2000 may be formed by performing the process at least once. The amount, size, and thickness of the surface of the stack 1000 of the surface modification member 2000 may vary depending on the amount of oxide, the amount of the stack 1000, a process time, and the like. That is, the amount of the oxide and the processing time increases, the distribution amount of the surface modifying member 2000, that is, the surface area, size and thickness may increase, and as the amount of the laminate 1000 increases, the amount of distribution of the surface modifying member 2000 increases. That is, the surface area, size and thickness can be reduced. For example, the quantity of the laminated body 1000 is 20000-60000, and 2g-15g of oxides can be thrown in, and the oxide of 0 micrometer-10 micrometers thickness can be distributed on the surface of the laminated body 1000, and one laminated body ( The oxide may be applied in an amount of 50 μg to 200 μg per 1000). At this time, the rotational speed may be, for example, 50 to 100 rpm, and the volume of the cylinder may be 500 to 1000 cc. In addition, the process time may be 30 minutes to 2 hours. In an embodiment, when 60000 laminates 1000 having a surface area of 9.92 mm 2 are put in a predetermined cylinder together with 4 g of oxide, and then rotated for a predetermined time, the oxide is formed to a thickness of 0 μm to 4 μm, and 6.7 per surface area. About μg / mm 2 is formed to distribute oxides in an amount of about 67 μg per chip. The surface photograph at this time is shown in FIG. Further, when 60000 laminates 1000 having a surface area of 9.92 mm 2 were put in a predetermined cylinder together with 8 g of oxide, and then rotated for a predetermined time, the oxide was formed to a thickness of 1 µm to 6 µm and 13.4 µg / surface area. It is formed in about 2 mm 2 and the oxide is distributed in an amount of about 133 µg per chip. The surface photograph at this time is shown in FIG. Then, when 60000 laminates 1000 having a surface area of 9.92 mm 2 were charged into a predetermined cylinder with 11 g of oxide, and then rotated for a predetermined time, the oxide was formed to a thickness of 2 μm to 10 μm, and 18.5 μg / per surface area. It is formed in about 2 mm 2 and the oxide is distributed in an amount of about 183 μg per chip. The surface photograph at this time is shown in FIG.
한편, 표면 개질 부재(2000)를 형성하기 이전에 적층체(1000) 표면을 산세 공정을 실시할 수도 있다. 산세 공정은 적층체(1000)의 표면을 개질하기 위한 전단계로서 적층체(1000)를 약산 처리하여 적층체(1000)의 표면에 균일한 기공을 형성할 수 있다. 적층체(1000)의 표면에 기공을 형성함으로써 표면 개질 부재(2000)가 적층체(1000)의 형성을 더욱 용이하게 할 수 있다. 또한, 표면 개질 부재(2000) 형성 시 산화물과 함께 복수의 매개물을 더 투입할 수 있는데, 매개물을 투입함으로써 산화물을 균일하게 분포시킬 수 있다. 즉, 매개물이 투입되지 않은 경우 산화물은 불균일하게 분포되면 서로 응집되는 양이 증가할 수 있으나, 매개물이 투입되면 산화물이 균일하게 분포되고 서로 응집되는 양을 줄일 수 있다. 이때, 매개물은 적층체(1000) 및 표면 개질 부재(2000)와 다른 재질을 이용할 수 있는데, 예를 들어 스테인레스 스틸, 세라믹 등을 이용할 수 있다. 또한, 매개물은 구 형태, 육면체 형태 등 다양한 형태를 이용할 수 있다. 이때, 복수의 매개물은 총 부피가 산화물 분말의 총 부피보다 크고 적층체(1000)의 총 부피보다 작은 부피를 이용할 수 있는데, 예를 들어 매개물의 총 부피는 적층체(1000) 총 부피의 10% 내지 90%를 이용할 수 있다. 한편, 매개물의 크기에 따라 적층체(1000)에 분산되는 산화물의 크기 및 간격을 조절할 수 있는데, 매개물의 크기가 클수록 산화물의 크기 및 간격이 커지고, 매개물의 크기가 작을수록 산화물의 크기 및 간격이 작아진다. 즉, 매개물의 부피가 적층체(1000) 부피의 10% 미만일 경우 매개물을 이용하지 않을 때와 동일한 분포 상태를 보이며, 적층체(1000) 부피의 90%를 초과할 경우 산화물이 매개물의 표면에 뭍는 양이 증가하여 적층체(1000) 표면에는 도포되지 않을 수 있다. 도 10의 (a) 및 도 11의 (a)는 매개물을 이용하지 않는 경우의 표면 개질 부재의 분포 형상을 설명하기 위한 개략 단면도 및 평면 사진으로서, 도시된 바와 같이 표면 개질 부재(2000)는 적층체(1000)의 표면에 불규칙하게 분포되고, 응집 또는 연결되는 양이 증가하여 적어도 일 영역에서 막 형태를 이룰 수 있다. 또한, 사이즈가 작은 매개물을 이용할 경우 도 10의 (b) 및 도 11의 (b)에 도시된 바와 같이 표면 개질 부재(2000)는 적층체(1000)의 표면에 도 10의 (a) 및 도 11의 (a)에 도시된 경우보다 규칙적으로 분포되고, 응집 또는 연결되는 양이 감소한다. 그런데, 사이즈가 큰 매개물을 이용할 경우 도 10의 (c) 및 도 11의 (c)에 도시된 바와 같이 표면 개질 부재(2000)는 적층체(1000)의 표면에 규칙적으로 분포되고, 도 10의 (b) 및 도 11의 (b)에 도시된 작은 매개물을 이용하는 경우에 비해 큰 사이즈로 적층체(1000)의 표면에 형성된다. 이렇게 매개물을 이용함으로써 적층체(1000) 표면에 붙는 산화물을 다져주어 산화물이 적층체(1000)의 표면으로부터 소정 깊이로 부착될 수 있도록 한다. In addition, before the surface modification member 2000 is formed, the surface of the laminate 1000 may be pickled. The pickling process is a preliminary step for modifying the surface of the stack 1000 to weakly treat the stack 1000 to form uniform pores on the surface of the stack 1000. By forming pores on the surface of the laminate 1000, the surface modification member 2000 may further facilitate the formation of the laminate 1000. In addition, when the surface modification member 2000 is formed, a plurality of mediators may be further added together with the oxides, and the mediators may be added to uniformly distribute the oxides. In other words, when the medium is not added, the oxides may increase in agglomeration with each other if the media are unevenly distributed, but when the medium is added, the oxides may be uniformly distributed and the amount of aggregates may be reduced. In this case, the medium may use a material different from that of the laminate 1000 and the surface modifying member 2000, for example, stainless steel, ceramic, or the like. In addition, the medium may use a variety of forms, such as spherical, hexahedral. In this case, the plurality of media may use a volume whose total volume is larger than the total volume of the oxide powder and smaller than the total volume of the stack 1000, for example, the total volume of the medium is 10% of the total volume of the stack 1000. To 90% may be used. On the other hand, the size and spacing of the oxide dispersed in the stack 1000 can be adjusted according to the size of the mediator. The larger the mediator, the larger the size and spacing of the oxide, and the smaller the mediator, the smaller the mediator's size and spacing. Becomes smaller. That is, when the volume of the medium is less than 10% of the volume of the laminate 1000, the media shows the same distribution state as when the medium is not used. When the volume of the medium exceeds 90% of the volume of the laminate 1000, oxides appear on the surface of the medium. Since the amount is increased, it may not be applied to the surface of the laminate 1000. 10 (a) and 11 (a) are schematic cross-sectional views and planar photographs for explaining the distribution shape of the surface modifying member when no medium is used, and as shown, the surface modifying member 2000 is laminated. Irregularly distributed on the surface of the sieve 1000, the amount of aggregation or connection may be increased to form a film in at least one region. In addition, in the case of using a medium having a small size, as shown in FIGS. 10B and 11B, the surface modification member 2000 may be formed on the surface of the laminate 1000 in FIGS. 10A and 10B. It is distributed more regularly than the case shown in (a) of 11, and the amount of aggregation or connection is reduced. However, when using a medium having a large size, as shown in FIGS. 10C and 11C, the surface modification member 2000 is regularly distributed on the surface of the laminate 1000, and It is formed on the surface of the laminate 1000 in a larger size than in the case of using the small medium shown in (b) and (b) of FIG. By using the medium as described above, the oxide adhering to the surface of the stack 1000 is compacted so that the oxide can be attached to a predetermined depth from the surface of the stack 1000.
이어서, 필요에 따라 표면 개질 부재(2000)가 형성된 적층체(1000)를 표면 연마할 수 있다(S150). 표면 연마에 따라 표면 개질 부재(2000)의 일부를 연마할 수 있고, 그에 따라 표면 개질 부재(2000)가 섬 형태로 형성될 수 있도록 한다. 연마 공정은 습식 연마 또는 건식 연마 공정으로 실시할 수 있다. 습식 연마의 경우 소정의 내부 공간이 마련된 통 내에 표면 개질 부재(2000)가 형성된 복수의 적층체(1000)와 순수 및 연마제를 투입한 후 50 내지 100rpm의 회전 속도로 연마할 수 있다. 건식 연마의 경우 통 내에 표면 개질 부재(2000)가 형성된 복수의 적층체(1000)와 연마제를 투입한 후 100 내지 200rpm의 회전 속도로 연마할 수 있다. 즉, 건식 연마는 순수를 투입하지 않고 고속으로 실시할 수 있다. 이때, 연마제는 알루미나를 이용할 수 있다. 한편, 연마 시간은 적층체(1000), 순수 및 연마제의 투입량, 연마제의 거칠기, 연마 속도 등에 따라 달라질 수 있는데, 저속 및 습식 연마는 30분 이상 실시하고 고속 및 건식 연마는 1시간 이하로 실시할 수 있다. 예를 들어 습식 연마는 30분 이상 24시간 이하로 실시할 수 있고, 건식 연마는 1시간 이상 24시간 이하로 실시할 수 있다. 도 12 및 도 13은 습식 연마와 건식 연마 후의 적층체 표면 사진으로서, 각 도의 (a)는 연마 이전, (b)는 1시간 연마 후, (c)는 4시간 연마 후, (d)는 6시간 연마 후, (e)는 24시간 연마 후의 사진을 각각 도시한다. 도시된 바와 같이 연마 공정을 실시하면 적층체(1000)의 표면 개질 부재(2000)의 크기 및 분포를 조절할 수 있다. Subsequently, the laminated body 1000 in which the surface modification member 2000 was formed can be surface-polished as needed (S150). A part of the surface modification member 2000 may be polished according to the surface polishing, thereby allowing the surface modification member 2000 to be formed in an island shape. The polishing process can be carried out by a wet polishing or a dry polishing process. In the case of wet polishing, a plurality of laminates 1000 in which the surface modification member 2000 is formed, pure water, and an abrasive are introduced into a cylinder having a predetermined internal space, and then polished at a rotational speed of 50 to 100 rpm. In the case of dry grinding, after the plurality of laminates 1000 and the abrasive, in which the surface modification member 2000 is formed, are added to the cylinder, the polishing may be performed at a rotational speed of 100 to 200 rpm. That is, dry polishing can be performed at high speed without adding pure water. At this time, the abrasive may be alumina. On the other hand, the polishing time may vary depending on the laminate 1000, the amount of pure water and abrasives, the roughness of the abrasive, the polishing rate, etc., and the low speed and wet polishing may be performed for 30 minutes or more, and the high speed and dry polishing may be performed for 1 hour or less. Can be. For example, wet grinding can be performed for 30 minutes or more and 24 hours or less, and dry polishing can be performed for 1 hour or more and 24 hours or less. 12 and 13 are photographs of the surface of the laminate after wet polishing and dry polishing, (a) before each polishing, (b) after one hour polishing, (c) after four hours polishing, and (d) 6 After time polishing, (e) shows photographs after 24 hours polishing, respectively. As shown in the figure, the polishing process may control the size and distribution of the surface modification member 2000 of the laminate 1000.
도 14 및 도 15는 표면 개질 부재를 형성한 본 발명에 따른 칩 부품의 외부 전극 형상과 표면 개질 부재를 형성하지 않은 종래 예에 따른 칩 부품의 외부 전극 형상의 사진이다. 도 14의 (a)에 도시된 바와 같이 표면 개질 부재를 형성한 본 발명은 도 14의 (b)에 도시된 바와 같이 표면 개질 부재를 형성하지 않는 종래에 비해 적층체(1000) 표면의 절연성을 더욱 띄게 하여 도금 번짐을 방지할 수 있어 외부 전극의 형상을 제어할 수 있다. 또한, 도 15의 (a)에 도시된 바와 같이 표면 개질 부재를 형성한 본 발명은 도 15의 (b)에 도시된 바와 같이 표면 개질 부재를 형성하지 않는 종래에 비해 표면 개질읕 통해 표면 거칠기를 부여하여 도금 시 퍼짐 현상을 방지할 수 있다.14 and 15 are photographs of the external electrode shape of the chip component according to the present invention in which the surface modification member is formed and the external electrode shape of the chip component according to the conventional example in which the surface modification member is not formed. The present invention in which the surface modification member is formed as shown in (a) of FIG. 14 has an insulating property of the surface of the laminate 1000 as compared with the prior art which does not form the surface modification member as shown in (b) of FIG. It is possible to further prevent the plating bleeding to control the shape of the external electrode. In addition, the present invention in which the surface modification member is formed as shown in FIG. 15A shows surface roughness through surface modification as compared with the prior art in which the surface modification member is not formed as shown in FIG. 15B. The spreading phenomenon can be prevented during plating.
그리고, 내습성을 확인하기 위해 본 발명에 따른 표면 개질 부재가 형성된 복수의 칩 부품과 종래에 따른 표면 개질 부재가 형성되지 않은 복수의 칩 부품을 85℃의 온도와 85%의 습도를 유지하는 환경에서 12시간 유지시킨 후 5V의 전압을 인가하여 누설 전류를 확인하였다. 이때, 데이터 라인과 접지 라인 사이의 누설 전류(cross IL)와 데이터 라인끼리(IL)의 누설 전류를 측정하였으며, 10nA 이상의 전류가 흐르는 경우 불량으로 판단하였다. 이러한 본 발명 및 종래 예에 따른 내습성 결과를 [표 1]에 나타내었다.In order to confirm moisture resistance, the plurality of chip parts having the surface modification member according to the present invention and the plurality of chip parts without the surface modification member according to the related art are maintained at 85 ° C. and 85% humidity. After maintaining for 12 hours at 5V voltage was applied to check the leakage current. At this time, the leakage current (cross IL) between the data line and the ground line and the leakage current between the data lines (IL) were measured, and when a current of 10 nA or more flowed, it was determined as defective. Table 1 shows the results of moisture resistance according to the present invention and the conventional example.
시험 조건Exam conditions 시험 결과Test result
본 발명The present invention 종래 예Conventional example
cross ILcross IL 85℃/85%/12시간/5V 인가85 ℃ / 85% / 12 hours / 5V 0%0% 3%3%
ILIL 85℃/85%/12시간/5V 인가85 ℃ / 85% / 12 hours / 5V 0%0% 18%18%
상기한 바와 같이 본 발명에 따른 표면 개질 부재를 형성한 칩 부품의 경우 누설 전류가 측정되지 않아 불량이 전혀 발생되지 않았지만, 표면 개질 부재를 형성하지 않은 종래의 칩 부품은 3% 내지 18%의 불량률이 발생하였다. 즉, 종래의 경우 데이터 라인과 접지 라인 사이에는 3% 정도가 누설 전류가 발생하여 불량으로 판단되었고, 데이터 라인끼리에는 18% 정도가 누설 전류가 발생하여 불량으로 판단되었다. 또한, 불량이 발생된 칩 부품은 누설 전류가 수십 nA로부터 쇼트(short)까지 측정되었다. 따라서, 본 발명은 표면 개질 부재를 형성함으로써 칩 부품의 내습성을 향상시킬 수 있고, 그에 따라 칩 부품의 수명 및 신뢰성을 향상시킬 수 있다.As described above, in the case of the chip component having the surface modified member according to the present invention, no leakage current was measured and no defect occurred. However, in the conventional chip component which does not form the surface modified member, the defective rate is 3% to 18%. This occurred. That is, in the conventional case, about 3% of leakage current occurred between the data line and the ground line, and it was determined to be defective, and about 18% of the data lines were determined to be defective. In addition, defective chip components were measured for leakage currents ranging from tens of nA to short. Therefore, the present invention can improve the moisture resistance of the chip component by forming the surface modification member, thereby improving the life and reliability of the chip component.
본 발명의 기술적 사상은 상기 실시 예에 따라 구체적으로 기술되었으나, 상기 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지해야 한다. 또한, 본 발명의 기술분야에서 당업자는 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above embodiment, it should be noted that the above embodiment is for the purpose of description and not for the purpose of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (22)

  1. 적층체; 및Laminate; And
    상기 적층체의 적어도 일 영역에 형성된 표면 개질 부재를 포함하고,A surface modification member formed on at least one region of the laminate,
    상기 표면 개질 부재는 상기 적층체 표면의 적어도 일부를 노출시키도록 형성된 칩 부품.And the surface modification member is formed to expose at least a portion of the surface of the laminate.
  2. 청구항 1에 있어서, 상기 적층체는 복수의 시트가 적층되고, 상기 적층체 내에 상기 시트와는 이종의 물질층이 형성된 칩 부품.The chip component of claim 1, wherein a plurality of sheets are stacked, and a layer of a material different from the sheets is formed in the laminate.
  3. 청구항 2에 있어서, 상기 이종의 물질층은 소정 형상의 도전 패턴 및 과전압 방호 물질층을 포함하는 칩 부품.The chip component of claim 2, wherein the heterogeneous material layer comprises a conductive pattern having a predetermined shape and an overvoltage protection material layer.
  4. 청구항 1에 있어서, 상기 표면 개질 부재는 상기 적층체의 표면적의 5% 내지 90%의 면적으로 분포된 칩 부품.The chip component of claim 1, wherein the surface modification member is distributed in an area of 5% to 90% of the surface area of the laminate.
  5. 청구항 4에 있어서, 상기 표면 개질 부재는 결정 상태 및 비결정 상태의 산화물 중 적어도 하나를 포함하는 칩 부품.The chip component of claim 4, wherein the surface modification member includes at least one of an oxide in a crystalline state and an amorphous state.
  6. 청구항 5에 있어서, 상기 산화물은 Bi2O3, BO2, B2O3, ZnO, Co3O4, SiO2, Al2O3, MnO, H2BO3, Ca(CO3)2, Ca(NO3)2, CaCO3 중 적어도 하나를 포함하는 칩 부품.The method of claim 5, wherein the oxide is Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca (CO 3 ) 2 , A chip component comprising at least one of Ca (NO 3 ) 2 and CaCO 3 .
  7. 청구항 6에 있어서, 상기 산화물은 적어도 일부가 상기 적층체의 표면 내측으로 박힌 칩 부품.The chip component of claim 6, wherein the oxide is at least partially embedded in the surface of the laminate.
  8. 청구항 6에 있어서, 상기 산화물은 적어도 하나 이상의 크기를 갖는 입자가 적어도 일 영역에서 응집 또는 연결되는 칩 부품.The chip component of claim 6, wherein the oxide aggregates or connects particles having at least one or more sizes in at least one region.
  9. 청구항 6에 있어서, 상기 산화물 입자의 평균 크기는 0.1㎛ 내지 10㎛인 칩 부품.The chip component of claim 6, wherein the oxide particles have an average size of 0.1 μm to 10 μm.
  10. 청구항 1에 있어서, 상기 적층체 표면의 적어도 일부에 형성된 오목부를 더 포함하는 칩 부품.The chip component of claim 1, further comprising a recess formed in at least part of the surface of the laminate.
  11. 청구항 1 내지 청구항 10 중 어느 한 항에 있어서, 상기 적층체 내부에 형성된 제 2 표면 개질 부재를 더 포함하는 칩 부품.The chip component according to any one of claims 1 to 10, further comprising a second surface modification member formed inside the laminate.
  12. 청구항 11에 있어서, 상기 제 2 표면 개질 부재는 상기 적층체를 이루는 적어도 하나의 시트에 형성된 칩 부품.The chip component of claim 11, wherein the second surface modification member is formed in at least one sheet constituting the laminate.
  13. 복수의 시트가 적층된 적층체;A laminate in which a plurality of sheets are stacked;
    상기 적층체 내부에 형성되며 상기 시트와는 다른 물질로 형성된 이종 물질층; 및A heterogeneous material layer formed inside the laminate and formed of a material different from that of the sheet; And
    상기 적층체의 적어도 일 면에 형성된 외부 전극을 포함하고,An external electrode formed on at least one surface of the laminate;
    상기 적층체는 적어도 일 표면이 둘 이상의 성분을 갖는 칩 부품.And said laminate has at least one surface having at least two components.
  14. 청구항 13에 있어서, 상기 적층체의 적어도 일 면에 상기 적층체 표면의 적어도 일부를 노출시키도록 형성된 표면 개질 부재를 포함하는 칩 부품.The chip component of claim 13, comprising a surface modification member formed on at least one side of the laminate to expose at least a portion of the laminate surface.
  15. 청구항 14에 있어서, 상기 표면 개질 부재는 산화물을 포함하는 칩 부품.The chip component of claim 14, wherein the surface modification member comprises an oxide.
  16. 청구항 15에 있어서, 상기 산화물은 상기 적층체 두께의 0.01% 내지 10%의 두께로 형성된 칩 부품.The chip component of claim 15, wherein the oxide is formed to a thickness of 0.01% to 10% of the thickness of the laminate.
  17. 복수의 칩 부품을 마련하는 과정;Preparing a plurality of chip components;
    상기 복수의 칩 부품의 적어도 일면에 표면 개질 부재를 형성하는 과정을 포함하고,Forming a surface modification member on at least one surface of the plurality of chip components;
    상기 표면 개질 부재는 상기 칩 부품 표면의 적어도 일부가 노출되도록 형성하는 칩 부품의 제조 방법.And the surface modification member is formed such that at least a portion of the surface of the chip component is exposed.
  18. 청구항 17에 있어서, 상기 표면 개질 부재는 상기 복수의 칩 부품과 산화물 분말을 용기 내에 투입하고 회전하여 형성하는 칩 부품의 제조 방법.The method of manufacturing a chip component according to claim 17, wherein the surface modification member is formed by inserting and rotating the plurality of chip components and oxide powder into a container.
  19. 청구항 18에 있어서, 상기 복수의 칩 부품 및 상기 산화물 분말과 함께 복수의 매개물을 더 투입하는 칩 부품의 제조 방법.The method of manufacturing a chip component according to claim 18, wherein a plurality of mediators are further added together with the plurality of chip components and the oxide powder.
  20. 청구항 19에 있어서, 상기 복수의 매개물은 상기 칩 부품 및 상기 산화물 분말과 이종의 물질로 이루어진 칩 부품의 제조 방법.The method of claim 19, wherein the plurality of mediators comprise the chip component and the oxide powder and a heterogeneous material.
  21. 청구항 20에 있어서, 상기 복수의 매개물은 총 부피가 상기 산화물 분말의 총 부피보다 크고 상기 복수의 적층체의 총 부피보다 작은 칩 부품의 제조 방법.The method of claim 20, wherein the plurality of mediators has a total volume greater than the total volume of the oxide powder and less than the total volume of the plurality of laminates.
  22. 청구항 17 내지 청구항 21 중 어느 한 항에 있어서, 상기 표면 개질 부재를 형성하기 전 산세 처리하는 과정과, 상기 표면 개질 부재를 형성한 후 상기 칩 부품을 표면 연마하는 과정의 적어도 하나를 더 포함하는 칩 부품의 제조 방법.22. The chip of any one of claims 17 to 21, further comprising at least one of pickling before forming the surface modification member and surface polishing the chip component after forming the surface modification member. Method of manufacturing the part.
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CN109478465B (en) 2021-02-26
TW201807798A (en) 2018-03-01

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