TWI645532B - Chip component and method of manufacturing the same - Google Patents

Chip component and method of manufacturing the same Download PDF

Info

Publication number
TWI645532B
TWI645532B TW106121501A TW106121501A TWI645532B TW I645532 B TWI645532 B TW I645532B TW 106121501 A TW106121501 A TW 106121501A TW 106121501 A TW106121501 A TW 106121501A TW I645532 B TWI645532 B TW I645532B
Authority
TW
Taiwan
Prior art keywords
laminate
wafer
surface modifying
oxide
disposed
Prior art date
Application number
TW106121501A
Other languages
Chinese (zh)
Other versions
TW201807798A (en
Inventor
白政哲
李政勳
金楨寀
金周星
Original Assignee
南韓商摩達伊諾琴股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商摩達伊諾琴股份有限公司 filed Critical 南韓商摩達伊諾琴股份有限公司
Publication of TW201807798A publication Critical patent/TW201807798A/en
Application granted granted Critical
Publication of TWI645532B publication Critical patent/TWI645532B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G29/00Compounds of bismuth
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G45/00Compounds of manganese
    • C01G45/02Oxides; Hydroxides
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G51/00Compounds of cobalt
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G51/00Compounds of cobalt
    • C01G51/40Cobaltates
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01GCOMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G9/00Compounds of zinc
    • C01G9/02Oxides; Hydroxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/14Protection against electric or thermal overload
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F2017/0093Common mode choke coil

Abstract

提供一種晶片構件及其製造方法。所述晶片構件包括:疊層體;以及表面改質部件,設置於所述疊層體的至少一個區域上,且所述表面改質部件被配置成暴露出所述疊層體的表面的至少一部分。A wafer member and a method of manufacturing the same are provided. The wafer member includes: a laminate; and a surface modifying member disposed on at least one region of the laminate, and the surface modifying member is configured to expose at least a surface of the laminate portion.

Description

晶片構件及其製造方法Wafer component and method of manufacturing same

本發明是有關於一種晶片構件及其製造方法,且更具體而言是有關於一種能夠控制外部電極的形狀的晶片構件及其製造方法。 The present invention relates to a wafer member and a method of fabricating the same, and more particularly to a wafer member capable of controlling the shape of an external electrode and a method of fabricating the same.

近年來,隨著例如智慧型電話等可攜式電子裝置的多功能化,各種頻寬得到使用。亦即,在一個智慧型電話中採用使用例如無線區域網路(wireless LAN)、藍芽(Bluetooth)及全球定位系統(global positioning system,GPS)等不同頻寬的多種功能。此外,隨著電子裝置的高度積體化,有限空間中的內部電路密度增大,且因此,在內部電路之間會不可避免地產生雜訊干擾(noise interference)。 In recent years, various bandwidths have been used with the versatility of portable electronic devices such as smart phones. That is, a plurality of functions using different bandwidths such as a wireless LAN, a Bluetooth, and a global positioning system (GPS) are employed in a smart phone. Further, as the electronic device is highly integrated, the internal circuit density in the limited space increases, and therefore, noise interference is inevitably generated between the internal circuits.

為抑制可攜式電子裝置中具有各種頻率的雜訊及亦對內部電路之間的雜訊加以約束,目前使用多個晶片構件。舉例而言,目前使用用於分別消除具有彼此不同的頻寬的雜訊的晶片珠(chip bead)及共模濾波器(common mode filter)等。 In order to suppress noise having various frequencies in portable electronic devices and also to constrain noise between internal circuits, a plurality of wafer members are currently used. For example, chip beads, common mode filters, and the like for respectively eliminating noises having different bandwidths from each other are currently used.

此外,為保護電子裝置免受例如靜電放電(electro-static discharge,ESD)等自外部施加至所述電子裝置的高電壓影響,需要例如可變電阻器(varistor)及抑制器(suppressor)等靜電放電保護裝置。另外,可將具有彼此不同的特性的至少二或更多個晶片構件疊層並製造成所述晶片構件,以減小由該些晶片構件所佔的面積。舉例而言,將雜訊濾波器及靜電放電保護裝置疊層於一個晶片中以達成所述晶片構件。 In addition, to protect the electronic device from, for example, electrostatic discharge (electro-static Electrostatic discharge protection devices such as varistors and suppressors are required for high voltage effects applied from the outside to the electronic device, such as discharge, ESD). In addition, at least two or more wafer members having different characteristics from each other may be laminated and fabricated into the wafer member to reduce the area occupied by the wafer members. For example, a noise filter and an electrostatic discharge protection device are stacked in a single wafer to achieve the wafer structure.

在此晶片構件中,外部電極設置於其中設置有預定結構的疊層體(laminate)外部,且與電子裝置的內部電路之間的連接是經由所述外部電極而建立。此處,外部電極可藉由鍍覆製程(plating process)來提供。亦即,晶片構件可焊接及安裝於電子裝置的印刷電路板(printed circuit board,PCB)基板上,且外部電極是藉由鍍覆製程來提供以改善焊接特性。 In this wafer member, the external electrode is disposed outside the laminate in which the predetermined structure is provided, and the connection with the internal circuit of the electronic device is established via the external electrode. Here, the external electrode can be provided by a plating process. That is, the wafer member can be soldered and mounted on a printed circuit board (PCB) substrate of the electronic device, and the external electrode is provided by a plating process to improve soldering characteristics.

然而,疊層體的表面具有非均勻有阻力狀態(non-uniform resistive state),且當在此狀態下執行鍍覆製程時鍍覆層將出現非均勻生長。亦即,鍍覆層將出現模糊現象(blurring phenomenon),且因此外部電極被設置成非期望形狀。 However, the surface of the laminate has a non-uniform resistive state, and the plating layer will exhibit non-uniform growth when the plating process is performed in this state. That is, the plating layer will exhibit a blurring phenomenon, and thus the external electrodes are set to an undesired shape.

眾所周知,為防止此鍍覆模糊現象,將以玻璃等來塗佈疊層體的表面。亦即,使用玻璃在疊層體的表面上設置塗佈層。然而,由於表面塗佈層是藉由在設置疊層體之後在所述疊層體的表面上塗覆玻璃成分來製成,因此不會獲得與疊層體的完全結合性質,且可能出現其中因塗佈層的存在而使得疊層體內部的導體不連接至外部電極的局限性。 It is known that the surface of the laminate is coated with glass or the like in order to prevent this plating blur. That is, a coating layer is provided on the surface of the laminate using glass. However, since the surface coating layer is formed by coating a glass component on the surface of the laminate after the laminate is disposed, complete bonding properties with the laminate are not obtained, and The presence of the coating layer makes the conductor inside the laminate not connected to the external electrode.

(先前技術文獻) (previous technical literature)

韓國專利登記第10-0876206號 Korean Patent Registration No. 10-0876206

韓國專利公開案第2002-0045782號 Korean Patent Publication No. 2002-0045782

本發明提供一種其中外部電極的形狀得到輕易控制的晶片構件及其製造方法。 The present invention provides a wafer member in which the shape of an external electrode is easily controlled and a method of manufacturing the same.

本發明提供一種其中藉由使表面改質來輕易控制外部電極的形狀的晶片構件及其製造方法。 The present invention provides a wafer member in which the shape of an external electrode is easily controlled by modifying a surface and a method of manufacturing the same.

根據示例性實施例,一種晶片構件包括:疊層體;以及表面改質部件,設置於所述疊層體的至少一個區域上,其中所述表面改質部件被配置成暴露出表面的至少一部分。 According to an exemplary embodiment, a wafer member includes: a laminate; and a surface modifying member disposed on at least one region of the laminate, wherein the surface modifying member is configured to expose at least a portion of the surface .

所述疊層體可包括多個疊層片材,且在所述疊層體內可設置有與所述片材不同的異質材料層。 The laminate may include a plurality of laminated sheets, and a layer of a heterogeneous material different from the sheets may be disposed within the laminate.

所述異質材料層可包括導電圖案,所述導電圖案具有預定形狀並具有用於防止過電壓的材料層。 The heterogeneous material layer may include a conductive pattern having a predetermined shape and having a material layer for preventing an overvoltage.

所述表面改質部件可以佔所述疊層體的表面積的5%至90%的表面積分佈。 The surface modifying component may comprise a surface area distribution of from 5% to 90% of the surface area of the laminate.

所述表面改質部件可包含晶體狀態的氧化物與非晶體狀態的氧化物中的至少一者。 The surface modifying member may include at least one of an oxide in a crystalline state and an oxide in an amorphous state.

所述氧化物可包括以下中的至少一者:Bi2O3、BO2、B2O3、ZnO、Co3O4、SiO2、Al2O3、MnO、H2BO3、Ca(CO3)2、Ca(NO3)2及CaCO3The oxide may include at least one of Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca ( CO 3 ) 2 , Ca(NO 3 ) 2 and CaCO 3 .

所述氧化物的至少一部分可嵌入所述疊層體的所述表面中。 At least a portion of the oxide may be embedded in the surface of the laminate.

所述氧化物可包括具有至少一或多種粒徑的微粒,所述具有至少一或多種粒徑的微粒在至少一個區中聚集或連接至彼此。 The oxide may comprise particles having at least one or more particle sizes, the particles having at least one or more particle sizes being aggregated or connected to each other in at least one zone.

所述氧化物的所述微粒可具有0.1微米(μm)至10微米的平均粒徑。 The microparticles of the oxide may have an average particle diameter of from 0.1 micrometers (μm) to 10 micrometers.

可更包括界定於所述疊層體的所述表面的至少一部分中的凹陷部。 A recess defined in at least a portion of the surface of the laminate may be further included.

可更包括設置於所述疊層體中的第二表面改質部件。 A second surface modifying member disposed in the laminate may be further included.

所述第二表面改質部件可設置於構成所述疊層體的至少一個片材上。 The second surface modifying member may be disposed on at least one of the sheets constituting the laminate.

根據另一示例性實施例,一種晶片構件包括:疊層體,在所述疊層體中疊層有多個片材;以及異質材料層,設置於所述疊層體中且由與所述片材中的每一者的材料不同的材料製成;以及外部電極,設置於所述疊層體的至少一個表面上,其中所述疊層體具有至少一個表面包含二或更多種元素。 According to another exemplary embodiment, a wafer member includes: a laminate in which a plurality of sheets are laminated; and a heterogeneous material layer disposed in the laminate and Each of the sheets is made of a different material; and an external electrode is disposed on at least one surface of the laminate, wherein the laminate has at least one surface comprising two or more elements.

可包括表面改質部件,所述表面改質部件設置於所述疊層體的至少一個表面上以暴露出所述疊層體的表面的至少一部分。 A surface modifying component may be included, the surface modifying component being disposed on at least one surface of the laminate to expose at least a portion of a surface of the laminate.

所述表面改質部件可包含氧化物。 The surface modifying component can comprise an oxide.

所述氧化物可具有等於所述疊層體的厚度的0.01%至 10%的厚度。 The oxide may have a thickness equal to 0.01% of the thickness of the laminate to 10% thickness.

根據又一示例性實施例,一種製造晶片構件的方法包括:製備多個晶片構件;以及在所述多個晶片構件的至少一個表面上形成表面改質部件,其中所述表面改質部件被形成為暴露出所述晶片構件的表面的至少一部分。 According to still another exemplary embodiment, a method of fabricating a wafer member includes: preparing a plurality of wafer members; and forming a surface modifying member on at least one surface of the plurality of wafer members, wherein the surface modifying member is formed To expose at least a portion of the surface of the wafer member.

可將所述多個晶片構件及氧化物粉末饋送至容器中並旋轉以形成所述表面改質部件。 The plurality of wafer members and oxide powder can be fed into a container and rotated to form the surface modifying component.

可更與所述多個晶片構件及所述氧化物粉末一起饋送多種媒體。 A plurality of media may be fed together with the plurality of wafer members and the oxide powder.

所述多種媒體可由與所述晶片構件及所述氧化物粉末的材料不同的材料製成。 The plurality of media may be made of a material different from that of the wafer member and the oxide powder.

所述多種媒體的總體積可大於所述氧化物粉末的總體積且小於所述多個疊層體的總體積。 The total volume of the plurality of media may be greater than the total volume of the oxide powder and less than the total volume of the plurality of laminates.

可更包括以下中的至少一個製程:在形成所述表面改質部件之前執行浸洗處理,以及在形成所述表面改質部件之後對所述晶片構件執行表面拋光。 At least one of the following may be further included: performing a dip process before forming the surface modifying member, and performing surface polishing on the wafer member after forming the surface modifying member.

110、120、130、140、150、160、170、180、190‧‧‧片材 110, 120, 130, 140, 150, 160, 170, 180, 190‧‧ sheets

310‧‧‧第一線圈圖案 310‧‧‧First coil pattern

320‧‧‧第二線圈圖案 320‧‧‧second coil pattern

330‧‧‧第三線圈圖案 330‧‧‧ Third coil pattern

340‧‧‧第四線圈圖案 340‧‧‧fourth coil pattern

351、352、353、361、362、363‧‧‧孔 351, 352, 353, 361, 362, 363‧ ‧ holes

410、420、430、440、620‧‧‧引出電極 410, 420, 430, 440, 620‧‧‧ lead electrodes

511、512、513、514‧‧‧第一放電電極 511, 512, 513, 514‧‧‧ first discharge electrode

520‧‧‧第二放電電極 520‧‧‧second discharge electrode

531、532、533、534‧‧‧靜電放電保護層 531, 532, 533, 534‧‧‧ Electrostatic discharge protection layer

610‧‧‧電容器電極 610‧‧‧ capacitor electrode

1000‧‧‧疊層體 1000‧‧‧Laminated body

1100‧‧‧上部覆蓋層 1100‧‧‧Upper cover

1200‧‧‧下部覆蓋層 1200‧‧‧lower cover

2000‧‧‧表面改質部件 2000‧‧‧Surface modified parts

3000、3100、3110、3120、3200、3210、3220‧‧‧外部電極 3000, 3100, 3110, 3120, 3200, 3210, 3220‧‧‧ external electrodes

S110、S120、S130、S140、S150‧‧‧步驟 S110, S120, S130, S140, S150‧‧ steps

X、Y、Z‧‧‧方向 X, Y, Z‧‧ Direction

結合附圖閱讀以下說明,可更詳細地理解示例性實施例,在附圖中:圖1是根據示例性實施例的晶片構件的立體圖。 The exemplary embodiments may be understood in more detail in conjunction with the following description in which: FIG. 1 is a perspective view of a wafer member in accordance with an exemplary embodiment.

圖2(a)至圖2(e)是說明根據示例性實施例的晶片構件的表面的示意圖。 2(a) to 2(e) are schematic views illustrating a surface of a wafer member according to an exemplary embodiment.

圖3至圖5是根據示例性實施例的晶片構件的分解立體圖。 3 through 5 are exploded perspective views of a wafer member in accordance with an exemplary embodiment.

圖6是用於闡釋根據示例性實施例的製造晶片構件的方法的製程流程圖。 FIG. 6 is a process flow diagram for explaining a method of manufacturing a wafer member according to an exemplary embodiment.

圖7至圖9是相依於氧化物的饋送量(feeding amount)的疊層體表面的影像。 7 to 9 are images of the surface of the laminate depending on the feeding amount of the oxide.

圖10(a)至圖10(c)及圖11(a)至圖11(c)是說明與其中不使用媒體(medium)的情形有關且相依於媒體的大小的表面改質部件的形狀以及疊層體表面的影像的示意圖。 10(a) to 10(c) and FIGS. 11(a) to 11(c) are diagrams illustrating the shape of a surface modifying member related to a case in which no medium is used and depending on the size of the medium, and A schematic representation of an image of the surface of a laminate.

圖12(a)至圖12(e)及圖13(a)至圖13(e)是在濕拋光(wet-polishing)及乾拋光(dry-polishing)之後疊層體表面的影像。 12(a) to 12(e) and Figs. 13(a) to 13(e) are images of the surface of the laminate after wet-polishing and dry-polishing.

圖14(a)至圖14(b)及圖15(a)至圖15(b)是根據其中形成表面改質部件的示例性實施例及根據其中不形成表面改質部件的相關實施例的晶片構件的外部電極的照片。 14(a) to 14(b) and 15(a) to 15(b) are diagrams according to an exemplary embodiment in which a surface modifying member is formed and according to a related embodiment in which a surface modifying member is not formed Photograph of the external electrodes of the wafer member.

在下文中,將參照附圖來詳細闡述具體實施例。然而,本發明可實施為不同形式,而不應被視為僅限於本文所述的實施例。確切而言,提供該些實施例是為了使此揭露內容將透徹及完整,並將向熟習此項技術者充分傳達本發明的範圍。在各圖中,為清楚說明若干層及各種區中的每一者,放大了厚度,且在所有圖中相同的參考編號指代相同的元件。 Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed by those skilled in the art. In the figures, the thickness of the layers and the various regions are exaggerated for clarity, and the same reference numerals are used throughout the drawings.

圖1是根據示例性實施例的晶片構件的立體圖,且圖2(a)至圖2(e)是晶片構件的示意圖。 1 is a perspective view of a wafer member according to an exemplary embodiment, and FIGS. 2(a) to 2(e) are schematic views of a wafer member.

參照圖1及圖2(a)至圖2(e),根據示例性實施例的晶片構件可包括其中疊層有多個片材的疊層體1000、設置於疊層體1000的至少一個表面上的表面改質部件2000及設置於疊層體1000的至少一個表面上的外部電極3000。 1 and 2(a) to 2(e), a wafer member according to an exemplary embodiment may include a laminate 1000 in which a plurality of sheets are laminated, and is disposed on at least one surface of the laminate 1000 The upper surface modifying member 2000 and the external electrode 3000 disposed on at least one surface of the laminate 1000.

疊層體Laminate

疊層體1000可被設置成在一個方向(例如,X方向)及與所述一個方向垂直的另一方向(例如,Y方向)上分別具有預定長度及寬度且在垂直方向(例如,Z方向)上具有預定高度的近似六面體形狀。亦即,當外部電極3000的形成方向是X方向(即,縱向方向)時,與X方向水平垂直的方向可為Y方向(即,寬度方向),且垂直方向可為Z方向(即,厚度方向)。此處,舉例而言,X方向上的長度可等於或大於Y方向上的寬度及Z方向上的高度,且Y方向上的寬度可等於或不同於Z方向上的高度。當寬度(Y方向)不同於高度(Z方向)時,所述寬度可大於或小於所述高度。舉例而言,長度、寬度及高度的比率可為1至5:1:0.5至2。亦即,以寬度為基礎,長度可為寬度的近似一倍至五倍,且高度可為寬度的0.5倍至二倍。然而,X方向、Y方向及Z方向上的大小僅為一個實例,且因此可依據連接至晶片構件的電子裝置的內部結構、所述晶片構件的形狀及所述晶片構件的功能而有各種變化。此疊層體1000可藉由對具有預定大小的多個近似板形狀 的片材進行疊層來提供。亦即,片材可被設置成呈在X方向及Y方向上具有預定長度及寬度且在Z方向上具有預定厚度的近似四角形形狀。該些片材疊層有多個以提供具有近似六面體形狀的疊層體1000。構成疊層體1000的所述多個片材可由例如包括例如多層陶瓷電容器(Multi-layer Ceramic Capacitor,MLCC)、BaTiO3、BaCO3、TiO2、Nd2O3、Bi2O3、ZnO及Al2O3等介電材料粉末中的一或多者的材料製成。因此,片材可依據材料品質而具有相應介電常數(dielectric constant),例如5至20000的介電常數、較佳地為7至5000的介電常數、且更佳地為200至3000的介電常數。此外,所述多個片材可由可變電阻器材料組成。舉例而言,片材可藉由將例如Bi2O3、Pr6O11、CoO及MnO等添加劑添加至ZnO粉末來提供。此外,所述多個片材可為非磁性片材或磁性片材。亦即,所述多個片材可為由上述材料製成的非磁性片材且具有預定介電常數,或者為更包含磁性材料的磁性片材。作為另一選擇,所述多個片材中的至少一者可由磁性片材或非磁性片材製成以便適合於晶片構件的用途。另外,所述多個片材可由金屬粉末與聚合物形成的混合物製成。如上所述,所述多個片材可依據晶片構件的用途而由各種材料製成。此外,所述多個片材中的所有者可具有相同的厚度,或者所述片材中的至少一者可具有較所述片材中的其他片材的厚度大或較所述厚度小的厚度。 The laminate 1000 may be disposed to have a predetermined length and width and a vertical direction (for example, the Z direction) in one direction (for example, the X direction) and another direction (for example, the Y direction) perpendicular to the one direction. An approximately hexahedral shape having a predetermined height. That is, when the formation direction of the external electrode 3000 is the X direction (ie, the longitudinal direction), the direction perpendicular to the X direction may be the Y direction (ie, the width direction), and the vertical direction may be the Z direction (ie, the thickness) direction). Here, for example, the length in the X direction may be equal to or larger than the width in the Y direction and the height in the Z direction, and the width in the Y direction may be equal to or different from the height in the Z direction. When the width (Y direction) is different from the height (Z direction), the width may be larger or smaller than the height. For example, the ratio of length, width, and height can be from 1 to 5:1:0.5 to 2. That is, the length may be approximately one to five times the width and the height may be from 0.5 to 2 times the width. However, the sizes in the X direction, the Y direction, and the Z direction are only one example, and thus various changes may be made depending on the internal structure of the electronic device connected to the wafer member, the shape of the wafer member, and the function of the wafer member. . This laminate 1000 can be provided by laminating sheets having a plurality of approximate plate shapes having a predetermined size. That is, the sheet may be disposed in an approximately quadrangular shape having a predetermined length and width in the X direction and the Y direction and a predetermined thickness in the Z direction. The plurality of sheets are laminated to provide a laminate 1000 having an approximately hexahedral shape. The plurality of sheets constituting the laminate 1000 may include, for example, a multi-layer ceramic capacitor (MLCC), BaTiO 3 , BaCO 3 , TiO 2 , Nd 2 O 3 , Bi 2 O 3 , ZnO, and the like. A material of one or more of the dielectric material powders such as Al 2 O 3 is used. Therefore, the sheet may have a corresponding dielectric constant depending on the material quality, for example, a dielectric constant of 5 to 20,000, preferably a dielectric constant of 7 to 5,000, and more preferably 200 to 3,000. Electric constant. Further, the plurality of sheets may be composed of a variable resistor material. For example, the sheet may be provided by adding an additive such as Bi 2 O 3 , Pr 6 O 11 , CoO, and MnO to the ZnO powder. Further, the plurality of sheets may be non-magnetic sheets or magnetic sheets. That is, the plurality of sheets may be non-magnetic sheets made of the above materials and have a predetermined dielectric constant, or a magnetic sheet further containing a magnetic material. Alternatively, at least one of the plurality of sheets can be made of a magnetic sheet or a non-magnetic sheet to suit the use of the wafer member. Additionally, the plurality of sheets may be made of a mixture of metal powder and polymer. As described above, the plurality of sheets can be made of various materials depending on the use of the wafer member. Further, an owner of the plurality of sheets may have the same thickness, or at least one of the sheets may have a larger or smaller thickness than other sheets in the sheet thickness.

作為另一選擇,疊層體1000內部的所述多個片材中可設置有各種結構。亦即,疊層體1000內部可設置有各種形狀的導電 圖案,且可設置靜電放電保護材料。亦即,疊層體1000內可設置有具有與構成疊層體1000的片材的成分不同的成分的至少一或多個不同的材料層。舉例而言,疊層體1000內的所述多個片材中可分別設置有螺旋形線圈圖案及其中填充有導電材料的孔,且因此可達成電感器或雜訊濾波器。此外,疊層體1000中可達成例如可變電阻器及靜電放電保護零件等結構以防止高電壓。此外,疊層體1000內部的所述多個片材中可設置有多個內部電極以分別地且交替地連接至外部電極3000,且因此電容器可由所述兩個相鄰內部電極及所述兩個相鄰內部電極之間的片材來提供。另外,疊層體1000內設置有其中至少一個表面上設置有線圈圖案的基板,且由金屬粉末及聚合物組成的片材可疊層於所述基板的上部部分上以提供功率電感器(power inductor)。電感器、雜訊濾波器、電容器、功率電感器、可變電阻器及靜電放電保護零件中的一者可設置於疊層體1000中,或者電感器、雜訊濾波器、電容器、功率電感器、可變電阻器及靜電放電保護零件中的至少二或更多者可彼此組合地設置於疊層體1000中。作為另一選擇,疊層體1000可更包括分別設置於最下部層及最上部層中的下部覆蓋層(圖中未示出)及上部覆蓋層(圖中未示出)。亦即,最下部層的片材可充當下部覆蓋層,且最上部層的片材可充當上部覆蓋層。下部覆蓋層及上部覆蓋層可藉由對多個磁性片材進行疊層來提供,且可具有相同的厚度。此處,由磁性片材組成的上部覆蓋層及下部覆蓋層的最外部部分(即,下表面及上表面)上可進一步設置有例如 玻璃質片材(vitreous sheet)等非磁性片材。此外,下部覆蓋層及上部覆蓋層可具有較內部片材的厚度大的厚度。 Alternatively, various structures may be provided in the plurality of sheets inside the laminate 1000. That is, the laminate 1000 may be internally provided with various shapes of conductive A pattern and an electrostatic discharge protection material can be provided. That is, at least one or a plurality of different material layers having components different from the components constituting the sheet of the laminate 1000 may be provided in the laminate 1000. For example, the plurality of sheets in the laminate 1000 may be respectively provided with a spiral coil pattern and a hole filled with a conductive material therein, and thus an inductor or a noise filter may be achieved. Further, a structure such as a variable resistor and an electrostatic discharge protection member can be realized in the laminate 1000 to prevent a high voltage. Further, a plurality of internal electrodes may be disposed in the plurality of sheets inside the laminate 1000 to be respectively and alternately connected to the external electrodes 3000, and thus the capacitors may be the two adjacent internal electrodes and the two A sheet between adjacent internal electrodes is provided. In addition, a substrate in which at least one surface is provided with a coil pattern is disposed in the laminate 1000, and a sheet composed of metal powder and a polymer may be laminated on an upper portion of the substrate to provide a power inductor (power) Inductor). One of an inductor, a noise filter, a capacitor, a power inductor, a variable resistor, and an ESD protection component may be disposed in the laminate 1000, or an inductor, a noise filter, a capacitor, a power inductor At least two or more of the variable resistor and the electrostatic discharge protection member may be disposed in the laminate 1000 in combination with each other. Alternatively, the laminate 1000 may further include a lower cover layer (not shown) and an upper cover layer (not shown) disposed in the lowermost layer and the uppermost layer, respectively. That is, the sheet of the lowermost layer can serve as the lower cover layer, and the sheet of the uppermost layer can serve as the upper cover layer. The lower cover layer and the upper cover layer may be provided by laminating a plurality of magnetic sheets and may have the same thickness. Here, the outer cover layer composed of the magnetic sheet and the outermost portions (ie, the lower surface and the upper surface) of the lower cover layer may be further provided with, for example, A non-magnetic sheet such as a vitreous sheet. Further, the lower cover layer and the upper cover layer may have a thickness greater than the thickness of the inner sheet.

表面改質部件Surface modification component

表面改質部件2000可設置於疊層體1000的至少一個表面上。表面改質部件2000可例如在提供外部電極3000之前藉由分配氧化物而設置於疊層體1000的表面上。此處,所述氧化物可以晶體狀態或非晶體狀態分散於且分配於疊層體1000的表面上。當外部電極3000是藉由鍍覆製程來形成時,表面改質部件2000可在所述鍍覆製程之前分配於疊層體1000的表面上。亦即,表面改質部件2000可在藉由印刷製程(printing process)形成外部電極3000的一部分之前進行分配,或者可在所述印刷製程之後在鍍覆製程之前進行分配。作為另一選擇,當不執行印刷製程時,可在分配表面改質部件2000之後執行鍍覆製程。此處,分配於表面上的表面改質部件2000的至少一部分可熔化。 The surface modifying member 2000 may be disposed on at least one surface of the laminate 1000. The surface modifying member 2000 may be disposed on the surface of the laminate 1000 by dispensing an oxide, for example, before the external electrode 3000 is provided. Here, the oxide may be dispersed and distributed on the surface of the laminate 1000 in a crystalline state or an amorphous state. When the external electrode 3000 is formed by a plating process, the surface modifying member 2000 may be dispensed on the surface of the laminate 1000 before the plating process. That is, the surface modifying member 2000 may be dispensed prior to forming a portion of the external electrode 3000 by a printing process, or may be dispensed prior to the printing process after the printing process. Alternatively, when the printing process is not performed, the plating process may be performed after the surface modifying component 2000 is dispensed. Here, at least a portion of the surface modifying member 2000 dispensed on the surface may be melted.

此外,表面改質部件2000的至少一部分可如圖2(a)中所示以相同的大小均勻地分佈於疊層體1000的表面上,且表面改質部件2000的至少一部分可如圖2(b)中所示以彼此不同的大小不規則地進行分配。此外,如圖2(c)中所示,疊層體1000的表面的至少一部分上可界定有凹陷部。亦即,表面改質部件2000被設置成界定突出部,且上面不設置表面改質部件2000的區域的至少一部分可下凹以界定凹陷部。此處,表面改質部件2000的至少一部分可安置於較疊層體1000的表面的深度深的深度處。亦即, 表面改質部件2000可嵌入預定厚度(即,預定深度),且表面改質部件2000的其餘部分可具有較疊層體1000的表面的高度高的高度。此處,嵌入疊層體1000中的表面改質部件2000可具有等於氧化物微粒的平均直徑的1/20至1的厚度。亦即,氧化物微粒的所有部分可下陷至疊層體1000中,且所述氧化物微粒的至少一部分可如圖2(d)中所示下陷。作為另一選擇,氧化物微粒可如圖2(d)中所示僅設置於疊層體1000的表面上。因此,氧化物微粒可以半球形或球形設置於疊層體1000的表面上。此外,表面改質部件2000可如上所述部分地分配於疊層體1000的表面上且可以膜形狀分配於所述表面的至少一部分上。亦即,如圖2(a)至圖2(d)中所示,氧化物微粒以島形狀分配於疊層體1000的表面上以設置表面改質部件2000。亦即,具有晶體狀態或非晶體狀態的氧化物可彼此間隔開且以島形狀分配於疊層體1000的表面上,且因此疊層體1000的所述表面的至少一部分可被暴露出。此外,如圖2(e)中所示,表面改質部件2000可藉由連接至少二或更多種氧化物而以膜形狀設置於至少一個區域上,且可以島形狀設置於所述至少一個區域的至少一部分上。亦即,至少二或更多個氧化物微粒聚集於一起,或者相鄰的氧化物微粒連接至彼此,且因此可達成膜形狀。然而,當氧化物以微粒狀態存在時,或者甚至當所述二或更多個微粒聚集或連接於一起時,疊層體1000的所述表面的至少一部分可被表面改質部件2000暴露至外部。 Further, at least a portion of the surface modifying member 2000 may be uniformly distributed on the surface of the laminate 1000 in the same size as shown in FIG. 2(a), and at least a portion of the surface modifying member 2000 may be as shown in FIG. 2 ( The distribution shown in b) is irregularly distributed in sizes different from each other. Further, as shown in FIG. 2(c), at least a portion of the surface of the laminate 1000 may define a depressed portion. That is, the surface modifying member 2000 is disposed to define the protrusion, and at least a portion of the area on which the surface modifying member 2000 is not disposed may be recessed to define the recess. Here, at least a portion of the surface modifying member 2000 may be disposed at a depth deeper than the surface of the laminate 1000. that is, The surface modifying member 2000 may be embedded in a predetermined thickness (ie, a predetermined depth), and the remaining portion of the surface modifying member 2000 may have a height higher than the height of the surface of the laminate 1000. Here, the surface modifying member 2000 embedded in the laminate 1000 may have a thickness equal to 1/20 to 1 of the average diameter of the oxide particles. That is, all portions of the oxide fine particles may be depressed into the laminate 1000, and at least a portion of the oxide fine particles may be depressed as shown in Fig. 2(d). Alternatively, the oxide particles may be provided only on the surface of the laminate 1000 as shown in Fig. 2(d). Therefore, the oxide fine particles may be disposed on the surface of the laminate 1000 in a hemispherical or spherical shape. Further, the surface modifying member 2000 may be partially distributed on the surface of the laminate 1000 as described above and may be distributed on at least a portion of the surface. That is, as shown in FIGS. 2(a) to 2(d), oxide fine particles are distributed in the shape of an island on the surface of the laminate 1000 to provide the surface modifying member 2000. That is, the oxide having a crystalline state or an amorphous state may be spaced apart from each other and distributed on the surface of the laminate 1000 in an island shape, and thus at least a portion of the surface of the laminate 1000 may be exposed. Further, as shown in FIG. 2(e), the surface modifying member 2000 may be disposed on at least one region in a film shape by connecting at least two or more oxides, and may be disposed in the at least one island shape At least part of the area. That is, at least two or more oxide fine particles are aggregated together, or adjacent oxide fine particles are connected to each other, and thus a film shape can be achieved. However, when the oxide exists in a particulate state, or even when the two or more particles are aggregated or joined together, at least a portion of the surface of the laminate 1000 may be exposed to the outside by the surface modifying member 2000. .

此處,表面改質部件2000的總面積可為例如疊層體1000 的所述表面的總面積的5%至90%。儘管可依據表面改質部件2000的面積來控制疊層體1000的表面上的鍍覆模糊現象,然而當表面改質部件2000被過量設置時,疊層體1000內部的導電圖案可能難以接觸外部電極3000。亦即,當表面改質部件2000以佔疊層體1000的表面積的小於5%的面積設置時,可能無法輕易控制鍍覆模糊現象,且當以佔大於90%的面積設置時,疊層體1000內部的導電圖案可能無法接觸外部電極3000。因此,表面改質部件2000較佳地以能控制鍍覆模糊現象且使疊層體1000內部的導電圖案接觸外部電極3000的程度的面積設置。為此,表面改質部件2000可以佔疊層體1000的表面積的10%至90%、較佳地佔疊層體1000的表面積的30%至70%,更佳地佔疊層體1000的表面積的40%至50%的面積設置。此處,疊層體1000的表面積可為一個表面的表面積或者可為構成六面體的六個表面的表面積。作為另一選擇,表面改質部件2000可具有等於或小於疊層體1000的厚度的10%的厚度。亦即,表面改質部件2000可具有等於疊層體1000的厚度的0.01%至10%的厚度。舉例而言,表面改質部件2000可以0.1微米至50微米的大小存在,且因此,表面改質部件2000可自疊層體1000的表面具有0.1微米至50微米的厚度。亦即,除表面改質部件2000的嵌入部分以外,表面改質部件2000可自疊層體1000的表面具有0.1微米至50微米的厚度。因此,當包括嵌入疊層體1000內部的厚度時,表面改質部件2000可具有較0.1微米至50微米厚的厚度。當表面改質部件2000具有較疊層體1000的厚度 的0.01%小的厚度時,可能無法輕易控制鍍覆模糊現象,且當表面改質部件2000具有較疊層體1000的厚度的10%大的厚度時,疊層體1000內部的導電圖案可能無法接觸外部電極3000。亦即,表面改質部件2000可依據材料性質(導電性、半導電性(semiconductivity)、絕緣、磁體(magnetic body)等)而具有各種厚度,且可依據氧化物粉末的粒徑、分配量及是否欲聚集而具有各種厚度。 Here, the total area of the surface modifying member 2000 may be, for example, a laminate 1000 5% to 90% of the total area of the surface. Although the plating blur phenomenon on the surface of the laminate 1000 can be controlled depending on the area of the surface modifying member 2000, when the surface modifying member 2000 is excessively disposed, the conductive pattern inside the laminate 1000 may be difficult to contact the external electrode. 3000. That is, when the surface modifying member 2000 is disposed in an area of less than 5% of the surface area of the laminate 1000, the plating blur may not be easily controlled, and when it is disposed in an area of more than 90%, the laminate The conductive pattern inside 1000 may not be in contact with the external electrode 3000. Therefore, the surface modifying member 2000 is preferably provided in an area capable of controlling the plating blur phenomenon and bringing the conductive pattern inside the laminate 1000 into contact with the external electrode 3000. To this end, the surface modifying member 2000 may constitute 10% to 90% of the surface area of the laminate 1000, preferably 30% to 70% of the surface area of the laminate 1000, and more preferably occupy the surface area of the laminate 1000. 40% to 50% area setting. Here, the surface area of the laminate 1000 may be the surface area of one surface or may be the surface area of the six surfaces constituting the hexahedron. Alternatively, the surface modifying member 2000 may have a thickness equal to or less than 10% of the thickness of the laminate 1000. That is, the surface modifying member 2000 may have a thickness equal to 0.01% to 10% of the thickness of the laminate 1000. For example, the surface modifying member 2000 may exist in a size of 0.1 to 50 μm, and thus, the surface modifying member 2000 may have a thickness of 0.1 μm to 50 μm from the surface of the laminate 1000. That is, the surface modifying member 2000 may have a thickness of 0.1 μm to 50 μm from the surface of the laminate 1000 in addition to the embedded portion of the surface modifying member 2000. Therefore, when including the thickness embedded inside the laminate 1000, the surface modifying member 2000 may have a thickness of from 0.1 μm to 50 μm thick. When the surface modifying component 2000 has a thickness greater than that of the laminate 1000 When the thickness is 0.01%, the plating blur may not be easily controlled, and when the surface modifying member 2000 has a thickness greater than 10% of the thickness of the laminate 1000, the conductive pattern inside the laminate 1000 may not be able to The external electrode 3000 is contacted. That is, the surface modifying member 2000 may have various thicknesses depending on material properties (electrical conductivity, semiconductivity, insulation, magnetic body, etc.), and may be based on the particle size and the amount of the oxide powder. Whether you want to gather and have various thicknesses.

由於如上所述表面改質部件2000設置於疊層體1000的表面上,因此疊層體1000的所述表面上可存在其中成分彼此不同的至少兩個區。亦即,自上面設置有表面改質部件2000的區域偵測到的成分可不同於自上面不設置表面改質部件2000的區域偵測到的成分。舉例而言,依表面改質部件2000而定的成分(即,氧化物)可存在於上面設置有表面改質部件2000的區上,且依疊層體1000而定的成分(即,片材的成分)可存在於上面不設置表面改質部件2000的區上。疊層體1000的表面可如上所述藉由在鍍覆製程之前在疊層體1000的表面上分配表面改質部件2000而被賦予粗糙度(roughness)且被改質。因此,鍍覆製程可均勻地執行,且因此,外部電極3000的形狀可得到控制。亦即,疊層體1000的表面上的至少一個區的電阻可能不同於另一區的電阻,且當在其中電阻不均勻的狀態中執行鍍覆製程時,鍍覆層將出現非均勻生長。針對此情形,可將微粒狀態的氧化物或熔化狀態的氧化物分散於本體1000的表面上以設置表面改質部件2000,藉此能夠使 疊層體1000的表面改質且控制鍍覆層的生長。 Since the surface modifying member 2000 is disposed on the surface of the laminate 1000 as described above, at least two regions in which the components are different from each other may exist on the surface of the laminate 1000. That is, the component detected from the region in which the surface modifying member 2000 is disposed may be different from the component detected from the region in which the surface modifying member 2000 is not disposed. For example, a component (ie, an oxide) depending on the surface modifying member 2000 may exist on a region on which the surface modifying member 2000 is disposed, and a component depending on the laminate 1000 (ie, a sheet) The component may be present on the area on which the surface modifying component 2000 is not disposed. The surface of the laminate 1000 can be imparted with roughness and modified by dispensing the surface modifying member 2000 on the surface of the laminate 1000 before the plating process as described above. Therefore, the plating process can be performed uniformly, and thus, the shape of the external electrode 3000 can be controlled. That is, the resistance of at least one region on the surface of the laminate 1000 may be different from the resistance of the other region, and when the plating process is performed in a state in which the resistance is uneven, the plating layer will exhibit non-uniform growth. In this case, an oxide in a particulate state or an oxide in a molten state may be dispersed on the surface of the body 1000 to provide the surface modifying member 2000, thereby enabling The surface of the laminate 1000 is modified and the growth of the plating layer is controlled.

此處,可使用例如Bi2O3、BO2、B2O3、ZnO、Co3O4、SiO2、Al2O3、MnO、H2BO3、Ca(CO3)2、Ca(NO3)2及CaCO3中的至少一或多者來作為用以使疊層體1000的表面電阻均勻化的所述微粒狀態的氧化物或熔化狀態的氧化物。作為另一選擇,表面改質部件2000亦可設置於疊層體1000內的至少一個片材上。亦即,片材上的具有各種形狀的導電圖案可藉由鍍覆製程來設置,且導電圖案的形狀可藉由設置表面改質部件2000來控制。 Here, for example, Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca(CO 3 ) 2 , Ca (for example) can be used. At least one or more of NO 3 ) 2 and CaCO 3 are used as the oxide in the particulate state or the oxide in the molten state for uniformizing the surface resistance of the laminate 1000. Alternatively, the surface modifying member 2000 may be disposed on at least one of the sheets in the laminate 1000. That is, the conductive patterns having various shapes on the sheet can be set by a plating process, and the shape of the conductive pattern can be controlled by providing the surface modifying member 2000.

外部電極External electrode

外部電極3000(3100及3200)設置於兩個相對側表面上且選擇性地連接至設置於疊層體1000內部的導電圖案。亦即,外部電極3000可以如下方式設置:在所述方式中,在所述兩個相對側表面中的每一者上(例如,在第一側表面及第二側表面中的每一者上)設置一個外部電極,或者如圖1中所示設置二或更多個外部電極。此外,與第一側表面及第二側表面垂直的第三側表面及第四側表面中的至少一者上可進一步設置有至少一個外部電極。外部電極3000可被設置成至少一個層。外部電極3000中的每一者可被設置成例如銀等金屬層,且至少一個鍍覆層可設置於所述金屬層上。舉例而言,外部電極3000可藉由對銅層、鍍鎳層,及鍍錫層或鍍錫/銀層進行疊層來設置。此外,外部電極3000可例如藉由對0.5%至20%的Bi2O3或以SiO2作為主要成分的多組分玻璃熔塊(multi-component glass frit)與金屬粉末進行混合來形成。 此處,玻璃熔塊與金屬粉末的混合物可被製造成膏體形式且接著可塗覆至疊層體1000的兩個表面。如上所述,由於外部電極3000中含有所述玻璃熔塊,因此外部電極3000與疊層體1000之間的黏合力可得到提高,且疊層體1000內部的導電圖案與外部電極3000之間的接觸反應(contact response)可得到改善。此外,塗覆包含玻璃的導電膏體,且接著在所述導電膏體的上部部分上設置至少一個鍍覆層以設置外部電極3000。亦即,設置包含玻璃的金屬層及所述金屬層的上部部分上的所述至少一個鍍覆層,且因此可設置外部電極3000。舉例而言,外部電極3000可以如下方式設置:在所述方式中,設置玻璃熔塊以及包含銀及銅中的至少一者的層,且接著藉由電解鍍覆(electrolytic plating)或無電鍍覆(electroless plating)來順次地設置鍍鎳層及鍍錫層。此處,鍍錫層可具有等於或大於鍍鎳層的厚度的厚度。作為另一選擇,外部電極3000可設置有至少一個鍍覆層。亦即,可在不塗覆膏體的條件下利用一個鍍覆製程來設置至少一個鍍覆層,以藉此提供外部電極3000。此外,外部電極3000可具有2微米至100微米的厚度,其中鍍鎳層具有1微米至10微米的厚度,且鍍錫/銀層具有2微米至10微米的厚度。 The external electrodes 3000 (3100 and 3200) are disposed on the two opposite side surfaces and are selectively connected to the conductive patterns disposed inside the laminate 1000. That is, the external electrode 3000 may be disposed in such a manner as to be on each of the two opposite side surfaces (eg, on each of the first side surface and the second side surface) An external electrode is provided, or two or more external electrodes are provided as shown in FIG. Further, at least one external electrode may be further disposed on at least one of the third side surface and the fourth side surface perpendicular to the first side surface and the second side surface. The external electrode 3000 may be provided in at least one layer. Each of the external electrodes 3000 may be provided as a metal layer such as silver, and at least one plating layer may be disposed on the metal layer. For example, the external electrode 3000 can be disposed by laminating a copper layer, a nickel plating layer, and a tin plating layer or a tin/silver layer. Further, the external electrode 3000 can be formed, for example, by mixing 0.5% to 20% of Bi 2 O 3 or a multi-component glass frit having SiO 2 as a main component with the metal powder. Here, a mixture of the glass frit and the metal powder may be fabricated in a paste form and then applied to both surfaces of the laminate 1000. As described above, since the glass frit is contained in the external electrode 3000, the adhesion between the external electrode 3000 and the laminate 1000 can be improved, and the conductive pattern inside the laminate 1000 and the external electrode 3000 are The contact response can be improved. Further, a conductive paste containing glass is applied, and then at least one plating layer is provided on the upper portion of the conductive paste to set the external electrode 3000. That is, the metal layer including the glass and the at least one plating layer on the upper portion of the metal layer are disposed, and thus the external electrode 3000 may be disposed. For example, the external electrode 3000 may be disposed in such a manner that a glass frit and a layer containing at least one of silver and copper are provided, and then by electrolytic plating or electroless plating (electroless plating) to sequentially provide a nickel plating layer and a tin plating layer. Here, the tin plating layer may have a thickness equal to or greater than the thickness of the nickel plating layer. Alternatively, the external electrode 3000 may be provided with at least one plating layer. That is, at least one plating layer may be provided by a plating process without applying a paste to thereby provide the external electrode 3000. Further, the external electrode 3000 may have a thickness of 2 micrometers to 100 micrometers, wherein the nickel plating layer has a thickness of 1 micrometer to 10 micrometers, and the tin plating/silver layer has a thickness of 2 micrometers to 10 micrometers.

疊層體內部的結構實例Structure example inside the laminate

此處,在圖3至圖5中說明根據示例性實施例的疊層體1000的結構。圖3至圖5是根據示例性實施例的疊層體1000的分解立體圖及包括螺旋形線圈圖案的雜訊濾波器的分解立體圖。如 上所述,疊層體1000內部將達成例如電容器、可變電阻器、電感器及功率電感器等各種晶片構件,且以下示例性實施例闡釋共模雜訊濾波器(common mode noise filter)的實例。 Here, the structure of the laminated body 1000 according to an exemplary embodiment is explained in FIGS. 3 to 5. 3 to 5 are exploded perspective views of a laminated body 1000 and an exploded perspective view of a noise filter including a spiral coil pattern, according to an exemplary embodiment. Such as As described above, various wafer components such as capacitors, variable resistors, inductors, and power inductors will be realized inside the laminate 1000, and the following exemplary embodiments illustrate a common mode noise filter. Example.

參照圖3,疊層體1000可以如下方式設置:在所述方式中,將多個片材110至150進行疊層,且在至少一個所選擇片材120至150上分別設置至少一個線圈圖案(即,第一線圈圖案310至第四線圈圖案340)。此外,當線圈圖案(即,第一線圈圖案310至第四線圈圖案340)設置有多個時,至少兩個線圈圖案(即,第一線圈圖案310至第四線圈圖案340)可經由其中填充有導電材料的孔351、352、361及362垂直連接至彼此。舉例而言,第一線圈圖案310可經由其中填充有導電材料的孔351及352連接至第三線圈圖案330,且第二線圈圖案320可經由其中填充有導電材料的孔361及362連接至第四線圈圖案340。另外,設置自相應線圈圖案(即,第一線圈圖案310至第四線圈圖案340)引出至外部的引出電極(lead-out electrode)410至440且因此引出電極410至440可連接至外部電極。此外,最上部的片材110的上部部分及最下部的片材150的下部部分上可分別設置有上部覆蓋層1100及下部覆蓋層1200。上部覆蓋層1100及下部覆蓋層1200中的每一者可具有較片材110至150中的每一者的厚度大的厚度。 Referring to FIG. 3, the laminate 1000 may be disposed in such a manner that a plurality of sheets 110 to 150 are laminated, and at least one coil pattern is respectively disposed on at least one of the selected sheets 120 to 150 ( That is, the first to fourth coil patterns 310 to 340). Further, when a plurality of coil patterns (ie, the first coil pattern 310 to the fourth coil pattern 340) are provided, at least two coil patterns (ie, the first coil pattern 310 to the fourth coil pattern 340) may be filled therein The holes 351, 352, 361 and 362 having a conductive material are vertically connected to each other. For example, the first coil pattern 310 may be connected to the third coil pattern 330 via holes 351 and 352 filled with a conductive material therein, and the second coil pattern 320 may be connected to the first via holes 361 and 362 filled with a conductive material therein Four coil patterns 340. In addition, lead-out electrodes 410 to 440 which are taken out from the respective coil patterns (ie, the first coil pattern 310 to the fourth coil pattern 340) to the outside are provided and thus the lead electrodes 410 to 440 may be connected to the external electrodes. Further, an upper cover layer 1100 and a lower cover layer 1200 may be respectively disposed on the upper portion of the uppermost sheet 110 and the lower portion of the lowermost sheet 150. Each of the upper cover layer 1100 and the lower cover layer 1200 may have a thickness greater than the thickness of each of the sheets 110 to 150.

如圖4中所示,疊層體1000內部可進一步設置有靜電放電保護零件。亦即,共模雜訊濾波器與靜電放電保護零件進行疊層以達成複合裝置。疊層體1000可包括:多個片材110至180; 第一線圈圖案310至第四線圈圖案340,分別設置於至少一或多個所選擇片材120至150上;孔351、352、361及362,被界定成填充有導電材料以使第一線圈圖案310至第四線圈圖案340分別進行連接;引出電極410至440,自第一線圈圖案310至第四線圈圖案340引出且連接至外部電極;多個第一放電電極511、512、513及514,設置於所選擇片材170上;靜電放電保護層531、532、533及534,填充於在第一放電電極511至514兩端形成的孔內;以及第二放電電極520,設置於所選擇片材180上且連接至靜電放電保護層531至534。此處,第一放電電極511至514與所述多個引出電極410至440一起連接至外部電極,且第二放電電極520連接至單獨的外部電極。此外,為自靜電放電保護零件劃分共模雜訊濾波器,可在所述靜電放電保護零件與所述共模雜訊濾波器之間設置片材160。 As shown in FIG. 4, the inside of the laminated body 1000 may be further provided with an electrostatic discharge protection member. That is, the common mode noise filter is laminated with the electrostatic discharge protection component to achieve a composite device. The laminate 1000 may include: a plurality of sheets 110 to 180; The first to fourth coil patterns 310 to 340 are respectively disposed on the at least one or more selected sheets 120 to 150; the holes 351, 352, 361 and 362 are defined to be filled with a conductive material to make the first coil pattern The 310 to fourth coil patterns 340 are respectively connected; the extraction electrodes 410 to 440 are taken out from the first coil pattern 310 to the fourth coil pattern 340 and connected to the external electrodes; the plurality of first discharge electrodes 511, 512, 513 and 514, Provided on the selected sheet 170; electrostatic discharge protection layers 531, 532, 533 and 534 filled in the holes formed at both ends of the first discharge electrodes 511 to 514; and a second discharge electrode 520 disposed on the selected sheet The material 180 is connected to the electrostatic discharge protection layers 531 to 534. Here, the first discharge electrodes 511 to 514 are connected to the external electrodes together with the plurality of extraction electrodes 410 to 440, and the second discharge electrodes 520 are connected to the separate external electrodes. Further, in order to divide the common mode noise filter from the electrostatic discharge protection component, a sheet 160 may be disposed between the electrostatic discharge protection component and the common mode noise filter.

如圖5中所示,疊層體1000內可進一步設置有至少一個電容器電極610。亦即,所述兩個線圈圖案(即,第二線圈圖案320與第三線圈圖案330)之間設置有片材190,電容器電極610可設置於片材190上,且可設置自電容器電極610引出至外部的引出電極620。此外,片材190中可界定有其中填充有導電材料的孔353及363且因此可將上部線圈圖案連接至下部線圈圖案。電容器電極610與第二線圈圖案320及第三線圈圖案330中的每一者之間可設置有具有預定電容的電容器,第二線圈圖案320及第三線圈圖案330設置於電容器電極610上方及電容器電極610下 方,片材130及190中的每一者位於第二線圈圖案320與第三線圈圖案330之間。 As shown in FIG. 5, at least one capacitor electrode 610 may be further disposed in the laminate 1000. That is, a sheet 190 is disposed between the two coil patterns (ie, the second coil pattern 320 and the third coil pattern 330), and the capacitor electrode 610 may be disposed on the sheet 190 and may be disposed from the capacitor electrode 610. The extraction electrode 620 is taken out to the outside. Further, holes 353 and 363 in which the conductive material is filled may be defined in the sheet 190 and thus the upper coil pattern may be connected to the lower coil pattern. A capacitor having a predetermined capacitance may be disposed between the capacitor electrode 610 and each of the second coil pattern 320 and the third coil pattern 330, and the second coil pattern 320 and the third coil pattern 330 are disposed above the capacitor electrode 610 and the capacitor Electrode 610 Each of the sheets 130 and 190 is located between the second coil pattern 320 and the third coil pattern 330.

如上所述,在根據示例性實施例的晶片構件中,外部電極3000的形狀可藉由在疊層體1000的表面上設置表面改質部件2000來控制。亦即,表面改質部件2000設置於疊層體1000的表面上以使疊層體1000的所述表面改質,且因此可防止因鍍覆而造成的外部電極3000的模糊現象及攤開現象(spreading phenomenon),且因此可輕易控制外部電極3000的形狀。此外,根據示例性實施例,具有與疊層體1000的成分不同的成分的表面改質部件2000設置於疊層體1000的表面上,且因此可防止水分滲透至疊層體1000中,且因此晶片構件的壽命及可靠性可提高。防水性質可藉由在將晶片構件維持在高溫及高濕環境中達預定時間之後量測洩漏電流來辨識。 As described above, in the wafer member according to the exemplary embodiment, the shape of the external electrode 3000 can be controlled by providing the surface modifying member 2000 on the surface of the laminate 1000. That is, the surface modifying member 2000 is disposed on the surface of the laminate 1000 to modify the surface of the laminate 1000, and thus the blurring and spreading of the external electrode 3000 due to plating can be prevented. The spreading phenomenon, and thus the shape of the external electrode 3000 can be easily controlled. Further, according to the exemplary embodiment, the surface modifying member 2000 having a composition different from that of the laminate 1000 is disposed on the surface of the laminate 1000, and thus moisture can be prevented from penetrating into the laminate 1000, and thus The life and reliability of the wafer components can be improved. The waterproof property can be identified by measuring the leakage current after maintaining the wafer member in a high temperature and high humidity environment for a predetermined time.

製造晶片構件的方法Method of manufacturing a wafer member

將參照圖6來闡述根據示例性實施例的製造晶片構件的方法。圖6是用於闡釋根據示例性實施例的製造晶片構件的方法的製程流程圖。 A method of manufacturing a wafer member according to an exemplary embodiment will be explained with reference to FIG. FIG. 6 is a process flow diagram for explaining a method of manufacturing a wafer member according to an exemplary embodiment.

首先,製備具有預定厚度的近似四角形形狀的片材(S110)。此處,多個片材可具有較晶片構件的大小大的大小。亦即,在所述多個片材上形成多個導電圖案等且接著可將所述多個導電圖案等切割成晶片構件的大小。此外,所述多個片材可為具有預定介電常數的非磁性片材或者磁性片材。亦即,所述多個片 材中的至少一者可為非磁性片材或磁性片材。作為另一選擇,所述多個片材可由具有預定擊穿電壓的可變電阻器材料製成。 First, a sheet having an approximately quadrangular shape having a predetermined thickness is prepared (S110). Here, the plurality of sheets may have a size larger than the size of the wafer member. That is, a plurality of conductive patterns and the like are formed on the plurality of sheets and then the plurality of conductive patterns or the like can be cut into the size of the wafer member. Further, the plurality of sheets may be a non-magnetic sheet or a magnetic sheet having a predetermined dielectric constant. That is, the plurality of pieces At least one of the materials may be a non-magnetic sheet or a magnetic sheet. Alternatively, the plurality of sheets may be made of a variable resistor material having a predetermined breakdown voltage.

接著,在至少一個片材上形成具有預定形狀的導電圖案等(S120)。此處,可在導電圖案上形成多個絕緣圖案。可將導電圖案形成為具有預定面積的四角形或自中心區至外部具有螺旋形狀。此外,可藉由使用例如銀、鉑、鎳、錫及銅等導電材料的網版印刷方法(screen printing method)或鍍覆方法來形成導電圖案。此處,可在藉由鍍覆方法形成導電圖案之前在片材的至少一個表面上形成表面改質部件2000。亦即,可藉由在片材的表面上形成表面改質部件2000來使所述片材的所述表面改質以控制鍍覆形狀。此外,可在至少一個片材上形成靜電放電保護部件,以屏蔽例如靜電放電等高電壓。可在於垂直方向或水平方向上彼此間隔開的兩個導電圖案之間形成靜電放電保護部件。舉例而言,可將靜電放電保護部件形成為使得穿透片材的孔隙(pore)被填充,或者可將所述靜電放電保護部件形成於所述片材上以在彼此間隔開的兩個導電圖案之間部分地交疊所述兩個導電圖案。此外,靜電放電保護部件可為製備於所述兩個導電圖案之間的孔隙。亦即,不於在垂直方向或水平方向上彼此間隔開的所述兩個導電圖案之間形成單獨的材料,且可在所述兩個導電圖案之間維持孔隙且因此可使用所述孔隙作為靜電放電保護部件。 Next, a conductive pattern or the like having a predetermined shape is formed on at least one of the sheets (S120). Here, a plurality of insulating patterns may be formed on the conductive pattern. The conductive pattern may be formed into a quadrangle having a predetermined area or have a spiral shape from the central portion to the outside. Further, the conductive pattern can be formed by a screen printing method or a plating method using a conductive material such as silver, platinum, nickel, tin, and copper. Here, the surface modifying member 2000 may be formed on at least one surface of the sheet before the conductive pattern is formed by a plating method. That is, the surface of the sheet can be modified to control the plated shape by forming the surface modifying member 2000 on the surface of the sheet. Further, an electrostatic discharge protection member may be formed on at least one of the sheets to shield a high voltage such as an electrostatic discharge. An electrostatic discharge protection member may be formed between two conductive patterns spaced apart from each other in the vertical direction or the horizontal direction. For example, the electrostatic discharge protection member may be formed such that a pore of the penetrating sheet is filled, or the electrostatic discharge protection member may be formed on the sheet to be spaced apart from each other by two conductive The two conductive patterns are partially overlapped between the patterns. Further, the electrostatic discharge protection member may be a void prepared between the two conductive patterns. That is, separate materials are not formed between the two conductive patterns spaced apart from each other in the vertical direction or the horizontal direction, and pores may be maintained between the two conductive patterns and thus the pores may be used as Electrostatic discharge protection components.

接著,以如下方式形成疊層體1000:在所述方式中,對上面形成有導電圖案及/或靜電放電保護部件的多個片材進行疊 層、切割及塑化(S130)。因此,可形成其中形成有多個螺旋形線圈的電感器或共模雜訊濾波器,或者可形成其中所述兩個導電圖案與所述兩個導電圖案之間的片材構成電容的電容器。此外,可形成靜電放電保護零件。藉由對如上所述的所述多個片材進行疊層來形成用於各種用途的晶片構件:可依據導電圖案像何種形狀、靜電放電保護零件是否存在及片材使用何種材料等。 Next, the laminate 1000 is formed in such a manner that a plurality of sheets on which the conductive patterns and/or the electrostatic discharge protection members are formed are stacked Layer, cutting and plasticizing (S130). Therefore, an inductor or a common mode noise filter in which a plurality of spiral coils are formed may be formed, or a capacitor in which a sheet between the two conductive patterns and the two conductive patterns constitutes a capacitance may be formed. In addition, an electrostatic discharge protection component can be formed. The wafer member for various uses is formed by laminating the plurality of sheets as described above: depending on the shape of the conductive pattern, the presence or absence of the electrostatic discharge protection member, and the material used for the sheet.

接著,在疊層體1000的表面上形成表面改質部件2000(S140)。可藉由將氧化物分配於疊層體1000的表面上來形成表面改質部件2000。舉例而言,可使用Bi2O3、BO2、B2O3、ZnO、Co3O4、SiO2、Al2O3、MnO、H2BO3、Ca(CO3)2、Ca(NO3)2、CaCO3中的至少一者。此外,為在疊層體1000的表面上形成表面改質部件2000,將氧化物及疊層體1000饋送至其中設置有預定空間的容器中,且接著在水平方向上及/或垂直方向上旋轉所述容器,藉此能夠將氧化物分配於疊層體1000的表面上。亦即,可執行碾磨製程(milling process)。此處,容器可具有近似圓柱形形狀。此外,執行至少一次此製程以形成表面改質部件2000。疊層體1000的表面上的表面改質部件2000的分配量、大小及厚度等可依據氧化物的饋送量、疊層體1000的饋送量、製程時間等而變化。亦即,隨著氧化物的饋送量及製程時間的增加,表面改質部件2000的分配量(即,表面積、大小及厚度)可增加,且隨著疊層體1000的饋送量的增加,表面改質部件2000的分配量(即,表面積、大小及厚度)可增加。舉例而言,可藉由供應20,000個疊層體至60,000 個疊層體及饋送2克(g)至15克的氧化物來在疊層體1000的表面上分配具有0微米至10微米的厚度的氧化物,且可每一個疊層體1000以50微米至200微米的量來塗覆所述氧化物。此處,轉速可為例如50轉/分(rpm)至100轉/分,且容器的體積可為500立方公分(cc)至1000立方公分。此外,加工時間可為30分鐘至2小時。在示例性實施例中,當具有9.92平方毫米(mm2)的表面積的60000個疊層體1000被饋送至具有4克氧化物的預定容器中且接著旋轉預定時間時,氧化物被形成至0微米至4微米的厚度,且所述氧化物是以每一表面積近似6.7微克/平方毫米(μg/mm2)來形成且是以每一晶片近似67微克的量進行分配。圖7中說明此情形中的表面的影像。此外,當具有9.92平方毫米的表面積的60000個疊層體1000被饋送至具有8克氧化物的預定容器中且接著旋轉預定時間時,氧化物被形成至1微米至6微米的厚度,且所述氧化物是以每一表面積近似13.4微克/平方毫米來形成且是以每一晶片近似133微克的量進行分配。圖8中說明此情形中的表面的影像。另外,當具有9.92平方毫米的表面積的60000個疊層體1000被饋送至具有11克氧化物的預定容器中且接著旋轉預定時間時,氧化物被形成至2微米至10微米的厚度,且所述氧化物是以每一表面積近似18.5微克/平方毫米來形成且是以每一晶片近似183微克的量進行分配。圖9中說明此情形中的表面的影像。 Next, a surface modifying member 2000 is formed on the surface of the laminate 1000 (S140). The surface modifying member 2000 can be formed by dispensing an oxide on the surface of the laminate 1000. For example, Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca(CO 3 ) 2 , Ca ( At least one of NO 3 ) 2 and CaCO 3 . Further, in order to form the surface modifying member 2000 on the surface of the laminate 1000, the oxide and the laminate 1000 are fed into a container in which a predetermined space is provided, and then rotated in the horizontal direction and/or the vertical direction. The container, whereby the oxide can be distributed on the surface of the laminate 1000. That is, a milling process can be performed. Here, the container may have an approximately cylindrical shape. Further, at least one such process is performed to form the surface modifying member 2000. The distribution amount, size, thickness, and the like of the surface modifying member 2000 on the surface of the laminate 1000 may vary depending on the amount of the oxide to be fed, the amount of the sheet 1000 to be fed, the processing time, and the like. That is, as the amount of oxide feeding and the processing time increase, the amount of distribution of the surface modifying member 2000 (i.e., surface area, size, and thickness) may increase, and as the amount of the laminated body 1000 is increased, the surface The amount of distribution (i.e., surface area, size, and thickness) of the modifying component 2000 can be increased. For example, a thickness of 0 micrometers to 10 micrometers can be dispensed on the surface of the laminate 1000 by supplying 20,000 laminates to 60,000 laminates and feeding 2 grams (g) to 15 grams of oxide. The oxide may be applied to each of the laminates 1000 in an amount of from 50 micrometers to 200 micrometers. Here, the rotational speed may be, for example, 50 revolutions per minute (rpm) to 100 rpm, and the volume of the container may be 500 cubic centimeters (cc) to 1000 cubic centimeters. In addition, the processing time can be from 30 minutes to 2 hours. In an exemplary embodiment, when 60,000 laminates 1000 having a surface area of 9.92 square millimeters (mm 2 ) are fed into a predetermined container having 4 grams of oxide and then rotated for a predetermined time, the oxide is formed to 0. The thickness is from micron to 4 microns, and the oxide is formed with approximately 6.7 micrograms per square millimeter (μg/mm 2 ) per surface area and is dispensed in an amount of approximately 67 micrograms per wafer. An image of the surface in this case is illustrated in FIG. Further, when 60,000 laminated bodies 1000 having a surface area of 9.92 mm 2 are fed into a predetermined container having 8 g of oxide and then rotated for a predetermined time, the oxide is formed to a thickness of 1 μm to 6 μm, and The oxides were formed at approximately 13.4 micrograms per square millimeter per surface area and were dispensed in an amount of approximately 133 micrograms per wafer. An image of the surface in this case is illustrated in FIG. In addition, when 60,000 laminated bodies 1000 having a surface area of 9.92 mm 2 are fed into a predetermined container having 11 g of oxide and then rotated for a predetermined time, the oxide is formed to a thickness of 2 μm to 10 μm, and The oxides were formed at approximately 18.5 micrograms per square millimeter per surface area and were dispensed in an amount of approximately 183 micrograms per wafer. An image of the surface in this case is illustrated in FIG.

作為另一選擇,可在形成表面改質部件2000之前執行針 對疊層體1000的表面的浸洗製程(pickling process)。浸洗製程是用於使疊層體1000的表面改質的預先進行的步驟(pre-step),其中可藉由使用弱酸對疊層體1000進行處理來在疊層體1000的表面上形成均勻的孔隙。在疊層體1000的表面上形成孔隙,且因此表面改質部件2000可進一步方便形成疊層體1000。此外,當形成表面改質部件2000時可進一步與氧化物一起填送多種媒體,且可藉由饋送所述媒體來均勻地分配所述氧化物。亦即,當不饋送媒體時,氧化物的分配是非均勻的且因此聚集至彼此的氧化物的量可能增多,但當饋送所述媒體時,氧化物的分配是均勻的且因此聚集至彼此的氧化物的量可減少。此處,可使用與疊層體1000及表面改質部件2000的材料不同的材料作為所述媒體。舉例而言,可使用不銹鋼、陶瓷等。此外,可使用例如球形及六面體形狀等各種形狀來作為所述媒體。此處,所述多種媒體的總體積可大於氧化物粉末的總體積且小於疊層體1000的總體積。舉例而言,媒體的總體積可為疊層體1000的總體積的10%至90%。此外,可依據媒體的大小來調整分散於疊層體1000上的氧化物的粒徑及間隔,其中隨著媒體的大小的增大,氧化物的粒徑及間隔增大,且隨著媒體的大小的減小,氧化物的粒徑及間隔減小。亦即,當媒體的體積小於疊層體1000的體積的10%時,表現出與當不使用媒體時的分配狀態相同的分配狀態,且當媒體的體積大於疊層體1000的體積的90%時,黏合至媒體的表面的氧化物的量增加,且因此可不在疊層體1000的表面上塗覆氧化物。在圖10(a)及圖 11(a)中,示出用於闡釋在其中不使用媒體的情形中表面改質部件的分配形狀的示意性剖視圖及平面影像。如圖所示,在疊層體1000的表面上不規則地分配表面改質部件2000,且聚集及連接至彼此的表面改質部件的量增加,且因此在至少一個區上可設置有膜形狀。此外,當使用具有小的大小的媒體時,如圖10(b)及圖11(b)中所示,表面改質部件2000在疊層體1000的表面上的分配較圖10(a)及圖11(a)中所示的情形更規則,且聚集及連接至彼此的表面改質部件的量減少。然而,當使用具有大的大小的媒體時,如圖10(c)及圖11(c)中所示,表面改質部件2000規則地分配於疊層體1000的表面上且以較如圖10(b)及圖11(b)中所示其中使用小的媒體的情形大的大小形成於疊層體1000的表面上。如上所述使用媒體將貼合至疊層體1000的表面的氧化物硬化,且因此可在距疊層體1000的表面預定深度處貼合所述氧化物。 Alternatively, the needle can be performed prior to forming the surface modifying component 2000 A pickling process on the surface of the laminate 1000. The dip process is a pre-step for modifying the surface of the laminate 1000, wherein the laminate 1000 can be treated to form a uniform on the surface of the laminate 1000 by using a weak acid. The pores. The voids are formed on the surface of the laminate 1000, and thus the surface modifying member 2000 can further facilitate the formation of the laminate 1000. Further, a plurality of media may be further filled together with the oxide when the surface modifying member 2000 is formed, and the oxide may be uniformly distributed by feeding the medium. That is, when the medium is not fed, the distribution of the oxide is non-uniform and thus the amount of oxides aggregated to each other may increase, but when the medium is fed, the distribution of the oxide is uniform and thus aggregates to each other. The amount of oxide can be reduced. Here, a material different from that of the laminate 1000 and the surface modifying member 2000 may be used as the medium. For example, stainless steel, ceramics, or the like can be used. Further, various shapes such as a spherical shape and a hexahedral shape may be used as the medium. Here, the total volume of the plurality of media may be greater than the total volume of the oxide powder and less than the total volume of the laminate 1000. For example, the total volume of the media can range from 10% to 90% of the total volume of the laminate 1000. In addition, the particle size and spacing of the oxide dispersed on the laminate 1000 can be adjusted according to the size of the medium, wherein as the size of the medium increases, the particle size and spacing of the oxide increase, and with the media As the size decreases, the particle size and spacing of the oxide decrease. That is, when the volume of the medium is less than 10% of the volume of the laminate 1000, the distribution state is the same as that when the medium is not used, and when the volume of the medium is larger than 90% of the volume of the laminate 1000 At the time, the amount of the oxide bonded to the surface of the medium is increased, and thus the oxide may not be coated on the surface of the laminate 1000. In Figure 10(a) and Figure In 11(a), a schematic cross-sectional view and a plan view for explaining the distribution shape of the surface modifying member in the case where the medium is not used are shown. As shown, the surface modifying member 2000 is irregularly distributed on the surface of the laminate 1000, and the amount of surface modifying members that are gathered and joined to each other is increased, and thus a film shape may be disposed on at least one of the regions. . Further, when a medium having a small size is used, as shown in FIGS. 10(b) and 11(b), the distribution of the surface modifying member 2000 on the surface of the laminate 1000 is better than that of FIG. 10(a). The situation shown in Fig. 11(a) is more regular, and the amount of surface modifying components that are gathered and connected to each other is reduced. However, when a medium having a large size is used, as shown in FIGS. 10(c) and 11(c), the surface modifying member 2000 is regularly distributed on the surface of the laminate 1000 and is as shown in FIG. (b) and the case where a small medium is used as shown in FIG. 11(b) is formed in a large size on the surface of the laminate 1000. The oxide bonded to the surface of the laminate 1000 is hardened using a medium as described above, and thus the oxide can be attached at a predetermined depth from the surface of the laminate 1000.

接著,視需要,可對疊層體1000的上面形成有表面改質部件2000的表面進行拋光(S150)。根據表面拋光而定,表面改質部件2000的一部分可被拋光,且因此表面改質部件2000可被形成為具有島形狀。可作為乾拋光製程及濕拋光製程來執行所述拋光製程。在濕拋光的情形中,可在將去離子水(deionized water,ID)水、研磨劑(abrasive)及包括形成於其上的表面改質部件2000的多個疊層體1000饋送至具有預定空間的容器中之後,以50轉/分至100轉/分的轉速來進行拋光。在乾拋光的情形中,可在將研磨劑及包括形成於其上的表面改質部件2000的多個疊層體1000 饋送至所述容器中之後,以100轉/分至200轉/分的轉速來進行拋光。亦即,可在不饋送DI水的條件下以高速進行乾拋光。此處,可使用氧化鋁作為研磨劑。此外,可依據疊層體1000、DI水及研磨劑的饋送量、研磨劑的粗糙度、拋光速度等來改變拋光時間,且因此低速濕拋光可進行超過30分鐘,且高速乾拋光可進行小於一小時。舉例而言,濕拋光可進行30分鐘至24小時,且乾拋光可進行1小時至24小時。圖12(a)至圖12(e)及圖13(a)至圖13(e)是在濕拋光及乾拋光之後疊層體的表面影像。對於圖中的每一者,圖12(a)及圖13(a)說明在拋光之前的影像,圖12(b)及圖13(b)說明在一小時的拋光之後的影像,圖12(c)及圖13(c)說明在四小時的拋光之後的影像,圖12(d)及圖13(d)說明在六小時的拋光之後的影像,且圖12(e)及圖13(e)說明在24小時拋光之後的影像。如上所示,當進行拋光製程時,可調整疊層體1000上的表面改質部件2000的大小及分配。 Next, if necessary, the surface of the surface modification member 2000 on which the upper surface of the laminate 1000 is formed may be polished (S150). Depending on the surface finish, a portion of the surface modifying member 2000 may be polished, and thus the surface modifying member 2000 may be formed to have an island shape. The polishing process can be performed as a dry polishing process and a wet polishing process. In the case of wet polishing, a plurality of stacked bodies 1000 including deionized water (ID) water, abrasive, and surface modifying member 2000 formed thereon may be fed to have a predetermined space After the container, the polishing was performed at a rotational speed of 50 rpm to 100 rpm. In the case of dry polishing, the abrasive and the plurality of laminates 1000 including the surface modifying member 2000 formed thereon may be used After feeding into the container, polishing was performed at a number of revolutions of 100 rpm to 200 rpm. That is, dry polishing can be performed at a high speed without feeding DI water. Here, alumina can be used as an abrasive. Further, the polishing time can be changed depending on the feeding amount of the laminate 1000, the DI water and the abrasive, the roughness of the abrasive, the polishing speed, and the like, and thus the low-speed wet polishing can be performed for more than 30 minutes, and the high-speed dry polishing can be performed less than One hour. For example, wet polishing can be carried out for 30 minutes to 24 hours, and dry polishing can be performed for 1 hour to 24 hours. 12(a) to 12(e) and Figs. 13(a) to 13(e) are surface images of the laminate after wet polishing and dry polishing. For each of the figures, Figures 12(a) and 13(a) illustrate the image before polishing, and Figures 12(b) and 13(b) illustrate the image after one hour of polishing, Figure 12 ( c) and Figure 13(c) illustrate the image after four hours of polishing, Figures 12(d) and 13(d) illustrate the image after six hours of polishing, and Figure 12(e) and Figure 13(e) ) Description of the image after 24 hours of polishing. As indicated above, the size and distribution of the surface modifying member 2000 on the laminate 1000 can be adjusted when the polishing process is performed.

圖14(a)至圖14(b)及圖15(a)至圖15(b)是根據示例性實施例的上面形成有表面改質部件的晶片構件的外部電極的形狀的影像及根據先前技術的不具有表面改質部件的晶片構件的外部電極的形狀的影像。相較於如圖14(b)中所示其中不形成表面改質部件的先前技術,如圖14(a)中所示其中形成有表面改質部件的示例性實施例可更對疊層體1000的表面提供絕緣性質以防止鍍覆模糊,藉此能夠控制外部電極的形狀。此為,相較於如圖15(b)中所示其中不形成表面改質部件的先前技術,如圖 15(a)中所示其中形成有表面改質部件的示例性實施例可藉由表面改質來提供表面粗糙度以在進行鍍覆時防止模糊現象。 14(a) to 14(b) and 15(a) to 15(b) are images of the shape of an external electrode of a wafer member on which a surface modifying member is formed, according to an exemplary embodiment, and according to the prior art An image of the shape of the external electrode of a wafer member that does not have a surface modifying component. An exemplary embodiment in which the surface modifying member is formed as shown in FIG. 14(a) may be more a laminate than the prior art in which the surface modifying member is not formed as shown in FIG. 14(b) The surface of 1000 provides insulating properties to prevent plating blurring, thereby enabling control of the shape of the external electrodes. This is compared to the prior art in which the surface modifying component is not formed as shown in FIG. 15(b), as shown in FIG. The exemplary embodiment in which the surface modifying member is formed as shown in 15(a) can provide surface roughness by surface modification to prevent blurring when plating is performed.

另外,為確定防水性質,將形成根據示例性實施例的其中形成有表面改質部件的多個晶片構件及根據先前技術的其中不形成表面改質部件的多個晶片構件在其中溫度為85℃且濕度為85%的環境中維持了12小時,且接著施加了5伏(V)的電壓以確定洩漏電流。此處,量測了資料線與接地線之間的洩漏電流(交叉IL)及各資料線之間的洩漏電流(IL),且將當有10奈安(nA)或高於10奈安的電流流動時的情形確定為缺陷。表1中示出根據示例性實施例及先前技術實施例的防水性質的結果。 In addition, in order to determine the waterproof property, a plurality of wafer members in which the surface modifying member is formed according to an exemplary embodiment and a plurality of wafer members in which the surface modifying member is not formed according to the prior art are formed in which the temperature is 85 ° C The environment was maintained for 12 hours in an environment with a humidity of 85%, and then a voltage of 5 volts (V) was applied to determine the leakage current. Here, the leakage current (crossing IL) between the data line and the ground line and the leakage current (IL) between each data line are measured, and will be 10 nanoamperes (nA) or higher than 10 nanoamperes. The situation when the current flows is determined as a defect. The results of the waterproof properties according to the exemplary embodiments and prior art embodiments are shown in Table 1.

如上所述,未偵測到洩漏電流且因此根據示例性實施例的其中形成有表面改質部件的晶片構件中未出現任何缺陷,但在根據先前技術的其中不形成表面改質部件的晶片構件中出現了3%至18%的缺陷率。亦即,在先前技術的情形中,由於資料線與接地線之間出現了近似3%的洩漏電流,因此此被確定為缺陷。此外,由於各資料線之間出現了近似18%的洩漏電流,因此此被確定為缺陷。此外,在其中出現了缺陷的晶片構件中,量測到的洩 漏電流介於幾十奈安至短接(short)範圍內。因此,根據示例性實施例,可形成表面改質部件以改善晶片構件的防水性質且因此提高所述晶片構件的壽命及可靠性。 As described above, no leakage current is detected and thus no defect occurs in the wafer member in which the surface modifying member is formed according to the exemplary embodiment, but in the wafer member in which the surface modifying member is not formed according to the prior art A defect rate of 3% to 18% has occurred. That is, in the case of the prior art, since a leakage current of approximately 3% occurred between the data line and the ground line, this was determined as a defect. In addition, this was determined to be a defect due to a leakage current of approximately 18% between the data lines. In addition, in the wafer member in which the defect has occurred, the measured leak Leakage currents range from tens of nanometers to shorts. Thus, according to an exemplary embodiment, a surface modifying component may be formed to improve the waterproof property of the wafer member and thus improve the life and reliability of the wafer component.

在根據示例性實施例的晶片構件中,將表面改質部件設置於疊層體上,且因此可控制外部電極的形狀。亦即,表面改質部件設置於疊層體的表面上以使所述疊層體的所述表面改質,且因此可防止因鍍覆而造成的外部電極的模糊現象及攤開現象,且因此可輕易控制外部電極的形狀。 In the wafer member according to the exemplary embodiment, the surface modifying member is disposed on the laminate, and thus the shape of the external electrode can be controlled. That is, the surface modifying member is disposed on the surface of the laminate to modify the surface of the laminate, and thus the blurring and spreading of the external electrodes due to plating can be prevented, and Therefore, the shape of the external electrode can be easily controlled.

另外,可提供表面改質部件以防止水分滲透至疊層體中,且因此可提高晶片構件的壽命及可靠性。 In addition, a surface modifying member can be provided to prevent moisture from penetrating into the laminate, and thus the life and reliability of the wafer member can be improved.

儘管已關於以上實施例具體闡述了本發明的技術理念,然而應注意,上述實施例僅供用於說明而非限制本發明。此外,熟習此項技術者將理解,在本發明的技術理念範圍內可作出各種實施例。 While the technical concept of the present invention has been specifically described with respect to the above embodiments, it should be noted that the above-described embodiments are merely illustrative and not limiting. Further, those skilled in the art will understand that various embodiments can be made within the scope of the technical idea of the present invention.

Claims (21)

一種晶片構件,包括:疊層體;以及表面改質部件,設置於所述疊層體的至少一個區域上,其中所述表面改質部件被配置成分散於所述疊層體的所述表面上且暴露出所述疊層體的表面的至少一部分。 A wafer member comprising: a laminate; and a surface modifying member disposed on at least one region of the laminate, wherein the surface modifying member is configured to be dispersed on the surface of the laminate At least a portion of the surface of the laminate is exposed and exposed. 如申請專利範圍第1項所述的晶片構件,其中所述疊層體包括多個疊層片材,且在所述疊層體內設置有與所述片材不同的異質材料層。 The wafer member according to claim 1, wherein the laminate comprises a plurality of laminated sheets, and a layer of a heterogeneous material different from the sheet is disposed in the laminate. 如申請專利範圍第2項所述的晶片構件,其中所述異質材料層包括導電圖案,所述導電圖案具有預定形狀並具有用於防止過電壓的材料層。 The wafer member of claim 2, wherein the heterogeneous material layer comprises a conductive pattern having a predetermined shape and having a material layer for preventing an overvoltage. 如申請專利範圍第1項所述的晶片構件,其中所述表面改質部件以佔所述疊層體的表面積的5%至90%的表面積分佈。 The wafer member according to claim 1, wherein the surface modifying member is distributed in a surface area of 5% to 90% of the surface area of the laminate. 如申請專利範圍第4項所述的晶片構件,其中所述表面改質部件包含晶體狀態的氧化物與非晶體狀態的氧化物中的至少一者。 The wafer member according to claim 4, wherein the surface modifying member comprises at least one of an oxide in a crystalline state and an oxide in an amorphous state. 如申請專利範圍第5項所述的晶片構件,其中所述氧化物包括以下中的至少一者:Bi2O3、BO2、B2O3、ZnO、Co3O4、SiO2、Al2O3、MnO、H2BO3、Ca(CO3)2、Ca(NO3)2及CaCO3The wafer member of claim 5, wherein the oxide comprises at least one of the following: Bi 2 O 3 , BO 2 , B 2 O 3 , ZnO, Co 3 O 4 , SiO 2 , Al 2 O 3 , MnO, H 2 BO 3 , Ca(CO 3 ) 2 , Ca(NO 3 ) 2 and CaCO 3 . 如申請專利範圍第6項所述的晶片構件,其中所述氧化物的至少一部分嵌入所述疊層體的所述表面中。 The wafer member of claim 6, wherein at least a portion of the oxide is embedded in the surface of the laminate. 如申請專利範圍第6項所述的晶片構件,其中所述氧化物包括具有至少一或多種粒徑的微粒,所述具有至少一或多種粒徑的微粒在至少一個區中聚集或連接至彼此。 The wafer member of claim 6, wherein the oxide comprises particles having at least one or more particle sizes, the particles having at least one or more particle sizes being aggregated or connected to each other in at least one region . 如申請專利範圍第6項所述的晶片構件,其中所述氧化物的所述微粒具有0.1微米至10微米的平均粒徑。 The wafer member of claim 6, wherein the particles of the oxide have an average particle diameter of from 0.1 micrometer to 10 micrometers. 如申請專利範圍第1項所述的晶片構件,更包括界定於所述疊層體的所述表面的至少一部分中的凹陷部。 The wafer member of claim 1, further comprising a recess defined in at least a portion of the surface of the laminate. 如申請專利範圍第1項至第10項中任一項所述的晶片構件,更包括設置於所述疊層體中的第二表面改質部件。 The wafer member according to any one of claims 1 to 10, further comprising a second surface modifying member disposed in the laminate. 如申請專利範圍第11項所述的晶片構件,其中所述第二表面改質部件設置於構成所述疊層體的至少一個片材上。 The wafer member according to claim 11, wherein the second surface modifying member is disposed on at least one of the sheets constituting the laminate. 一種晶片構件,包括:疊層體,在所述疊層體中疊層有多個片材;異質材料層,設置於所述疊層體中且由與所述片材中的每一者的材料不同的材料製成;外部電極,設置於所述疊層體的至少一個表面上,以及表面改質部件,配置成分散在疊層體的表面上且暴露出所述疊層體的所述表面的至少一部分。 A wafer member comprising: a laminate in which a plurality of sheets are laminated; a layer of a heterogeneous material disposed in the laminate and composed of each of the sheets The material is made of a different material; the external electrode is disposed on at least one surface of the laminate, and the surface modifying member is configured to be dispersed on the surface of the laminate and expose the surface of the laminate At least part of it. 如申請專利範圍第13項所述的晶片構件,其中所述表面改質部件包含氧化物。 The wafer member of claim 13, wherein the surface modifying component comprises an oxide. 如申請專利範圍第14項所述的晶片構件,其中所述氧化物具有等於所述疊層體的厚度的0.01%至10%的厚度。 The wafer member according to claim 14, wherein the oxide has a thickness equal to 0.01% to 10% of a thickness of the laminate. 一種製造晶片構件的方法,包括:製備多個晶片構件;以及在所述多個晶片構件的至少一個表面上依序形成表面改質部件和外部電極,其中所述表面改質部件被分散在所述晶片構件的所述表面的至少一部分並暴露出所述晶片構件的所述表面的至少一部分。 A method of manufacturing a wafer member, comprising: preparing a plurality of wafer members; and sequentially forming a surface modifying member and an external electrode on at least one surface of the plurality of wafer members, wherein the surface modifying member is dispersed At least a portion of the surface of the wafer member and exposing at least a portion of the surface of the wafer member. 如申請專利範圍第16項所述的方法,其中將所述多個晶片構件及氧化物粉末饋送至容器中並旋轉以形成所述表面改質部件。 The method of claim 16, wherein the plurality of wafer members and oxide powder are fed into a container and rotated to form the surface modifying member. 如申請專利範圍第17項所述的方法,其中更與所述多個晶片構件及所述氧化物粉末一起饋送多種媒體。 The method of claim 17, wherein the plurality of media are further fed together with the plurality of wafer members and the oxide powder. 如申請專利範圍第18項所述的方法,其中所述多種媒體是由與所述晶片構件及所述氧化物粉末的材料不同的材料製成。 The method of claim 18, wherein the plurality of media are made of a material different from a material of the wafer member and the oxide powder. 如申請專利範圍第19項所述的方法,其中所述多種媒體的總體積大於所述氧化物粉末的總體積且小於所述多個疊層體的總體積。 The method of claim 19, wherein the total volume of the plurality of media is greater than a total volume of the oxide powder and less than a total volume of the plurality of laminates. 如申請專利範圍第16項至第20項中任一項所述的方法,更包括以下中的至少一個製程:在形成所述表面改質部件之前執行浸洗處理,以及在形成所述表面改質部件之後對所述晶片構件執行表面拋光。 The method of any one of claims 16 to 20, further comprising at least one of the following: performing a dipping process prior to forming the surface modifying component, and forming the surface modification Surface polishing is performed on the wafer member after the material component.
TW106121501A 2016-07-01 2017-06-28 Chip component and method of manufacturing the same TWI645532B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
??10-2016-0083680 2016-07-01
KR1020160083680A KR101825696B1 (en) 2016-07-01 2016-07-01 Chip component and method of manufacturing the same

Publications (2)

Publication Number Publication Date
TW201807798A TW201807798A (en) 2018-03-01
TWI645532B true TWI645532B (en) 2018-12-21

Family

ID=60787063

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106121501A TWI645532B (en) 2016-07-01 2017-06-28 Chip component and method of manufacturing the same

Country Status (4)

Country Link
KR (1) KR101825696B1 (en)
CN (1) CN109478465B (en)
TW (1) TWI645532B (en)
WO (1) WO2018004276A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023084858A1 (en) * 2021-11-09 2023-05-19 株式会社村田製作所 Electronic component

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339068A (en) * 1992-12-18 1994-08-16 Mitsubishi Materials Corp. Conductive chip-type ceramic element and method of manufacture thereof
US20060158824A1 (en) * 2003-03-31 2006-07-20 Keiji Kawajiri Composite electronic component
US20060249811A1 (en) * 2003-01-21 2006-11-09 Tdk Corporation Composition for thin film capacitance element, insulating film of high dielectric constant, thin film capacitance element, thin film laminated capacitor and method for manufacturing thin film capacitance element
TW200934305A (en) * 2007-10-01 2009-08-01 Innochips Technology Co Ltd Circuit protection device
US20110141660A1 (en) * 2009-12-10 2011-06-16 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06295803A (en) * 1993-04-07 1994-10-21 Mitsubishi Materials Corp Chip type thermister and production thereof
JP5267511B2 (en) * 2010-06-23 2013-08-21 Tdk株式会社 Electronic components
KR101580350B1 (en) * 2012-06-04 2015-12-23 삼성전기주식회사 Multilayered ceramic elements
KR101792275B1 (en) * 2012-08-22 2017-11-01 삼성전기주식회사 Conductive paste for internal electrode, multilayer ceramic components using the same and manufacturing method of the same
JP5915813B2 (en) * 2013-03-19 2016-05-11 株式会社村田製作所 Multilayer ceramic electronic components
KR102315812B1 (en) * 2014-12-15 2021-10-21 (주)아모텍 Circuit protection device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339068A (en) * 1992-12-18 1994-08-16 Mitsubishi Materials Corp. Conductive chip-type ceramic element and method of manufacture thereof
US20060249811A1 (en) * 2003-01-21 2006-11-09 Tdk Corporation Composition for thin film capacitance element, insulating film of high dielectric constant, thin film capacitance element, thin film laminated capacitor and method for manufacturing thin film capacitance element
US20060158824A1 (en) * 2003-03-31 2006-07-20 Keiji Kawajiri Composite electronic component
TW200934305A (en) * 2007-10-01 2009-08-01 Innochips Technology Co Ltd Circuit protection device
US20110141660A1 (en) * 2009-12-10 2011-06-16 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor

Also Published As

Publication number Publication date
TW201807798A (en) 2018-03-01
CN109478465B (en) 2021-02-26
KR101825696B1 (en) 2018-02-05
KR20180003910A (en) 2018-01-10
WO2018004276A1 (en) 2018-01-04
CN109478465A (en) 2019-03-15

Similar Documents

Publication Publication Date Title
US9583251B2 (en) Chip electronic component and board having the same
CN104021937B (en) Laminated ceramic electronic component and its manufacture method
JP6016637B2 (en) Capacitor including a three-dimensional electrode having a large surface area and manufacturing method
TWI544507B (en) Embedded multilayer ceramic electronic component and printed circuit board having the same
JP2018098278A (en) Coil component
US20150109088A1 (en) Chip electronic component and manufacturing method thereof
JP2014209550A (en) Ceramic electronic component and glass paste
JP2010258223A (en) Multilayer ceramic electronic component
EP3460812B1 (en) Element for protecting circuit
KR20200104841A (en) Multilayer capacitor
KR102216555B1 (en) Circuit protection device
JP2017073539A (en) Electronic component
US20140226254A1 (en) Conductive paste composition, multilayer ceramic capacitor using the same, and method of manufacturing multilayer ceramic capacitor using the same
TWI645532B (en) Chip component and method of manufacturing the same
CN103177875B (en) Monolithic ceramic electronic component
KR101949442B1 (en) Complex component and electronic device having the same
KR20180101048A (en) Laminate type device
US9667036B2 (en) ESD protection component
JP4111340B2 (en) Chip-type electronic components
KR102053355B1 (en) Laminated component and electronic device having the same
KR101789243B1 (en) Complex protection device and electronic device having the same
KR101934084B1 (en) Complex component and electronic device having the same
KR101444613B1 (en) Composite conductive powder, Paste compound for termination electrode and manufacturing method of multilayer ceramic capacitor
JP3038296B2 (en) Electronic component manufacturing method
KR20180044018A (en) Circuit protection device