JPH06295803A - Chip type thermister and production thereof - Google Patents

Chip type thermister and production thereof

Info

Publication number
JPH06295803A
JPH06295803A JP5080471A JP8047193A JPH06295803A JP H06295803 A JPH06295803 A JP H06295803A JP 5080471 A JP5080471 A JP 5080471A JP 8047193 A JP8047193 A JP 8047193A JP H06295803 A JPH06295803 A JP H06295803A
Authority
JP
Japan
Prior art keywords
electrode
thermistor
element body
inorganic
thermistor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5080471A
Other languages
Japanese (ja)
Inventor
Hiroaki Nakajima
弘明 中島
Masami Koshimura
正己 越村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP5080471A priority Critical patent/JPH06295803A/en
Priority to KR1019930010430A priority patent/KR100204255B1/en
Priority to US08/079,347 priority patent/US5339068A/en
Publication of JPH06295803A publication Critical patent/JPH06295803A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C17/00Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/28Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/02Housing; Enclosing; Embedding; Filling the housing or enclosure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/14Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Thermistors And Varistors (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Details Of Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PURPOSE:To produce a highly reliable chip type thermister excellent in solderability and soldering heat resistance in which fluctuation of resistance due to plating of enclosing electrode is suppressed easily at low cost. CONSTITUTION:A chip body stamped out from a green sheet for thermister is fired to produce a thermister body 10 and internal electrodes 11 are formed at the opposite ends of the body 10 while wrapping them. The body 10 is then coated with a dielectric inorganic layer 14 of 0.1-10mum thick over the entire surface thereof. A conductive paste containing a metal powder and an inorganic coupler is applied to the opposite end parts of the body 10 while wrapping them over an area smaller than the internal electrode and then the paste is fired at a temperature lower than the melting point or softening point of the inorganic layer. Consequently, a part of the underlying inorganic layer is fused to the inorganic coupler in the paste thus forming an external electrode 16. Subsequently, plating layers 18, 19 are formed on the surface of the external electrode.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種電子機器の温度補
償用のセンサに、また表面温度測定用のセンサにそれぞ
れ適するチップ型サーミスタに関する。更に詳しくは、
プリント回路基板等に表面実装されるチップ型のNTC
サーミスタ、PTCサーミスタ等のサーミスタ及びその
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type thermistor suitable for a sensor for temperature compensation of various electronic devices and a sensor for measuring a surface temperature. For more details,
Chip-type NTC that is surface-mounted on a printed circuit board, etc.
The present invention relates to a thermistor such as a thermistor and a PTC thermistor, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来、チップ型サーミスタは、サーミス
タ素体の両端部に銀−パラジウムを主成分とする端子電
極が焼付けられている。電極成分に銀の他にパラジウム
を含有する理由は、基板にチップ型サーミスタをはんだ
付けする際に、銀がはんだ中に溶出して消失することを
防止し、電極のはんだ耐熱性を得るためである。しか
し、パラジウムの含有量を増加すると電極のはんだ付着
性が低下して基板へのサーミスタの固着力が弱くなるた
め、パラジウムの含有量には一定の限界があった。この
ため電極のはんだ付けが高温で長時間行われる場合に
は、従来のチップ型サーミスタはなおはんだ耐熱性が不
十分であった。
2. Description of the Related Art Conventionally, in a chip type thermistor, terminal electrodes containing silver-palladium as a main component are printed on both ends of a thermistor body. The reason for containing palladium in addition to silver in the electrode component is to prevent the silver from eluting and disappearing in the solder when soldering the chip type thermistor to the substrate, and to obtain the solder heat resistance of the electrode. is there. However, when the palladium content is increased, the solder adhesion of the electrode is reduced and the thermistor adhesion to the substrate is weakened, so the palladium content has a certain limit. Therefore, when the electrodes are soldered at a high temperature for a long time, the conventional chip type thermistor still has insufficient solder heat resistance.

【0003】このはんだ耐熱性とはんだ付着性を向上さ
せるために、チップ型コンデンサと同様に、焼付け電極
の表面にめっき層を設けることが考えられるが、サーミ
スタ素体はコンデンサ用のセラミック素体と異なり導電
性を有するため、このサーミスタ素体を露出したままめ
っき処理した場合、素体表面にめっきが付着してサーミ
スタの抵抗値が所期の値と異なり、しかもサーミスタ素
体がめっき液で浸食されてサーミスタの信頼性が低下す
る等の不具合を生じる。
In order to improve the solder heat resistance and the solder adhesion, it is conceivable to provide a plating layer on the surface of the baking electrode as in the case of the chip type capacitor. However, the thermistor element body is a ceramic element body for capacitors. Since the thermistor element has different conductivity, if the thermistor element is plated with the element exposed, plating will adhere to the element surface and the resistance of the thermistor will be different from the desired value, and the thermistor element will be eroded by the plating solution. As a result, the reliability of the thermistor is deteriorated and other problems occur.

【0004】このめっき処理時の不具合を解消し、端子
電極の材料を広く選定し得ることを目的として、本出願
人は両端面に内包電極を形成したサーミスタ素体の全面
を絶縁性無機物層で被覆した後、このサーミスタ素体の
両端部を外包電極で包込み、更にこの外包電極の表面に
めっき層を形成したチップ型サーミスタを特許出願した
(特願平3−355048)。このサーミスタの絶縁性
無機物層は外包電極を形成するときの焼成温度より高い
融点又は軟化点を有し、外包電極の形成時にその導電性
ペーストの下地部分に相当する無機物層の一部が導電性
ペーストに含まれる無機結合材に反応溶融して外包電極
に吸収され消滅するように構成される。この外包電極に
吸収消滅させるために、無機物層は2〜10μmの極薄
の厚さに形成される。
For the purpose of eliminating the problem at the time of the plating treatment and allowing a wide selection of materials for the terminal electrodes, the applicant of the present invention has formed an insulating inorganic material layer over the entire surface of the thermistor element body having internal electrodes formed on both end surfaces. After coating, both ends of this thermistor body were wrapped with an outer envelope electrode, and a chip type thermistor in which a plating layer was formed on the surface of the outer envelope electrode was applied for a patent (Japanese Patent Application No. 3-355048). The insulating inorganic material layer of this thermistor has a melting point or a softening point higher than the firing temperature when forming the outer envelope electrode, and when forming the outer envelope electrode, a part of the inorganic layer corresponding to the base portion of the conductive paste is conductive. The inorganic binder contained in the paste is melted by reaction and absorbed by the outer envelope electrode to disappear. The inorganic layer is formed to have an extremely thin thickness of 2 to 10 μm in order to absorb and extinguish it by the outer envelope electrode.

【0005】[0005]

【発明が解決しようとする課題】しかし、上記チップ型
サーミスタには次の問題点があった。 (a) 製造条件等のばらつきにより絶縁性無機物層の厚さ
が2μm未満になった場合には、外包電極を形成すると
きにサーミスタ素体の端部包込み部分の無機結合材が無
機物層と溶融して外包電極の端部包込み部分がサーミス
タ素体に直接接触し、サーミスタ素体と電気的に導通す
るため、チップ型サーミスタの抵抗値にばらつきが生じ
る。 (b) これにより絶縁性無機物層の厚さは2μm以上に限
定され、しかも無機物層の厚さが2μm以上であって
も、導電性ペーストに含まれる無機結合材の種類及び無
機物層の種類によっては、なお同様の現象がみられ、サ
ーミスタの抵抗値がばらつくことがある。
However, the above-mentioned chip type thermistor has the following problems. (a) When the thickness of the insulating inorganic material layer is less than 2 μm due to variations in manufacturing conditions, etc., the inorganic binder in the end-encapsulating portion of the thermistor element is not compatible with the inorganic material layer when forming the outer envelope electrode. Since the end-wrapped portion of the outer-wrapping electrode comes into direct contact with the thermistor element body after being melted and electrically connected to the thermistor element body, the resistance value of the chip type thermistor varies. (b) As a result, the thickness of the insulating inorganic material layer is limited to 2 μm or more, and even if the thickness of the inorganic material layer is 2 μm or more, depending on the type of the inorganic binder contained in the conductive paste and the type of the inorganic material layer. The same phenomenon is still observed, and the resistance value of the thermistor may vary.

【0006】(c) また2μm厚を越える無機物層の全面
形成はこれをスパッタリングにより形成する場合には、
無機物層の形成時間が長くなりサーミスタの生産性に劣
る。 (d) 更に無機物層の厚さが適切であって外包電極の端部
包込み部分がサーミスタ素体に直接接触しない場合に
は、サーミスタ素体への内包電極の接触面積がサーミス
タの抵抗値を決定するが、この内包電極がサーミスタ素
体の両端面にのみ有するため、サーミスタ素体の寸法に
ばらつきが生じたり、内包電極形成時にその導電性ペー
ストが端面から側面に垂れ込んだ場合には、サーミスタ
の抵抗値が所期の値とずれ易い。
(C) Further, when the inorganic layer having a thickness of more than 2 μm is formed on the entire surface by sputtering,
The formation time of the inorganic layer becomes long and the productivity of the thermistor is poor. (d) If the thickness of the inorganic layer is appropriate and the end-wrapping part of the outer-wrapping electrode does not directly contact the thermistor body, the contact area of the inner-wrapping electrode with the thermistor body determines the resistance value of the thermistor. Although it is determined, since this internal electrode has only the both end surfaces of the thermistor element body, variations occur in the dimensions of the thermistor element body, or when the conductive paste drips from the end surface to the side surface during the formation of the internal electrode, The resistance value of the thermistor tends to deviate from the expected value.

【0007】本発明の目的は、はんだ耐熱性及びはんだ
付着性に優れ、電極のめっき処理による抵抗値の変化が
なく、信頼性の高いチップ型サーミスタを提供すること
にある。本発明の別の目的は導電性のあるサーミスタ素
体の両端部の電極にめっき処理を行っても所期の特性が
得られるチップ型サーミスタを提供することにある。
An object of the present invention is to provide a chip type thermistor which is excellent in solder heat resistance and solder adhesion, has no change in resistance value due to electrode plating, and has high reliability. Another object of the present invention is to provide a chip type thermistor which can obtain desired characteristics even if electrodes on both ends of a conductive thermistor body are plated.

【0008】本発明の別の目的は抵抗値のばらつきが小
さく、外包電極の材料を広く選定できるチップ型サーミ
スタを提供することにある。本発明の更に別の目的は、
上記優れたチップ型サーミスタを比較的容易にかつ安価
に製造でき、量産に適するチップ型サーミスタの製造方
法を提供することにある。
Another object of the present invention is to provide a chip type thermistor in which variations in resistance value are small and the material of the outer envelope electrode can be widely selected. Still another object of the present invention is to
It is an object of the present invention to provide a method for manufacturing a chip-type thermistor suitable for mass production, in which the excellent chip-type thermistor can be manufactured relatively easily and inexpensively.

【0009】[0009]

【問題点を解決するための手段】図1及び図2に示すよ
うに、本発明のチップ型サーミスタは、サーミスタ素体
10と、このサーミスタ素体10の両端部に設けられた
内包電極11と、この内包電極11が形成されたサーミ
スタ素体10の全面を被覆する絶縁性無機物層14と、
この無機物層14を被覆したサーミスタ素体10の両端
部に設けられた外包電極16と、この外包電極16の表
面に形成されためっき層18,19とを備える。そして
その特徴ある構成は、内包電極11がサーミスタ素体1
0の両端部を包込むように形成され、外包電極16が金
属粉末と無機結合材を含む導電性ペーストを内包電極1
1より少ない包込み面積でサーミスタ素体10の両端部
を包込むように塗布して焼付けることにより形成され、
無機物層14は厚さが0.1〜10μmであって、外包
電極16を形成する時の焼成温度より高い融点又は軟化
点を有し、かつそのペーストの下地部分の無機物層の一
部が外包電極16の形成時に無機結合材に反応溶融して
外包電極16に吸収され消滅したことにある。
As shown in FIGS. 1 and 2, a chip type thermistor of the present invention comprises a thermistor body 10 and internal electrodes 11 provided at both ends of the thermistor body 10. An insulating inorganic material layer 14 covering the entire surface of the thermistor element body 10 on which the internal electrode 11 is formed,
The thermistor element body 10 covering the inorganic layer 14 is provided with outer envelope electrodes 16 provided at both ends, and plating layers 18 and 19 formed on the surfaces of the outer envelope electrode 16. The characteristic configuration is that the internal electrode 11 has the thermistor element body 1.
0 is formed so as to enclose both ends, and the outer envelope electrode 16 includes a conductive paste containing a metal powder and an inorganic binding material.
It is formed by coating and baking both ends of the thermistor element body 10 with a wrapping area less than 1.
The inorganic layer 14 has a thickness of 0.1 to 10 μm, has a melting point or a softening point higher than the firing temperature for forming the outer envelope electrode 16, and a part of the inorganic layer of the base portion of the paste is the outer envelope. This is because when the electrode 16 was formed, it was reacted and melted with the inorganic binder to be absorbed by the outer envelope electrode 16 and disappeared.

【0010】図3〜図6に示すように、本発明のチップ
型サーミスタの製造方法は、金属酸化物粉末と結合材と
を混合してスラリーを調製する工程と、このスラリーを
成膜乾燥してグリーンシートを形成する工程と、このグ
リーンシートからチップ体2を打抜く工程と、このチッ
プ体2を焼成してサーミスタ素体10にする工程と、こ
のサーミスタ素体10の両端面にこの両端部を包込むよ
うに内包電極11を形成する工程と、この内包電極11
が形成されたサーミスタ素体10の全面に厚さ0.1〜
10μmの絶縁性無機物層14を被覆する工程と、この
無機物層14を被覆したサーミスタ素体10の両端部に
金属粉末と無機結合材32を含む導電性ペースト30を
内包電極11より少ない包込み面積でその両端部を包込
むように塗布する工程と、このペースト30を塗布した
サーミスタ素体10を無機物層14の融点又は軟化点よ
り低い温度で焼成し、塗布したペーストの無機結合材3
2にそのペーストの下地部分の無機物層の一部を反応溶
融させることにより消滅させて外包電極16を形成する
工程と、この外包電極16の表面にめっき層18,19
を形成する工程とを含む方法である。
As shown in FIGS. 3 to 6, the method of manufacturing a chip type thermistor according to the present invention comprises the steps of preparing a slurry by mixing a metal oxide powder and a binder, and drying the slurry to form a film. To form a green sheet, a step of punching the chip body 2 from the green sheet, a step of firing the chip body 2 to form the thermistor body 10, and the both ends on both end faces of the thermistor body 10. Of forming the internal electrode 11 so as to enclose the part, and the internal electrode 11
The thermistor element body 10 having the formed
A step of coating the insulating inorganic layer 14 of 10 μm, and a wrapping area smaller than that of the inclusion electrode 11 with the conductive paste 30 containing the metal powder and the inorganic binder 32 at both ends of the thermistor element body 10 coated with the inorganic layer 14. And the step of applying so as to wrap both ends thereof, and the thermistor element body 10 applied with this paste 30 is fired at a temperature lower than the melting point or softening point of the inorganic material layer 14 to apply the inorganic binder 3 of the applied paste.
2, a step of extinguishing a part of the inorganic layer of the base portion of the paste by reaction melting to form the outer envelope electrode 16, and plating layers 18, 19 on the surface of the outer envelope electrode 16.
And a step of forming.

【0011】以下、本発明を詳述する。 (a) サーミスタ素体の製造 本発明のサーミスタ素体は次の方法により作られる。先
ずMn,Fe,Co,Ni,Cu,Al等の金属の酸化
物粉末を1種又は2種以上採取して混合する。2種以上
混合するときは、所定の金属原子比になるように各金属
酸化物を秤量する。この混合物を仮焼し粉砕した後、有
機結合材及び溶剤を加え混練してスラリーを調製する。
次いでこのスラリーをドクターブレード法等により成膜
乾燥してグリーンシートを形成する。このグリーンシー
トから図3(a)に示すチップ体2を打抜き、これを焼
成して図3(b)に示すチップ状のサーミスタ素体10
を得る。
The present invention will be described in detail below. (a) Production of thermistor element body The thermistor element body of the present invention is produced by the following method. First, one kind or two or more kinds of oxide powders of metals such as Mn, Fe, Co, Ni, Cu and Al are sampled and mixed. When two or more kinds are mixed, each metal oxide is weighed so as to have a predetermined metal atomic ratio. After calcining and pulverizing this mixture, an organic binder and a solvent are added and kneaded to prepare a slurry.
Then, this slurry is dried by a doctor blade method or the like to form a green sheet. A chip body 2 shown in FIG. 3A is punched out from this green sheet, and is fired to form a chip-like thermistor body 10 shown in FIG. 3B.
To get

【0012】(b) 内包電極の形成 図3(c)に示すようにサーミスタ素体の両端部にこの
両端部を包込むように導電性ペーストを塗布した後、乾
燥し焼付けることにより内包電極11を形成する。この
塗布は導電性ペースト中にサーミスタ素体の両端部を浸
漬させるディッピング法が好ましい。このペースト中に
含まれる金属粉末はサーミスタ素体10と導電性を維持
するものであれば特に制限されない。これを例示すれ
ば、Ag,Au,Pd,Pt等の貴金属、又はこれらを
混合した粉末が挙げられる。
(B) Formation of Encapsulating Electrode As shown in FIG. 3 (c), the conductive paste is applied to both ends of the thermistor element body so as to wrap both ends, and then the encapsulating electrode is dried and baked. 11 is formed. The application is preferably a dipping method in which both ends of the thermistor element body are dipped in a conductive paste. The metal powder contained in this paste is not particularly limited as long as it maintains conductivity with the thermistor element body 10. Examples of this include noble metals such as Ag, Au, Pd and Pt, or powders obtained by mixing these.

【0013】(c) サーミスタ素体への絶縁性無機物層の
被覆 内包電極11が形成されたサーミスタ素体10はその全
面に厚さ0.1〜10μmの絶縁性無機物層が被覆され
る(図3(d))。10μmより厚いと、後述する外包
電極の形成時に溶融した無機物層が外包電極中に完全に
吸収されず、無機物層が外包電極と内包電極の界面に絶
縁性皮膜として残留するため外包電極と内包電極とが導
通しない。また0.1μmより薄いと、後述するめっき
処理に際して、まためっき処理後のサーミスタ素体の保
護機能に劣る。この絶縁性無機物層14(図1及び図
2)を例示すると、SiO2膜、又は50重量%以上の
SiO2と残部がAl23,MgO,ZrO2及びTiO
2の1種又は2種以上の酸化物により構成された薄膜、
或いはSiO2,B23,Na2O,PbO,ZnO及び
BaOの1種又は2種以上の酸化物を主成分とするガラ
スにより構成された薄膜が挙げられる。この無機物層1
4は後述する外包電極を形成するときの焼成温度より高
い融点又は軟化点を有することが必要である。例えば、
外包電極としてAgのペーストを焼付ける場合にはその
焼成温度は600〜850℃であるため、この温度より
高い融点又は軟化点を有するものが選ばれる。この理由
はペーストの焼付け温度より融点又は軟化点が大幅に低
いと、ペースト焼付け時に無機物層が電極表面に浮き上
がったり、或いはサーミスタ素体同士又は素体と焼成治
具との貼り付きが生じて歩留りが低下し易いからであ
る。
(C) Coating of Insulating Inorganic Material Layer on Thermistor Element Body The entire surface of the thermistor element body 10 on which the inclusion electrode 11 is formed is coated with an insulating inorganic material layer having a thickness of 0.1 to 10 μm (see FIG. 3 (d)). When the thickness is more than 10 μm, the inorganic layer melted during the formation of the external electrode described later is not completely absorbed in the external electrode, and the inorganic layer remains as an insulating film at the interface between the external electrode and the internal electrode, so that the external electrode and the internal electrode And do not connect. When the thickness is less than 0.1 μm, the function of protecting the thermistor element during the plating treatment described later and after the plating treatment is poor. As an example of this insulating inorganic material layer 14 (FIGS. 1 and 2), a SiO 2 film, or 50 wt% or more of SiO 2 and the balance of Al 2 O 3 , MgO, ZrO 2 and TiO 2 is used.
Thin film composed of one or more oxides of 2,
Alternatively, a thin film made of glass containing one or more oxides of SiO 2 , B 2 O 3 , Na 2 O, PbO, ZnO and BaO as a main component may be mentioned. This inorganic layer 1
No. 4 needs to have a melting point or softening point higher than the firing temperature when forming the envelope electrode described later. For example,
When an Ag paste is baked as the envelope electrode, the baking temperature is 600 to 850 ° C., and therefore a material having a melting point or a softening point higher than this temperature is selected. The reason for this is that if the melting point or softening point is significantly lower than the baking temperature of the paste, the inorganic material layer floats up on the electrode surface during paste baking, or the thermistor element bodies or the element body and the firing jig adhere to each other and yield increases. Is easily reduced.

【0014】無機物層14は、この要件以外は耐めっき
性があって、後述する導電性ペーストに含まれる無機結
合材と反応して溶融する性質を有するものであれば特に
制限はなく、結晶質であっても非結晶質であってもよ
い。しかし、上記ガラスが結晶質であって、無機物層1
4を結晶化ガラスにするとサーミスタの抗折強度が高ま
り好ましい。このサーミスタ素体への無機物層の被覆は
真空蒸着法、スッパタリング法、イオンプレーティング
法のような物理蒸着法(PVD法)又は化学蒸着法(C
VD法)により行われる。この中でスパッタリング法が
量産に適しているため好ましい。この方法で量産するに
は、図4に示すように水平軸20を中心に回動可能なス
テンレススチール製の篭22を用意し、この中に多数の
サーミスタ素体10を収納する。この篭22を図示しな
いスパッタリング装置内に入れる。装置内には所期の無
機物層を得るためのターゲット24を装着しておく。例
えば、無機物層がSiO2膜であれば石英ガラスを用
い、またSiO2,Al23,MgO,ZrO2,TiO
2,B23,Na2O,PbO,ZnO,BaO等の複合
酸化物膜であれば、これらを粉末冶金でディスク状に成
形するか、或いはこれらを溶融後冷却しディスク状の複
合ガラスにして用いる。水平軸20を中心に篭22を揺
動させながらスパッタリングを実施すると、ターゲット
24から叩き出されたターゲット材料がサーミスタ素体
10の全面に凝縮し、ターゲット材料からなる無機物層
14が形成される。
Other than this requirement, the inorganic layer 14 is not particularly limited as long as it has resistance to plating and has a property of reacting with an inorganic binder contained in a conductive paste described later and melting. Or may be amorphous. However, the glass is crystalline and the inorganic layer 1
When 4 is crystallized glass, the bending strength of the thermistor is increased, which is preferable. The thermistor body is coated with an inorganic layer by a physical vapor deposition method (PVD method) such as a vacuum vapor deposition method, a sputtering method, an ion plating method, or a chemical vapor deposition method (C).
VD method). Among these, the sputtering method is preferable because it is suitable for mass production. For mass production by this method, as shown in FIG. 4, a stainless steel basket 22 rotatable around a horizontal shaft 20 is prepared, and a large number of thermistor bodies 10 are housed therein. The basket 22 is put in a sputtering device (not shown). A target 24 for obtaining a desired inorganic layer is mounted in the apparatus. For example, if the inorganic layer is a SiO 2 film, quartz glass is used, and SiO 2 , Al 2 O 3 , MgO, ZrO 2 , TiO 2 are used.
In the case of a composite oxide film of 2 , B 2 O 3 , Na 2 O, PbO, ZnO, BaO, etc., these are formed into a disk shape by powder metallurgy, or they are melted and cooled to form a disk-shaped composite glass. To use. When the sputtering is performed while swinging the basket 22 around the horizontal axis 20, the target material knocked out from the target 24 is condensed on the entire surface of the thermistor element body 10, and the inorganic material layer 14 made of the target material is formed.

【0015】(d) 外包電極の形成 図3(e)に示すように、絶縁性無機物層14を被覆し
たサーミスタ素体10の両端部に金属粉末と無機結合材
を含む導電性ペースト30を塗布する。この塗布は導電
性ペースト30を内包電極11より少ない包込み面積で
サーミスタ素体の両端部を包込むように行う。この塗布
は内包電極の形成法と同様に導電性ペースト中にサーミ
スタ素体の両端部を浸漬させるディッピング法が好まし
い。また導電性ペーストに含まれる金属粉末も内包電極
と同種のAg,Au,Pd,Pt等の貴金属、又はこれ
らを混合した粉末が挙げられる。導電性ペースト30に
含まれる無機結合材を例示すれば、SiO2,B23
Na2O,PbO,ZnO及びBaOの1種又は2種以
上の酸化物を主成分とする、ほうけい酸系ガラス、ほう
酸亜鉛系ガラス、ほう酸カドミウム系ガラス、けい酸鉛
亜鉛系ガラス等のガラス微粒子が挙げられる。
(D) Formation of outer electrode As shown in FIG. 3 (e), a conductive paste 30 containing a metal powder and an inorganic binder is applied to both ends of the thermistor element body 10 covered with the insulating inorganic material layer 14. To do. This application is performed so that the conductive paste 30 wraps the both ends of the thermistor element body in a wrapping area smaller than that of the internal electrode 11. This coating is preferably a dipping method in which both ends of the thermistor element body are dipped in a conductive paste, similar to the method of forming the internal electrodes. Further, the metal powder contained in the conductive paste may be a noble metal such as Ag, Au, Pd, or Pt which is the same type as the inclusion electrode, or a powder obtained by mixing these. As an example of the inorganic binder contained in the conductive paste 30, SiO 2 , B 2 O 3 ,
Glasses such as borosilicate glass, zinc borate glass, cadmium borate glass, lead zinc silicate glass, which contain one or more oxides of Na 2 O, PbO, ZnO and BaO as main components. Examples include fine particles.

【0016】図5に示すように、塗布された導電性ペー
スト30中には無機結合材32が均一に分散しており、
この無機結合材32は導電性ペーストの焼付け時にペー
スト30に接触する無機物層14と反応して、図6に示
すようにこの無機物層14の一部を溶融消滅させる性質
を有することが必要である。図3(f)及び図6に示す
ように導電性ペースト30は焼付けによって外包電極1
6を生成し、この外包電極16はその焼付け時に無機物
層14の一部が消滅することによって、内包電極11に
電気的に接続する。
As shown in FIG. 5, the inorganic binder 32 is uniformly dispersed in the applied conductive paste 30.
The inorganic binder 32 needs to have a property of reacting with the inorganic layer 14 that comes into contact with the paste 30 during baking of the conductive paste to melt and extinguish a part of the inorganic layer 14 as shown in FIG. . As shown in FIGS. 3 (f) and 6, the conductive paste 30 is baked to cover the outer electrode 1.
6 is generated, and the outer electrode 16 is electrically connected to the inner electrode 11 due to the disappearance of a part of the inorganic layer 14 during the baking.

【0017】(e) めっき層の形成 外包電極16の表面にめっき層が形成される。このめっ
き層は図3(g)に示すようにNiめっき層18を形成
した後、図3(h)に示すようにSnめっき層19を形
成して二重構造にすることが好ましい。Niめっき層1
8ははんだ耐熱性を向上して、はんだによる外包電極の
電極食われを防止し、Snめっき層19ははんだ付着性
を向上する。内包電極11、外包電極16、めっき層1
8及び19により端子電極12が形成される(図1及び
図2)。
(E) Formation of Plating Layer A plating layer is formed on the surface of the envelope electrode 16. This plating layer preferably has a double structure by forming a Ni plating layer 18 as shown in FIG. 3 (g) and then forming an Sn plating layer 19 as shown in FIG. 3 (h). Ni plating layer 1
8 improves solder heat resistance, prevents electrode erosion of the outer envelope electrode by solder, and the Sn plating layer 19 improves solder adhesion. Inner electrode 11, outer electrode 16, plating layer 1
The terminal electrode 12 is formed by 8 and 19 (FIGS. 1 and 2).

【0018】[0018]

【作用】外包電極用の導電性ペーストを塗布したサーミ
スタ素体を無機物層の融点又は軟化点より低い温度で焼
成すると、図3(f)及び図6に示すように外包電極1
6が形成される。即ち、この焼成時にはペースト中に均
一に分散した無機結合材32が無機物層14の一部と反
応してこれを溶融させる。流動化した無機物層14の無
機物は金属が焼結する際にできる外包電極16内の細孔
に侵入する。無機物層14の厚さは0.1〜10μmに
設定されているため、無機物層14の一部は焼成の過程
で上記細孔内に吸収されて内包電極11の表面から部分
的に消滅する。この結果、外包電極16と内包電極11
は無機物層14の消滅した部分を通じて直接接着し、互
いに電気的に導通する。内包電極11はサーミスタ素体
10と導電性を維持するように形成されているから、外
包電極16とサーミスタ素体10とは電気的に導通す
る。
When the thermistor element body coated with the conductive paste for the envelope electrode is fired at a temperature lower than the melting point or softening point of the inorganic layer, the envelope electrode 1 as shown in FIG. 3 (f) and FIG.
6 is formed. That is, during the firing, the inorganic binder 32 uniformly dispersed in the paste reacts with a part of the inorganic layer 14 to melt it. The fluidized inorganic substance of the inorganic substance layer 14 penetrates into the pores in the outer envelope electrode 16 formed when the metal is sintered. Since the thickness of the inorganic material layer 14 is set to 0.1 to 10 μm, a part of the inorganic material layer 14 is absorbed in the pores during the firing process and partially disappears from the surface of the inclusion electrode 11. As a result, the outer electrode 16 and the inner electrode 11
Are directly bonded through the disappeared portion of the inorganic layer 14 and are electrically connected to each other. Since the inner electrode 11 is formed so as to maintain conductivity with the thermistor body 10, the outer electrode 16 and the thermistor body 10 are electrically connected.

【0019】また、外包電極16の両端部の包込み面積
は内包電極11の包込み面積より狭いため、外包電極1
6は内包電極11が存在しない部分の無機物層14上を
被覆しない。このため無機物層14の厚さが下限値であ
る0.1μmの極薄であっても、外包電極16が直接サ
ーミスタ素体10に接触することはなく、電流は外包電
極16、内包電極11、サーミスタ素体10を通じて流
れる。一方、外包電極用の導電性ペーストが塗布されて
いない無機物層14の部分はペーストを焼付けても、そ
の無機物層の融点又は軟化点が焼成温度より高いため、
何ら変化を生じることなくサーミスタ素体10の表面に
残留し、その絶縁保護機能を保持する。
Since the wrapping area of both ends of the outer envelope electrode 16 is smaller than the wrapping area of the inner envelope electrode 11, the outer envelope electrode 1
6 does not cover the part of the inorganic layer 14 where the internal electrode 11 does not exist. Therefore, even if the thickness of the inorganic layer 14 is as thin as 0.1 μm, which is the lower limit value, the outer envelope electrode 16 does not directly contact the thermistor element body 10, and the current is the outer envelope electrode 16, the inner envelope electrode 11, It flows through the thermistor body 10. On the other hand, even if the paste of the inorganic layer 14 to which the conductive paste for the envelope electrode is not applied is baked, the melting point or softening point of the inorganic layer is higher than the baking temperature.
It remains on the surface of the thermistor element body 10 without any change and maintains its insulation protection function.

【0020】[0020]

【発明の効果】以上述べたように、従来の製造方法で
は、工程数が多く複雑であったものが、本発明の製造方
法によれば、少ない工程で比較的容易にチップ型サーミ
スタの端子電極を形成できるため、量産に適し、電極形
成コストが安価になる。また本発明のチップ型サーミス
タは、外包電極が接触する部分を除いてサーミスタ素体
が絶縁性無機物層で被覆され、サーミスタ素体がこの無
機物層で保護されているため、めっき処理してもめっき
液の素体への浸食やめっき付着による特性の変化がな
い。外包電極の表面にめっき層を形成することにより、
はんだ耐熱性とはんだ付着性に優れた効果を奏する。特
に、外包電極の包込み面積が内包電極の包込み面積より
狭いため、内包電極を設けているためサーミスタの抵抗
値はこの内包電極で正確に設定できるとともに、外包電
極の材料を広く選定できる。またこれにより絶縁性無機
物層の厚さを極薄にでき、無機物層の形成が蒸着法によ
る場合には、無機物層の形成時間が短縮され、サーミス
タの生産性が向上する。
As described above, in the conventional manufacturing method, the number of steps is large and complicated, but according to the manufacturing method of the present invention, the terminal electrode of the chip type thermistor can be relatively easily manufactured with a small number of steps. Since it can be formed, it is suitable for mass production and the cost for forming electrodes is low. Further, in the chip type thermistor of the present invention, the thermistor element body is covered with the insulating inorganic material layer except for the portion where the outer envelope electrode is in contact, and the thermistor element body is protected by this inorganic material layer, so that plating is performed even if plating There is no change in properties due to erosion of the liquid on the element body or plating adhesion. By forming a plating layer on the surface of the envelope electrode,
It has excellent effects on solder heat resistance and solder adhesion. In particular, since the wrapping area of the external electrode is smaller than the wrapping area of the internal electrode, the resistance value of the thermistor can be accurately set by this internal electrode because the internal electrode is provided, and the material of the external electrode can be widely selected. Further, by this, the thickness of the insulating inorganic material layer can be made extremely thin, and when the inorganic material layer is formed by the vapor deposition method, the formation time of the inorganic material layer is shortened and the thermistor productivity is improved.

【0021】[0021]

【実施例】次に本発明の具体的態様を示すために、本発
明を実施例に基づいて説明する。以下に述べる実施例は
本発明の技術的範囲を限定するものではない。 <実施例1>次の方法により図1及び図2に示すチップ
型サーミスタを作製した。先ず市販の炭酸マンガン、炭
酸ニッケル、炭酸コバルトを出発原料とし、これらをM
nO2:NiO:CoOに換算して金属原子比3:1:
2の割合でそれぞれ秤量した。秤量物をボールミルで1
6時間均一に混合した後に脱水乾燥した。次いでこの混
合物を900℃で2時間仮焼し、この仮焼物を再びボー
ルミルで粉砕して脱水乾燥した。粉砕物100重量%に
対してポリビニルブチラール6重量%、エタノール30
重量%及びブタノール30重量%の結合材を加え、均一
に混合してスラリーを調製した。このスラリーをドクタ
ーブレード法により成膜乾燥して厚さ0.80mmのグ
リーンシートを形成した。このシートから2.34mm
×1.48mmの大きさのチップ体を打抜き、大気圧
下、1200℃で4時間焼成し、長さ1.9mm、幅
1.2mm、厚さ0.65mmの焼結体を得た。
EXAMPLES The present invention will now be described based on examples in order to show specific embodiments of the present invention. The examples described below do not limit the technical scope of the present invention. Example 1 A chip type thermistor shown in FIGS. 1 and 2 was manufactured by the following method. First, commercially available manganese carbonate, nickel carbonate, and cobalt carbonate were used as starting materials, and M
Converted to nO 2 : NiO: CoO, the metal atom ratio is 3: 1:
Each was weighed in the ratio of 2. Weigh 1 with ball mill
After uniformly mixing for 6 hours, it was dehydrated and dried. Next, this mixture was calcined at 900 ° C. for 2 hours, and the calcined product was again pulverized with a ball mill and dehydrated and dried. Polyvinyl butyral 6% by weight, ethanol 30% with respect to 100% by weight of pulverized product
Binders of 30% by weight and 30% by weight of butanol were added and uniformly mixed to prepare a slurry. The slurry was dried by a doctor blade method to form a green sheet having a thickness of 0.80 mm. 2.34 mm from this sheet
A chip body with a size of 1.48 mm was punched out and fired at 1200 ° C. for 4 hours under atmospheric pressure to obtain a sintered body having a length of 1.9 mm, a width of 1.2 mm and a thickness of 0.65 mm.

【0022】この焼結体を図3(b)に示すサーミスタ
素体10とし、このサーミスタ素体の両端部に銀ペース
トをディッピング法により塗布した。両端部の銀ペース
トを乾燥した後、大気圧下、800℃で焼付けて内包電
極11を形成した(図3(c))。
This sintered body was used as the thermistor body 10 shown in FIG. 3B, and silver paste was applied to both ends of this thermistor body by a dipping method. After the silver paste on both ends was dried, it was baked at 800 ° C. under atmospheric pressure to form the internal electrode 11 (FIG. 3C).

【0023】次に内包電極11を形成したサーミスタ素
体10を図4に示すスパッタリング装置を用いてその表
面全体にSiO2膜からなる絶縁性無機物層を形成し
た。即ち、石英ガラスをターゲット24とするスパッタ
リング装置の中に多数のサーミスタ素体10を入れたス
テンレススチール製の篭22を設置し、この篭22を揺
動させながらスパッタリングを行い、サーミスタ素体1
0の表面全体にSiO2膜を2μmの厚さで形成した
(図3(d))。
Next, the thermistor element body 10 having the encapsulated electrode 11 formed thereon was formed with an insulating inorganic material layer made of a SiO 2 film on the entire surface thereof by using the sputtering apparatus shown in FIG. That is, a stainless steel cage 22 containing a large number of thermistor bodies 10 is set in a sputtering device using a quartz glass as a target 24, and the thermistor body 1 is subjected to sputtering while rocking the cage 22.
A SiO 2 film having a thickness of 2 μm was formed on the entire surface of No. 0 (FIG. 3D).

【0024】更に全面がSiO2膜14で被覆されたサ
ーミスタ素体10の両端部に端子電極12を設けた。こ
の端子電極12は、内包電極11と外包電極16とNi
めっき層18とSnめっき層19により構成される。先
ず無機物層14を形成したサーミスタ素体の両端部に導
電性ペーストをディッピング法により塗布した(図3
(e))。この塗布は導電性ペーストを内包電極11よ
り少ない包込み面積でサーミスタ素体の両端部を包込む
ように行った。導電性ペーストは市販の銀ペースト(デ
ュポン社製JPN−1176J)であって、Ag粉末
と、SiO2,TiO2,B23,Na2O及びK2Oから
なるガラス微粒子と、有機ビヒクルとからなる。導電性
ペーストを塗布したサーミスタ素体を大気圧下、乾燥し
た後、30℃/分の速度で、820℃まで昇温しそこで
10分間保持し、30℃/分の速度で室温まで降温して
Agからなる外包電極16を得た(図3(f))。次い
で電解バレルめっき法で電極16の表面に厚さ2〜3μ
mのNiめっき層18を形成し、続いて厚さ1〜2μm
のSnめっき層19を形成した。 <比較例1>内包電極をサーミスタ素体の両端部を包込
まずにその両端面のみに形成し、外包電極をサーミスタ
素体の両端部を包込んで形成した以外は、上記実施例1
と同じ方法で、めっき層付きチップ型サーミスタを作製
した。
Further, terminal electrodes 12 are provided on both ends of the thermistor element body 10 whose entire surface is covered with the SiO 2 film 14. The terminal electrode 12 includes an inner electrode 11, an outer electrode 16 and Ni.
It is composed of the plating layer 18 and the Sn plating layer 19. First, a conductive paste was applied by a dipping method to both ends of the thermistor element body on which the inorganic layer 14 was formed (FIG. 3).
(E)). This application was performed so that both ends of the thermistor element body were covered with the conductive paste with a smaller covering area than the inclusion electrode 11. The conductive paste is a commercially available silver paste (JPN-1176J manufactured by DuPont), and Ag powder, glass fine particles composed of SiO 2 , TiO 2 , B 2 O 3 , Na 2 O and K 2 O, and an organic vehicle. Consists of. After drying the thermistor element coated with the conductive paste under atmospheric pressure, the temperature is raised to 820 ° C. at a rate of 30 ° C./minute, held there for 10 minutes, and then lowered to room temperature at a rate of 30 ° C./minute. An envelope electrode 16 made of Ag was obtained (FIG. 3 (f)). Next, the thickness of the electrode 16 is 2-3 μm by the electrolytic barrel plating method.
m Ni plating layer 18 is formed, and then the thickness is 1-2 μm.
The Sn plating layer 19 was formed. <Comparative Example 1> Example 1 described above except that the inner electrode was formed only on both end surfaces of the thermistor element body without enclosing the both end portions of the thermistor element body, and the outer electrode was formed by enclosing both end portions of the thermistor element body.
A chip type thermistor with a plated layer was produced by the same method as described above.

【0025】<実施例2>絶縁性無機物層をSiO
PbO,K2O系のガラス膜にし、外包電極の導電性ペ
ーストを塗布後の焼成温度を600℃とした以外は、実
施例1と同じ方法で、めっき層付きチップ型サーミスタ
を作製した。
<Embodiment 2> The insulating inorganic material layer is made of SiO 2 ,
A chip type thermistor with a plating layer was produced in the same manner as in Example 1 except that a PbO, K 2 O based glass film was used and the firing temperature after applying the conductive paste for the outer envelope electrode was 600 ° C.

【0026】<比較例2>内包電極をサーミスタ素体の
両端部を包込まずにその両端面のみに形成し、外包電極
をサーミスタ素体の両端部を包込んで形成した以外は、
上記実施例2と同じ方法で、めっき層付きチップ型サー
ミスタを作製した。
<Comparative Example 2> Except that the internal electrodes are formed only on both end surfaces of the thermistor element body without enclosing the both ends of the thermistor element body, and the outer electrode is formed by enclosing both end portions of the thermistor element body.
A chip type thermistor with a plated layer was produced in the same manner as in Example 2 above.

【0027】<比較試験と結果>実施例1、実施例2、
比較例1及び比較例2の各サーミスタを100個ずつ用
意した。 ・抵抗値のばらつき これらのサーミスタのそれぞれの抵抗値を測定し、その
抵抗基準値に対する抵抗値平均値のずれ及びその平均値
と標準偏差から抵抗値のばらつきを計算した。その結果
を表1に示す。
<Comparison Test and Results> Example 1, Example 2,
100 each of the thermistors of Comparative Example 1 and Comparative Example 2 were prepared. -Dispersion of resistance value The resistance value of each of these thermistors was measured, and the deviation of the resistance value was calculated from the deviation of the resistance value average value from the resistance reference value and the average value and standard deviation. The results are shown in Table 1.

【0028】・研磨断面の顕微鏡観察 これらのサーミスタをそれぞれ図2に示す断面が現れる
ように研磨してその断面を顕微鏡で観察し、外包電極が
サーミスタ素体に直接接続しているチップ数をカウント
した。その結果を表1に示す。 表1から明かなように、実施例1及び実施例2のサーミ
スタは、比較例1及び比較例2のサーミスタと比べて、
外包電極がサーミスタ素体に接続しているものは皆無
で、かつ抵抗値のずれやばらつきは少なく良好な特性が
得られていた。
Microscopic Observation of Polished Cross Section Each of these thermistors is polished so that the cross section shown in FIG. 2 appears, and the cross section is observed with a microscope to count the number of chips in which the outer electrode is directly connected to the thermistor body. did. The results are shown in Table 1. As is clear from Table 1, the thermistors of Example 1 and Example 2 are compared with the thermistors of Comparative Example 1 and Comparative Example 2.
None of the external electrodes were connected to the thermistor element body, and there were few deviations and variations in resistance values, and good characteristics were obtained.

【0029】[0029]

【表1】 [Table 1]

【0030】[0030]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のチップ型サーミスタの要部破断斜視
図。
FIG. 1 is a fragmentary perspective view of a chip type thermistor of the present invention.

【図2】その中央断面図。FIG. 2 is a central sectional view thereof.

【図3】本発明のサーミスタ素体からチップ型サーミス
タを作るまでの工程における素体の斜視図。
FIG. 3 is a perspective view of an element body in a process from the thermistor element body of the present invention to a chip type thermistor.

【図4】そのサーミスタ素体表面に絶縁性無機物層を被
覆するためのスパッタリング装置の概略斜視図。
FIG. 4 is a schematic perspective view of a sputtering apparatus for coating the surface of the thermistor element body with an insulating inorganic material layer.

【図5】そのサーミスタ素体に外包電極用の導電性ペー
ストを塗布した状態の要部拡大断面図。
FIG. 5 is an enlarged cross-sectional view of a main part of the thermistor element body in which a conductive paste for an envelope electrode is applied.

【図6】その導電性ペーストを焼付けて、外包電極を形
成した状態の要部拡大断面図。
FIG. 6 is an enlarged cross-sectional view of a main part in a state where the conductive paste is baked to form an outer envelope electrode.

【符号の説明】[Explanation of symbols]

2 チップ体 10 サーミスタ素体 11 内包電極 12 端子電極 14 絶縁性無機物層 16 外包電極 18 Niめっき層 19 Snめっき層 30 導電性ペースト 32 無機結合材 2 Chip Body 10 Thermistor Element 11 Internal Electrode 12 Terminal Electrode 14 Insulating Inorganic Material Layer 16 External Encapsulation Electrode 18 Ni Plating Layer 19 Sn Plating Layer 30 Conductive Paste 32 Inorganic Binder

【手続補正書】[Procedure amendment]

【提出日】平成5年4月9日[Submission date] April 9, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0011[Correction target item name] 0011

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0011】以下、本発明を詳述する。 (a) サーミスタ素体の製造 本発明のサーミスタ素体は次の方法により作られる。先
ずMn,Fe,Co,Ni,Cu,Al等の金属の酸化
物粉末を1種又は2種以上採取して混合する。2種以上
混合するときは、所定の金属原子比になるように各金属
酸化物を秤量する。この混合物を仮焼し粉砕した後、有
機結合材及び溶剤を加え混練してスラリーを調製する。
次いでこのスラリーをドクターブレード法等により成膜
乾燥してグリーンシートを形成する。このグリーンシー
トから図3(a)に示すチップ体2を打抜き、これを焼
成して図3(b)に示すチップ状のサーミスタ素体10
を得る。このサーミスタ素体10をチップ型積層コンデ
ンサと同様にバレル研磨処理してサーミスタ素体の角取
りをしておくことが好ましい。
The present invention will be described in detail below. (a) Production of thermistor element body The thermistor element body of the present invention is produced by the following method. First, one kind or two or more kinds of oxide powders of metals such as Mn, Fe, Co, Ni, Cu and Al are sampled and mixed. When two or more kinds are mixed, each metal oxide is weighed so as to have a predetermined metal atomic ratio. After calcining and pulverizing this mixture, an organic binder and a solvent are added and kneaded to prepare a slurry.
Then, this slurry is dried by a doctor blade method or the like to form a green sheet. A chip body 2 shown in FIG. 3A is punched out from this green sheet, and is fired to form a chip-like thermistor body 10 shown in FIG. 3B.
To get It is preferable that the thermistor element body 10 is barrel-polished in the same manner as the chip type multilayer capacitor to square off the thermistor element body.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0021[Correction target item name] 0021

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0021】[0021]

【実施例】次に本発明の具体的態様を示すために、本発
明を実施例に基づいて説明する。以下に述べる実施例は
本発明の技術的範囲を限定するものではない。 <実施例1>次の方法により図1及び図2に示すチップ
型サーミスタを作製した。先ず市販の炭酸マンガン、炭
酸ニッケル、炭酸コバルトを出発原料とし、これらをM
nO2:NiO:CoOに換算して金属原子比3:1:
2の割合でそれぞれ秤量した。秤量物をボールミルで1
6時間均一に混合した後に脱水乾燥した。次いでこの混
合物を900℃で2時間仮焼し、この仮焼物を再びボー
ルミルで粉砕して脱水乾燥した。粉砕物100重量%に
対してポリビニルブチラール6重量%、エタノール30
重量%及びブタノール30重量%の結合材を加え、均一
に混合してスラリーを調製した。このスラリーをドクタ
ーブレード法により成膜乾燥して厚さ0.80mmのグ
リーンシートを形成した。このシートから2.34mm
×1.48mmの大きさのチップ体を打抜き、大気圧
下、1200℃で4時間焼成し、長さ1.9mm、幅
1.2mm、厚さ0.65mmの焼結体を得た。この焼
結体をバレル研磨処理して焼結体の角取りを行った。
EXAMPLES The present invention will now be described based on examples in order to show specific embodiments of the present invention. The examples described below do not limit the technical scope of the present invention. Example 1 A chip type thermistor shown in FIGS. 1 and 2 was manufactured by the following method. First, commercially available manganese carbonate, nickel carbonate, and cobalt carbonate were used as starting materials, and M
Converted to nO 2 : NiO: CoO, the metal atom ratio is 3: 1:
Each was weighed in the ratio of 2. Weigh 1 with ball mill
After uniformly mixing for 6 hours, it was dehydrated and dried. Next, this mixture was calcined at 900 ° C. for 2 hours, and the calcined product was again pulverized with a ball mill and dehydrated and dried. Polyvinyl butyral 6% by weight, ethanol 30% with respect to 100% by weight of pulverized product
Binders of 30% by weight and 30% by weight of butanol were added and uniformly mixed to prepare a slurry. The slurry was dried by a doctor blade method to form a green sheet having a thickness of 0.80 mm. 2.34 mm from this sheet
A chip body with a size of 1.48 mm was punched out and fired at 1200 ° C. for 4 hours under atmospheric pressure to obtain a sintered body having a length of 1.9 mm, a width of 1.2 mm and a thickness of 0.65 mm. The sintered body was barrel-polished and the sintered body was chamfered.

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0024[Name of item to be corrected] 0024

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0024】更に全面がSiO2膜14で被覆されたサ
ーミスタ素体10の両端部に電極を設けた。これによ
り、内包電極11と外包電極16とNiめっき層18と
Snめっき層19からなる端子電極12が形成された。
先ず無機物層14を形成したサーミスタ素体の両端部に
導電性ペーストをディッピング法により塗布した(図3
(e))。この塗布は導電性ペーストを内包電極11よ
り少ない包込み面積でサーミスタ素体の両端部を包込む
ように行った。導電性ペーストは市販の銀ペースト(デ
ュポン社製JPN−1176J)であって、Ag粉末
と、SiO2,TiO2,B23,Na2O及びK2Oから
なるガラス微粒子と、有機ビヒクルとからなる。導電性
ペーストを塗布したサーミスタ素体を大気圧下、乾燥し
た後、30℃/分の速度で、820℃まで昇温しそこで
10分間保持し、30℃/分の速度で室温まで降温して
Agからなる外包電極16を得た(図3(f))。次い
で電解バレルめっき法で電極16の表面に厚さ2〜3μ
mのNiめっき層18を形成し、続いて厚さ1〜2μm
のSnめっき層19を形成した。 <比較例1>内包電極をサーミスタ素体の両端部を包込
まずにその両端面のみに形成し、外包電極をサーミスタ
素体の両端部を包込んで形成した以外は、上記実施例1
と同じ方法で、めっき層付きチップ型サーミスタを作製
した。 ─────────────────────────────────────────────────────
Further, electrodes were provided on both ends of the thermistor body 10 whose entire surface was covered with the SiO 2 film 14. As a result, the terminal electrode 12 including the inner electrode 11, the outer electrode 16, the Ni plating layer 18, and the Sn plating layer 19 was formed.
First, a conductive paste was applied by a dipping method to both ends of the thermistor element body on which the inorganic layer 14 was formed (FIG. 3).
(E)). This application was performed so that both ends of the thermistor element body were covered with the conductive paste with a smaller covering area than the inclusion electrode 11. The conductive paste is a commercially available silver paste (JPN-1176J manufactured by DuPont), and Ag powder, glass fine particles composed of SiO 2 , TiO 2 , B 2 O 3 , Na 2 O and K 2 O, and an organic vehicle. Consists of. After drying the thermistor element coated with the conductive paste under atmospheric pressure, the temperature is raised to 820 ° C. at a rate of 30 ° C./minute, held there for 10 minutes, and then lowered to room temperature at a rate of 30 ° C./minute. An envelope electrode 16 made of Ag was obtained (FIG. 3 (f)). Next, the thickness of the electrode 16 is 2-3 μm by the electrolytic barrel plating method.
m Ni plating layer 18 is formed, and then the thickness is 1-2 μm.
The Sn plating layer 19 was formed. <Comparative Example 1> Example 1 described above except that the inner electrode was formed only on both end surfaces of the thermistor element body without enclosing the both end portions of the thermistor element body, and the outer electrode was formed by enclosing both end portions of the thermistor element body.
A chip type thermistor with a plated layer was produced by the same method as described above. ─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年7月8日[Submission date] July 8, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】請求項2[Name of item to be corrected] Claim 2

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】請求項3[Name of item to be corrected] Claim 3

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0013[Correction target item name] 0013

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0013】(c) サーミスタ素体への絶縁性無機物層の
被覆 内包電極11が形成されたサーミスタ素体10はその全
面に厚さ0.1〜10μmの絶縁性無機物層が被覆され
る(図3(d))。10μmより厚いと、後述する外包
電極の形成時に溶融した無機物層が外包電極中に完全に
吸収されず、無機物層が外包電極と内包電極の界面に絶
縁性皮膜として残留するため外包電極と内包電極とが導
通しない。また0.1μmより薄いと、後述するめっき
処理に際して、まためっき処理後のサーミスタ素体の保
護機能に劣る。この絶縁性無機物層14(図1及び図
2)を例示すると、SiO2膜、又は50重量%以上の
SiO2と残部がAl23,MgO,ZrO2又はTiO
2のいずれか1種又は2種以上の酸化物により構成され
た薄膜、或いはSiO2,B23,Na2O,PbO,Z
nO又はBaOのいずれか1種又は2種以上の酸化物を
主成分とするガラスにより構成された薄膜が挙げられ
る。この無機物層14は後述する外包電極を形成すると
きの焼成温度より高い融点又は軟化点を有することが必
要である。例えば、外包電極としてAgのペーストを焼
付ける場合にはその焼成温度は600〜850℃である
ため、この温度より高い融点又は軟化点を有するものが
選ばれる。この理由はペーストの焼付け温度より融点又
は軟化点が大幅に低いと、ペースト焼付け時に無機物層
が電極表面に浮き上がったり、或いはサーミスタ素体同
士又は素体と焼成治具との貼り付きが生じて歩留りが低
下し易いからである。
(C) Coating of Insulating Inorganic Material Layer on Thermistor Element Body The entire surface of the thermistor element body 10 on which the inclusion electrode 11 is formed is coated with an insulating inorganic material layer having a thickness of 0.1 to 10 μm (see FIG. 3 (d)). When the thickness is more than 10 μm, the inorganic layer melted during the formation of the external electrode described later is not completely absorbed in the external electrode, and the inorganic layer remains as an insulating film at the interface between the external electrode and the internal electrode, so that the external electrode and the internal electrode And do not connect. When the thickness is less than 0.1 μm, the function of protecting the thermistor element during the plating treatment described later and after the plating treatment is poor. As an example of the insulating inorganic material layer 14 (FIGS. 1 and 2), a SiO 2 film, or 50 wt% or more of SiO 2 and the balance of Al 2 O 3 , MgO, ZrO 2 or TiO 2 is used.
Thin film constituted by any one or more oxides of 2, or SiO 2, B 2 O 3, Na 2 O, PbO, Z
Examples of the thin film include glass containing, as a main component, one or more oxides of nO and BaO. The inorganic layer 14 needs to have a melting point or a softening point higher than the firing temperature when forming the envelope electrode described later. For example, when an Ag paste is baked as the envelope electrode, the baking temperature is 600 to 850 ° C., and therefore, a material having a melting point or a softening point higher than this temperature is selected. The reason for this is that if the melting point or softening point is significantly lower than the baking temperature of the paste, the inorganic material layer floats up on the electrode surface during paste baking, or the thermistor element bodies or the element body and the firing jig adhere to each other and yield increases. Is easily reduced.

【手続補正4】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0015[Name of item to be corrected] 0015

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0015】(d) 外包電極の形成 図3(e)に示すように、絶縁性無機物層14を被覆し
たサーミスタ素体10の両端部に金属粉末と無機結合材
を含む導電性ペースト30を塗布する。この塗布は導電
性ペースト30を内包電極11より少ない包込み面積で
サーミスタ素体の両端部を包込むように行う。この塗布
は内包電極の形成法と同様に導電性ペースト中にサーミ
スタ素体の両端部を浸漬させるディッピング法が好まし
い。また導電性ペーストに含まれる金属粉末も内包電極
と同種のAg,Au,Pd,Pt等の貴金属、又はこれ
らを混合した粉末が挙げられる。導電性ペースト30に
含まれる無機結合材を例示すれば、SiO2,B23
Na2O,PbO,ZnO又はBaOのいずれか1種又
は2種以上の酸化物を主成分とする、ほうけい酸系ガラ
ス、ほう酸亜鉛系ガラス、ほう酸カドミウム系ガラス、
けい酸鉛亜鉛系ガラス等のガラス微粒子が挙げられる。
(D) Formation of outer electrode As shown in FIG. 3 (e), a conductive paste 30 containing a metal powder and an inorganic binder is applied to both ends of the thermistor element body 10 covered with the insulating inorganic material layer 14. To do. This application is performed so that the conductive paste 30 wraps the both ends of the thermistor element body in a wrapping area smaller than that of the internal electrode 11. This coating is preferably a dipping method in which both ends of the thermistor element body are dipped in a conductive paste, similar to the method of forming the internal electrodes. Further, the metal powder contained in the conductive paste may be a noble metal such as Ag, Au, Pd, or Pt which is the same type as the inclusion electrode, or a powder obtained by mixing these. As an example of the inorganic binder contained in the conductive paste 30, SiO 2 , B 2 O 3 ,
Borosilicate-based glass, zinc borate-based glass, cadmium borate-based glass containing, as a main component, one or more oxides of Na 2 O, PbO, ZnO, and BaO.
Examples thereof include fine glass particles such as lead zinc silicate based glass.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 サーミスタ素体(10)と、このサーミスタ
素体(10)の両端部に設けられた内包電極(11)と、この内
包電極(11)が形成されたサーミスタ素体(10)の全面を被
覆する絶縁性無機物層(14)と、この無機物層(14)を被覆
したサーミスタ素体(10)の両端部に設けられた外包電極
(16)と、この外包電極(16)の表面に形成されためっき層
(18,19)とを備えたチップ型サーミスタであって、 前記内包電極(11)は前記サーミスタ素体(10)の両端部を
包込むように形成され、 前記外包電極(16)は金属粉末と無機結合材を含む導電性
ペーストを前記内包電極(11)より少ない包込み面積で前
記サーミスタ素体(10)の両端部を包込むように塗布して
焼付けることにより形成され、 前記無機物層(14)は厚さが0.1〜10μmであって、
前記外包電極(16)を形成する時の焼成温度より高い融点
又は軟化点を有し、かつ前記ペーストの下地部分の前記
無機物層の一部が前記外包電極(16)の形成時に前記無機
結合材に反応溶融して前記外包電極(16)に吸収され消滅
するように構成されたことを特徴とするチップ型サーミ
スタ。
1. A thermistor element body (10), internal electrodes (11) provided at both ends of the thermistor element body (10), and a thermistor element body (10) on which the internal electrode (11) is formed. Insulating inorganic material layer (14) covering the entire surface of the thermistor and outer electrode provided on both ends of the thermistor element body (10) covering the inorganic material layer (14)
(16) and a plating layer formed on the surface of the outer electrode (16)
(18, 19) is a chip-type thermistor, wherein the inner electrode (11) is formed so as to enclose both ends of the thermistor body (10), the outer electrode (16) is a metal powder And a conductive paste containing an inorganic binder is formed by coating and baking so as to wrap both ends of the thermistor element body (10) in a wrapping area smaller than the inclusion electrode (11), the inorganic material layer (14) has a thickness of 0.1 to 10 μm,
The external electrode (16) has a melting point or a softening point higher than the firing temperature at the time of forming, and a part of the inorganic layer of the base portion of the paste is the inorganic binder when the external electrode (16) is formed. A chip-type thermistor, which is configured so as to react with and melt into the outer envelope electrode (16) and disappear.
【請求項2】 絶縁性無機物層(14)がSiO2又は50
重量%以上のSiO2と、残部がAl23,MgO,Z
rO2及びTiO2の1種又は2種以上の酸化物とにより
構成され、外包電極(16)を形成するための導電性ペース
トに含まれる無機結合材がSiO2,B23,Na2O,
PbO,ZnO及びBaOの1種又は2種以上の酸化物
を主成分とするガラス微粒子により構成された請求項1
記載のチップ型サーミスタ。
2. The insulating inorganic material layer (14) is made of SiO 2 or 50.
% By weight of SiO 2 and the balance Al 2 O 3 , MgO, Z
is constituted by the one or more oxides of and rO 2 and TiO 2, SiO 2 inorganic binder contained in the conductive paste for forming the envelope electrode (16), B 2 O 3 , Na 2 O,
A glass fine particle containing, as a main component, one or more oxides of PbO, ZnO and BaO.
The described chip type thermistor.
【請求項3】 絶縁性無機物層(14)がSiO2,B
23,Na2O,PbO,ZnO及びBaOの1種又は
2種以上の酸化物を主成分とするガラスにより構成さ
れ、外包電極(16)を形成するための導電性ペーストに含
まれる無機結合材がSiO2,B23,Na2O,Pb
O,ZnO及びBaOの1種又は2種以上の酸化物を主
成分とするガラス微粒子により構成された請求項1記載
のチップ型サーミスタ。
3. The insulating inorganic layer (14) comprises SiO 2 , B.
Inorganic contained in the conductive paste for forming the envelope electrode (16), which is composed of glass containing one or more oxides of 2 O 3 , Na 2 O, PbO, ZnO and BaO as a main component. The binder is SiO 2 , B 2 O 3 , Na 2 O, Pb
The chip type thermistor according to claim 1, wherein the chip type thermistor is composed of glass fine particles containing at least one oxide of O, ZnO and BaO as a main component.
【請求項4】 絶縁性無機物層(14)が結晶化ガラスから
なる請求項3記載のチップ型サーミスタ。
4. The chip type thermistor according to claim 3, wherein the insulating inorganic material layer (14) is made of crystallized glass.
【請求項5】 金属酸化物粉末と結合材とを混合してス
ラリーを調製する工程と、 前記スラリーを成膜乾燥してグリーンシートを形成する
工程と、 前記グリーンシートからチップ体(2)を打抜く工程と、 前記チップ体(2)を焼成してサーミスタ素体(10)にする
工程と、 前記サーミスタ素体(10)の両端部にこの両端部を包込む
ように内包電極(11)を形成する工程と、 前記内包電極(11)が形成された前記サーミスタ素体(10)
の全面に厚さ0.1〜10μmの絶縁性無機物層(14)を
被覆する工程と、 前記無機物層(14)を被覆したサーミスタ素体(10)の両端
部に金属粉末と無機結合材(32)を含む導電性ペースト(3
0)を前記内包電極(11)より少ない包込み面積で前記両端
部を包込むように塗布する工程と、 前記ペースト(30)を塗布したサーミスタ素体(10)を前記
無機物層(14)の融点又は軟化点より低い温度で焼成し、
前記塗布したペーストの無機結合材(32)にそのペースト
の下地部分の前記無機物層の一部を反応溶融させること
により消滅させて外包電極(16)を形成する工程と、 前記外包電極(16)の表面にめっき層(18,19)を形成する
工程とを含むチップ型サーミスタの製造方法。
5. A step of preparing a slurry by mixing a metal oxide powder and a binder, a step of film-forming and drying the slurry to form a green sheet, and a step of forming a chip body (2) from the green sheet. A step of punching, a step of firing the chip body (2) to form a thermistor element body (10), and an encapsulating electrode (11) so as to wrap both ends of the thermistor element body (10). And a step of forming the thermistor element body (10) on which the internal electrode (11) is formed.
A step of coating an insulating inorganic layer (14) having a thickness of 0.1 to 10 μm on the entire surface of the thermistor element body (10) coated with the inorganic layer (14) on both sides of the metal powder and the inorganic binder ( 32) Conductive paste (3
A step of applying 0) so as to wrap the both ends in a wrapping area smaller than the inclusion electrode (11), and a thermistor element body (10) coated with the paste (30) of the inorganic material layer (14) Firing at a temperature below the melting or softening point,
A step of forming the envelope electrode (16) by extinguishing a part of the inorganic layer of the base portion of the paste by reaction melting in the inorganic binder (32) of the applied paste, and the envelope electrode (16) And a step of forming a plating layer (18, 19) on the surface of the chip-type thermistor.
【請求項6】 サーミスタ素体(10)への絶縁性無機物層
(14)の被覆が物理蒸着法により行われる請求項5記載の
チップ型サーミスタの製造方法。
6. An insulating inorganic material layer for the thermistor element body (10)
The method for manufacturing a chip type thermistor according to claim 5, wherein the coating of (14) is performed by a physical vapor deposition method.
JP5080471A 1992-12-18 1993-04-07 Chip type thermister and production thereof Withdrawn JPH06295803A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP5080471A JPH06295803A (en) 1993-04-07 1993-04-07 Chip type thermister and production thereof
KR1019930010430A KR100204255B1 (en) 1992-12-18 1993-06-09 Chip type ceramic element and method of manufature thereof
US08/079,347 US5339068A (en) 1992-12-18 1993-06-18 Conductive chip-type ceramic element and method of manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5080471A JPH06295803A (en) 1993-04-07 1993-04-07 Chip type thermister and production thereof

Publications (1)

Publication Number Publication Date
JPH06295803A true JPH06295803A (en) 1994-10-21

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ID=13719184

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Country Status (2)

Country Link
JP (1) JPH06295803A (en)
KR (1) KR100204255B1 (en)

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