JPH04293214A - Conductive paste for chip type electronic component - Google Patents

Conductive paste for chip type electronic component

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Publication number
JPH04293214A
JPH04293214A JP8199491A JP8199491A JPH04293214A JP H04293214 A JPH04293214 A JP H04293214A JP 8199491 A JP8199491 A JP 8199491A JP 8199491 A JP8199491 A JP 8199491A JP H04293214 A JPH04293214 A JP H04293214A
Authority
JP
Japan
Prior art keywords
chip
conductive paste
type electronic
electrode
metal powder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8199491A
Other languages
Japanese (ja)
Other versions
JP2973558B2 (en
Inventor
Kaoru Nishizawa
薫 西澤
Seiji Saito
斉藤 征士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP3081994A priority Critical patent/JP2973558B2/en
Publication of JPH04293214A publication Critical patent/JPH04293214A/en
Application granted granted Critical
Publication of JP2973558B2 publication Critical patent/JP2973558B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Conductive Materials (AREA)

Abstract

PURPOSE:To relieve thermal shock to a bare chip when an electrode surface is electroplated, reduce the generation of cracks in the bare chip, and prevent the deterioration of electric characteristics and bonding characteristics to a substrate, by decreasing stress and hardness which make a baked electrode layer contract which layer is the substratum electrode of a chip type electronic parts such as a chip capacitor, a chip resistor and a chip thermistor. CONSTITUTION:This invention relates to the additive to conductive paste for forming a terminal electrode 12 by baking after the surface of a bare chip 11 constituted of ceramic dielectric is coated with said paste. In addition to metal powder, glass frit, and inert organic vehicles, one or more kinds of filler for sintering control selected out of Al2O3, MgO, Cab, BaO and ZnO is contained as additive. Said filter of 0.3-5wt.% is added to metal powder.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はチップコンデンサ、チッ
プ抵抗、チップサーミスタ等のチップ型電子部品の端子
電極を形成するための導電性ペーストに関する。更に詳
しくは導電性ペーストの添加剤に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive paste for forming terminal electrodes of chip-type electronic components such as chip capacitors, chip resistors, and chip thermistors. More specifically, it relates to additives for conductive pastes.

【0002】0002

【従来の技術】この種のチップ型電子部品を構成するセ
ラミック誘電体からなるベアチップの表面には端子電極
が形成される。この端子電極は金属粉末とガラスフリッ
トと不活性有機ビヒクルとを混練してつくられた導電性
ペーストをベアチップの表面に塗布し乾燥した後、60
0〜800℃程度の温度で焼成して形成される。このチ
ップ型電子部品は端子電極を基板にはんだ付けして使用
される。
2. Description of the Related Art Terminal electrodes are formed on the surface of a bare chip made of a ceramic dielectric that constitutes this type of chip-type electronic component. This terminal electrode is made by applying a conductive paste made by kneading metal powder, glass frit, and an inert organic vehicle to the surface of the bare chip and drying it for 60 minutes.
It is formed by firing at a temperature of about 0 to 800°C. This chip-type electronic component is used with terminal electrodes soldered to a substrate.

【0003】従来、導電性ペーストの金属粉末には、A
g,Au,Pd,Pt等の貴金属、Cu,Ni等の卑金
属、又はこれらを混合した粉末が使用される。Ag粉を
含む導電性ペーストで形成された端子電極ははんだ付け
時にAgがはんだに溶解するいわゆるはんだ食われが起
こるため、Ag粉にPd粉を加えたAg/Pd混合粉が
多用されている。しかしPdを多く含むとはんだ付け性
が劣り、焼付け時にベアチップにクラックが生じ易いた
め、Ag−Pd端子電極のPdの含有率は1〜15%と
比較的低く押えられている。このため従来のAg−Pd
端子電極のはんだ耐熱性はそれほど高くなく、チップ型
電子部品をはんだ付けできる温度範囲は狭い。また端子
電極の膜厚は薄いため、はんだ食われを生じると信頼性
に劣るようになる。この点を解決するため、従来より焼
付け電極層の表面にNiめっき、Sn又はSn/Pbめ
っきの2層のめっき電極層が形成されている。Niめっ
きは、はんだ耐熱性の向上と、はんだによる電極食われ
の防止とを主たる目的とし、Sn又はSn/Pbめっき
は、酸化防止とはんだ濡れ性の向上を目的としている。
Conventionally, metal powder for conductive paste contains A
Precious metals such as g, Au, Pd, and Pt, base metals such as Cu and Ni, or powders of mixtures thereof are used. Terminal electrodes formed from conductive paste containing Ag powder suffer from so-called solder erosion, in which Ag dissolves into the solder during soldering, so Ag/Pd mixed powder, which is a combination of Ag powder and Pd powder, is often used. However, if a large amount of Pd is contained, the solderability is poor and the bare chip is likely to crack during baking, so the Pd content of the Ag-Pd terminal electrode is kept relatively low at 1 to 15%. Therefore, conventional Ag-Pd
The soldering heat resistance of terminal electrodes is not very high, and the temperature range in which chip-type electronic components can be soldered is narrow. Furthermore, since the film thickness of the terminal electrode is thin, if solder is eaten away, reliability will be degraded. To solve this problem, a two-layer plating electrode layer of Ni plating, Sn or Sn/Pb plating has conventionally been formed on the surface of the baked electrode layer. The main purpose of Ni plating is to improve solder heat resistance and prevent electrode erosion by solder, and the purpose of Sn or Sn/Pb plating is to prevent oxidation and improve solder wettability.

【0004】0004

【発明が解決しようとする課題】しかし、焼付け電極層
の表面にNiめっき層とSn又はSn/Pbめっき層を
形成した従来のチップ型電子部品、例えばチップコンデ
ンサは、ベアチップを予熱せずに300℃以上のはんだ
層に浸漬して引上げると、Niめっき層の降温時の引張
り応力が高くしかも焼付け電極層が高硬度になっていて
この応力を吸収できないため、端子電極の内側のベアチ
ップにクラックが発生し易い。クラックが発生すると耐
湿性が低下してクラックから水分が浸入しコンデンサと
しての絶縁抵抗が劣化する。またこのチップコンデンサ
を基板の表面にはんだ付けにより実装し、例えば−25
℃から室温を経由して+85℃まで昇温し、反対に降温
させる温度サイクル試験を行った場合には、高い熱応力
から上記クラックが成長して端子電極の部分が折損する
か、或いはコンデンサの絶縁抵抗が劣化するようになる
[Problems to be Solved by the Invention] However, conventional chip-type electronic components, such as chip capacitors, in which a Ni plating layer and a Sn or Sn/Pb plating layer are formed on the surface of a baked electrode layer, do not require preheating of the bare chip. If the solder layer is immersed in a solder layer at a temperature of ℃ or higher and pulled up, the tensile stress of the Ni plating layer is high when the temperature falls, and the baked electrode layer is too hard to absorb this stress, resulting in cracks in the bare chip inside the terminal electrode. is likely to occur. When cracks occur, moisture resistance decreases and moisture infiltrates through the cracks, degrading the insulation resistance of the capacitor. In addition, this chip capacitor is mounted on the surface of the board by soldering, for example, -25
If a temperature cycle test was performed in which the temperature was raised from ℃ to +85℃ via room temperature and then lowered, the above cracks would grow due to high thermal stress and the terminal electrode part would break, or the capacitor would break. Insulation resistance begins to deteriorate.

【0005】本発明の目的は、下地電極である焼付け電
極層の収縮しようとするストレスや硬度を和らげること
によりこの電極層表面に電解めっき処理を行ったときの
ベアチップに対するサーマルショックを緩和して、ベア
チップのクラックの発生率を減少させ、電気特性及び基
板への接着特性を劣化させないチップ型電子部品用導電
性ペーストを提供することにある。
An object of the present invention is to alleviate the thermal shock to the bare chip when electrolytic plating is performed on the surface of the electrode layer by alleviating the stress and hardness of the baked electrode layer, which is the base electrode, to shrink. An object of the present invention is to provide a conductive paste for chip-type electronic components that reduces the incidence of cracks in bare chips and does not deteriorate electrical properties and adhesive properties to substrates.

【0006】[0006]

【課題を解決するための手段】本発明者らは、従来の導
電性ペーストが金属粉末の焼結を円滑に促進することに
重点がおかれた結果、緻密で硬度の高い焼付け電極層が
形成され、サーマルショックを受けたときに熱応力が十
分に緩和されないことを見出し、本発明に到達した。本
発明は金属粉末とガラスフリットと不活性有機ビヒクル
と添加剤を含み、セラミック誘電体からなるベアチップ
の表面に塗布した後焼付けて端子電極を形成するチップ
型電子部品用導電性ペーストである。その特徴ある構成
は添加剤がAl2O3,MgO,CaO,BaO,Zn
Oのいずれか1種又は2種以上の焼結制御用フィラーを
含み、このフィラーを金属粉末に対して0.3〜5重量
%添加したことにある。
[Means for Solving the Problems] The present inventors have focused on promoting the smooth sintering of metal powder with conventional conductive pastes, and as a result, a dense and hard baked electrode layer is formed. The present invention was developed based on the discovery that thermal stress is not sufficiently relaxed when a thermal shock is applied. The present invention is a conductive paste for chip-type electronic components, which contains metal powder, glass frit, an inert organic vehicle, and additives, and which is applied to the surface of a bare chip made of a ceramic dielectric and then baked to form a terminal electrode. Its characteristic structure is that the additives are Al2O3, MgO, CaO, BaO, Zn.
The present invention includes one or more fillers for sintering control such as O, and this filler is added in an amount of 0.3 to 5% by weight based on the metal powder.

【0007】以下、本発明を詳述する。本発明の金属粉
末には、Ag,Au,Pd,Pt等の貴金属、Cu,N
i等の卑金属、又はこれらを混合した粉末が使用される
。金属粉末は焼結して端子電極に導電性を与える。ガラ
スフリットには、ホウケイ酸亜鉛、アルカリ金属及びア
ルカリ土類金属を含有するホウケイ酸亜鉛、ホウケイ酸
鉛、ホウケイ酸ビスマス等のホウケイ酸系ガラス、ホウ
酸亜鉛系ガラス、ホウ酸カドミウム系ガラス等が用いら
れる。ガラスフリットは金属粉末の焼結を促進し、ベア
チップとの界面を接合させるために用いられる。また不
活性有機ビヒクルには、メチルセルロース、エチルセル
ロース等をブチルカルビトール、テルピネオール等の有
機溶剤に溶解したものが用いられる。上記セルロース類
は上記有機溶剤に5〜30重量%の割合で混合される。 有機ビヒクルはペーストの粘度を調整し、ベアチップ表
面への塗布を容易にするために用いられる。
The present invention will be explained in detail below. The metal powder of the present invention includes noble metals such as Ag, Au, Pd, and Pt, Cu, N, etc.
Base metals such as i, or powders of mixtures thereof are used. The metal powder is sintered to provide electrical conductivity to the terminal electrode. Glass frits include zinc borosilicate, borosilicate glass containing alkali metals and alkaline earth metals, lead borosilicate, bismuth borosilicate, etc., zinc borate glass, cadmium borate glass, etc. used. Glass frit is used to promote sintering of the metal powder and bond the interface with the bare chip. Further, as the inert organic vehicle, a solution of methyl cellulose, ethyl cellulose, etc. in an organic solvent such as butyl carbitol, terpineol, etc. is used. The celluloses are mixed in the organic solvent in a proportion of 5 to 30% by weight. The organic vehicle is used to adjust the viscosity of the paste and facilitate its application to the bare chip surface.

【0008】導電性ペーストの添加剤は、Al2O3,
MgO,CaO,BaO,ZnOのいずれか1種又は2
種以上の焼結制御用フィラーを含む。この添加剤は金属
粉末の焼結を遅延させるために用いられる。導電性ペー
ストは、ペースト100重量%とするとき、65〜80
重量%の金属粉末と、この金属粉末に対して1〜30重
量%のガラスフリットと、この金属粉末に対して0.3
〜5重量%の焼結制御用フィラーと、残部が有機ビヒク
ルとにより構成される。金属粉末が65重量%未満にな
ると電極の導電性に劣り、80重量%を越えるとベアチ
ップとの接着性が劣化する。ガラスフリットが1重量%
未満になると焼結金属が多孔質になり電解めっき時の電
解液が空孔に浸入し易くなる。この結果、長期の信頼性
に対して問題があり、端子電極とベアチップとの接着強
度が低下し、端子電極の耐湿性が劣化する。コンデンサ
の場合には誘電正接(tanδ)が劣化する。またガラ
スフリットが30重量%を越えると焼付け時に電極層の
表面にガラスフリットが浮き出て、めっき膜の形成が阻
害され、はんだ耐熱性が不十分となる。焼結制御用フィ
ラーが0.3重量%未満になると、金属粉末の焼結を遅
延させる効果がなく、無添加の場合と変らない。これに
対して5重量%を越えると焼結が抑制され過ぎ、焼結金
属が多孔質になり、ガラスフリットが少ない場合と同様
の問題がある。
[0008] Additives for the conductive paste include Al2O3,
Any one or two of MgO, CaO, BaO, ZnO
Contains more than one filler for sintering control. This additive is used to retard the sintering of metal powders. The conductive paste has a content of 65 to 80% when the paste is 100% by weight.
% by weight of metal powder, 1-30% by weight of glass frit relative to this metal powder, and 0.3% by weight relative to this metal powder.
It is comprised of ~5% by weight filler for sintering control, and the remainder is an organic vehicle. If the metal powder content is less than 65% by weight, the conductivity of the electrode will be poor, and if it exceeds 80% by weight, the adhesion to the bare chip will deteriorate. Glass frit is 1% by weight
If it is less than this, the sintered metal becomes porous and the electrolytic solution during electrolytic plating tends to penetrate into the pores. As a result, there are problems with long-term reliability, the adhesive strength between the terminal electrode and the bare chip decreases, and the moisture resistance of the terminal electrode deteriorates. In the case of a capacitor, the dielectric loss tangent (tan δ) deteriorates. If the glass frit exceeds 30% by weight, the glass frit will stand out on the surface of the electrode layer during baking, inhibiting the formation of a plating film, and resulting in insufficient soldering heat resistance. When the amount of the sintering control filler is less than 0.3% by weight, it has no effect of delaying the sintering of the metal powder, and is no different from the case where no filler is added. On the other hand, if it exceeds 5% by weight, sintering will be suppressed too much, and the sintered metal will become porous, causing the same problem as when the amount of glass frit is small.

【0009】本発明の導電性ペーストはチップコンデン
サ、チップ抵抗、チップサーミスタ等のチップ型電子部
品の端子電極に用いられる。特に、チップ型積層セラミ
ックコンデンサに好適に用いられる。この場合、コンデ
ンサを構成するセラミック誘電体には鉛系ペロブスカイ
ト又はチタン酸バリウムを主成分とする誘電体材料が好
ましい。鉛系ペロブスカイトを主成分にする誘電体材料
としては、Pb(Mg1/3Nb2/3)O3,Pb(
Fe1/2Nb1/2)O3,PbTiO3等が挙げら
れる。
The conductive paste of the present invention is used for terminal electrodes of chip-type electronic components such as chip capacitors, chip resistors, and chip thermistors. In particular, it is suitably used for chip-type multilayer ceramic capacitors. In this case, the ceramic dielectric constituting the capacitor is preferably a dielectric material containing lead-based perovskite or barium titanate as a main component. Dielectric materials whose main component is lead-based perovskite include Pb(Mg1/3Nb2/3)O3, Pb(
Examples include Fe1/2Nb1/2)O3, PbTiO3, and the like.

【0010】0010

【作用】導電性ペースト中に上記割合でAl2O3,M
gO,CaO,BaO,ZnOのいずれか1種又は2種
以上の焼結制御用フィラーを添加すると、これらの金属
酸化物はいずれも焼付け時には金属粉末と殆ど反応せず
むしろ金属粉末の焼結を遅延させる。その結果、焼付け
電極層の収縮しようとするストレスや硬度が和られ、こ
の電極層表面に電解めっき処理を行ったときのベアチッ
プに対するサーマルショックが緩和される。またこの焼
結制御用フィラーは耐めっき性があり、めっき時に電極
中にめっき液が浸入することがない。
[Operation] Al2O3,M in the above proportion in the conductive paste
When one or more of gO, CaO, BaO, and ZnO are added as fillers for sintering control, these metal oxides hardly react with the metal powder during baking, but rather promote the sintering of the metal powder. delay. As a result, the stress and hardness of the baked electrode layer that tends to shrink is alleviated, and the thermal shock to the bare chip when electrolytic plating is performed on the surface of this electrode layer is alleviated. Furthermore, this filler for sintering control has plating resistance, and the plating solution does not enter into the electrode during plating.

【0011】[0011]

【発明の効果】以上述べたように、本発明によれば、導
電性ペーストにAl2O3等の金属酸化物からなる焼結
制御用フィラーを少量添加することにより、下地電極で
ある焼付け電極層の収縮しようとするストレスや硬度が
低下し、サーマルショックが緩和され、ベアチップのク
ラックの発生率を減少させ、電気特性が低下せず、基板
への接着特性が劣化しない。この結果、信頼性の高いチ
ップ型電子部品が得られる。
As described above, according to the present invention, by adding a small amount of a sintering control filler made of a metal oxide such as Al2O3 to the conductive paste, the shrinkage of the baked electrode layer, which is the base electrode, can be reduced. The stress and hardness of the chip are reduced, the thermal shock is alleviated, the incidence of bare chip cracking is reduced, the electrical properties are not degraded, and the adhesion properties to the substrate are not degraded. As a result, a highly reliable chip-type electronic component can be obtained.

【0012】0012

【実施例】次に本発明の実施例を図面に基づいて比較例
とともに説明する。 <実施例>図1に示すように、この例ではチップ型電子
部品はチップ型積層セラミックコンデンサ10である。 このコンデンサ10はベアチップ11とこのチップ11
の両端部に形成された下地電極12とを備える。チップ
11は鉛ペロブスカイト系であって、貴金属のAg70
/Pd30からなる内部電極13を有し、長さ3.2m
m、幅1.6mm、厚み0.85mmのサイズを有する
。下地電極12の表面にはNiめっき層14及びSn/
Pbめっき層15がこの順に形成される。
EXAMPLES Next, examples of the present invention will be explained based on the drawings together with comparative examples. <Embodiment> As shown in FIG. 1, the chip-type electronic component in this example is a chip-type multilayer ceramic capacitor 10. This capacitor 10 has a bare chip 11 and this chip 11
and base electrodes 12 formed at both ends of the base electrode. The chip 11 is made of lead perovskite and is made of noble metal Ag70.
It has an internal electrode 13 made of /Pd30 and has a length of 3.2 m.
It has a size of 1.6 mm in width and 0.85 mm in thickness. The surface of the base electrode 12 is coated with a Ni plating layer 14 and Sn/
Pb plating layer 15 is formed in this order.

【0013】下地電極を次の条件により形成した。導電
性ペースト100重量%とするとき75重量%の金属粉
末と、この金属成分に対して10重量%のガラスフリッ
トと、表1に示すように金属粉末に対して0.3〜5重
量%の範囲内になるように配合した9種類の焼結制御用
フィラーと、残部が不活性有機ビヒクルとを混練して導
電性ペーストを調製した。ここで金属粉末はAg100
重量%からなり、ガラスフリットはCdO(15重量%
)−PbO(25重量%)−B2O3(20重量%)−
SiO2(40重量%)からなる。また有機ビヒクルは
エチルセルロースをブチルカルビトールとテルピネオー
ルに混合したものを用いた。焼結制御用フィラーはAl
2O3,MgO,CaO,BaO,ZnOのいずれか1
種と、Al2O3とMgOを混合したものを用いた。こ
のペーストを焼付け後の厚さが90μmになるようにベ
アチップの両端部にディップ方式で塗布し、大気圧下、
150℃で10分間乾燥した。このチップを25℃/分
の速度で、大気圧下、680℃まで昇温しそこで5分間
保持した後、20分/分の速度で室温まで降温してAg
からなる下地電極を得た。
A base electrode was formed under the following conditions. When the conductive paste is 100% by weight, 75% by weight of metal powder, 10% by weight of glass frit based on this metal component, and 0.3 to 5% by weight based on the metal powder as shown in Table 1. A conductive paste was prepared by kneading nine types of sintering control fillers blended within the range and the remainder being an inert organic vehicle. Here, the metal powder is Ag100
% by weight, and the glass frit contains CdO (15% by weight).
)-PbO (25% by weight)-B2O3 (20% by weight)-
Consists of SiO2 (40% by weight). The organic vehicle used was a mixture of ethyl cellulose, butyl carbitol, and terpineol. Filler for sintering control is Al
Any one of 2O3, MgO, CaO, BaO, ZnO
A mixture of seeds, Al2O3 and MgO was used. This paste was applied by dipping to both ends of the bare chip so that the thickness after baking was 90 μm, and the paste was applied under atmospheric pressure.
It was dried at 150°C for 10 minutes. The chip was heated to 680°C under atmospheric pressure at a rate of 25°C/min, held there for 5 minutes, and then cooled to room temperature at a rate of 20 minutes/min to remove Ag.
A base electrode was obtained.

【0014】Niめっき層及びSn/Pbめっき層を次
の条件により形成した。pH4.0、温度50℃のスル
ファミン酸ニッケル(Ni(NH2SO3)2・4H2
O)120g/Lの組成の浴を用い、電解バレルめっき
法で下地電極の表面に2μm厚のNiめっき層を形成し
た。pH4.5、温度25℃の錫(Sn)と鉛(Pb)
が9:1の組成の浴を用い、電解バレルめっき法でNi
めっき層の表面に6μm厚のSn/Pbめっき層を形成
した。 これにより、下地電極の上に更に2層のめっき層を形成
した積層セラミックコンデンサを得た。
A Ni plating layer and a Sn/Pb plating layer were formed under the following conditions. Nickel sulfamate (Ni(NH2SO3)2.4H2 at pH 4.0 and temperature 50°C)
O) A 2 μm thick Ni plating layer was formed on the surface of the base electrode by electrolytic barrel plating using a bath with a composition of 120 g/L. Tin (Sn) and lead (Pb) at pH 4.5 and temperature 25°C
Ni was deposited by electrolytic barrel plating using a bath with a composition of 9:1.
A 6 μm thick Sn/Pb plating layer was formed on the surface of the plating layer. As a result, a multilayer ceramic capacitor was obtained in which two further plating layers were formed on the base electrode.

【0015】<比較例>表1に示すように焼結制御用フ
ィラーを全く添加しない導電性ペースト、或いはAl2
O3,MgO,ZnOのいずれか1種からなる焼結制御
用フィラーを0.3〜5重量%の範囲外になるように配
合した導電性ペーストをそれぞれ実施例と同一のベアチ
ップの両端部に塗布して焼付けた以外は実施例と同様に
して積層セラミックコンデンサを得た。
<Comparative Example> As shown in Table 1, a conductive paste containing no filler for sintering control, or an Al2
A conductive paste containing a filler for sintering control consisting of any one of O3, MgO, and ZnO in an amount outside the range of 0.3 to 5% by weight was applied to both ends of the same bare chip as in the example. A multilayer ceramic capacitor was obtained in the same manner as in the example except that the capacitor was baked.

【0016】<測定方法>上記実施例及び比較例で作製
しためっき層付きの積層セラミックコンデンサについて
次の(a)〜(d)の特性を、また2層のめっき層を施
さない以外は上記実施例及び比較例と同一の積層セラミ
ックコンデンサについて次の(a)〜(c)の特性を測
定した。括弧内の数値nは試験した試料数である。 (a) 誘電正接(%)(n=30) 1kHz、1Vrmsで測定した。 (b) サーマルショック後の下地電極内側のクラック
発生(n=100) 350℃の共晶はんだ(Sn63/Pb37)中に金属
ピンセットで掴んだ試料を予熱せずに1秒間浸漬し、引
上げた後、熱濃硝酸で煮沸、溶解して下地電極を除去し
、下地電極の内側のベアチップにクラックが入っている
かどうかを調べた。 (c) 引張強度(n=10) 積層セラミックコンデンサの下地電極に0.8mmのは
んだ引き鋼線を230℃のホットプレート上で共晶クリ
ームはんだ(千住金属社製SPT−55−2062−M
10)により接着し、この鋼線を引張ることにより引張
強度を測定した。 (d) 信頼性(耐湿負荷試験)(n=20)+85℃
の温度で85%の相対湿度下、50Vの直流電圧を印加
して1000時間に至るまでの劣化の有無を調べた。
<Measurement method> The following characteristics (a) to (d) were measured for the multilayer ceramic capacitors with plating layers manufactured in the above Examples and Comparative Examples, and in the above implementation except that two plating layers were not provided. The following characteristics (a) to (c) were measured for the same multilayer ceramic capacitors as those in the examples and comparative examples. The number n in parentheses is the number of samples tested. (a) Dielectric loss tangent (%) (n=30) Measured at 1 kHz and 1 Vrms. (b) Cracks on the inside of the base electrode after thermal shock (n = 100) A sample held with metal tweezers was immersed in eutectic solder (Sn63/Pb37) at 350°C for 1 second without preheating, and then pulled out. The base electrode was removed by boiling and dissolving it in hot concentrated nitric acid, and it was examined whether there were any cracks in the bare chip inside the base electrode. (c) Tensile strength (n=10) A 0.8 mm soldered steel wire was soldered to the base electrode of a multilayer ceramic capacitor on a hot plate at 230°C with eutectic cream solder (SPT-55-2062-M manufactured by Senju Metal Co., Ltd.).
10), and the tensile strength was measured by pulling the steel wire. (d) Reliability (humidity load test) (n=20) +85°C
The presence or absence of deterioration was examined for 1000 hours by applying a DC voltage of 50 V at a temperature of 85% and a relative humidity of 85%.

【0017】<測定結果と評価>上記(a)〜(d)の
結果を表1に示す。表1より、4種類の比較例の積層セ
ラミックコンデンサは下地電極内側のクラック発生率が
高く、また4種類の比較例のうち、焼結制御用フィラー
が5重量%を越えるもの(比較例3,比較例4)は、め
っき層が有無により誘電正接、接着強度の値が大きく変
動し、更に焼結制御用フィラーの添加量が所定の範囲外
であるものは350時間以下で劣化した。これに対して
、9種類の実施例の積層セラミックコンデンサはめっき
層の有無に拘らず誘電正接、接着強度の値の変動は極め
て小さかった。また下地電極内側のクラックの発生率は
極めて低く、更に焼結制御用フィラーの添加量が所定の
範囲内であるものは1000時間経過後も劣化が見られ
なかった。
<Measurement Results and Evaluation> Table 1 shows the results of (a) to (d) above. From Table 1, the multilayer ceramic capacitors of the four comparative examples have a high crack occurrence rate on the inside of the base electrode, and among the four comparative examples, the ones containing more than 5% by weight of filler for sintering control (Comparative Example 3, In Comparative Example 4), the values of dielectric loss tangent and adhesive strength varied greatly depending on the presence or absence of a plating layer, and furthermore, those in which the amount of sintering control filler added was outside the predetermined range deteriorated within 350 hours. On the other hand, in the multilayer ceramic capacitors of the nine types of Examples, variations in the values of dielectric loss tangent and adhesive strength were extremely small regardless of the presence or absence of a plating layer. Furthermore, the rate of occurrence of cracks on the inside of the base electrode was extremely low, and no deterioration was observed even after 1000 hours had passed when the amount of sintering control filler added was within a predetermined range.

【0017】[0017]

【表1】[Table 1]

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明実施例の積層セラミックコンデンサの断
面図。
FIG. 1 is a sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10  積層セラミックコンデンサ 11  ベアチップ 12  下地電極 13  内部電極 14,15  めっき層 10 Multilayer ceramic capacitor 11 Bare chip 12 Base electrode 13 Internal electrode 14,15 Plating layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  金属粉末とガラスフリットと不活性有
機ビヒクルと添加剤を含み、セラミック誘電体からなる
ベアチップの表面に塗布した後焼付けて端子電極を形成
するチップ型電子部品用導電性ペーストであって、前記
添加剤はAl2O3,MgO,CaO,BaO,ZnO
のいずれか1種又は2種以上の焼結制御用フィラーを含
み、前記フィラーを前記金属粉末に対して0.3〜5重
量%添加したことを特徴とするチップ型電子部品用導電
性ペースト。
1. A conductive paste for chip-type electronic components, which contains metal powder, glass frit, an inert organic vehicle, and additives, and which is applied to the surface of a bare chip made of a ceramic dielectric and then baked to form a terminal electrode. The additives include Al2O3, MgO, CaO, BaO, ZnO.
A conductive paste for chip-type electronic components, characterized in that it contains one or more fillers for sintering control, and the filler is added in an amount of 0.3 to 5% by weight based on the metal powder.
【請求項2】  チップ型電子部品がセラミックコンデ
ンサである請求項1記載のチップ型電子部品用導電性ペ
ースト。
2. The conductive paste for a chip-type electronic component according to claim 1, wherein the chip-type electronic component is a ceramic capacitor.
【請求項3】  セラミック誘電体が鉛系ペロブスカイ
ト又はチタン酸バリウムを主成分とする請求項2記載の
チップ型電子部品用導電性ペースト。
3. The conductive paste for a chip-type electronic component according to claim 2, wherein the ceramic dielectric material contains lead-based perovskite or barium titanate as a main component.
JP3081994A 1991-03-20 1991-03-20 Conductive paste for chip-type electronic components Expired - Fee Related JP2973558B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3081994A JP2973558B2 (en) 1991-03-20 1991-03-20 Conductive paste for chip-type electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3081994A JP2973558B2 (en) 1991-03-20 1991-03-20 Conductive paste for chip-type electronic components

Publications (2)

Publication Number Publication Date
JPH04293214A true JPH04293214A (en) 1992-10-16
JP2973558B2 JP2973558B2 (en) 1999-11-08

Family

ID=13762027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3081994A Expired - Fee Related JP2973558B2 (en) 1991-03-20 1991-03-20 Conductive paste for chip-type electronic components

Country Status (1)

Country Link
JP (1) JP2973558B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280248A (en) * 2001-03-21 2002-09-27 Sumitomo Metal Mining Co Ltd Copper paste composition for external electrode, and stacked ceramic capacitor using the same
WO2007032151A1 (en) * 2005-09-13 2007-03-22 Toyo Aluminium Kabushiki Kaisha Aluminum paste composition and solar cell element making use of the same
US7267713B2 (en) 2003-04-28 2007-09-11 Murata Manufacturing Co., Ltd. Conductive paste and glass circuit structure
JP2008503103A (en) * 2004-06-09 2008-01-31 フエロ コーポレーション Copper termination ink containing lead-free and cadmium-free glass for capacitors
JP2008117790A (en) * 2008-01-16 2008-05-22 Murata Mfg Co Ltd Conductive paste, and glass circuit structure
JP2012156171A (en) * 2011-01-24 2012-08-16 Taiyo Yuden Co Ltd Multilayer ceramic capacitor and manufacturing method of the same
CN108470614A (en) * 2017-02-23 2018-08-31 E.I.内穆尔杜邦公司 Chip resistor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280248A (en) * 2001-03-21 2002-09-27 Sumitomo Metal Mining Co Ltd Copper paste composition for external electrode, and stacked ceramic capacitor using the same
JP4670164B2 (en) * 2001-03-21 2011-04-13 住友金属鉱山株式会社 Copper paste composition for external electrodes and multilayer ceramic capacitor using the same
US7267713B2 (en) 2003-04-28 2007-09-11 Murata Manufacturing Co., Ltd. Conductive paste and glass circuit structure
JP2008503103A (en) * 2004-06-09 2008-01-31 フエロ コーポレーション Copper termination ink containing lead-free and cadmium-free glass for capacitors
JP4805268B2 (en) * 2004-06-09 2011-11-02 フエロ コーポレーション Copper termination ink containing lead-free and cadmium-free glass for capacitors
WO2007032151A1 (en) * 2005-09-13 2007-03-22 Toyo Aluminium Kabushiki Kaisha Aluminum paste composition and solar cell element making use of the same
JP2008117790A (en) * 2008-01-16 2008-05-22 Murata Mfg Co Ltd Conductive paste, and glass circuit structure
JP2012156171A (en) * 2011-01-24 2012-08-16 Taiyo Yuden Co Ltd Multilayer ceramic capacitor and manufacturing method of the same
CN108470614A (en) * 2017-02-23 2018-08-31 E.I.内穆尔杜邦公司 Chip resistor
CN108470614B (en) * 2017-02-23 2022-03-22 E.I.内穆尔杜邦公司 Chip resistor

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