JPH0878279A - Formation of outer electrode on electronic chip device - Google Patents

Formation of outer electrode on electronic chip device

Info

Publication number
JPH0878279A
JPH0878279A JP6212689A JP21268994A JPH0878279A JP H0878279 A JPH0878279 A JP H0878279A JP 6212689 A JP6212689 A JP 6212689A JP 21268994 A JP21268994 A JP 21268994A JP H0878279 A JPH0878279 A JP H0878279A
Authority
JP
Japan
Prior art keywords
chip
electrode
forming
base electrode
type electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6212689A
Other languages
Japanese (ja)
Inventor
Yoshiomi Go
良臣 郷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6212689A priority Critical patent/JPH0878279A/en
Publication of JPH0878279A publication Critical patent/JPH0878279A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To form an outer electrode excellent in solder heat resistance and solderability. CONSTITUTION: A paste containing a metal. powder, a glass and/or an inorganic oxide is baked on the side face of a bare chip 3 comprising a sintered ceramic to form an underlying electrode 4. The underlying electrode is then subjected to abrasion and the surface layer is removed partially before plating films 5, 6 are formed. When the surface layer of the underlying electrode is removed partially by abrasion, glass and inorganic oxide projecting from the surface are removed and thereby continuous plating layers 5, 6 can be formed easily on the surface of the underlying electrode. Consequently, an outer electrode excellent in solderability and solder heat resistance can be formed without decreasing the content of glass and/or inorganic oxide in the conductive paste for forming the underlying electrode and thereby ensuring the plating liquid permeation resistance and the bonding strength to a bare chip of the underlying electrode.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層セラミックコンデ
ンサ、チップ抵抗、チップサーミスタ、チップインダク
ターなどのチップ型電子部品の外部電極形成方法に係
り、特に、下地電極を被層するメッキ膜を良好に形成し
て、はんだ耐熱性及びはんだ付け性に優れた外部電極を
形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an external electrode of a chip type electronic component such as a multilayer ceramic capacitor, a chip resistor, a chip thermistor, a chip inductor, etc. And an external electrode having excellent solder heat resistance and solderability.

【0002】[0002]

【従来の技術】積層セラミックコンデンサ、チップ抵
抗、チップサーミスタ、チップインダクターなどのチッ
プ型電子部品は、セラミック焼結体からなるベアチップ
と、その内部に設けられた内部電極及びこの内部電極に
導通するように、セラミック素体の側面に設けられた端
子電極とで主に構成され、この端子電極を基板にはんだ
付けすることにより実装されている。
2. Description of the Related Art Chip-type electronic components such as multilayer ceramic capacitors, chip resistors, chip thermistors, and chip inductors are bare chips made of a ceramic sintered body, internal electrodes provided therein, and conduction to the internal electrodes. As described above, it is mainly configured with the terminal electrode provided on the side surface of the ceramic body, and is mounted by soldering this terminal electrode to the substrate.

【0003】従来、チップ型電子部品の端子電極は、次
のようにして形成されている。即ち、まず、貴金属粉末
とガラスフリットを混合したものを有機ビヒクルに混練
し、得られた導電性ペーストをベアチップの側面に塗布
した後、600〜800℃程度の温度で焼成してメッキ
下地電極を形成する。その後、この下地電極上にはんだ
付け時のくわれ(溶蝕)を防止するためのNi(ニッケ
ル)メッキ皮膜を形成し、更に、このNiメッキ皮膜の
酸化によるはんだ付け性の低下を防止するために、Ni
メッキ皮膜表面をSn(スズ)メッキ皮膜又ははんだメ
ッキ皮膜で被覆して外部電極を形成する。
Conventionally, the terminal electrodes of chip type electronic parts are formed as follows. That is, first, a mixture of a noble metal powder and a glass frit is kneaded in an organic vehicle, the obtained conductive paste is applied to the side surface of the bare chip, and then baked at a temperature of about 600 to 800 ° C. to form a plating base electrode. Form. After that, a Ni (nickel) plating film is formed on the base electrode to prevent cracking (corrosion) during soldering, and further, in order to prevent deterioration of solderability due to oxidation of the Ni plating film. , Ni
An external electrode is formed by coating the surface of the plating film with a Sn (tin) plating film or a solder plating film.

【0004】[0004]

【発明が解決しようとする課題】上記従来のチップ型電
子部品の外部電極形成方法では、次のような問題があっ
た。即ち、下地電極のベアチップへの接着強度を高め、
また、メッキ時のメッキ液の浸入を防止して、高い信頼
性を得るために、下地電極形成のためのペーストに、接
着力が強く、耐メッキ液性の高いガラスフリットを配合
しているが、このガラスフリットは、下地電極の焼成過
程で軟化、流動し、貴金属粉末の焼結に伴いしばしば下
地電極表面に浮き出し、この表面にガラス層を形成す
る。しかし、下地電極表面にガラスが存在すると、この
下地電極上へのメッキ膜の形成が阻害され、メッキ膜面
が不連続となり、欠陥のない連続的なメッキ皮膜を形成
し得ない。この場合には端子電極のはんだ耐熱性及びは
んだ付け性が損なわれる。
The above-mentioned conventional method of forming external electrodes of chip-type electronic parts has the following problems. That is, the adhesion strength of the base electrode to the bare chip is increased,
In addition, in order to prevent the penetration of the plating solution during plating and to obtain high reliability, the paste for forming the base electrode contains a glass frit that has a strong adhesive force and high resistance to the plating solution. The glass frit softens and flows during the firing process of the base electrode, and often floats on the surface of the base electrode as the precious metal powder is sintered, forming a glass layer on the surface. However, if glass is present on the surface of the base electrode, the formation of the plating film on the base electrode is hindered, the surface of the plating film becomes discontinuous, and a continuous plating film without defects cannot be formed. In this case, the solder heat resistance and solderability of the terminal electrode are impaired.

【0005】連続的なメッキ皮膜を容易に形成して、は
んだ耐熱性及びはんだ付け性を確保するためには、下地
電極形成のためのペースト中へのガラスフリットの配合
量を抑える必要があるが、この場合には、下地電極の接
着強度が不足し、また、メッキ液の浸入を防止し得なく
なる。
In order to easily form a continuous plating film and secure solder heat resistance and solderability, it is necessary to suppress the amount of glass frit compounded in the paste for forming the base electrode. In this case, the adhesive strength of the base electrode is insufficient, and it is impossible to prevent the plating solution from entering.

【0006】本発明は上記従来の問題点を解決し、チッ
プ型電子部品の外部電極の形成に当り、下地電極表面へ
のメッキ皮膜の形成阻害を防止して、信頼性が高く、は
んだ耐熱性及びはんだ付け性に優れた外部電極を形成す
る方法を提供することを目的とする。
The present invention solves the above-mentioned conventional problems and prevents the formation of a plating film on the surface of a base electrode when forming an external electrode of a chip-type electronic component, thus ensuring high reliability and solder heat resistance. Another object of the present invention is to provide a method for forming an external electrode having excellent solderability.

【0007】[0007]

【課題を解決するための手段】請求項1のチップ型電子
部品の外部電極形成方法は、セラミック焼結体からなる
ベアチップの側面に、金属粉末とガラス及び/又は無機
酸化物とを含むペーストを焼き付けて下地電極を形成し
た後、該下地電極上にメッキ膜を形成して外部電極を形
成する方法において、メッキ膜の形成に先立ち、下地電
極表面を研磨処理して、該下地電極の表層の一部を除去
することを特徴とする。
According to a first aspect of the present invention, there is provided an external electrode forming method for a chip type electronic component, wherein a paste containing metal powder and glass and / or an inorganic oxide is applied to a side surface of a bare chip made of a ceramic sintered body. In the method of forming an external electrode by forming a plated film on the underlying electrode after baking to form the underlying electrode, a surface of the underlying electrode is polished to form a surface layer of the underlying electrode before the plating film is formed. It is characterized by removing a part.

【0008】請求項2のチップ型電子部品の外部電極形
成方法は、請求項1に記載の方法において、金属として
Ag或いはAgとPdを含有する下地電極の上にNiメ
ッキ膜を形成し、更に、このNiメッキ膜上にSn或い
はSn/Pbメッキ膜を形成することを特徴とする。
According to a second aspect of the present invention, there is provided an external electrode forming method for a chip-type electronic component, wherein the Ni plating film is formed on a base electrode containing Ag or Ag and Pd as a metal. A Sn or Sn / Pb plated film is formed on the Ni plated film.

【0009】請求項3のチップ型電子部品の外部電極形
成方法は、請求項1又は2に記載の方法において、研磨
処理は研磨粉を用いて行うことを特徴とする。
According to a third aspect of the present invention, there is provided a method of forming an external electrode for a chip-type electronic component, which is characterized in that the polishing treatment is performed by using polishing powder.

【0010】請求項4のチップ型電子部品の外部電極形
成方法は、請求項3の方法において、研磨粉はSiC研
磨粉であることを特徴とする。
According to a fourth aspect of the present invention, there is provided an external electrode forming method for a chip-type electronic component, wherein the polishing powder is SiC polishing powder.

【0011】請求項5のチップ型電子部品の外部電極形
成方法は、請求項3又は4の方法において、研磨処理を
研磨粉と界面活性剤とを用いて行うことを特徴とする。
According to a fifth aspect of the present invention, there is provided an external electrode forming method for a chip-type electronic component, which is characterized in that in the third or fourth aspect, the polishing process is performed by using polishing powder and a surfactant.

【0012】請求項6のチップ型電子部品の外部電極形
成方法は、請求項1ないし5のいずれか1項に記載の方
法において、チップ型電子部品が積層セラミックコンデ
ンサであることを特徴とする。
According to a sixth aspect of the present invention, there is provided a method of forming external electrodes for a chip-type electronic component, wherein the chip-type electronic component is a laminated ceramic capacitor in the method according to any one of the first to fifth aspects.

【0013】以下に図面を参照して本発明を詳細に説明
する。
The present invention will be described in detail below with reference to the drawings.

【0014】図1は、本発明の方法で製造されるチップ
型電子部品の一実施例に係る積層セラミックコンデンサ
を示す断面図である。
FIG. 1 is a sectional view showing a monolithic ceramic capacitor according to an embodiment of a chip type electronic component manufactured by the method of the present invention.

【0015】図示の積層セラミックコンデンサ10は、
表面実装型のチップコンデンサであり、内部電極1を有
するセラミック誘電体2を複数回積層して得られたグリ
ーンチップを焼成して得られるベアチップ3にメッキ下
地電極4、Niメッキ皮膜5及びはんだメッキ皮膜6を
形成したものである。
The illustrated monolithic ceramic capacitor 10 is
A surface mounting type chip capacitor, a bare chip 3 obtained by firing a green chip obtained by laminating a plurality of ceramic dielectrics 2 having an internal electrode 1 a plurality of times, a plating base electrode 4, a Ni plating film 5 and a solder plating. The film 6 is formed.

【0016】ここで、このセラミック誘電体2として
は、鉛系、チタン酸バリウム系等の誘電体が用いられ、
内部電極1としてはPd,Pt,Ag/Pd等の貴金
属、或いはNi,Cu,Fe,Co等の卑金属が用いら
れる。
Here, as the ceramic dielectric 2, a lead-based or barium titanate-based dielectric is used.
As the internal electrode 1, a noble metal such as Pd, Pt, Ag / Pd or a base metal such as Ni, Cu, Fe or Co is used.

【0017】メッキ下地電極4は、Ag,Pd,Pt,
Cu等の金属の1種又は2種以上と、ガラスフリット或
いは無機酸化物粉末とを、不活性有機ビヒクルで混練し
て得られた導電性ペーストをセラミック誘電体2よりな
るベアチップ3の両端面に塗布、焼成して形成される。
The plating base electrode 4 is made of Ag, Pd, Pt,
A conductive paste obtained by kneading one or more metals such as Cu and glass frit or inorganic oxide powder with an inert organic vehicle is applied to both end surfaces of the bare chip 3 made of the ceramic dielectric 2. It is formed by coating and baking.

【0018】具体的には、ベアチップ3に導電性ペース
トを塗布し、150℃〜200℃で乾燥した後、600
℃〜800℃で焼成してメッキ下地電極4を焼き付け
る。その際、ガラスフリットが軟化、流動し、金属の焼
結に伴いしばしば下地電極表面へ浮き出し、表面にガラ
ス及び/又は無機酸化物層を形成する。このため、焼成
後のメッキ下地電極表面にはガラス及び/又は無機酸化
物が存在したものとなる。
Specifically, the bare chip 3 is coated with a conductive paste, dried at 150 to 200 ° C., and then 600
The plating base electrode 4 is baked by baking at ℃ to 800 ℃. At that time, the glass frit softens and flows, and often floats to the surface of the base electrode due to the sintering of the metal to form a glass and / or an inorganic oxide layer on the surface. For this reason, the glass and / or the inorganic oxide are present on the surface of the plating base electrode after firing.

【0019】本発明においては、ベアチップ3に下地電
極4を形成した後、この下地電極4の表面を研磨処理
し、下地電極4の表層の一部を除去することで、下地電
極4の焼き付け過程で下地電極4の表面に浮き出したガ
ラス及び/又は無機酸化物を除去する。
In the present invention, after the base electrode 4 is formed on the bare chip 3, the surface of the base electrode 4 is polished to remove a part of the surface layer of the base electrode 4 to burn the base electrode 4. Then, the glass and / or the inorganic oxide that are raised on the surface of the base electrode 4 are removed.

【0020】研磨処理方法としては、例えば、ポットに
SiC等の研磨粉、界面活性剤、水及びメッキ下地電極
焼き付け後のベアチップを入れ、所定時間回転させ、そ
の後、ベアチップを篩い分け等により研磨粉と分離し、
洗浄後、100℃〜150℃で乾燥する方法が挙げられ
る。
As a polishing treatment method, for example, polishing powder such as SiC, a surfactant, water and a bare chip after baking of the plating base electrode are put in a pot and rotated for a predetermined time, and then the bare chip is sieved to remove the polishing powder. Separated from
The method of drying after washing | cleaning at 100 degreeC-150 degreeC is mentioned.

【0021】この場合、使用する研磨粉の種類としては
特に制限はなく、SiC、その他各種無機物の研磨粉等
を好適に使用できる。この研磨粉の粒度は適度に粗いも
のが好ましく、通常の場合、300〜500μm程度の
粒度のものが好適である。
In this case, the type of the polishing powder used is not particularly limited, and polishing powder of SiC or other various inorganic substances can be preferably used. The particle size of the polishing powder is preferably appropriately coarse, and in the normal case, the particle size of about 300 to 500 μm is suitable.

【0022】研磨粉の使用量は、少なすぎると本発明に
よるメッキ下地電極表面のガラス及び/又は無機酸化物
の研磨除去効果が十分に得られず、多すぎると取り扱い
性や研磨粉コストの面で不利になる。従って、研磨粉
は、チップに対して、体積割合で、チップ:研磨粉=
1:3〜10となるように用いるのが好ましい。また、
水はチップに対して体積割合で1:5〜20となるよう
に用いるのが好ましい。
If the amount of the polishing powder used is too small, the effect of polishing and removing the glass and / or the inorganic oxide on the surface of the plating base electrode according to the present invention cannot be sufficiently obtained, and if it is too large, the handling property and the cost of the polishing powder are reduced. Will be at a disadvantage. Therefore, the polishing powder is a volume ratio of the chip to the chip: polishing powder =
It is preferable to use it so as to be 1: 3 to 10. Also,
Water is preferably used in a volume ratio of 1: 5 to 20 with respect to chips.

【0023】界面活性剤を研磨粉及び水と混合して用い
るのは、研磨粉と水だけでは研磨粉の分散性が悪く、本
発明によるガラス及び/又は無機酸化物の研磨除去効果
が十分に得られないためであるが、界面活性剤は、研磨
粉と水との合計に対して、0.5〜1重量%の割合で添
加して使用するのが好ましい。
When the surfactant is mixed with the polishing powder and water, the dispersibility of the polishing powder is poor only with the polishing powder and water, and the effect of polishing and removing the glass and / or the inorganic oxide according to the present invention is sufficient. This is because the surfactant cannot be obtained, but it is preferable to use the surfactant by adding it in a proportion of 0.5 to 1% by weight based on the total amount of the polishing powder and water.

【0024】なお、界面活性剤としては、非イオン界面
活性剤等を用いることができる。
As the surfactant, a nonionic surfactant or the like can be used.

【0025】研磨処理により除去する下地電極の表層部
分の量は上記ポットの回転時間を制御することにより適
宜調整することができる。通常の場合、回転時間は60
〜240分程度とし、下地電極の表層の約10〜50μ
mの厚さ部分を除去するのが好ましい。
The amount of the surface layer portion of the base electrode removed by the polishing treatment can be appropriately adjusted by controlling the rotation time of the pot. Normally, the rotation time is 60
Approximately 240 minutes, approximately 10 to 50 μm of the surface layer of the base electrode
It is preferable to remove the m thick portion.

【0026】この研磨処理により研磨除去される成分
は、ガラスのみとは限らず、結晶性無機酸化物を含むガ
ラス、或いは全て結晶化したものである場合もある。
The component polished and removed by this polishing treatment is not limited to glass, but may be glass containing a crystalline inorganic oxide, or may be all crystallized.

【0027】このような研磨処理後は、常法に従って、
Niメッキ皮膜5及びはんだメッキ皮膜6を順次積層形
成する。
After such a polishing treatment, according to a conventional method,
The Ni plating film 5 and the solder plating film 6 are sequentially laminated.

【0028】このような本発明の方法において、対象と
なるチップ型電子部品としては特に制限はなく、本発明
は、積層セラミックコンデンサ、チップ抵抗、チップサ
ーミスタ、チップインダクター等の各種チップ型電子部
品に適用可能である。
In the method of the present invention as described above, the target chip type electronic component is not particularly limited, and the present invention is applicable to various chip type electronic components such as a monolithic ceramic capacitor, a chip resistor, a chip thermistor and a chip inductor. Is applicable to.

【0029】[0029]

【作用】ベアチップに外部電極形成用の導電性ペースト
を塗布、焼き付けした後、下地電極の表層の一部を研磨
処理により除去することにより、下地電極表面に浮き出
したガラス及び/又は無機酸化物が除去され、下地電極
表面に、連続したメッキ層を容易に形成することができ
るようになる。これにより、下地電極形成用の導電性ペ
ーストのガラス及び/又は無機酸化物配合量を低減する
ことなく、従って、下地電極の耐メッキ液浸透性及びベ
アチップへの接着強度を確保した上で、はんだ付け性及
びはんだ耐熱性に優れた外部電極を形成することができ
る。
[Function] The bare chip is coated with a conductive paste for forming an external electrode and baked, and then a part of the surface layer of the base electrode is removed by a polishing treatment to remove the glass and / or the inorganic oxide that is raised on the surface of the base electrode. After the removal, the continuous plating layer can be easily formed on the surface of the base electrode. Thereby, without reducing the glass and / or the inorganic oxide compounding amount of the conductive paste for forming the base electrode, and thus ensuring the resistance to penetration of the plating liquid of the base electrode and the adhesive strength to the bare chip, It is possible to form an external electrode having excellent attachability and solder heat resistance.

【0030】[0030]

【実施例】以下に実施例及び比較例を挙げて、本発明を
より具体的に説明する。
EXAMPLES The present invention will be described more specifically with reference to Examples and Comparative Examples below.

【0031】なお、以下において使用した積層セラミッ
クコンデンサチップは、鉛ペロブスカイト系セラミック
誘電体よりなる4.5mm×3.2mm×1.25mm
厚さのものであり、下地電極形成用の導電性ペーストと
しては、金属としてAgを75重量%含み、フリットと
してPbO−ZnO−B23 −SiO2 系ガラスフリ
ットをAgに対して10重量%含有するAgペーストを
用いた。
The laminated ceramic capacitor chip used in the following is 4.5 mm × 3.2 mm × 1.25 mm made of lead perovskite ceramic dielectric.
The thickness of the conductive paste for forming the base electrode includes 75% by weight of Ag as a metal and 10% by weight of PbO—ZnO—B 2 O 3 —SiO 2 -based glass frit as a frit with respect to Ag. % Contained Ag paste was used.

【0032】実施例1,比較例1 コンデンサチップにAgペーストを塗布した後、200
℃で10分間乾燥し、次いで、750℃で5分間保持し
て下地電極を焼き付けた。次に、この下地電極表面を研
磨処理した。
Example 1, Comparative Example 1 After coating Ag paste on a capacitor chip, 200
The substrate was dried at 0 ° C for 10 minutes, and then kept at 750 ° C for 5 minutes to burn the base electrode. Next, the surface of the base electrode was polished.

【0033】研磨処理はポットに下記割合で下地電極を
形成したコンデンサチップと、SiC研磨粉(平均粒径
200μm)と、界面活性剤(非イオン界面活性剤)と
水とを入れ、120分間回転させることにより行った。
In the polishing treatment, a capacitor chip having a base electrode formed at the following ratio in a pot, SiC polishing powder (average particle size 200 μm), a surfactant (nonionic surfactant) and water were put, and the mixture was rotated for 120 minutes. It was done by doing.

【0034】 SiC研磨粉:コンデンサチップの体積に対して10倍 水:コンデンサチップの体積に対して20倍 界面活性剤:研磨粉と水との合計重量に対して0.5重
量% この研磨処理により、下地電極の表面に浮き出した厚さ
10μm程度のガラス層が除去された。
SiC polishing powder: 10 times the volume of the capacitor chip Water: 20 times the volume of the capacitor chip Surfactant: 0.5% by weight based on the total weight of the polishing powder and water This polishing treatment As a result, the glass layer having a thickness of about 10 μm that was raised on the surface of the base electrode was removed.

【0035】その後、下地電極上に、常法に従ってNi
メッキ皮膜及びSn/Pb皮膜を順次形成した(実施例
1)。
After that, Ni was formed on the base electrode by a conventional method.
A plating film and a Sn / Pb film were sequentially formed (Example 1).

【0036】比較のため、上記研磨処理を施さないこと
以外は全く同様にして、コンデンサチップに外部電極を
形成した(比較例1)。
For comparison, an external electrode was formed on the capacitor chip in the same manner except that the polishing process was not performed (Comparative Example 1).

【0037】得られた積層セラミックコンデンサについ
て、下記方法により、はんだ付け性、はんだ耐熱性及び
Niメッキ皮膜被覆率を調べ、結果を表1に示した。
With respect to the obtained multilayer ceramic capacitor, solderability, solder heat resistance and Ni plating film coverage were examined by the following methods, and the results are shown in Table 1.

【0038】 はんだ付け性 作製した試料をロジン25重量%のエタノール溶液に2
秒浸漬後、230℃の共晶はんだSn/Pb(=63/
37(重量比))に2秒間浸漬した。その後、外部電極
表面が90%以上はんだで覆われているかどうかを実体
顕微鏡(×15倍)で調べ、はんだで覆われている面積
が90%以下のものを不良とした。
Solderability The prepared sample was immersed in an ethanol solution containing 25% by weight of rosin.
After the second dipping, the eutectic solder Sn / Pb (= 63 /
37 (weight ratio)) for 2 seconds. Then, it was examined by a stereoscopic microscope (× 15 times) whether or not the surface of the external electrode was covered with 90% or more of solder, and the case where the area covered with solder was 90% or less was determined to be defective.

【0039】 はんだ耐熱性 作製した試料をロジン25重量%のエタノール溶液に2
秒浸漬後、300℃の共晶はんだSn/Pb(=63/
37(重量比))に30秒間浸漬した。その後、はんだ
の付いていない部分を実体顕微鏡(×15倍)と断面の
光学顕微鏡観察により調べ、Niメッキ皮膜が存在しな
い部分が10%以上のものを不良とした。
Solder heat resistance The prepared sample was immersed in an ethanol solution containing 25% by weight of rosin.
After the second dipping, the eutectic solder Sn / Pb (= 63 /
37 (weight ratio)) for 30 seconds. After that, a portion without solder was examined by a stereoscopic microscope (× 15) and an optical microscope observation of a cross section, and a portion having no Ni plating film of 10% or more was determined to be defective.

【0040】 Niメッキ皮膜被覆率 Niメッキ皮膜形成後、光学顕微鏡により端子電極表面
を観察し、下地電極上のNiメッキ皮膜の被覆率を調べ
た。
Ni plating film coverage After the Ni plating film was formed, the surface of the terminal electrode was observed with an optical microscope to examine the coverage of the Ni plating film on the base electrode.

【0041】[0041]

【表1】 [Table 1]

【0042】表1より明らかなように、本発明によれ
ば、下地電極上に良好なメッキ皮膜を形成し、はんだ付
け性、はんだ耐熱性に優れた製品を製造することができ
る。
As is clear from Table 1, according to the present invention, a product having excellent solderability and solder heat resistance can be produced by forming a good plating film on the base electrode.

【0043】なお、上記実施例では、積層セラミックコ
ンデンサを例示したが、本発明は、積層セラミックコン
デンサに限らず、チップ抵抗、チップサーミスタ、チッ
プインダクター等の外部電極を有する全てのチップ型電
子部品に適用できることは言うまでもない。
In the above-mentioned embodiment, the monolithic ceramic capacitor is exemplified, but the present invention is not limited to the monolithic ceramic capacitor, and all chip type electronic parts having external electrodes such as chip resistors, chip thermistors, chip inductors and the like. It goes without saying that it can be applied to.

【0044】[0044]

【発明の効果】以上詳述した通り、本発明のチップ型電
子部品の外部電極形成方法によれば、はんだ付け性とは
んだ耐熱性に優れた非常に信頼性の高いチップ型電子部
品が提供される。
As described in detail above, according to the external electrode forming method for a chip-type electronic component of the present invention, a very reliable chip-type electronic component excellent in solderability and solder heat resistance is provided. It

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の方法で製造されるチップ型電子部品の
一実施例に係る積層セラミックコンデンサを示す断面図
である。
FIG. 1 is a cross-sectional view showing a monolithic ceramic capacitor according to an embodiment of a chip-type electronic component manufactured by the method of the present invention.

【符号の説明】[Explanation of symbols]

1 内部電極 2 セラミック誘電体 3 ベアチップ 4 下地電極 5 Niメッキ皮膜 6 はんだメッキ皮膜 10 積層セラミックコンデンサ 1 Internal Electrode 2 Ceramic Dielectric 3 Bare Chip 4 Base Electrode 5 Ni Plating Film 6 Solder Plating Film 10 Multilayer Ceramic Capacitor

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01G 4/252 4/30 311 E 7924−5E 9174−5E H01G 1/14 V ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01G 4/252 4/30 311 E 7924-5E 9174-5E H01G 1/14 V

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 セラミック焼結体からなるベアチップの
側面に、金属粉末とガラス及び/又は無機酸化物とを含
むペーストを焼き付けて下地電極を形成した後、該下地
電極上にメッキ膜を形成して外部電極を形成する方法に
おいて、 メッキ膜の形成に先立ち、下地電極表面を研磨処理し
て、該下地電極の表層の一部を除去することを特徴とす
るチップ型電子部品の外部電極形成方法。
1. A base electrode is formed by baking a paste containing metal powder and glass and / or an inorganic oxide on a side surface of a bare chip made of a ceramic sintered body, and then a plating film is formed on the base electrode. A method of forming an external electrode by a method of forming an external electrode of a chip-type electronic component, the method comprising: polishing a surface of a base electrode to remove a part of a surface layer of the base electrode before forming a plating film. .
【請求項2】 請求項1に記載の方法において、金属と
してAg或いはAgとPdを含有する下地電極の上にN
iメッキ膜を形成し、更に、このNiメッキ膜上にSn
或いはSn/Pbメッキ膜を形成することを特徴とする
チップ型電子部品の外部電極形成方法。
2. The method according to claim 1, wherein N is formed on the base electrode containing Ag or Ag and Pd as a metal.
An i-plated film is formed, and Sn is deposited on the Ni-plated film
Alternatively, a method of forming an external electrode of a chip-type electronic component, which comprises forming a Sn / Pb plating film.
【請求項3】 請求項1又は2に記載の方法において、
研磨処理は研磨粉を用いて行うことを特徴とするチップ
型電子部品の外部電極形成方法。
3. The method according to claim 1 or 2, wherein
A method of forming an external electrode for a chip-type electronic component, wherein the polishing process is performed using polishing powder.
【請求項4】 請求項3の方法において、研磨粉はSi
C研磨粉であることを特徴とするチップ型電子部品の外
部電極形成方法。
4. The method according to claim 3, wherein the polishing powder is Si.
A method for forming an external electrode for a chip-type electronic component, which is C polishing powder.
【請求項5】 請求項3又は4の方法において、研磨処
理を研磨粉と界面活性剤とを用いて行うことを特徴とす
るチップ型電子部品の外部電極形成方法。
5. The method for forming an external electrode for a chip-type electronic component according to claim 3, wherein the polishing treatment is performed using polishing powder and a surfactant.
【請求項6】 請求項1ないし5のいずれか1項に記載
の方法において、チップ型電子部品が積層セラミックコ
ンデンサであることを特徴とするチップ型電子部品の外
部電極形成方法。
6. The method according to claim 1, wherein the chip-type electronic component is a laminated ceramic capacitor.
JP6212689A 1994-09-06 1994-09-06 Formation of outer electrode on electronic chip device Withdrawn JPH0878279A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6212689A JPH0878279A (en) 1994-09-06 1994-09-06 Formation of outer electrode on electronic chip device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6212689A JPH0878279A (en) 1994-09-06 1994-09-06 Formation of outer electrode on electronic chip device

Publications (1)

Publication Number Publication Date
JPH0878279A true JPH0878279A (en) 1996-03-22

Family

ID=16626802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6212689A Withdrawn JPH0878279A (en) 1994-09-06 1994-09-06 Formation of outer electrode on electronic chip device

Country Status (1)

Country Link
JP (1) JPH0878279A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0836199A2 (en) * 1996-10-09 1998-04-15 Murata Manufacturing Co., Ltd. Thermistor chips and methods of making same
JP2011035147A (en) * 2009-07-31 2011-02-17 Tdk Corp Method of manufacturing coil component, and coil component
KR20180035133A (en) * 2016-09-28 2018-04-05 가부시키가이샤 무라타 세이사쿠쇼 Medium and method of manufacturing electronic component
JP2019140371A (en) * 2018-02-08 2019-08-22 サムソン エレクトロ−メカニックス カンパニーリミテッド. Inductor
US10957489B2 (en) 2016-09-28 2021-03-23 Murata Manufacturing Co., Ltd. Medium and method of manufacturing electronic component

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0836199A2 (en) * 1996-10-09 1998-04-15 Murata Manufacturing Co., Ltd. Thermistor chips and methods of making same
EP0836199A3 (en) * 1996-10-09 1999-01-07 Murata Manufacturing Co., Ltd. Thermistor chips and methods of making same
US5952911A (en) * 1996-10-09 1999-09-14 Murata Manufacturing Co., Ltd. Thermistor chips and methods of making same
US6100110A (en) * 1996-10-09 2000-08-08 Murata Manufacturing Co., Ltd. Methods of making thermistor chips
JP2011035147A (en) * 2009-07-31 2011-02-17 Tdk Corp Method of manufacturing coil component, and coil component
KR20180035133A (en) * 2016-09-28 2018-04-05 가부시키가이샤 무라타 세이사쿠쇼 Medium and method of manufacturing electronic component
US10957489B2 (en) 2016-09-28 2021-03-23 Murata Manufacturing Co., Ltd. Medium and method of manufacturing electronic component
JP2019140371A (en) * 2018-02-08 2019-08-22 サムソン エレクトロ−メカニックス カンパニーリミテッド. Inductor
US11056272B2 (en) 2018-02-08 2021-07-06 Samsung Electro-Mechanics Co., Ltd. Inductor

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