WO2017206954A1 - 一种光口实现方法、装置及现场可编程门阵列器件 - Google Patents

一种光口实现方法、装置及现场可编程门阵列器件 Download PDF

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Publication number
WO2017206954A1
WO2017206954A1 PCT/CN2017/087076 CN2017087076W WO2017206954A1 WO 2017206954 A1 WO2017206954 A1 WO 2017206954A1 CN 2017087076 W CN2017087076 W CN 2017087076W WO 2017206954 A1 WO2017206954 A1 WO 2017206954A1
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data
data packet
packet
optical port
message
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PCT/CN2017/087076
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English (en)
French (fr)
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张勇生
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0003—Details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q11/0071—Provisions for the electrical-optical layer interface

Definitions

  • the invention relates to the field of optical transmission technology, in particular to an optical port implementation method and device and a field programmable gate array device.
  • IEEE1588 is commonly referred to as the Precision Time Protocol, the PTP protocol, and its full name is: a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems).
  • the IEEE 1588 system only needs a high-precision clock source input bearer network, and can automatically realize the time synchronization of sub-microsecond time precision of the whole network according to the clock quality and the system master-slave relationship, thereby reducing the system cost. Enhance the security and stability of the communication network. Based on these considerations, the current 1588 technology is being widely adopted in the field of transmission.
  • the 1588 clock time synchronization system is further divided into the in-band clock time synchronization and the out-of-band clock time synchronization.
  • the in-band clock time synchronization refers to the method of encapsulating PTP packets into GFP-F format and inserting them into the OTN reservation overhead.
  • the mode of transmission in the outband, and the out-of-band clock time synchronization is a way of transmitting PTP messages between different time nodes using a 100 Mbps optical port.
  • the implementation method of the 100-megabit optical port supporting the clock time has two modes:
  • the packet passes through the FPGA device before entering the switch chip, and the existing FPGA device does not have an IPCore (Intellectual Property Core, IP core) directly supporting the 100 Mbps Ethernet PHY function, and the minimum rate is Gigabit.
  • IPCore Intelligent Property Core, IP core
  • the PHY must be used for switching between the SFP optical module and the FPGA. It is difficult to implement on a board with a large number of clocks and a large board density, and the PHY device will increase the cost.
  • the optical port is directly connected to the switch chip. Since the 1588 timestamp must be performed at the ingress, it cannot pass through any buffer. Otherwise, non-fixed delay will be introduced, and the accuracy cannot meet the requirements. Therefore, the high-end switch chip supporting the 1588 function must be selected. To achieve, there will be a big increase in the cost of the chip.
  • the technical problem to be solved by the present invention is to provide an optical port implementation method, device and field programmable gate array device to solve the problem that an additional PHY device is needed in the prior art or a switch chip supporting the 1588 function is needed.
  • an embodiment of the present invention provides a method for implementing an optical port, which is applied to a field programmable gate array FPGA device, and the method includes:
  • the data packet is a packet received by the SFP optical module
  • the data packet is sequentially subjected to Gigabit serial conversion, oversampling, clock recovery, phase adjustment, and time stamp processing to obtain a 100-megabit optical port.
  • the data packet is a packet that needs to be sent by the SFP optical module
  • the data packet is sequentially time-stamped, rate matched, and converted into a gigabit string to obtain a second direction of transmission of the 100-megabit optical port. Message.
  • the step of oversampling the data packet includes:
  • the Gigabyte serially converted data signal is locked to the sampling point according to the position of the bit hopping and the sampling data is acquired;
  • a data signal of a hundred megabit rate is obtained based on the sampled data.
  • the step of performing clock recovery on the data packet includes:
  • the effect information includes a clock signal that is homologous to the real input clock
  • the divided 8k clock signal is sent to an external clock chip.
  • the step of performing phase adjustment on the data packet includes:
  • the step of performing time stamp processing on the data packet includes:
  • the time stamp is inserted into the phase-compensated data packet to obtain a data packet transmitted by the 100-megabit optical port.
  • the step of performing time stamp processing on the data packet includes:
  • the timestamp of the data packet is modified according to the egress time.
  • the step of performing rate matching on the data packet includes:
  • an embodiment of the present invention provides an optical port implementation device, which is applied to a field programmable gate array FPGA device, and the device includes:
  • a receiving module configured to receive data packets during network transmission
  • the first processing module is configured to: when the data packet is a packet received by the SFP optical module, perform the Gigabit serial conversion, oversampling, clock recovery, and phase Bit adjustment and time stamp processing to obtain a first direction message transmitted by a 100 Mbps optical port;
  • the second processing module is configured to: when the data packet is a packet that needs to be sent by the SFP optical module, perform the timestamp processing, rate matching, and gigabit serial conversion on the data packet to obtain a hundred megabytes.
  • the second direction message transmitted by the optical port is configured to: when the data packet is a packet that needs to be sent by the SFP optical module, perform the timestamp processing, rate matching, and gigabit serial conversion on the data packet to obtain a hundred megabytes.
  • the first processing module includes:
  • a first processing unit configured to: after performing the Gigabyte serial conversion on the data message, lock the data signal after the Gigabyte serial conversion, and lock the sampling point according to the position of the bit hopping and acquire the sampling data;
  • the first obtaining unit is configured to obtain a data signal of a hundred megabit rate according to the sampled data.
  • an embodiment of the present invention provides a field programmable gate array FPGA device, comprising the optical port implementation device of any of the above.
  • the method and device for implementing the optical port and the field programmable gate array device receive the data packet in the network transmission process; when the data packet is the packet received by the SFP optical module, The data packet is sequentially subjected to Gigabit serial conversion, oversampling, clock recovery, phase adjustment, and time stamp processing to obtain a first direction packet transmitted by the 100 Mbps optical port; when the data packet needs to pass the SFP light
  • the module sends a packet the data packet is sequentially subjected to time stamp processing, rate matching, and gigabit serial conversion, and the second direction packet transmitted by the 100 megabit optical port is obtained, and no additional PHY device is needed. It is not necessary to use a switch chip that supports the 1588 function, which can reduce the density of the board and control the cost.
  • the data packet is time stamped, it does not pass any buffer and does not affect the performance requirements of the 1588 time clock.
  • a storage medium comprising a stored program, wherein the program is executed to perform the method of any of the above.
  • a processor for running a program wherein the program is executed to perform the method of any of the above.
  • FIG. 1 is a schematic diagram showing the connection of a 100 mega-op optical port according to an embodiment of the present invention
  • FIG. 2 is a schematic flow chart of a method for implementing an optical port according to an embodiment of the present invention
  • FIG. 3 is a schematic flow chart showing an optical port receiving direction in an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart showing a direction in which an optical port is sent in an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of an optical port implementation apparatus according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method, an apparatus, and a field programmable gate array device for implementing an optical port, and an internal function of an external PHY device or a switching chip in a conventional solution in an FPGA, and a specific implementation idea thereof is to use an existing Gigabit rate.
  • Ethernet IPCore combined with logic coding, to realize the PHY function of 100M Ethernet, and in the receiving direction of data packets, use phase compensation method to adjust the phase of data packets to achieve the purpose of fixed delay, thus satisfying The purpose of transmitting 1588 time clock information on a 100 megabit optical port.
  • the method of the embodiment of the present invention reduces an external PHY device, and the FPGA is respectively connected to the SFP optical module and the switch chip, and at the same time, the switch chip does not need to select a switch chip that supports the 1588 function, and can reduce the single Board density and cost control.
  • the switch chip does not need to select a switch chip that supports the 1588 function, and can reduce the single Board density and cost control.
  • the data packet is time stamped, it does not pass any buffer and does not affect the performance requirements of the 1588 time clock.
  • FIG. 2 it is a schematic flowchart of a method for implementing an optical port according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method for implementing an optical port, which is applied to a field programmable gate array FPGA device, and the method may include:
  • Step 201 Receive a data packet in a network transmission process.
  • Step 202 When the data packet is a packet received by the SFP optical module, The data packet is sequentially subjected to Gigabit serial conversion, oversampling, clock recovery, phase adjustment, and time stamp processing to obtain a first direction message transmitted by the 100 Mbps optical port;
  • the data packet is a packet received by the SFP optical module
  • this is the internal optical port receiving direction of the FPGA
  • the Gigabyte serial conversion (Gigabit GXB) and oversampling are sequentially performed on the data packet.
  • clock recovery, phase adjustment and time stamp processing obtain the first direction message transmitted by the 100M optical port, to realize the function of the PHY device of the 100M Ethernet, reduce the external PHY device, and satisfy the transmission on the 100M optical port.
  • the purpose of the 1588 time clock information When the data packet is time stamped, the data packet does not pass any buffer and does not affect the performance requirements of the 1588 time clock.
  • Step 203 When the data packet is a packet that needs to be sent by the SFP optical module, the data packet is sequentially subjected to timestamp processing, rate matching, and gigabit serial conversion, to obtain a 100 megabit optical port transmission. The second direction message.
  • the data packet is a packet that needs to be sent by the SFP optical module
  • the direction of the internal optical interface of the FPGA is sent, and the data packet is sequentially time stamped, rate matched, and converted into a gigabit string.
  • Gigabit GXB obtains the second direction message transmitted by the 100M optical port to realize the function of the PHY device of the 100M Ethernet, reduces the external PHY device, and satisfies the transmission of 1588 time clock information on the 100M optical port. Purpose, and does not affect the accuracy of 1588 time processing.
  • step 202 the step of oversampling the data packet may include:
  • the Gigabyte serial converted data signal is locked to the sampling point according to the position of the bit hopping and the sampling data is acquired.
  • the data message is converted into a Gigabit string (Gigabit GXB), and the serial 100 Mbps data message sent by the SFP optical module is converted into parallel Gigabit data. signal.
  • the data signal sent by Gigabit GXB is a 10-bit wide data signal
  • the clock frequency is 125M
  • the 1.25G data is effectively extracted. 125M data.
  • the converted data signal locks the sampling point according to the position of the bit hopping and acquires the sampling data, for example, finds the bit hopping position of the gigabyte string and the converted data signal, thereby determining the bit boundary, and determining the sampling point according to the bit boundary.
  • the sampling point can be set to the middle position of the 10-bit data.
  • a data signal of a hundred megabit rate is obtained based on the sampled data.
  • a data signal of a hundred megabit rate is acquired based on the sampled data obtained by sampling.
  • step 202 the step of clock recovery of the data packet may include:
  • the data valid information includes a clock signal that is homologous to a real input clock.
  • the PLL (Phase Locked Loop) in the Gigabit GXB is set in advance to forcibly lock the local reference clock so that the Gigabit GXB samples the serial data message at a fixed frequency.
  • the data signal of 100 Mbps is sampled, the data signal of the 100 Mbps rate is outputted in a 5-bit group.
  • the data bit width of the obtained data signal of 100 Mbps is 5 bits.
  • the data signal is combined with the data valid information, that is, the obtained data signal of the 100 megabit rate includes the data valid information, while obtaining the data signal of the hundred megabit rate according to the sampled data.
  • the data valid information includes a clock signal that is homologous to the real input clock. In this step, the data valid information in the data signal of the hundred megabit rate is obtained, and the subsequent steps are prepared.
  • the clock signal is divided into 8k clock signals.
  • the clock signal is divided down to an 8k clock signal, and the 8k clock signal duty cycle is close to 50%.
  • counter counting can be used to complete the frequency division.
  • the divided 8k clock signal is sent to an external clock chip.
  • the divided 8k clock signal is sent to an external clock chip (such as ACS8530 or ACS3280), and then can be multiplied by the external clock chip, that is, the extraction of the 100M optical port clock can be completed.
  • an external clock chip such as ACS8530 or ACS3280
  • step 202 the step of performing phase adjustment on the data packet may include:
  • the sampled 100 Mbps data signal is transmitted to a Physical Coding Sublayer (PCS), and after being decoded by the physical coding sublayer, the encoded data message is received.
  • PCS Physical Coding Sublayer
  • the physical coding sublayer performs byte alignment, NRZI decoding, and 4b/5b decoding of 100 megabytes of data, which is done according to the 802.3 standard protocol.
  • a phase difference between a packet header of the decoded data message and a packet header of the data signal of the hundred megabit rate is detected.
  • the output 5 bit block arbitrary position may be the boundary of the current byte, and the 4 bit bit width data obtained by the decoding of the PCS layer, therefore, the decoded datagram
  • the maximum possible introduction of 5*8 ns 40 ns before and after the reset.
  • the delay difference which causes the asymmetric delay of the entire link to change, affecting the performance of the clock time.
  • detecting the data packet header of the decoded data packet and the data packet header of the data signal of the hundred megabit rate The phase difference between them is prepared for the next steps. Specifically, detecting the byte side of the decoded data packet The position information of the boundary is calculated, and the phase difference between the byte frame header of the decoded data message and the byte frame header of the data signal of the hundred megabit rate is calculated according to the position information of the byte boundary.
  • the byte boundary of the decoded data packet is in the highest bit of the 5 bit group, and the phase difference is 5 clock cycles. If the byte boundary of the decoded data packet is in the next highest bit of the 5 bit group, the phase difference is 4 clock cycles, and so on, can get the phase difference between the two.
  • the phased compensation is performed on the decoded data message according to the phase difference.
  • the phase difference is uniformly compensated to 5 clock cycles according to the phase difference. That is, if the phase difference is 5 clock cycles, no additional compensation can be directly output; if the phase difference is 4 clock cycles, then 1 clock cycle is compensated, and the data packet of the decoded data message is beat and outputted; Others can be deduced by analogy. In this way, the phase deviation caused by oversampling can be compensated back.
  • the phase compensation method will cause a 5-shot delay, the delay is fixed regardless of whether the device is reset before or after reset, or during operation, so it does not affect the performance of the 1588 time clock.
  • time stamp processing is also required to control the position of the 1588 timestamp.
  • the reference clock and the recovery clock of the Gigabit GXB in the FPGA are both 125M, which is the same as the clock rate of the Gigabit Ethernet. Therefore, in the embodiment of the present invention, the interface processing refers to the design mode of the Gigabit Ethernet, and 8-bit data is adopted. Bit width, the interface can use the standard GMII interface.
  • step 202 when the data packet is a packet that is received by the SFP optical module, the step of performing time stamp processing on the data packet may include:
  • phase-compensated data message is sent to the media independent interface MII, and the time stamp is latched.
  • phase-compensated data message is sent to the MII, that is, when a message header is detected on the MII, the timestamp is latched, and the entry timestamp operation is completed.
  • the time stamp is inserted into the phase-compensated data packet to obtain a data packet transmitted by the 100-megabit optical port.
  • the switching of the receiving clock domain to the system clock domain is completed, and the MII interface is converted into the GMII interface, and the time stamp is inserted into the phase-compensated data packet to make the phase compensation.
  • the packet header and the packet of the data packet form a one-to-one correspondence, and the data packet transmitted by the 100 Mbps optical port is obtained.
  • the FIFO First Input First Output
  • the timestamp is extracted to perform timestamp calculation processing (ie, 1588 timestamp processing), such as cf domain modification.
  • timestamp calculation processing ie, 1588 timestamp processing
  • step 203 when the data packet is a packet that needs to be sent by the SFP optical module, the step of performing timestamp processing on the data packet may include:
  • the exit time is recorded.
  • the data message is sent to the GMII interface, and then the switching of the system 125M clock domain to the sending 125M clock domain is completed, and the GMII interface is converted into the MII interface format.
  • the MII interface is detected.
  • the exit time is recorded, and the exit timestamp operation is completed.
  • the timestamp of the data packet is modified according to the egress time.
  • the modification of the internal timestamp of the message is completed according to the egress time, and the 1588 timestamp processing is completed.
  • the FIFO is designed to be in a non-empty or read mode, so that the output timestamp can be obtained before the data message is sent to modify the message content.
  • the data rate of the FIFO write end is 1000M, and the read end data rate is 100 megabytes. The design of the non-empty read mode will not cause the FIFO to be read empty before the data message is written.
  • rate matching of the data packet is required.
  • step 203 when the data packet is a packet that needs to be sent by the SFP optical module, the step of rate matching the data packet may include:
  • the data message is transmitted to the physical code.
  • the sub-layer performs 4b/5b encoding processing on the data packet to obtain the encoded data signal.
  • the physical coding sublayer mainly performs NRZI coding and 4b/5b coding of 100 megabytes of data, which is completed according to the 802.3 standard protocol. Since there is a difference between the rate of the encoded data signal and the rate of the Gigabit GXB, the data rate can be increased by copying the encoded data signal by a predetermined number of copies.
  • the data signal matching the data the data bit width is 10 bits at this time
  • the Gigabit string is converted and converted (Gigabit GXB)
  • the parallel Gigabit data signals are converted into serial hundreds of megabytes.
  • the data packet is the second direction message that is transmitted by the 100 Mbps optical port.
  • the optical interface implementation method provided by the embodiment of the present invention receives the data packet in the network transmission process, and when the data packet is the packet received by the SFP optical module, the data packet is sequentially Gigabit.
  • the serial-to-parallel conversion, oversampling, clock recovery, phase adjustment, and timestamp processing are performed to obtain a first direction message transmitted by the 100 Mbps optical port; when the data message is a message that needs to be sent by the SFP optical module,
  • the data packet is sequentially subjected to time stamp processing, rate matching, and gigabit serial conversion, and obtains a second direction message transmitted by the 100 Mbps optical port, and does not require an additional PHY device, and does not need to use a switch chip supporting the 1588 function. It can reduce the density of the veneer and control the cost.
  • the PTP data packet is time stamped, it does not pass any buffer and does not affect the performance requirement of the 1588 time clock.
  • an embodiment of the present invention further provides an apparatus for implementing the above method.
  • FIG. 5 it is a schematic structural diagram of an optical port implementation device according to an embodiment of the present invention.
  • the embodiment of the present invention provides an optical port implementation device, which is applied to a field programmable gate array FPGA device, and the device may include: a receiving module 510, a first processing module 520, and a second processing module 530.
  • the receiving module 510 is configured to receive a data packet during network transmission
  • the first processing module 520 is configured to perform the Gigabit serial conversion, oversampling, clock recovery, phase adjustment, and time in sequence when the data packet is a packet received by the SFP optical module. Stamp processing to obtain a first direction message transmitted by a 100 Mbps optical port;
  • the second processing module 530 is configured to perform time stamp processing, rate matching, and gigabit serial conversion on the data packet when the data packet is a packet that needs to be sent by the SFP optical module, and obtain the hundred The second direction message transmitted by the mega optical port.
  • the first processing module 520 can include: a first processing unit and a first acquiring unit.
  • a first processing unit configured to: after performing the Gigabyte serial conversion on the data message, lock the data signal after the Gigabyte serial conversion, and lock the sampling point according to the position of the bit hopping and acquire the sampling data;
  • the first obtaining unit is configured to obtain a data signal of a hundred megabit rate according to the sampled data.
  • the first processing module 520 may further include: a second acquiring unit, a frequency dividing unit, and a sending unit.
  • a second acquiring unit configured to acquire data valid information in the data signal of the 100 Mbps rate, where the data valid information includes a clock signal that is the same as a real input clock;
  • a frequency dividing unit configured to divide the clock signal to an 8k clock signal
  • the transmitting unit is configured to send the divided 8k clock signal to the external clock chip.
  • the first processing module 520 may further include: a second processing unit, a detecting unit, and a compensation unit.
  • a second processing unit configured to transmit the data signal of the 100 Mbps rate to a physical coding sublayer, and receive a data message decoded by the physical coding sublayer;
  • a detecting unit configured to detect a phase difference between a data packet header of the decoded data packet and a data packet header of the data signal of the hundred megabit rate
  • the compensation unit is configured to perform phase compensation on the decoded data message according to the phase difference.
  • the first processing module 520 may further include: a third processing unit and a fourth processing unit.
  • a third processing unit configured to send the phase-compensated data message to the media independent interface MII, and latch the timestamp
  • the fourth processing unit is configured to insert the time stamp into the phase-compensated data packet to obtain a data packet transmitted by the 100-megabit optical port when the MII switches to the Gigabit media independent interface GMII.
  • the second processing module 530 can include: a recording unit and a modifying unit.
  • a recording unit configured to record an exit time when detecting that the MII receives the data message
  • the modifying unit is configured to modify the timestamp of the data packet according to the egress time.
  • the second processing module 530 may further include: a fifth processing unit.
  • the fifth processing unit is configured to transmit the data message to the physical coding sublayer, and copy the data signal encoded by the physical coding sublayer to a predetermined number of copies.
  • optical port implementation device provided by the foregoing embodiment is the same as the optical port implementation method provided by the embodiment.
  • the specific implementation process is described in detail in the embodiment of the optical port implementation method. To avoid repetition, details are not described herein again.
  • the optical port implementation device receives the data packet in the network transmission process, and when the data packet is the packet received by the SFP optical module, the data packet is sequentially Gigabit.
  • the serial-to-parallel conversion, oversampling, clock recovery, phase adjustment, and timestamp processing are performed to obtain a first direction message transmitted by the 100 Mbps optical port; when the data message is a message that needs to be sent by the SFP optical module,
  • the data packet is sequentially subjected to time stamp processing, rate matching, and gigabit serial conversion, and obtains a second direction message transmitted by the 100 Mbps optical port, and does not require an additional PHY device, and does not need to use a switch chip supporting the 1588 function. It can reduce the density of the veneer and control the cost.
  • the PTP data packet is time stamped, it does not pass any buffer and does not affect the performance requirement of the 1588 time clock.
  • an embodiment of the present invention further provides a field programmable gate array FPGA device, which includes the optical port implementation device of any of the above.
  • optical port implementation device has the above-mentioned technical effects. Therefore, the FPGA device having the optical port implementation device should also have corresponding technical effects, and the specific implementation process is similar to the above embodiment, and details are not described herein.
  • Embodiments of the present invention also provide a storage medium including a stored program, wherein the program described above executes the method of any of the above.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), and a Random Access Memory (RAM).
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • Embodiments of the present invention also provide a processor for running a program, wherein the program is executed to perform the steps of any of the above methods.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the optical port implementation method and apparatus and the field programmable gate array device provided by the embodiments of the present invention have the following beneficial effects: receiving data packets during network transmission; and when the data packets are SFPs
  • the data packet is sequentially subjected to Gigabit serial conversion, oversampling, clock recovery, phase adjustment, and time stamp processing to obtain a first direction message transmitted by the 100 Mbps optical port;
  • the data packet is a packet that needs to be sent by the SFP optical module
  • the data packet is sequentially subjected to time stamp processing, rate matching, and gigabit serial conversion, and the second direction report of the 100 Mbps optical port transmission is obtained.
  • This article does not require additional PHY devices and does not require a switch chip that supports the 1588 function, which can reduce the density of the board and control the cost.
  • the data packet is time stamped, it does not pass any buffer and does not affect the performance requirements of the 1588 time clock.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Optical Communication System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

本发明实施例中提供一种光口实现方法、装置及现场可编程门阵列器件，其中，该光口实现方法，应用于现场可编程门阵列FPGA器件，方法包括：接收网络传输过程中的数据报文；当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。这样，能够降低单板密度和控制成本的目的。另外，在数据报文打时间戳的时候没有经过任何缓存，不影响1588时间时钟的性能要求。

Description

一种光口实现方法、装置及现场可编程门阵列器件 技术领域
本发明涉及光传输技术领域，特别是指一种光口实现方法、装置及现场可编程门阵列器件。
背景技术
在现代移动通讯网络中，各通讯设备之间需要保持时间同步，以保证用户在移动过程中基站的切换不会出现掉线等故障，目前只有GPS和IEEE 1588可以满足这一需求。GPS由于系统成本以及安全性的限制不方便全面推广。IEEE1588通常称为Precision Time Protocol，即PTP协议，其全称是：网络测量和控制系统的精密时钟同步协议标准(a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems)。IEEE 1588系统仅需要高精度时钟源输入承载网，就可以将各基站的时钟时间信息根据时钟质量、系统主从关系，自动实现全网亚微秒级时间精度的时间同步，减少了系统成本，增强了通信网络的安全性和稳定性。基于这些考虑，目前1588技术在传输领域正被广泛采用。
在OTN系统中，1588时钟时间同步系统又分为带内时钟时间同步和带外时钟时间同步，其中，带内时钟时间同步是指把PTP报文封装成GFP-F的格式插入到OTN保留开销中进行传输的方式，而带外时钟时间同步是使用百兆光口在不同时间节点之间传递PTP消息的方式。
在目前的OTN系统中，支持时钟时间的百兆光口的实现方法大体有两种模式：
1、SFP(Small Form-factor Pluggable，光模块)<＝＝＝>PHY(Physical Layer，物理层芯片)<＝＝＝>FPGA(Field－Programmable Gate Array，现场可编程门阵列)<＝＝＝>交换芯片
2、SFP<＝＝＝>交换芯片<＝＝＝>FPGA
在方案1中，报文进入交换芯片之前先经过FPGA器件，现有的FPGA器件上都没有直接支持百兆以太网PHY功能的IPCore(Intellectual Property Core，IP核)，最低速率为千兆，因此必须在SFP光模块和FPGA之间使用PHY来进行转接，在时钟时间端口较多，板密度较大的单板上，比较难以实现，并且PHY器件会增加成本。而方案2中，光口直接连接交换芯片，由于1588打时间戳必须在入口进行，不能经过任何缓存，否则会引入非固定延时，精度不能达到要求，这样必须选用支持1588功能的高端交换芯片来实现，芯片成本上会有比较大的提高。
发明内容
本发明要解决的技术问题是提供一种光口实现方法、装置及现场可编程门阵列器件，以解决现有技术中需要额外PHY器件或者需要选用支持1588功能的交换芯片的问题。
第一方面，本发明的实施例提供一种光口实现方法，应用于现场可编程门阵列FPGA器件，该方法包括：
接收网络传输过程中的数据报文；
当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；
当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。
其中，将所述数据报文进行过采样的步骤包括：
在将所述数据报文进行千兆串并转换之后，将经千兆串并转换后的数据信号，根据比特跳变的位置锁定采样点并获取采样数据；
根据所述采样数据获得百兆速率的数据信号。
其中，将所述数据报文进行时钟恢复的步骤包括：
获取所述百兆速率的数据信号中的数据有效信息，其中，所述数据有 效信息包括与真实输入时钟同源的时钟信号；
将所述时钟信号分频至8k时钟信号；
将分频得到的所述8k时钟信号发送至外部时钟芯片。
其中，将所述数据报文进行相位调整的步骤包括：
将所述百兆速率的数据信号传输至物理编码子层，并接收经物理编码子层解码得到的数据报文；
检测解码得到的数据报文的数据包头与所述百兆速率的数据信号的数据包头之间的相位差；
根据所述相位差，对所述解码得到的数据报文进行相位补偿。
其中，当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文进行时间戳处理的步骤包括：
将相位补偿后的数据报文发送至媒体独立接口MII，并锁存时间戳；
在MII切换至千兆媒体独立接口GMII时，将所述时间戳插入所述相位补偿后的数据报文，获得百兆光口传输的数据报文。
其中，当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文进行时间戳处理的步骤包括：
当检测到MII接收到数据报文时，记录出口时间；
根据所述出口时间修改数据报文的时间戳。
其中，当所述数据报文为需要发送至SFP光模块的报文时，将所述数据报文进行速率匹配的步骤包括：
将所述数据报文传输至物理编码子层，并将经物理编码子层编码后的数据信号，复制预定份数。
第二方面，本发明的实施例提供一种光口实现装置，应用于现场可编程门阵列FPGA器件，该装置包括：
接收模块，设置为接收网络传输过程中的数据报文；
第一处理模块，设置为当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相 位调整以及时间戳处理，获得百兆光口传输的第一方向报文；
第二处理模块，设置为当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。
其中，该第一处理模块包括：
第一处理单元，设置为在将所述数据报文进行千兆串并转换之后，将经千兆串并转换后的数据信号，根据比特跳变的位置锁定采样点并获取采样数据；
第一获取单元，设置为根据所述采样数据获得百兆速率的数据信号。
第三方面，本发明的实施例提供一种现场可编程门阵列FPGA器件，该FPGA器件包括上述任一所述的光口实现装置。
本发明实施例提供的光口实现方法、装置及现场可编程门阵列器件，通过接收网络传输过程中的数据报文；当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文，不需要额外的PHY器件，也不需要选用支持1588功能的交换芯片，能够降低单板密度和控制成本的目的。另外，在数据报文打时间戳的时候没有经过任何缓存，不影响1588时间时钟的性能要求。
根据本发明的又一个实施例，还提供了一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述任一项所述的方法。
根据本发明的又一个实施例，还提供了一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述任一项所述的方法。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图 仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示本发明实施例的百兆光口的连接示意图；
图2表示本发明实施例提供的光口实现方法的流程示意图；
图3表示本发明实施例中光口接收方向的流程示意图；
图4表示本发明实施例中光口发送方向的流程示意图；
图5表示本发明实施例提供的光口实现装置的结构示意图。
具体实施方式
为使本发明实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本发明实施例提供一种光口实现方法、装置及现场可编程门阵列器件，FPGA内部实现传统方案中外部PHY器件或交换芯片的相关功能，其具体实现思路是将使用现有的千兆速率以太网IPCore，结合逻辑编码，来实现百兆速率以太网的PHY功能，并且在数据报文的接收方向，使用相位补偿方法，调整数据报文的相位以达到延时固定的目的，从而满足在百兆光口上传递1588时间时钟信息的目的。参见图1，与现有技术相比，本发明实施例的方法减少了外部PHY器件，FPGA分别与SFP光模块和交换芯片连接，同时，交换芯片无需选用支持1588功能的交换芯片，能够降低单板密度且控制成本。另外，在数据报文打时间戳的时候没有经过任何缓存，不影响1588时间时钟的性能要求。
请参见图2，其示出的是本发明实施例提供的光口实现方法的流程示意图。
本发明的实施例提供一种光口实现方法，应用于现场可编程门阵列FPGA器件，该方法可以包括：
步骤201，接收网络传输过程中的数据报文；
步骤202，当所述数据报文为经过SFP光模块进行接收的报文时，将 所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；
这里，当所述数据报文为经过SFP光模块进行接收的报文时，此时为FPGA内部光口接收方向，通过对数据报文依次进行千兆串并转换(千兆GXB)、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文，以实现百兆速率以太网的PHY器件的功能，减少了外部PHY器件，满足了百兆光口上传递1588时间时钟信息的目的；并且在数据报文打时间戳的时候，数据报文没有经过任何缓存，不影响1588时间时钟的性能要求。
步骤203，当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。
这里，当所述数据报文为需要经过SFP光模块进行发送的报文时，此时为FPGA内部光口发送方向，通过对数据报文依次进行时间戳处理、速率匹配以及千兆串并转换(千兆GXB)，获得百兆光口传输的第二方向报文，以实现百兆速率以太网的PHY器件的功能，减少了外部PHY器件，满足了百兆光口上传递1588时间时钟信息的目的，且不影响1588时间处理的精度。
结合图3，在步骤202中，将所述数据报文进行过采样的步骤可以包括：
在将所述数据报文进行千兆串并转换之后，将经千兆串并转换后的数据信号，根据比特跳变的位置锁定采样点并获取采样数据。
这里，在将数据报文过采样之前，将数据报文进行千兆串并转换(千兆GXB)，将SFP光模块发送的串行的百兆的数据报文转换成并行的千兆的数据信号。其中，千兆GXB送出来的数据信号是10bit位宽的数据信号，时钟频率为125M，实际数据速率为125M*10＝1.25G，为了获取实际需要的百兆数据，从1.25G数据中提取有效的125M数据。因此，将千兆串并 转换后的数据信号根据比特跳变的位置锁定采样点并获取采样数据，例如，查找千兆串并转换后的数据信号的比特跳变位置，以此确定比特边界，根据该比特边界确定采样点，其中，当某一时钟周期没有检测到比特跳变，则保持前一次确定的比特边界，通过该比特边界确定采样点，理论上，以每10bit采样一次，以获取采样数据。这里，可以将采样点设置为10bit数据的中间位置。
根据所述采样数据获得百兆速率的数据信号。
这里，根据采样得到的采样数据获取百兆速率的数据信号。
其中，由于使用了千兆GXB结合过采样技术来实现数据报文的恢复，不能直接借用千兆GXB的CDR(Clock Data Recovery，时钟数据恢复)时钟恢复功能，否则会影响恢复钟的性能，因此，时钟的恢复必须依据过采样得到的百兆速率的数据信号来进行。
因此，结合图3，在步骤202中，将所述数据报文进行时钟恢复的步骤可以包括：
获取所述百兆速率的数据信号中的数据有效信息，其中，所述数据有效信息包括与真实输入时钟同源的时钟信号。
这里，预先将千兆GXB中的PLL(Phase Locked Loop，锁相环)设置为强制锁定本地参考钟，以使千兆GXB以一个固定的频率对串行的数据报文进行采样。在经过采样得到百兆速率的数据信号后，将该百兆速率的数据信号以5bit一组的方式输出，此时，得到的百兆速率的数据信号的数据位宽为5bit。其中，在过采样的步骤中，根据采样数据获得百兆速率的数据信号的同时，将数据信号结合数据有效信息，即得到的百兆速率的数据信号包括数据有效信息。该数据有效信息包括与真实输入时钟同源的时钟信号。该步骤中，获取百兆速率的数据信号中的数据有效信息，为后续步骤做准备。该数据有效信息的频率为125m/5＝25M，且其中的时钟信号的占空比不是50％。
将所述时钟信号分频至8k时钟信号。
这里，将时钟信号分频至8k时钟信号，该8k时钟信号占空比接近50％。具体的，可以使用计数器计数以完成分频。
将分频得到的所述8k时钟信号发送至外部时钟芯片。
这里，将分频得到的8k时钟信号发送到外部时钟芯片(如ACS8530或ACS3280)，然后可以经该外部时钟芯片倍频，即可以以完成对百兆光口时钟的提取。
结合图3，在步骤202中，将所述数据报文进行相位调整的步骤可以包括：
将所述百兆速率的数据信号传输至物理编码子层，并接收经物理编码子层解码得到的数据报文。
这里，将数据报文过采样后，千兆GXB输出的10bit并行数据被恢复为5bit的并行数据，由于时钟频率是125M，因此，此并行数据并不是一直有效的，有效数据的占空比为100M/(125*4)＝20％，即每5拍接口上的数据有效一次。将经过采样得到的百兆速率的数据信号传输至物理编码字层(Physical Coding Sublayer，PCS)，并经物理编码子层解码后，接收编码得到的数据报文。该物理编码子层进行百兆数据的字节对齐、NRZI解码和4b/5b解码，其根据802.3标准协议完成。
检测解码得到的数据报文的数据包头与所述百兆速率的数据信号的数据包头之间的相位差。
这里，由于过采样步骤中并没有实现字节对齐，因此输出的5bit块任意位置都可能是当前字节的边界，而经过PCS层的解码得到的4bit位宽数据，因此，解码得到的数据报文的数据包头可能与百兆速率的数据信号的数据包头之间存在1～5个周期的相位差，且无法保证每次复位后相位差是一致的，复位前后最大可能引入5*8ns＝40ns的延时差，这样就会使得整个链路的非对称延时改变，影响时钟时间的性能，因此，检测解码得到的数据报文的数据包头与所述百兆速率的数据信号的数据包头之间的相位差，为后续步骤做准备。具体的，检测解码得到的数据报文的字节边 界的位置信息，并根据该字节边界的位置信息计算解码得到的数据报文的字节帧头与百兆速率的数据信号的字节帧头的相位差。其中，解码得到的数据报文的字节边界在5bit组的最高位，代表相位差为5个时钟周期，如果解码得到的数据报文的字节边界在5bit组的次高位，代表相位差为4个时钟周期，可以依次类推，得到两者之间的相位差。
根据所述相位差，对所述解码得到的数据报文进行相位补偿。
这里，根据相位差，对解码得到的数据报文进行相位补偿。具体的，根据相位差，将相位差统一补偿到5个时钟周期。即如果相位差为5个时钟周期，则不额外补偿，可以直接输出；如果相位差为4个时钟周期，则补偿1个时钟周期，将解码得到的数据报文的数据包打一拍输出；其他可以此类推。这样，可以将过采样后造成的相位偏差补偿回来。另外，虽然相位补偿方式会造成5拍的延时，但不管是设备复位前还是复位后，或者是运行过程中，该延时都是固定的，因此不会影响1588时间时钟的性能。
其中，在接收方向上，为了支持1588功能，保证时钟时间的精度，在经过相位补偿后，还需要进行时间戳处理，控制1588打时间戳的位置。其中，FPGA内部千兆GXB的参考时钟和恢复时钟均是125M，与千兆以太网的时钟速率相同，因此，本发明实施例中，接口处理参考千兆以太网的设计方式，采用8位数据位宽，接口可使用标准GMII接口。
结合图3，在步骤202中，当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文进行时间戳处理的步骤可以包括：
将相位补偿后的数据报文发送至媒体独立接口MII，并锁存时间戳。
这里，将相位补偿后的数据报文发送至MII，即检测到MII上有报文头时，锁存时间戳，完成入口打时戳操作。
在MII切换至千兆媒体独立接口GMII时，将所述时间戳插入所述相位补偿后的数据报文，获得百兆光口传输的数据报文。
这里，在完成接收时钟域到系统时钟域的切换，并将MII接口转换为GMII接口，将时间戳插入到相位补偿后的数据报文，以使相位补偿后的 数据报文的报文头部和报文形成一一对应关系，获得百兆光口传输的数据报文；之后过FIFO(First Input First Output，先进先出队列)进行时钟域的切换。在FIFO读取侧，在将时间戳提取出来进行时间戳的计算处理(即1588时间戳处理)，如cf域修改等操作。这里，在整个数据接收路径上，由于时间戳是在报文过FIFO之前获取的，因此，不会引入非固定性延时。
其中，结合图4，在步骤203中，当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文进行时间戳处理的步骤可以包括：
当检测到MII接收到数据报文时，记录出口时间。
这里，将数据报文发送至GMII接口，然后完成系统125M时钟域到发送125M时钟域的切换，同时将GMII接口转换为MII接口形式，当检测到MII接收到数据报文，即检测到MII接口存在报文头时，记录出口时间，完成出口打时戳操作。
根据所述出口时间修改数据报文的时间戳。
这里，根据出口时间完成报文内部时间戳的修改，完成1588时间戳处理。另外，为保证有足够的时间去修改报文内容，将FIFO设计成非空即读模式，这样，在将数据报文发送完之前就能获取到出口时间戳来修改报文内容，同时，由于FIFO写端的数据速率是1000M，而读端数据速率是百兆，设计成非空即读模式也不会出现数据报文写完之前FIFO已经读空的情况。
其中，为使数据报文能够借用FPGA内部的千兆GXB完成百兆数据的发送需要对数据报文进行速率匹配。
结合图4，在步骤203中，当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文进行速率匹配的步骤可以包括：
将所述数据报文传输至物理编码子层，并将经物理编码子层编码后的数据信号，复制预定份数。
这里，在将报数据文进行速率匹配之前，将数据报文传输至物理编码 子层，对数据报文进行4b/5b编码处理，得到编码后的数据信号，此时，编码后的数据信号的速率为100*5/4＝125M，数据位宽为5bit。其中，该物理编码子层主要完成百兆数据的NRZI编码和4b/5b编码，其中根据802.3标准协议完成。由于，编码后的数据信号的速率与千兆GXB的速率之间存在差异，可以通过将编码后的数据信号复制预定份数以提高数据速率。具体的，FPGA内部的千兆GXB的速率为125*10＝1250M，与编码后的数据信号之间的速率存在10倍的差异，将编码后的数据信号复制10份，使得数据速率提高到1250M。在速率匹配之后，将该数据匹配后的数据信号(此时数据位宽为10bit)，发送千兆串并转换(千兆GXB)，将并行的千兆的数据信号转换成串行的百兆的数据报文，即获得百兆光口传输的第二方向报文。
本发明实施例提供的光口实现方法，通过接收网络传输过程中的数据报文；当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文，不需要额外的PHY器件，也不需要选用支持1588功能的交换芯片，能够降低单板密度和控制成本的目的。另外，在PTP数据报文打时间戳的时候没有经过任何缓存，不影响1588时间时钟的性能要求。
基于以上方法，本发明实施例还提供了一种用以实施上述方法的装置。请参见图5，其示出的是本发明实施例提供的光口实现装置的结构示意图。
本发明的实施例提供一种光口实现装置，应用于现场可编程门阵列FPGA器件，该装置可以包括：接收模块510、第一处理模块520以及第二处理模块530。
接收模块510，设置为接收网络传输过程中的数据报文；
第一处理模块520，设置为当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；
第二处理模块530，设置为当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。
其中，该第一处理模块520可以包括：第一处理单元以及第一获取单元。
第一处理单元，设置为在将所述数据报文进行千兆串并转换之后，将经千兆串并转换后的数据信号，根据比特跳变的位置锁定采样点并获取采样数据；
第一获取单元，设置为根据所述采样数据获得百兆速率的数据信号。
其中，该第一处理模块520还可以包括：第二获取单元、分频单元以及发送单元。
第二获取单元，设置为获取所述百兆速率的数据信号中的数据有效信息，其中，所述数据有效信息包括与真实输入时钟同源的时钟信号；
分频单元，设置为将所述时钟信号分频至8k时钟信号；
发送单元，设置为将分频得到的所述8k时钟信号发送至外部时钟芯片。
其中，该第一处理模块520还可以包括：第二处理单元、检测单元以及补偿单元。
第二处理单元，设置为将所述百兆速率的数据信号传输至物理编码子层，并接收经物理编码子层解码得到的数据报文；
检测单元，设置为检测解码得到的数据报文的数据包头与所述百兆速率的数据信号的数据包头之间的相位差；
补偿单元，设置为根据所述相位差，对所述解码得到的数据报文进行相位补偿。
其中，该第一处理模块520还可以包括：第三处理单元以及第四处理单元。
第三处理单元，设置为将相位补偿后的数据报文发送至媒体独立接口MII，并锁存时间戳；
第四处理单元，设置为在MII切换至千兆媒体独立接口GMII时，将所述时间戳插入所述相位补偿后的数据报文，获得百兆光口传输的数据报文。
其中，该第二处理模块530可以包括：记录单元以及修改单元。
记录单元，设置为当检测到MII接收到数据报文时，记录出口时间；
修改单元，设置为根据所述出口时间修改数据报文的时间戳。
其中，该第二处理模块530还可以包括：第五处理单元。
第五处理单元，设置为将所述数据报文传输至物理编码子层，并将经物理编码子层编码后的数据信号，复制预定份数。
上述实施例提供的光口实现装置与实施例提供的光口实现方法属于同一构思，其具体实现过程详见光口实现方法的实施例，为避免重复，这里不再赘述。
本发明实施例提供的光口实现装置，通过接收网络传输过程中的数据报文；当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文，不需要额外的PHY器件，也不需要选用支持1588功能的交换芯片，能够降低单板密度和控制成本的目的。另外，在PTP数据报文打时间戳的时候没有经过任何缓存，不影响1588时间时钟的性能要求。
另外，本发明的实施例还提供一种现场可编程门阵列FPGA器件，该FPGA器件包括上述任一所述的光口实现装置。
由于上述任一种所述光口实现装置具有前述技术效果，因此，具有该光口实现装置的FPGA器件也应具备相应的技术效果，其具体实施过程与上述实施例类似，兹不赘述。
本发明的实施例还提供了一种存储介质，该存储介质包括存储的程序，其中，上述程序运行时执行上述任一项所述的方法。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本发明的实施例还提供了一种处理器，该处理器用于运行程序，其中，该程序运行时执行上述任一项方法中的步骤。
对于前述的方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本发明所必需的。
需要说明的是，在发明实施例中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普 通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
工业实用性
如上所述，本发明实施例提供的一种光口实现方法、装置及现场可编程门阵列器件具有以下有益效果：通过接收网络传输过程中的数据报文；当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文，不需要额外的PHY器件，也不需要选用支持1588功能的交换芯片，能够降低单板密度和控制成本的目的。另外，在数据报文打时间戳的时候没有经过任何缓存，不影响1588时间时钟的性能要求。

Claims (11)

  1. 一种光口实现方法，应用于现场可编程门阵列FPGA器件，所述方法包括：
    接收网络传输过程中的数据报文；
    当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；
    当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。
  2. 根据权利要求1所述的方法，其中，将所述数据报文进行过采样的步骤包括：
    在将所述数据报文进行千兆串并转换之后，将经千兆串并转换后的数据信号，根据比特跳变的位置锁定采样点并获取采样数据；
    根据所述采样数据获得百兆速率的数据信号。
  3. 根据权利要求2所述的方法，其中，将所述数据报文进行时钟恢复的步骤包括：
    获取所述百兆速率的数据信号中的数据有效信息，其中，所述数据有效信息包括与真实输入时钟同源的时钟信号；
    将所述时钟信号分频至8k时钟信号；
    将分频得到的所述8k时钟信号发送至外部时钟芯片。
  4. 根据权利要求2所述的方法，其中，将所述数据报文进行相位调整的步骤包括：
    将所述百兆速率的数据信号传输至物理编码子层，并接收经物理编码子层解码得到的数据报文；
    检测解码得到的数据报文的数据包头与所述百兆速率的数据信号的数据包头之间的相位差；
    根据所述相位差，对所述解码得到的数据报文进行相位补偿。
  5. 根据权利要求4所述的方法，其中，当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文进行时间戳处理的步骤包括：
    将相位补偿后的数据报文发送至媒体独立接口MII，并锁存时间戳；
    在MII切换至千兆媒体独立接口GMII时，将所述时间戳插入所述相位补偿后的数据报文，获得百兆光口传输的数据报文。
  6. 根据权利要求1所述的方法，其中，当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文进行时间戳处理的步骤包括：
    当检测到MII接收到数据报文时，记录出口时间；
    根据所述出口时间修改数据报文的时间戳。
  7. 根据权利要求6所述的方法，其中，当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文进行速率匹配的步骤包括：
    将所述数据报文传输至物理编码子层，并将经物理编码子层编码后的数据信号，复制预定份数。
  8. 一种光口实现装置，应用于现场可编程门阵列FPGA器件，所述装置包括：
    接收模块，设置为接收网络传输过程中的数据报文；
    第一处理模块，设置为当所述数据报文为经过SFP光模块进行接收的报文时，将所述数据报文依次进行千兆串并转换、过采样、时钟 恢复、相位调整以及时间戳处理，获得百兆光口传输的第一方向报文；
    第二处理模块，设置为当所述数据报文为需要经过SFP光模块进行发送的报文时，将所述数据报文依次进行时间戳处理、速率匹配以及千兆串并转换，获得百兆光口传输的第二方向报文。
  9. 根据权利要求8所述的装置，其中，所述第一处理模块包括：
    第一处理单元，设置为在将所述数据报文进行千兆串并转换之后，将经千兆串并转换后的数据信号，根据比特跳变的位置锁定采样点并获取采样数据；
    第一获取单元，设置为根据所述采样数据获得百兆速率的数据信号。
  10. 一种现场可编程门阵列FPGA器件，所述FPGA器件包括如权利要求8至9任一项所述的光口实现装置。
  11. 一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行权利要求1至7中任一项所述的方法。
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CN113903366A (zh) * 2021-10-08 2022-01-07 安徽国芯智能装备有限公司 一种适用于直写光刻机的高速数据传输系统
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