WO2017206262A1 - 液晶显示面板、阵列基板及其制作方法 - Google Patents

液晶显示面板、阵列基板及其制作方法 Download PDF

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Publication number
WO2017206262A1
WO2017206262A1 PCT/CN2016/088495 CN2016088495W WO2017206262A1 WO 2017206262 A1 WO2017206262 A1 WO 2017206262A1 CN 2016088495 W CN2016088495 W CN 2016088495W WO 2017206262 A1 WO2017206262 A1 WO 2017206262A1
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Prior art keywords
layer
electrode
substrate
pattern layer
array substrate
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English (en)
French (fr)
Inventor
郝思坤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/124,352 priority Critical patent/US10345664B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel, an array substrate, and a method of fabricating the same.
  • Liquid crystal display is one of the most widely used flat panel displays, and has gradually become a widely used electronic device such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens with high-resolution color screens. monitor.
  • PDAs personal digital assistants
  • LCDs liquid crystal display
  • LCDs liquid crystal display
  • FIG. 1 is a schematic cross-sectional view of a prior art liquid crystal display panel.
  • 2 is a schematic view showing a pixel structure of a liquid crystal display panel of the prior art.
  • a conventional liquid crystal display panel includes a TFT substrate 1, a color filter substrate 2, and a liquid crystal layer 3 disposed between the TFT substrate 1 and the color filter substrate 2.
  • the TFT substrate 1 includes a glass substrate 11, a gate electrode 12 disposed on the glass substrate 11, and a gate insulating layer 13 covering the gate electrode 12 and the glass substrate 11, and is disposed on the gate insulating layer.
  • a via hole is required at the bridge between the pixel electrode and the TFT.
  • the via hole affects the pixel aperture ratio, resulting in a low transmittance of the liquid crystal display.
  • forming a source/drain pattern layer on the semiconductor layer while forming a pixel electrode and a data line on the gate insulating layer includes: covering the semiconductor layer and the gate insulating layer a second metal layer; the second metal layer is patterned by a yellow light process to form a source/drain pattern layer, a pixel electrode, and a data line.
  • the top electrode is a metal electrode or an ITO electrode, and the top electrode is electrically connected to the common electrode.
  • the array substrate further includes a top electrode formed on the passivation layer.
  • the top electrode is a metal electrode or an ITO electrode, and the top electrode is electrically connected to the common electrode.
  • FIG. 1 is a schematic cross-sectional structural view of a liquid crystal display panel of the prior art
  • FIG. 2 is a schematic diagram of a pixel structure of a liquid crystal display panel of the prior art
  • FIG. 5 is a schematic view showing a step of forming a gate insulating layer in the first embodiment of the method for fabricating the array substrate of the present invention
  • FIG. 6 is a schematic view showing a step of forming a semiconductor layer in the first embodiment of the method for fabricating the array substrate of the present invention
  • FIG. 8 is a schematic view showing a step of forming a passivation layer in the first embodiment of the method for fabricating the array substrate of the present invention
  • FIG. 10 is a schematic structural view of a gate pattern layer and a common electrode in the pixel structure of FIG. 9;
  • Figure 11 is a schematic view showing the structure after forming a semiconductor layer on Figure 10;
  • Figure 13 is a flow chart showing a second embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 14 is a schematic view showing a pixel structure finally formed in a second embodiment of the method for fabricating the array substrate of the present invention.
  • 16 is a schematic structural view showing a black matrix after forming a color filter substrate of the liquid crystal panel of the present invention.
  • FIG. 17 is a schematic structural view showing a red color resist formed in a process of fabricating a color filter substrate of a liquid crystal panel of the present invention.
  • FIG. 18 is a schematic structural view showing a green color resist formed in a process of manufacturing a color filter substrate of a liquid crystal panel according to the present invention.
  • 19 is a schematic structural view showing a blue color resist formed in a process of fabricating a color filter substrate of a liquid crystal panel of the present invention.
  • Fig. 20 is a structural schematic view showing the formation of a support member in the process of fabricating the color filter substrate of the liquid crystal panel of the present invention.
  • FIG. 3 is a flow chart of the first embodiment of the method for fabricating the array substrate of the present invention.
  • the invention provides a method for fabricating an array substrate, and in particular, the method comprises the following steps:
  • FIG. 4 is a schematic diagram showing the steps of forming a gate pattern layer and a common electrode in the first embodiment of the method for fabricating the array substrate of the present invention.
  • a first metal layer is formed on the substrate 31, and then the gate pattern layer 32 and the common electrode 33 are formed by exposure, development, and etching by a yellow light process.
  • the gate pattern layer 32 and the common electrode 33 are simultaneously formed and located in the same plane.
  • the gate pattern layer 32 and the common electrode 33 are formed of a material such as aluminum, aluminum alloy, or copper.
  • the gate insulating layer 34 may be a layer structure or a two-layer structure. If a two-layer structure is used, the first layer is SiNx, SiO or AlO, and the thickness is about 175-300 nm, and the second layer is generally SiNx. The thickness is about 300 nm, as shown in FIG. 5.
  • FIG. 5 is a schematic view showing a step of forming a gate insulating layer in the first embodiment of the method for fabricating the array substrate of the present invention.
  • the gate insulating layer 34 is formed by CVD or PECVD.
  • a semiconductor layer 35 is formed on the gate insulating layer 34.
  • FIG. 6 is a schematic view showing a step of forming a semiconductor layer in the first embodiment of the method for fabricating the array substrate of the present invention.
  • the semiconductor layer 35 has a thickness of 150 to 350 nm, for example, 250 nm, and the semiconductor layer 35 is also formed by the CVD process.
  • a source/drain pattern layer 36 is formed on the semiconductor layer 35 while a pixel electrode 37 and a data line 38 are formed on the gate insulating layer 34.
  • step S104 a second metal layer is first formed on the semiconductor layer 35 and the gate insulating layer 34, and the source/drain pattern layer 36, the pixel electrode 37, and the data line 38 are formed by exposure, development, and etching through a yellow light process.
  • FIG. 7 is a schematic diagram showing the steps of forming a source/drain pattern layer, a pixel electrode and a data line in the first embodiment of the method for fabricating the array substrate of the present invention.
  • the third metal layer may be made of aluminum alloy or metal aluminum or metal chromium.
  • the source/drain pattern layer has a thickness of from 350 nm to 450 nm, for example, 427 nm or 400 nm.
  • step S104 while the source/drain pattern layer 36 is formed, the pixel electrode 37 and the data line 38 are formed.
  • the pixel electrode 37 and the data line 38 are also metal. Specifically, a part of the source/drain pattern layer 36 is located in the semiconductor. Above layer 35, a portion of bit 34 is on the gate insulating layer.
  • the pixel electrode 37, the data line 38, the semiconductor layer 35, and a portion of the source/drain pattern layer 36 are all located on the gate insulating layer 34, that is, on the same plane. Therefore, the pixel electrode 37 and the source electrode need not be connected through the hole. Therefore, there is no problem that the transmittance of the liquid crystal display is too low due to the influence of the via hole on the aperture ratio, suggesting the pixel aperture ratio and the transmittance.
  • the first layer of metal forms the gate pattern layer and the common electrode
  • the second layer of metal forms the source/drain pattern layer, the pixel electrode and the data line, so that the third layer of metal may not be formed.
  • the passivation layer 39 of the present embodiment is silicon nitride having a thickness of 100 nm to 300 nm, for example, 200 nm or 250 nm, and the passivation layer 39 protects the components below it, as shown in FIG. BACKGROUND OF THE INVENTION
  • a method of fabricating an array substrate in the first embodiment is a schematic diagram of a step of forming a passivation layer.
  • FIG. 9 is a schematic diagram of the pixel structure finally formed in the first embodiment of the method for fabricating the array substrate of the present invention.
  • 10, 11, and 12 are hierarchical structural views of the pixel structure of Fig. 9.
  • 10 is a schematic structural view of the pixel pattern layer and the common electrode in the pixel structure of FIG.
  • Figure 11 is a schematic view showing the structure after forming a semiconductor layer on Figure 10.
  • FIG. 12 is a schematic structural view after the pixel electrode and the data line are formed on FIG.
  • the gate pattern layer 32 and the common electrode 33 are located on the same plane
  • the TFT 30 is disposed on the gate pattern layer 32
  • the data line 38 is disposed on the gate pattern layer 32 and the common electrode 33, and is formed at the same time, and thus is located on the same plane. Since the pixel electrode 37 and the source in the source/drain pattern layer are located on the same plane, the pixel electrode 37 is provided. There is no need to connect via a via between the source and the source.
  • the TFT 10, the storage capacitor 101 and the data line 16 are disposed on the gate electrode 12.
  • the common electrode 19 and the pixel electrode 18 are disposed on the data line 16 and the storage capacitor 101.
  • the pixel electrode 18 is further provided with a via hole 105.
  • the pixel electrode 18 and the source on the TFT 10 are connected through the via 106.
  • the present invention reduces the formation process by forming the common electrode 33 while forming the gate pattern layer 32, forming the pixel electrode 37 and the data line 38 while forming the source/drain pattern layer 36, and
  • the pixel electrode 37 is located on the same plane as the source/drain pattern layer 36, so that the connection between the pixel electrode 37 and the source electrode does not require a via hole, and even if the pixel is small, the problem that the pixel aperture ratio is affected by the via hole does not occur. , thereby increasing the pixel aperture ratio and the transmittance of the liquid crystal display, thereby making the display effect better.
  • FIG. 13 is a flow chart of a second embodiment of a method for fabricating an array substrate of the present invention.
  • step S201 includes: forming a first metal layer on the substrate 31; patterning the first metal layer to form the gate pattern layer 32 and the common electrode layer 33 by exposure, development, and etching through a yellow light process.
  • the gate insulating layer 34 is formed by CVD or PECVD, please continue to refer to FIG. 5.
  • the semiconductor layer 35 is also formed by the CVD process.
  • a source/drain pattern layer 36 is formed on the semiconductor layer 35 while a pixel electrode 37 and a data line 38 are formed on the gate insulating layer 34.
  • Step S204 includes: covering the semiconductor layer 35 and the gate insulating layer 34 with the second metal layer; patterning the second metal layer by the yellow light process to form the source/drain pattern layer 36, the pixel electrode 37, and the data line 38, such as Figure 6 shows.
  • the passivation layer 39 may be a silicon nitride protective film formed by a CVD process to protect components such as TFTs.
  • the top electrode 40 is an ITO electrode or a metal electrode, and the top electrode 40 is electrically connected to the common electrode 33, and the top electrode 40 is distributed through the common electrode 33.
  • the top electrode 40 of this embodiment is an ITO electrode.
  • step S206 includes: forming a top metal layer on the passivation layer 39; patterning the top metal layer to form the top electrode 40 by a yellow light process.
  • FIG. 14 is a schematic diagram of a pixel structure finally formed in the second embodiment of the method for fabricating the array substrate of the present invention.
  • the gate pattern layer 32 and the common electrode 33 are located on the same plane
  • the TFT 30 is disposed on the gate pattern layer 32
  • the data line 38 is disposed on the gate pattern layer 32 and the common electrode 33, and is formed at the same time, and thus is located on the same plane. Since the pixel electrode 37 and the source in the source/drain pattern layer are located on the same plane, the pixel electrode 37 is provided. There is no need to connect via a via between the source and the source.
  • a top electrode 40 is further disposed on the storage capacitor 370, the pixel electrode 37, the source/drain pattern layer in the TFT 30, and the layer on which the data line 38 is located. The top electrode 40 is connected to the common electrode 33.
  • the present invention also provides an array substrate comprising a substrate 31, a gate pattern layer 32 formed over the substrate 31, and a common electrode 33, as shown in FIG.
  • a gate insulating layer 34 over the gate pattern layer 32 and the common electrode 33 is covered.
  • a semiconductor layer 35 is formed over the gate insulating layer 34.
  • a source/drain pattern layer 36 formed over the semiconductor layer 35 and a pixel electrode 37 and a data line 38 disposed over the gate insulating layer 34.
  • a passivation layer 39 overlying the source/drain pattern layer 36, the semiconductor layer 35, the pixel electrode 37, and the data line 38 is overlaid.
  • the gate pattern layer 32 and the common electrode 33 are located on the same plane and are formed by the same metal layer.
  • the source/drain pattern layer 36, the pixel electrode 37 and the data line 38 are located on the same plane and are formed by the same metal layer. Since the pixel electrode 37 and the source/drain pattern layer 36 are on the same plane, the pixel electrode 37 and There is no need to connect the holes between the sources, so that the pixel electrodes 37 of the array substrate of the present invention do not need to be provided with via holes, so the pixel aperture ratio is not affected, thereby improving the transmittance.
  • the array substrate further includes a top electrode 40 formed over the passivation layer 39, as shown in FIG.
  • the top electrode 40 is a metal electrode or an ITO electrode, and the top electrode 40 is electrically connected to the common electrode 33.
  • FIG. 15 is a schematic structural diagram of an embodiment of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel includes a color filter substrate 50, an array substrate 60, and a liquid crystal layer 70 disposed between the color filter substrate 50 and the array substrate 60.
  • the array substrate 60 is the array substrate 60 of any of the above embodiments.
  • the array substrate 60 can be fabricated by the method of fabricating the array substrate of the present invention.
  • the formation process of the color filter substrate 50 is as follows:
  • FIG. 16 is a schematic structural view showing a black matrix after the color filter substrate of the liquid crystal panel of the present invention is formed.
  • FIG. 17 is a schematic structural view showing a red color resist in the process of fabricating the color filter substrate of the liquid crystal panel of the present invention
  • FIG. 18 is a color film of the liquid crystal panel of the present invention.
  • FIG. 19 is a schematic structural view of the color filter substrate of the liquid crystal panel of the present invention after blue color resist is formed.
  • FIG. 20 is a process of fabricating the color filter substrate of the liquid crystal panel of the present invention. In the middle, a schematic diagram of the structure after the support member is formed.
  • the array substrate 60 and the color filter substrate 50 are formed, the array substrate 60 and the color filter substrate 50 are aligned and assembled, and a liquid crystal layer 70 is formed between the array substrate 60 and the color filter substrate 50, thereby forming the liquid crystal display panel of the present invention. .
  • the present invention can improve the pixel aperture ratio and the transmittance, so that the display effect is better.

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Abstract

液晶显示面板、阵列基板（60）及其制作方法。阵列基板（60）的制作方法包括：在衬底（31）上同时形成栅极图案层（32）和公共电极（33）；在栅极图案层（32）、公共电极（33）和衬底（31）上覆盖栅极绝缘层（34）；在栅极绝缘层（34）上形成半导体层（35）；在半导体层（35）上形成源\漏极图案层（36），同时在栅极绝缘层（34）上形成像素电极（37）和数据线（38）；在源\漏极图案层（36）、半导体层（35）、像素电极（37）和数据线（38）上覆盖钝化层（39）。该阵列基板（60）能提高像素开口率和穿透率，使得显示效果更佳。

Description

液晶显示面板、阵列基板及其制作方法
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示面板、阵列基板及其制作方法。
【背景技术】
液晶显示器是目前使用最广泛的一种平板显示器，已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用具有高分辨率彩色屏幕的显示器。随着液晶显示器技术的发展进步，人们对液晶显示器的显示品质、外观设计、低成本和高穿透率等提出了更高的要求
IPS（平面控制模式）广视角技术的液晶显示让观察者任何时候都只能看到液晶分子的短轴，因此在各个角度上观看的画面都不会有太大差别，这样就比较完美地改善了液晶显示器的视角。第一代IPS技术针对TN模式的弊病提出了全新的液晶排列方式，实现较好的可视角度。第二代IPS技术（S-IPS即Super-IPS）采用人字形电极，引入双畴模式，改善IPS模式在某些特定角度的灰阶逆转现象。第三代IPS技术（AS-IPS即Advanced Super-IPS）减小液晶分子间距离，提高开口率，获得更高亮度。
如图1和图2所示，图1是现有技术的液晶显示面板的截面结构示意图。图2是现有技术的液晶显示面板的像素结构示意图。现有的液晶显示面板包括TFT基板1、彩膜基板2和设置在所述TFT基板1和彩膜基板2之间的液晶层3。其中，TFT基板1包括玻璃衬底11、设置在玻璃衬底11上的栅极12，覆盖所述栅极12和玻璃衬底11之上的栅极绝缘层13，设置在所述栅极绝缘层13上的半导体层14和源\漏极图案层15以及数据线16，覆盖所述半导体层14、源\漏极图案层15和所述数据线16的隔离层17，设置在所述隔离层17上的像素电极18和公共电极19。现有技术中的TFT基板11的形成需要形成三层金属，第一层金属形成栅极12、第二层金属形成源\漏极图案层15和数据线16、第三层金属形成像素电极18和公共电极19。图2所示的像素中， TFT10、存储电容101和数据线16设在栅极12之上，公共电极19和像素电极18设置在数据线16和存储电容101之上，其中，像素电极18上还设有过孔105，以使像素电极18和TFT10上的源极通过过孔106进行连接。
现有技术中，像素电极与TFT桥接处需要设过孔，当像素较小时，该过孔会影响像素开口率，导致液晶显示器的穿透率过低。
【发明内容】
本发明提供一种液晶显示面板、阵列基板及其制作方法，能够解决现有技术存在的过孔影响像素开口率导致液晶显示器穿透率低的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制作方法，该方法包括以下步骤：在衬底上同时形成栅极图案层和公共电极；在所述栅极图案层、所述公共电极和所述衬底上覆盖栅极绝缘层；在所述栅极绝缘层上形成半导体层；在所述半导体层上形成源\漏极图案层，同时在所述栅极绝缘层上形成像素电极和数据线；在所述源\漏极图案层、半导体层、像素电极和数据线上覆盖钝化层。
其中，在所述源\漏极图案层、半导体层、像素电极和数据线上覆盖钝化层的步骤之后，还包括：在所述钝化层上形成顶层电极。
其中，所述顶层电极为ITO电极，所述顶层电极与所述公共电极电连接。
其中，当所述顶层电极为金属电极，所述顶层电极与所述公共电极电连接；在所述钝化层上形成顶层电极的步骤包括：在所述钝化层上形成顶层金属层；通过黄光制程将所述顶层金属层图案化形成顶层电极。
其中，在衬底上同时形成栅极图案层和公共电极的步骤包括：在所述衬底上形成第一金属层；通过黄光制程将所述第一金属层图案化形成栅极图案层和公共电极层。
其中，在所述半导体层上形成源\漏极图案层，同时在所述栅极绝缘层上形成像素电极和数据线的步骤包括：在所述半导体层和所述栅极绝缘层上覆盖第二金属层；通过黄光制程将所述第二金属层图案化形成源\漏极图案层、像素电极和数据线。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括衬底；形成在所述衬底之上的栅极图案层和公共电极；覆盖在所述栅极图案层和所述公共电极之上的栅极绝缘层；形成在所述栅极绝缘层之上的半导体层；形成在所述半导体层之上的源\漏极图案层以及设置在所述栅极绝缘层之上的像素电极和数据线；覆盖在所述源\漏极图案层、半导体层、像素电极和数据线之上的钝化层。
其中，所述阵列基板还包括形成在所述钝化层之上的顶层电极。
其中，所述顶层电极为金属电极或者ITO电极，所述顶层电极与所述公共电极电连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，该液晶面板包括彩膜基板、阵列基板以及设置在所述彩膜基板和所述阵列基板之间的液晶层，所述阵列基板包括衬底；形成在所述衬底之上的栅极图案层和公共电极；覆盖在所述栅极图案层和所述公共电极之上的栅极绝缘层；形成在所述栅极绝缘层之上的半导体层；形成在所述半导体层之上的源\漏极图案层以及设置在所述栅极绝缘层之上的像素电极和数据线；覆盖在所述源\漏极图案层、半导体层、像素电极和数据线之上的钝化层。
其中，所述阵列基板还包括形成在所述钝化层之上的顶层电极。
其中，所述顶层电极为金属电极或者ITO电极，所述顶层电极与所述公共电极电连接。
本发明的有益效果是：区别于现有技术的情况，本发明通过在形成栅极图案层的同时形成公共电极，在形成源\漏极图案层的同时形成像素电极和数据线，减少了一道制程，并且使像素电极与源\漏极图案层位于同一平面上，从而使得像素电极和源电极之间的连接无需过孔，即使像素很小时，也不会发生因过孔影响像素开口率的问题，进而提高了像素开口率和液晶显示器的穿透率，从而使得显示效果更佳。
【附图说明】
图1是现有技术的液晶显示面板的截面结构示意图；
图2是现有技术的液晶显示面板的像素结构示意图；
图3是本发明阵列基板的制作方法第一实施例的流程图；
图4是本发明阵列基板的制作方法第一实施例中形成栅极图案层和公共电极的步骤的示意图；
图5是本发明阵列基板的制作方法第一实施例中形成栅极绝缘层的步骤的示意图；
图6是本发明阵列基板的制作方法第一实施例中形成半导体层的步骤的示意图；
图7是本发明阵列基板的制作方法第一实施例中形成源\漏极图案层、像素电极和数据线的步骤的示意图；
图8是本发明阵列基板的制作方法第一实施例中形成钝化层的步骤的示意图；
图9是本发明阵列基板的制作方法第一实施例最终形成的像素结构的示意图；
图10是图9的像素结构中栅极图案层和公共电极之后的结构示意图；
图11是在图10上形成半导体层后的结构示意图；
图12是在图11上形成像素电极和数据线之后的结构示意图；
图13是本发明阵列基板的制作方法第二实施例的流程图；
图14是本发明阵列基板的制作方法第二实施例最终形成的像素结构的示意图；
图15是本发明液晶显示面板实施例的结构示意图；
图16是本发明液晶面板的彩膜基板制作过程中，形成黑矩阵后的结构示意图；
图17是本发明液晶面板的彩膜基板制作过程中，形成了红色色阻后的结构示意图；
图18是本发明液晶面板的彩膜基板制作过程中，形成了绿色色阻后的结构示意图；
图19是本发明液晶面板的彩膜基板制作过程中，形成了蓝色色阻后的结构示意图；
图20是本发明液晶面板的彩膜基板制作过程中，形成了支撑件后的结构示意图。
【具体实施方式】
下面结合附图和具体实施方式对本发明进行详细说明。
请参阅图3，图3是本发明阵列基板的制作方法第一实施例的流程图。本发明提供了一种阵列基板的制作方法，具体地，该方法包括以下步骤：
S101、在衬底31上同时形成栅极图案层32和公共电极33。
请结合图4，图4是本发明阵列基板的制作方法第一实施例中形成栅极图案层和公共电极的步骤的示意图。步骤S101中，在衬底31上形成第一金属层，然后通过黄光制程经曝光、显影和蚀刻形成栅极图案层32和公共电极33。栅极图案层32和公共电极33同时形成，并且位于同一平面中。栅极图案层32和公共电极33采用铝及铝合金或者铜等材料形成。
S102、在栅极图案层32、公共电极33和衬底31上覆盖栅极绝缘层34。
其中，栅极绝缘层34可以是一层结构，也可以是两层结构，如果采用两层结构，第一层为SiNx，SiO或者AlO，厚度在175-300nm左右，第二层一般采用SiNx，厚度在300nm左右，如图5所示，图5是本发明阵列基板的制作方法第一实施例中形成栅极绝缘层的步骤的示意图。栅极绝缘层34通过CVD或者PECVD的方式形成。
S103、在栅极绝缘层34上形成半导体层35。
如图6所示，图6是本发明阵列基板的制作方法第一实施例中形成半导体层的步骤的示意图。半导体层35的厚度为150-350nm，例如250nm，半导体层35也通过该CVD工艺形成。
S104、在半导体层35上形成源\漏极图案层36，同时在栅极绝缘层34上形成像素电极37和数据线38。
步骤S104中首先在半导体层35和栅极绝缘层34上形成第二金属层，再通过黄光制程经曝光、显影和蚀刻形成源\漏极图案层36、像素电极37和数据线38。请参阅图7，图7是本发明阵列基板的制作方法第一实施例中形成源\漏极图案层、像素电极和数据线的步骤的示意图。
第三金属层可以由铝合金或者金属铝或者金属铬制成。源\漏极图案层的厚度为350nm-450nm，例如，427nm或者400nm。
步骤S104中，在形成源\漏极图案层36的同时，形成了像素电极37和数据线38，像素电极37和数据线38也是金属，具体地，源\漏极图案层36的一部分位于半导体层35的上方，一部分位34于栅极绝缘层上。像素电极37、数据线38、半导体层35以及一部分源\漏极图案层36均位于栅极绝缘层34上，即位于同一平面上，因此，像素电极37与源电极之间无需经过孔进行连接，因而不会产生因过孔影响开口率导致液晶显示器的穿透率过低的问题，提示像素开口率和穿透率。
并且，本实施例中，第一层金属形成了栅极图案层和公共电极，第二层金属形成了源\漏极图案层、像素电极和数据线，因而可以不用形成第三层金属。整个液晶显示面板的制作过程中，节省了一道制程，且光罩数量由五道降为四道，节约了成本。
S105、在源\漏极图案层36、半导体层35、像素电极37和数据线上38覆盖钝化层39。
本实施例的钝化层39为氮化硅，其厚度为100nm-300nm，例如200nm或者250nm，该钝化层39对其下方的元器件起保护作用，如图8所示，图8是本发明阵列基板的制作方法第一实施例中形成钝化层的步骤的示意图。
经过上述步骤之后，最终形成的阵列基板的像素结构如图9所示，图9是本发明阵列基板的制作方法第一实施例最终形成的像素结构的示意图。图10、图11和图12是图9中的像素结构的分层结构图。其中，图10是图9的像素结构中栅极图案层和公共电极之后的结构示意图。图11是在图10上形成半导体层后的结构示意图。图12是在图11上形成像素电极和数据线之后的结构示意图。所形成的像素结构中，栅极图案层32和公共电极33位于同一平面上，TFT30设在栅极图案层32之上，存储电容370、像素电极37、TFT30中的源\漏极图案层以及数据线38设置在栅极图案层32和公共电极33之上，且同时形成，因而位于同一平面上，由于像素电极37和源\漏极图案层中的源极位于同一平面，所以像素电极37和源极之间无需通过过孔进行连接。
TFT10、存储电容101和数据线16设在栅极12之上，公共电极19和像素电极18设置在数据线16和存储电容101之上，其中，像素电极18上还设有过孔105，以使像素电极18和TFT10上的源极通过过孔106进行连接。
区别于现有技术，本发明通过在形成栅极图案层32的同时形成公共电极33，在形成源\漏极图案层36的同时形成像素电极37和数据线38，减少了一道制程，并且使像素电极37与源\漏极图案层36位于同一平面上，从而使得像素电极37和源电极之间的连接无需过孔，即使像素很小时，也不会发生因过孔影响像素开口率的问题，进而提高了像素开口率和液晶显示器的穿透率，从而使得显示效果更佳。
请参阅图13，图13是本发明阵列基板的制作方法第二实施例的流程图。
S201、在衬底31上同时形成栅极图案层32和公共电极33。
请继续参阅图4。具体地，步骤S201包括：在衬底31上形成第一金属层；通过黄光制程，经曝光、显影和蚀刻将第一金属层图案化形成栅极图案层32和公共电极层33。
S202、在栅极图案层32、公共电极33和衬底31上覆盖栅极绝缘层34。
具体地，栅极绝缘层34通过CVD或者PECVD的方式形成，请继续参阅图5。
S203、在栅极绝缘层32上形成半导体层35。
请继续参阅图5，其中，半导体层35也通过该CVD工艺形成。
S204、在半导体层35上形成源\漏极图案层36，同时在栅极绝缘层34上形成像素电极37和数据线38。
步骤S204包括：在半导体层35和栅极绝缘层34上覆盖第二金属层；通过黄光制程将第二金属层图案化形成源\漏极图案层36、像素电极37和数据线38，如图6所示。
S205、在源\漏极图案层36、半导体层35、像素电极37和数据线38上覆盖钝化层39。
如图7所示，钝化层39可以是氮化硅保护膜，通过CVD工艺形成，对TFT等元器件进行保护。
S206、在钝化层39上形成顶层电极40。
具体地，顶层电极40为ITO电极或者金属电极，顶层电极40与公共电极33电连接，通过公共电极33给顶层电极40进行配电。本实施例的顶层电极40为ITO电极。当顶层电极40为金属电极时，步骤S206包括：在钝化层39上形成顶层金属层；通过黄光制程将顶层金属层图案化形成顶层电极40。
如图14所示，图14是本发明阵列基板的制作方法第二实施例最终形成的像素结构的示意图。所形成的像素结构中，栅极图案层32和公共电极33位于同一平面上，TFT30设在栅极图案层32之上，存储电容370、像素电极37、TFT30中的源\漏极图案层以及数据线38设置在栅极图案层32和公共电极33之上，且同时形成，因而位于同一平面上，由于像素电极37和源\漏极图案层中的源极位于同一平面，所以像素电极37和源极之间无需通过过孔进行连接。在存储电容370、像素电极37、TFT30中的源\漏极图案层以及数据线38所在层之上还设有顶层电极40，顶层电极40与公共电极33连接。
本发明还提供了一种阵列基板，如图8所示，该阵列基板包括衬底31、形成在衬底31之上的栅极图案层32和公共电极33。覆盖在栅极图案层32和公共电极33之上的栅极绝缘层34。形成在栅极绝缘层34之上的半导体层35。形成在半导体层35之上的源\漏极图案层36以及设置在栅极绝缘层34之上的像素电极37和数据线38。覆盖在源\漏极图案层36、半导体层35、像素电极37和数据线38之上的钝化层39。
其中，栅极图案层32和公共电极33位于同一平面上，由同一层金属层形成。源\漏极图案层36、像素电极37和数据线38位于同一平面上，由同一层金属层形成，由于像素电极37和源\漏极图案层36在同一平面上，因而，像素电极37与源极之间无需经过孔连接，因而本发明的阵列基板的像素电极37上不用设置过孔，所以不会影响像素开口率，从而提高了穿透率。
在另一个实施例中，阵列基板还包括形成在钝化层39之上的顶层电极40，如图14所示。顶层电极40为金属电极或者ITO电极，顶层电极40与公共电极33电连接。
本发明还提供了一种液晶显示面板，请参阅图15，图15是本发明液晶显示面板实施例的结构示意图。该液晶显示面板包括彩膜基板50、阵列基板60以及设置在彩膜基板50和阵列基板60之间的液晶层70。其中，阵列基板60为上述任一实施例的阵列基板60。
具体地，阵列基板60可以通过本发明的阵列基板的制作方法制作而成。
彩膜基板50的形成过程如下：
在衬底51上形成黑矩阵52，如图16所示，图16是本发明液晶面板的彩膜基板制作过程中，形成黑矩阵后的结构示意图。
在衬底51和黑矩阵52上覆盖不同颜色的色阻以形成色阻层53，例如，红色色阻、绿色色阻和蓝色色阻，不同的颜色的色阻之间的分界线形成在黑矩阵52之上，如图20、21和22所示，图17是本发明液晶面板的彩膜基板制作过程中，形成了红色色阻后的结构示意图，图18是本发明液晶面板的彩膜基板制作过程中，形成了绿色色阻后的结构示意图，图19是本发明液晶面板的彩膜基板制作过程中，形成了蓝色色阻后的结构示意图。
在色阻层53上形成支撑件54，支撑件54的作用是维持阵列基板60和彩膜基板50之间的间隔，如图20所示，图20是本发明液晶面板的彩膜基板制作过程中，形成了支撑件后的结构示意图。
当阵列基板60和彩膜基板50形成之后，将阵列基板60和彩膜基板50对位组装，并在阵列基板60和彩膜基板50之间形成液晶层70，从而形成本发明的液晶显示面板。
综上所述，本发明能提高像素开口率和穿透率，使得显示效果更佳。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种阵列基板的制作方法，其中，包括以下步骤：
    在衬底上同时形成栅极图案层和公共电极；
    在所述栅极图案层、所述公共电极和所述衬底上覆盖栅极绝缘层；
    在所述栅极绝缘层上形成半导体层；
    在所述半导体层上形成源\漏极图案层，同时在所述栅极绝缘层上形成像素电极和数据线；
    在所述源\漏极图案层、半导体层、像素电极和数据线上覆盖钝化层。
  2. 根据权利要求1所述的方法，其中，在所述源\漏极图案层、半导体层、像素电极和数据线上覆盖钝化层的步骤之后，还包括：
    在所述钝化层上形成顶层电极。
  3. 根据权利要求2所述的方法，其中， 所述顶层电极为ITO电极，所述顶层电极与所述公共电极电连接。
  4. 根据权利要求2所述的方法，其中，当所述顶层电极为金属电极，所述顶层电极与所述公共电极电连接；
    在所述钝化层上形成顶层电极的步骤包括：
    在所述钝化层上形成顶层金属层；
    通过黄光制程将所述顶层金属层图案化形成顶层电极。
  5. 根据权利要求1所述的方法，其中，在衬底上同时形成栅极图案层和公共电极的步骤包括：
    在所述衬底上形成第一金属层；
    通过黄光制程将所述第一金属层图案化形成栅极图案层和公共电极层。
  6. 根据权利要求1所述的方法，其中，在所述半导体层上形成源\漏极图案层，同时在所述栅极绝缘层上形成像素电极和数据线的步骤包括：
    在所述半导体层和所述栅极绝缘层上覆盖第二金属层；
    通过黄光制程将所述第二金属层图案化形成源\漏极图案层、像素电极和数据线。
  7. 一种阵列基板，其中，包括：
    衬底；
    形成在所述衬底之上的栅极图案层和公共电极；
    覆盖在所述栅极图案层和所述公共电极之上的栅极绝缘层；
    形成在所述栅极绝缘层之上的半导体层；
    形成在所述半导体层之上的源\漏极图案层以及设置在所述栅极绝缘层之上的像素电极和数据线；
    覆盖在所述源\漏极图案层、半导体层、像素电极和数据线之上的钝化层。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括形成在所述钝化层之上的顶层电极。
  9. 根据权利要求8所述的阵列基板，其中，所述顶层电极为金属电极或者ITO电极，所述顶层电极与所述公共电极电连接。
  10. 一种液晶显示面板，其中，包括彩膜基板、阵列基板以及设置在所述彩膜基板和所述阵列基板之间的液晶层，所述阵列基板包括：
    衬底；
    形成在所述衬底之上的栅极图案层和公共电极；
    覆盖在所述栅极图案层和所述公共电极之上的栅极绝缘层；
    形成在所述栅极绝缘层之上的半导体层；
    形成在所述半导体层之上的源\漏极图案层以及设置在所述栅极绝缘层之上的像素电极和数据线；
    覆盖在所述源\漏极图案层、半导体层、像素电极和数据线之上的钝化层。
  11. 根据权利要求10所述的液晶显示面板，其中，所述阵列基板还包括形成在所述钝化层之上的顶层电极。
  12. 根据权利要求11所述的液晶显示面板，其中，所述顶层电极为金属电极或者ITO电极，所述顶层电极与所述公共电极电连接
PCT/CN2016/088495 2016-06-01 2016-07-05 液晶显示面板、阵列基板及其制作方法 Ceased WO2017206262A1 (zh)

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