WO2017201820A1 - 电平移位电路及具有该电平移位电路的显示面板 - Google Patents

电平移位电路及具有该电平移位电路的显示面板 Download PDF

Info

Publication number
WO2017201820A1
WO2017201820A1 PCT/CN2016/088615 CN2016088615W WO2017201820A1 WO 2017201820 A1 WO2017201820 A1 WO 2017201820A1 CN 2016088615 W CN2016088615 W CN 2016088615W WO 2017201820 A1 WO2017201820 A1 WO 2017201820A1
Authority
WO
WIPO (PCT)
Prior art keywords
start signal
circuit
timing signals
level shifting
display panel
Prior art date
Application number
PCT/CN2016/088615
Other languages
English (en)
French (fr)
Inventor
张先明
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/128,217 priority Critical patent/US10186222B2/en
Publication of WO2017201820A1 publication Critical patent/WO2017201820A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display screens, and more particularly to a level shift circuit and a display panel having the same.
  • the array substrate gate drive (GOA) circuit is currently widely used in LCD panels, and the use of this circuit can save LCD gate drive.
  • the required gate circuit is made in the panel, and the required timing voltage is generated by a level shifting chip (Level Shifter).
  • the timing controller (TCON) transmits multiple signals, such as a start signal (STV) and a clock. Signal (CLK), etc., for the level shifting chip, each signal requires one pin output of the timing controller, which requires the timing controller to require multiple pins, and different timing controllers have different pin numbers, When a level shifting chip requires multiple signal outputs, some timing controllers cannot match.
  • the present invention provides a simplified level shifting circuit and a display panel having the same.
  • the present invention provides a level shifting circuit for use in an array substrate gate driving circuit, the level shifting circuit including a timing controller and a level shifting chip, the timing controller including an initial signal pin, the
  • the flat shift chip includes a memory module and an operational amplifier module, wherein the memory module stores an initial value, and the timing controller is connected to the level shift chip through the start signal pin, and the timing controller is configured to pass
  • the start signal pin sends a start signal to the operational amplification module, and the operational amplification module is configured to generate multiple sets of timing signals based on the initial signal according to the initialization assignment in the storage module, and The plurality of sets of timing signals are sent to the display circuit of the display panel.
  • the operational amplification module is configured to trigger generation of the plurality of sets of timing signals based on an initial value of the initial signal according to an initialization value in the storage module.
  • the initial speech assignment includes an interval between a generation time of each set of timing signals and a rising edge of the start signal.
  • the initialization assignment in the storage module further includes a high level duration and a cycle time of the plurality of sets of timing signals.
  • the level shifting chip includes a plurality of output pins, and the operational amplification module is configured to output each set of timing signals to the display circuit through an output pin.
  • the present invention also provides a display panel comprising a level shifting circuit and a display circuit, the level shifting circuit comprising a timing controller and a level shifting chip, the timing controller comprising an initial signal pin,
  • the level shifting chip includes a memory module and an operational amplification module, wherein the memory module stores an initial value, and the timing controller is communicably connected to the level shifting chip through the start signal pin, and the timing control is
  • the device is configured to send a start signal to the operational amplification module by using a start signal pin, where the operational amplification module is configured to generate multiple sets of timing signals by using the initial signal as a reference according to an initialization assignment in the storage module. And transmitting the plurality of sets of timing signals to the display circuit.
  • the operational amplification module is configured to trigger generation of the plurality of sets of timing signals based on an initial value of the initial signal according to an initialization value in the storage module.
  • the initial speech assignment includes an interval between a generation time of each set of timing signals and a rising edge of the start signal.
  • the initialization assignment in the storage module further includes a high level duration and a cycle time of the plurality of sets of timing signals.
  • the level shifting chip includes a plurality of output pins, and the operational amplification module is configured to output each set of timing signals to the display circuit through an output pin.
  • the level shift circuit includes a timing controller and a level shifting chip, and the timing controller transmits a start signal to the level shifting chip through a start signal pin, the level shifting The chip triggers the generation of the plurality of sets of timing signals based on the initial signal, and sends the plurality of sets of timing signals to the display circuit of the display panel, thereby reducing the pins between the timing controller and the level shifting chip.
  • the number simplifies the level shifting circuit.
  • FIG. 1 is a system block diagram of a preferred embodiment of a display panel of the present invention.
  • FIG. 2 is a timing diagram of a level shifting circuit of a preferred embodiment of the display panel of the present invention.
  • a preferred embodiment of the display panel of the present invention includes a level shifting circuit 100 and a display circuit 300.
  • the level shifting circuit includes a timing controller 10 and a level shifting chip 20.
  • the timing controller 10 and a level shifting chip 20 are disposed on a circuit driving board.
  • the level shifting chip 20 includes a memory module 201 and an operational amplification module 202.
  • the timing controller 10 is communicatively coupled to the level shifting chip 20 via a start signal pin.
  • the timing controller 10 is configured to send a start signal (STV) to the operational amplification module 202 through a start signal pin, where the storage module 201 stores an initial value, the initial speech assignment includes each set of timing signals.
  • the interval between the generation time and the rising edge of the start signal is T1 to Tn, the high-level duration Tn+1 of the timing signal, and the cycle time Tn+2 of the timing signal.
  • the operational amplification module 202 is configured to generate a plurality of sets of timing signals by using the initial signal as a reference according to the initialization assignment in the storage module 201, and send the multiple sets of timing signals to the display circuit 300 of the display panel.
  • the level shifting chip 20 correctly recognizes the rising edge of the start signal, and triggers the output four based on the rising edge of the start signal.
  • the initial speech assignment includes an interval T1 between a generation time of the first group of timing signals CKV1 and a rising edge of the start signal, an interval between a generation time of the second group of timing signals CKV2 and a rising edge of the start signal.
  • the initial value further includes a high-level duration T5 of the four sets of timing signals CKV1 CK CKV4 and a cycle time T6.
  • the high-level duration T5 and the cycle time T6 may be set up Different values. In this embodiment, only four sets of timing signals are taken as an example, but the present invention is not limited thereto, and can be applied to the case of more sets of timing signals.
  • the level shifting chip 20 can trigger a corresponding timing signal according to different states of the initial signal, thereby greatly improving The compatibility of the level shifting chip 20 is achieved.
  • the level shift circuit for a GOA-structured liquid crystal panel of the present invention can reduce the number of pins between the timing controller 10 and the level shifting chip 20 compared to the existing level shifting circuit for a GOA-structured liquid crystal panel
  • the total number of traces between the timing controller 10 and the level shifting chip 20 is reduced, the size of the circuit driving board is reduced, and the production cost is reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种用于阵列基板栅极驱动电路中的电平移位电路（100）及显示面板，所述电平移位电路（100）包括时序控制器（10）及电平移位芯片（20），所述时序控制器（10）包括初始信号引脚，所述电平移位芯片（20）内包括存储模块（202）及运算放大模块（201），所述存储模块（202）储存有初始化赋值，所述时序控制器（10）通过所述初始信号引脚与所述电平移位芯片（20）连接，所述时序控制器（10）用于通过初始信号引脚发送起始信号给所述运算放大模块（201），所述运算放大模块（201）用于根据所述存储模块（202）内的初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给显示面板的显示电路（300）。

Description

电平移位电路及具有该电平移位电路的显示面板 技术领域
本发明涉及显示屏领域，尤其涉及一种电平移位电路及具有该电平移位电路的显示面板。
背景技术
阵列基板栅极驱动(GOA)电路目前大量应用于LCD面板中，使用此电路可以节省LCD栅极驱动。其所需求栅极电路是在面板内做成，其需要的时序电压是由电平位移芯片(Level Shifter)产生，时序控制器(TCON)发送多个信号，例如起始信号(STV)、时钟信号(CLK)等，给所述电平位移芯片，每个信号需要时序控制器的一个引脚输出，这就要求时序控制器需要多个引脚，不同的时序控制器的引脚数量不同，当电平位移芯片需要多个信号输出，有些时序控制器无法匹配。
发明内容
为克服现有技术的不足，本发明提供一种简化的电平移位电路及具有该电平移位电路的显示面板。
本发明提供一种用于阵列基板栅极驱动电路中的电平移位电路，所述电平移位电路包括时序控制器及电平移位芯片，所述时序控制器包括初始信号引脚，所述电平移位芯片内包括存储模块及运算放大模块，所述存储模块储存有初始化赋值，所述时序控制器通过所述起始信号引脚与所述电平移位芯片连接，所述时序控制器用于通过起始信号引脚发送起始信号给所述运算放大模块，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给显示面板的显示电路。
进一步地，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号的上升沿为基准，触发产生所述多组时序信号。
所述初始话赋值包括每一组时序信号的产生时间与所述起始信号的上升沿之间的间隔时间。
进一步地，所述存储模块内的初始化赋值还包括所述多组时序信号的高电平持续时间及周期时间。
进一步地，所述电平移位芯片包括多个输出引脚，所述运算放大模块用于将每组时序信号通过一个输出引脚输出至所述显示电路。
本发明还提供一种显示面板，所述显示面板包括电平移位电路及显示电路，所述电平移位电路包括时序控制器及电平移位芯片，所述时序控制器包括初始信号引脚，所述电平移位芯片内包括存储模块及运算放大模块，所述存储模块储存有初始化赋值，所述时序控制器通过所述起始信号引脚与所述电平移位芯片通信连接，所述时序控制器用于通过起始信号引脚发送起始信号给所述运算放大模块，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给所述显示电路。
进一步地，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号的上升沿为基准，触发产生所述多组时序信号。
进一步地，所述初始话赋值包括每一组时序信号的产生时间与所述起始信号的上升沿之间的间隔时间。
进一步地，所述存储模块内的初始化赋值还包括所述多组时序信号的高电平持续时间及周期时间。
进一步地，所述电平移位芯片包括多个输出引脚，所述运算放大模块用于将每组时序信号通过一个输出引脚输出至所述显示电路。
本发明的有益效果：所述电平移位电路包括时序控制器及电平移位芯片，所述时序控制器通过起始信号引脚发送起始信号给所述电平移位芯片，所述电平移位芯片根据初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给显示面板的显示电路，从而减少时序控制器与电平移位芯片之间的引脚数，简化了电平移位电路。
附图说明
图1为本发明显示面板较佳实施方式的系统框图。
图2为本发明显示面板较佳实施方式的电平位移电路的时序图。
具体实施方式
下面，将结合附图对本发明各实施例作详细介绍。
请参阅图1及图2，本发明显示面板较佳实施方式包括电平移位电路100及显示电路300。所述电平移位电路包括一时序控制器10及一电平移位芯片20。在本实施例中，所述时序控制器10及一电平移位芯片20设于电路驱动板上。
所述电平移位芯片20内包括一存储模块201及一运算放大模块202。
所述时序控制器10通过起始信号引脚与电平移位芯片20通信连接。所述时序控制器10用于通过起始信号引脚发送起始信号(STV)给所述运算放大模块202，所述存储模块201储存有初始化赋值，所述初始话赋值包括每一组时序信号的产生时间与所述起始信号的上升沿之间的间隔时间T1～Tn、时序信号的高电平持续时间Tn+1及时序信号的周期时间Tn+2。所述运算放大模块202用于根据所述存储模块201内的初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给显示面板的显示电路300。
以所述电平移位芯片20输出四组时序信号CKV1～CKV4为例，所述电平移位芯片20的正确识别到起始信号的上升沿，以起始信号的上升沿为基准，触发输出四组时序信号CKV1～CKV4。所述初始话赋值包括第一组时序信号CKV1的产生时间与起始信号的上升沿之间的间隔时间T1、第二组时序信号CKV2的产生时间与起始信号的上升沿之间的间隔时间T2、第三组时序信号CKV3的产生时间与起始信号的上升沿之间的间隔时间T3、第四组时序信号CKV4的产生时间与起始信号的上升沿之间的间隔时间T4。另外，所述初始值还包括该四组时序信号CKV1～CKV4的高电平持续时间T5、与周期时间T6，针对不同解析度的液晶面板，所述高电平持续时间T5和周期时间T6可以设定 不同值。本实施例仅以四组时序信号为例进行说明，但本发明并不局限于此，还可以适用于更多组时序信号的情况。
另外，所述初始信号处于不同状态下，例如一般状态下、削角状况及预充电状况下，所述电平移位芯片20均能根据初始信号的不同状态来触发对应的时序信号，从而大大提升了所述电平移位芯片20的兼容性。
相比于现有的用于GOA架构液晶面板的电平移位电路，本发明的用于GOA架构液晶面板的电平移位电路能够减少时序控制器10与电平移位芯片20之间的引脚数，减少时序控制器10与电平移位芯片20之间的走线总数，减小电路驱动板的尺寸，降低生产成本。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (10)

  1. 一种用于阵列基板栅极驱动电路中的电平移位电路，其中，所述电平移位电路包括时序控制器及电平移位芯片，所述时序控制器包括初始信号引脚，所述电平移位芯片内包括存储模块及运算放大模块，所述存储模块储存有初始化赋值，所述时序控制器通过所述起始信号引脚与所述电平移位芯片连接，所述时序控制器用于通过起始信号引脚发送起始信号给所述运算放大模块，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给显示面板的显示电路。
  2. 根据权利要求1所述的电平移位电路，其中，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号的上升沿为基准，触发产生所述多组时序信号。
  3. 根据权利要求1所述的电平移位电路，其中，所述初始话赋值包括每一组时序信号的产生时间与所述起始信号的上升沿之间的间隔时间。
  4. 根据权利要求1所述的电平移位电路，其中，所述存储模块内的初始化赋值还包括所述多组时序信号的高电平持续时间及周期时间。
  5. 根据权利要求1所述的电平移位电路，其中，所述电平移位芯片包括多个输出引脚，所述运算放大模块用于将每组时序信号通过一个输出引脚输出至所述显示电路。
  6. 一种显示面板，其中，所述显示面板包括电平移位电路及显示电路，所述电平移位电路包括时序控制器及电平移位芯片，所述时序控制器包括初始信号引脚，所述电平移位芯片内包括存储模块及运算放大模块，所述存储模块储存有初始化赋值，所述时序控制器通过所述起始信号引脚与所述电平移位芯片通信连接，所述时序控制器用于通过起始信号引脚发送起始信号给所述运算放大模块，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号为基准触发产生多组时序信号，并将所述多组时序信号发送给所述显示电路。
  7. 根据权利要求6所述的显示面板，其中，所述运算放大模块用于根据所述存储模块内的初始化赋值以所述起始信号的上升沿为基准，触发产生所述多组时序信号。
  8. 根据权利要求6所述的显示面板，其中，所述初始话赋值包括每一组时 序信号的产生时间与所述起始信号的上升沿之间的间隔时间。
  9. 根据权利要求6所述的显示面板，其中，所述存储模块内的初始化赋值还包括所述多组时序信号的高电平持续时间及周期时间。
  10. 根据权利要求6所述的显示面板，其中，所述电平移位芯片包括多个输出引脚，所述运算放大模块用于将每组时序信号通过一个输出引脚输出至所述显示电路。
PCT/CN2016/088615 2016-05-25 2016-07-05 电平移位电路及具有该电平移位电路的显示面板 WO2017201820A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/128,217 US10186222B2 (en) 2016-05-25 2016-07-05 Level shift circuit and display panel having the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610356193.3 2016-05-25
CN201610356193.3A CN106448580A (zh) 2016-05-25 2016-05-25 电平移位电路及具有该电平移位电路的显示面板

Publications (1)

Publication Number Publication Date
WO2017201820A1 true WO2017201820A1 (zh) 2017-11-30

Family

ID=58183174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/088615 WO2017201820A1 (zh) 2016-05-25 2016-07-05 电平移位电路及具有该电平移位电路的显示面板

Country Status (3)

Country Link
US (1) US10186222B2 (zh)
CN (1) CN106448580A (zh)
WO (1) WO2017201820A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481682A (zh) 2017-07-21 2017-12-15 惠科股份有限公司 显示面板的驱动方法及驱动装置
CN107633828B (zh) * 2017-09-22 2020-05-12 深圳市华星光电技术有限公司 电平移位电路
CN108154859B (zh) * 2018-01-16 2020-09-08 深圳市华星光电技术有限公司 一种阵列基板及显示装置
CN111599299B (zh) * 2020-06-18 2023-12-12 京东方科技集团股份有限公司 电平转换电路、显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169793A1 (en) * 2009-09-14 2011-07-14 Au Optronics Corp. Liquid Crystal Display, Flat Display and Gate Driving Method Thereof
CN104680991A (zh) * 2015-03-03 2015-06-03 深圳市华星光电技术有限公司 用于goa架构液晶面板的电平移位电路及电平移位方法
CN105390106A (zh) * 2015-12-07 2016-03-09 深圳市华星光电技术有限公司 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3582082B2 (ja) * 1992-07-07 2004-10-27 セイコーエプソン株式会社 マトリクス型表示装置，マトリクス型表示制御装置及びマトリクス型表示駆動装置
US5900856A (en) * 1992-03-05 1999-05-04 Seiko Epson Corporation Matrix display apparatus, matrix display control apparatus, and matrix display drive apparatus
JP3758545B2 (ja) * 2001-10-03 2006-03-22 日本電気株式会社 サンプリングレベル変換回路と２相及び多相展開回路並びに表示装置
JP3896542B2 (ja) * 2002-11-29 2007-03-22 日本テキサス・インスツルメンツ株式会社 走査駆動用集積回路
JP2006178018A (ja) * 2004-12-21 2006-07-06 Renesas Technology Corp 液晶表示駆動用半導体集積回路
US7932884B2 (en) * 2007-01-15 2011-04-26 Lg Display Co., Ltd. Liquid crystal display and driving method thereof
KR100911982B1 (ko) * 2008-03-04 2009-08-13 삼성모바일디스플레이주식회사 이미션 구동부 및 이를 이용한 유기전계발광 표시장치
KR101322119B1 (ko) * 2008-12-15 2013-10-25 엘지디스플레이 주식회사 액정표시장치
KR101310919B1 (ko) * 2008-12-15 2013-09-25 엘지디스플레이 주식회사 액정표시장치
KR101325362B1 (ko) * 2008-12-23 2013-11-08 엘지디스플레이 주식회사 액정표시장치
KR101325435B1 (ko) * 2008-12-23 2013-11-08 엘지디스플레이 주식회사 액정표시장치
US8239745B2 (en) * 2009-06-02 2012-08-07 Freescale Semiconductor, Inc. Parity data encoder for serial communication
JP5780650B2 (ja) * 2011-11-11 2015-09-16 株式会社Ｊｏｌｅｄ レベルシフタ回路、走査回路、表示装置、及び、電子機器
TWI478142B (zh) * 2012-11-01 2015-03-21 Au Optronics Corp 顯示裝置與其驅動模組、電壓控制電路和方法
KR20140105932A (ko) * 2013-02-25 2014-09-03 삼성전자주식회사 전압 레벨 변환 회로 및 이를 포함하는 디스플레이 장치
KR102208396B1 (ko) * 2013-12-30 2021-01-26 엘지디스플레이 주식회사 전원 공급 장치 및 이를 포함하는 표시 장치
CN104660935B (zh) * 2015-02-12 2018-02-23 深圳创维－Rgb电子有限公司 一种t‑con电压调整装置、系统及方法
JP6582435B2 (ja) * 2015-02-24 2019-10-02 セイコーエプソン株式会社 集積回路装置及び電子機器
KR102578838B1 (ko) * 2016-09-30 2023-09-18 엘지디스플레이 주식회사 게이트 구동부 및 이를 포함하는 표시장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169793A1 (en) * 2009-09-14 2011-07-14 Au Optronics Corp. Liquid Crystal Display, Flat Display and Gate Driving Method Thereof
CN104680991A (zh) * 2015-03-03 2015-06-03 深圳市华星光电技术有限公司 用于goa架构液晶面板的电平移位电路及电平移位方法
CN105390106A (zh) * 2015-12-07 2016-03-09 深圳市华星光电技术有限公司 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法

Also Published As

Publication number Publication date
CN106448580A (zh) 2017-02-22
US10186222B2 (en) 2019-01-22
US20180218697A1 (en) 2018-08-02

Similar Documents

Publication Publication Date Title
WO2016138686A1 (zh) 用于goa架构液晶面板的电平移位电路及电平移位方法
WO2017201820A1 (zh) 电平移位电路及具有该电平移位电路的显示面板
US7688934B2 (en) Shift register and shift register unit for diminishing clock coupling effect
CN104751763B (zh) 显示装置和初始化显示装置的选通移位寄存器的方法
US20180174542A1 (en) Display driving circuit, driving method thereof, and display device
WO2015176511A1 (zh) 触摸显示屏及其分时驱动方法
TW201013625A (en) Apparatus, shift register unit, liquid crystal displaying device and method for eliminating afterimage
WO2017201839A1 (zh) 液晶显示器的驱动系统及驱动方法
CN106448536A (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
US20150154927A1 (en) Gate driver-on-array driving circuit and driving method
US10522065B2 (en) Transmitting electrode scan driving unit, driving circuit, driving method and array substrate
CN101656056A (zh) 时序控制器和具有该时序控制器的显示装置
KR101205543B1 (ko) 표시 장치 및 이의 구동 방법
CN102760409A (zh) 移位寄存器电路、显示器及移位寄存器
CN105390106A (zh) 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法
RU2667459C1 (ru) Управляющая схема драйвера затвора в матрице, применяемая для дисплейного устройства с плоской панелью, и дисплейное устройство с плоской панелью
US20110063278A1 (en) Tft-lcd driving circuit
KR102549431B1 (ko) 표시 장치
US20070236270A1 (en) Clock-pulse generator and shift register using the same
US10354610B2 (en) Scanning circuit, display device and method for driving scanning circuit
CN101271675B (zh) 利用自掩蔽的lcd驱动方法和掩蔽电路
TW200629207A (en) Liquid crystal display and driving method thereof
CN106601174A (zh) 移位寄存器、驱动方法、goa电路和显示装置
TWI443624B (zh) 重置電路
CN106409210A (zh) 信号产生电路及信号产生方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15128217

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16902808

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16902808

Country of ref document: EP

Kind code of ref document: A1