WO2016138686A1 - 用于goa架构液晶面板的电平移位电路及电平移位方法 - Google Patents

用于goa架构液晶面板的电平移位电路及电平移位方法 Download PDF

Info

Publication number
WO2016138686A1
WO2016138686A1 PCT/CN2015/075694 CN2015075694W WO2016138686A1 WO 2016138686 A1 WO2016138686 A1 WO 2016138686A1 CN 2015075694 W CN2015075694 W CN 2015075694W WO 2016138686 A1 WO2016138686 A1 WO 2016138686A1
Authority
WO
WIPO (PCT)
Prior art keywords
level shifting
liquid crystal
start signal
crystal panel
goa
Prior art date
Application number
PCT/CN2015/075694
Other languages
English (en)
French (fr)
Inventor
曾德康
徐枫程
吴晶晶
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/758,803 priority Critical patent/US20160335968A1/en
Publication of WO2016138686A1 publication Critical patent/WO2016138686A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a level shift circuit and a level shifting method for a GOA-structured liquid crystal panel.
  • the active matrix liquid crystal display includes a plurality of pixels, each of which has a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the gate of the TFT is connected to a scan line extending in a horizontal direction
  • the drain of the TFT is connected to a data line extending in a vertical direction
  • the source of the TFT is connected to a corresponding pixel electrode. If a sufficient positive voltage is applied to a certain scanning line in the horizontal direction, all the TFTs connected to the scanning line are turned on, and the data signal voltage loaded on the data line is written into the pixel electrode, thereby displaying a picture. .
  • the liquid crystal panel of one type of active matrix liquid crystal display adopts GOA architecture (Gate Drive On Array) to integrate a gate driver (Gate Drive IC) on a thin film transistor array (Array) substrate to realize progressive scanning on the liquid crystal panel. drive.
  • GOA architecture Gate Drive On Array
  • the GOA architecture can reduce the manufacturing process, reduce the cost, improve the integration of the liquid crystal display panel, and facilitate the realization of the panel. Ultra-narrow bezel and thin.
  • using the GOA architecture will cause a level shifting chip (Level Shift IC) on the circuit driver board (PCBA) to boost the low voltage driving signal to the high voltage driving signal to drive the TFT in the liquid crystal panel to work.
  • Level Shift IC level shifting chip
  • a conventional level shifting circuit for a GOA-structured liquid crystal panel generally includes: a timing controller (TCON) 100 disposed on a circuit board PCBA, the timing controller 100 is configured to generate and transmit a control signal such as a start signal STV, a timing signal CKVn, n is a positive integer; a level shifting chip 200 disposed on the circuit board PCBA for boosting the start sent by the timing controller 100 The voltage of the signal STV and the timing signal CKVn. The start signal STV boosted by the level shifting chip 200 and the timing signal CKVn drive the TFTs in the GOA-structured liquid crystal panel 300.
  • TCON timing controller
  • timing signals CKV1 to CKV4 or more are generally required to realize the display effect of the progressive scan.
  • Each control signal requires the timing controller 100 and the level shifting chip 200 to have corresponding pins for communication connection, as shown in FIG. 1, when there are four sets of timing signals CKV1 CK CKV4 and one At the start signal STV, a total of five pairs of one-to-one corresponding pins are required for the communication connection of the timing controller 100 and the level shifting chip 200 to boost the voltage of each control signal.
  • the timing controller 100 generates a start signal STV, and sequentially generates timing signals CKV1, CKV2, CKV3, and sequentially after T1, T2, T3, and T4 intervals, based on the rising edge of the start signal STV.
  • CKV4 The low level of the start signal STV and the timing signals CKV1 CK CKV4 is 0V, the high level is 3.3V, the high level duration is T5, and the cycle time is T6.
  • the low level of the start signal STV and the timing signals CKV1 to CKV4 boosted by the level shifting chip 200 is -6V, the high level is 30V, and the timing signals CKV1 to CKV4 are relative to the start signal.
  • the time interval, high level duration, and cycle time of the rising edge of STV are unchanged.
  • the above-described level shifting circuit for the GOA-structured liquid crystal panel can realize the voltage of each control signal to drive the TFT in the liquid crystal panel, but when the required timing signal CKVn is more and more, the timing controller 100 and There are more and more pins required between the level shifting chips 200, and each additional pin may increase the package size of the timing controller 100 and the level shifting chip 200.
  • the size of the package model directly affects the cost of the IC. At the same time, the more traces will increase the PCBA size, further increasing costs. Therefore, when the required number of timing signals CKVn is large, the cost of the IC and the cost of the PCBA are significantly increased, which is not conducive to the original intention of reducing the cost by using the GOA architecture.
  • the total number of traces between the timing controller and the level shifting chip is reduced, the circuit board size is reduced, and the production cost is reduced.
  • Another object of the present invention is to provide a level shifting method for a GOA-structured liquid crystal panel, which can generate a larger number of timing signals, and can reduce the number of pins between the timing controller and the level shifting chip, and reduce the number of pins.
  • the package type of the timing controller and the level shifting chip reduces the total number of traces between the timing controller and the level shifting chip, reduces the size of the circuit driver board, and reduces the production cost.
  • the present invention first provides a level shifting circuit for a GOA-structured liquid crystal panel, comprising: a timing controller and a level shifting chip;
  • the level shifting chip includes a delay calculation register module
  • the timing controller is communicably connected to the level shifting chip through an initial signal line and an IIC bus;
  • the timing controller calculates a registration module for a delay in a level shifting chip through an IIC bus Performing initial assignment, sending a start signal to the level shifting chip through the start signal line;
  • the level shifting chip triggers outputting at least four sets of timing signals according to an initial value in the delay calculation register module, and triggers outputting at least four sets of timing signals, and boosting voltages of the start signal and at least four sets of timing signals;
  • the start signal and each set of timing signals are respectively transmitted to the GOA architecture liquid crystal panel through a signal line.
  • the IIC bus includes a serial data signal line for transmitting a serial data signal and a serial timing signal line for transmitting a serial timing signal.
  • the level shifting chip triggers the output of at least four sets of timing signals based on the initial value of the start signal according to the initialization value in the delay calculation register module.
  • the high level duration and cycle time of the at least four sets of timing signals are also determined by an initialization assignment in the delay calculation register module.
  • the invention also provides a level shifting circuit for a GOA architecture liquid crystal panel, comprising: a timing controller and a level shifting chip;
  • the level shifting chip includes a delay calculation register module
  • the timing controller is communicably connected to the level shifting chip through an initial signal line and an IIC bus;
  • the timing controller performs initial value assignment on the delay calculation register module in the level shift chip through the IIC bus, and sends a start signal to the level shift chip through the start signal line;
  • the level shifting chip triggers outputting at least four sets of timing signals according to an initial value in the delay calculation register module, and triggers outputting at least four sets of timing signals, and boosting voltages of the start signal and at least four sets of timing signals;
  • the start signal and each set of timing signals are respectively transmitted to the GOA architecture liquid crystal panel through a signal line;
  • the IIC bus includes a serial data signal line for transmitting a serial data signal and a serial timing signal line for transmitting a serial timing signal;
  • the level shifting chip triggers the output of at least four sets of timing signals based on the initial value of the start signal according to the initialization value in the delay calculation register module.
  • the invention also provides a level shifting method for a GOA architecture liquid crystal panel, comprising the following steps:
  • Step 1 providing a GOA architecture liquid crystal panel, and a level shift circuit for the GOA architecture liquid crystal panel;
  • the level shifting circuit for a GOA-structured liquid crystal panel includes a timing controller and a level shifting chip; the level shifting chip includes a delay calculating register module; and the timing controller passes the start signal line And the IIC bus is connected to the level shifting chip;
  • Step 2 The timing controller performs initial value assignment on the delay calculation register module in the level shifting chip through the IIC bus;
  • Step 3 The timing controller generates a start signal and sends the same to the level shifting chip through the start signal line;
  • Step 4 The level shifting chip triggers outputting at least four sets of timing signals based on the initial value of the delay calculation register module, and boosting the voltage of the start signal and the at least four sets of timing signals;
  • the boosted start signal and each set of timing signals are respectively transmitted to the GOA-structured liquid crystal panel through a signal line.
  • the IIC bus includes a serial data signal line for transmitting a serial data signal and a serial timing signal line for transmitting a serial timing signal.
  • the initialization assignment in the delay calculation register module is determined according to the serial data signal and the serial timing signal.
  • the level shifting chip triggers the output of at least four sets of timing signals according to the initial value of the delay calculation calculation register based on the rising edge of the start signal; the generation time of each set of timing signals and the start signal A rising edge interval corresponds to an initial assignment.
  • the high level duration and the cycle time of the at least four sets of timing signals are also determined by the initialization assignment in the delay calculation register module.
  • the present invention provides a level shift circuit and a level shifting method for a GOA-structured liquid crystal panel, in which a delay calculation register module is set in a level shifting chip, using a start signal line and an IIC bus
  • the timing controller is communicatively coupled to the level shifting chip.
  • the timing controller initializes the delay calculation register module in the level shifting chip through the IIC bus, and sends a start signal to the level shifting chip through the initial signal line; the level shifting chip calculates the initialization in the register module according to the delay time.
  • the assignment is based on the start signal, triggering output of at least four sets of timing signals, and boosting the voltage of the start signal and at least four sets of timing signals to drive the GOA architecture liquid crystal panel, which can reduce the timing controller and level shifting
  • the number of pins between the chips reduces the package type of the timing controller and the level shifting chip, reduces the total number of traces between the timing controller and the level shifting chip, reduces the size of the circuit driver board, and reduces the production cost. A larger number of timing signals are generated at lower cost.
  • FIG. 1 is a schematic diagram of a conventional level shift circuit for a GOA-structured liquid crystal panel
  • FIG. 2 is a timing diagram of the circuit of FIG. 1 before boosting
  • Figure 3 is a timing diagram of the circuit of Figure 1 after boosting
  • FIG. 4 is a schematic diagram of a level shifting circuit for a GOA-structured liquid crystal panel according to the present invention.
  • Figure 5 is a timing diagram of the circuit of Figure 4 before boosting
  • Figure 6 is a timing diagram of the circuit of Figure 4 after boosting.
  • the present invention provides a level shifting circuit for a GOA-structured liquid crystal panel.
  • the level shifting circuit for the GOA-structured liquid crystal panel includes a timing controller 10 and a level shifting chip 20, and the timing controller 10 and a level shifting chip 20 are disposed on the circuit driving board PCBA.
  • the level shifting chip 20 includes a delay calculation register module 201.
  • the timing controller 10 is communicatively coupled to the level shifting chip 20 via an initial signal line 30 and an IIC bus 40.
  • the IIC bus 40 includes a serial data signal line for transmitting a serial data signal SDA and a serial timing signal line for transmitting a serial timing signal SCL.
  • the timing controller is configured to initialize the delay calculation register 201 in the level shifting chip 20 through the IIC bus 40 to assign initial values T1 to Tn, n is a positive integer, and send the start signal STV to the electrical translation through the start signal line 30. Bit chip 20.
  • the level shifting chip 20 is configured to trigger output of at least four sets of timing signals CKV1 CK CKVn according to the initial value T1 - Tn in the delay calculation register 201, with reference to the start signal STV, and raise the start signal STV And voltages of at least four sets of timing signals CKV1 CKCKVn; the boosted start signal STV and each set of timing signals are respectively transmitted to the GOA architecture liquid crystal panel 50 through a signal line.
  • the level shift circuit for a GOA-structured liquid crystal panel of the present invention can reduce the number of pins between the timing controller 10 and the level shifting chip 20 compared to the existing level shifting circuit for a GOA-structured liquid crystal panel
  • the package type of the timing controller 10 and the level shifting chip 20 is reduced, the total number of traces between the timing controller 10 and the level shifting chip 20 is reduced, the size of the circuit board PCBA is reduced, and the production cost is reduced.
  • the level shifting chip 20 triggers the output of at least four sets of timing signals CKV1 CK CKVn based on the rising edges of the start signal STV based on the initialization values T1 TTn in the delay calculation register 201.
  • An initialization assignment Tn corresponding to the generation time of each set of timing signals CKVn and the rising edge interval of the start signal STV.
  • the high level duration Tn+1 and the period time Tn+2 of the at least four sets of timing signals CKV1 CK CKVn are also determined by the initialization assignments in the delay calculation register module 201.
  • the level shifting chip 20 outputs four sets of timing signals CKV1 CK CKV4 as an example.
  • the timing controller 10 respectively passes through the serial data signal line and the serial timing signal line of the IIC bus 40 .
  • the serial data signal SDA and the serial timing signal SCL are sent to the delay calculation register 201 in the level shifting chip 20 for determining the initialization values T1 to T4 of the delay calculation register module 201, through the start signal line 30.
  • the start signal STV is sent to the level shifting chip 20.
  • the low level of the start signal STV, the serial data signal SDA, and the serial timing signal SCL are both 0V, and the high level is 3.3V.
  • the level shifting chip 20 correctly recognizes the rising edge of the start signal STV, and triggers the output of the four sets of timing signals CKV1 CK CKV4 with reference to the rising edge of the start signal STV.
  • the voltages of the start signal STV and the four sets of timing signals CKV1 to CKV4 are boosted.
  • the generation time of the first group of timing signals CKV1 and the rising edge of the start signal STV are initialized with the time corresponding to the value T1
  • the generation time of the second group of timing signals CKV2 and the rising edge of the start signal STV are initialized with the corresponding value T2.
  • the generation time of the third group timing signal CKV3 and the rising edge interval of the start signal STV are initialized with the time corresponding to the value T3, and the generation time of the fourth group timing signal CKV4 and the rising edge interval of the start signal STV are initialized by the value T4.
  • the high-level duration T5 and the cycle time T6 of the four sets of timing signals CKV1 CK CKV4 are also determined by the initialization assignment in the delay calculation register module 201, and the high-power is applied to the liquid crystal panels of different resolutions.
  • the flat duration T5 and the cycle time T6 can be set by different initialization assignments.
  • the low level of the start signal STV and the first, second, third, and fourth sets of timing signals CKV1, CKV2, CKV3, and CKV4 are both -6V, and the high voltage is high.
  • the average is 30V, which can be used to drive the TFTs in the GOA-structured liquid crystal panel 50 to realize progressive scanning.
  • only four sets of timing signals are taken as an example, but the present invention is not limited thereto, and can be applied to the case of more sets of timing signals.
  • the present invention further provides a level shifting method for a GOA-structured liquid crystal panel, comprising the following steps:
  • Step 1 Provide a GOA architecture liquid crystal panel 50 and a level shift circuit for the GOA architecture liquid crystal panel.
  • the level shifting circuit for the GOA-structured liquid crystal panel includes a timing controller 10 and a level shifting chip 20, and the timing controller 10 and a level shifting chip 20 are disposed on the circuit driving board PCBA.
  • the level shifting chip 20 includes a delay calculation register module 201.
  • the timing controller 10 is communicatively coupled to the level shifting chip 20 via an initial signal line 30 and an IIC bus 40.
  • the IIC bus 40 includes a serial data signal line for transmitting the serial data signal SDA and a serial timing signal line for transmitting the serial timing signal SCL.
  • Step 2 The timing controller 10 initializes the delay calculation register 201 in the level shifting chip 20 through the IIC bus 40 to initialize the values T1 to Tn, where n is a positive integer.
  • the step 2 determines the initialization assignments T1 to Tn in the delay calculation registration module 201 based on the serial data signal SDA and the serial timing signal SCL.
  • Step 3 the timing controller 10 generates a start signal STV and transmits it to the level shifting chip 20 through the start signal line 30.
  • the low level of the start signal STV, the serial data signal SDA, and the serial timing signal SCL are both 0V, and the high level is 3.3V.
  • Step 4 The level shifting chip 20 triggers the output of at least four sets of timings based on the initial value STV of the start signal STV based on the initial value T1 to Tn in the delay calculation register 201.
  • the signals CKV1 CK CKVn are raised, and the voltages of the start signal STV and the at least four sets of timing signals CKV1 CK CKVn are boosted; and the boosted start signal STV and each set of timing signals are respectively transmitted to the GOA architecture through a signal line.
  • Liquid crystal panel 50 Liquid crystal panel 50.
  • the generation time of each set of timing signals CKVn is an initialization assignment Tn corresponding to the rising edge interval of the start signal STV.
  • the high level duration Tn+1 and the period time Tn+2 of the at least four sets of timing signals CKV1 CK CKVn are also determined by the initialization assignments in the delay calculation register module 201.
  • the level shifting chip 20 outputs four sets of timing signals CKV1 CKCKV4 as an example.
  • the level shifting chip 20 correctly recognizes the rising edge of the start signal STV to start the signal STV.
  • the rising edge is used as a reference to trigger the output of the four sets of timing signals CKV1 CK CKV4, and the voltages of the start signal STV and the four sets of timing signals CKV1 CK CKV4 are boosted.
  • the generation time of the first group of timing signals CKV1 is initialized with the rising edge of the start signal STV.
  • the time corresponding to the value T1 the generation time of the second group timing signal CKV2 and the rising edge interval of the start signal STV are initialized with the time corresponding to the value T2, and the generation time of the third group timing signal CKV3 and the rising edge of the start signal STV
  • the interval is initialized to the time corresponding to the value T3
  • the generation time of the fourth group of timing signals CKV4 and the rising edge of the start signal STV are initialized to the time corresponding to the value T4.
  • the high-level duration T5 and the cycle time T6 of the four sets of timing signals CKV1 CK CKV4 are also determined by the initialization assignment in the delay calculation register module 201, and the high-power is applied to the liquid crystal panels of different resolutions.
  • the flat duration T5 and the cycle time T6 can be set by different initialization assignments.
  • the low level of the start signal STV and the first, second, third, and fourth sets of timing signals CKV1, CKV2, CKV3, and CKV4 are both -6V, and the high voltage is high.
  • the average is 30V, which can be used to drive the TFTs in the GOA-structured liquid crystal panel 50 to realize progressive scanning.
  • only four sets of timing signals are taken as an example, but the present invention is not limited thereto, and can be applied to the case of more sets of timing signals.
  • the effect of reducing the total number of traces between the timing controller 10 and the level shifting chip 20, reducing the size of the circuit board PCBA, and reducing the production cost is more obvious.
  • the level shift circuit and the level shifting method for the GOA architecture liquid crystal panel of the present invention the delay calculation register module is set in the level shifting chip, and the timing signal line and the IIC bus pair timing controller are used. Communicate with a level shifting chip.
  • the timing controller initializes the delay calculation register module in the level shifting chip through the IIC bus, and sends a start signal to the level shifting chip through the initial signal line; the level shifting chip calculates the initialization in the register module according to the delay time.
  • the assignment is based on the start signal, triggering output of at least four sets of timing signals, and boosting the voltage of the start signal and at least four sets of timing signals to drive the GOA architecture liquid crystal panel, which can reduce the timing controller and level shifting
  • the number of pins between the chips reduces the package type of the timing controller and the level shifting chip, reduces the total number of traces between the timing controller and the level shifting chip, reduces the size of the circuit board PCBA, and reduces the production cost. To achieve a higher number of timing signals at lower cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种用于GOA架构液晶面板的电平移位电路及电平移位方法，在电平移位芯片(20)内设置延时计算寄存模块(201)，使用起始信号线(30)和IIC总线(40)对时序控制器(10)与电平移位芯片(20)进行通信连接。时序控制器(10)通过IIC总线(40)对延时计算寄存模块(201)进行初始化赋值(T1～Tn)，通过起始信号线(30)发送起始信号(STV)给电平移位芯片(20)；电平移位芯片(20)根据延时计算寄存模块(201)内的初始化赋值(T1～Tn)以起始信号(STV)为基准，触发输出至少四组时序信号(CKV1～CKVn)，并提升该起始信号(STV)及至少四组时序信号(CKV1～CKVn))的电压，以对GOA架构液晶面板(50)进行驱动，实现在较低的成本下产生较多数量的时序信号。

Description

用于GOA架构液晶面板的电平移位电路及电平移位方法 技术领域
本发明涉及显示技术领域，尤其涉及一种用于GOA架构液晶面板的电平移位电路及电平移位方法。
背景技术
主动矩阵式液晶显示器(Active Matrix Liquid Crystal Display，AMLCD)是目前最常用的显示装置，所述主动矩阵式液晶显示器包含多个像素，每个像素具有一个薄膜晶体管(Thin Film Transistor，TFT)，该TFT的栅极连接至沿水平方向延伸的扫描线，该TFT的漏极连接至沿垂直方向延伸的数据线，而该TFT的源极连接至对应的像素电极。如果在水平方向的某一扫描线上施加足够的正电压，则会使得连接在该条扫描线上的所有TFT打开，将数据线上所加载的数据信号电压写入像素电极中，从而显示画面。
一种类型的主动矩阵式液晶显示器的液晶面板采用GOA架构(Gate Drive On Array)即将栅极驱动器(Gate Drive IC)整合在薄膜晶体管阵列(Array)基板上，以实现逐行扫描对液晶面板进行驱动。相比于传统的通过COMS制程将集成电路(Integrated Circuit，IC)制作在液晶面板外的驱动方法，采用GOA架构可减少制程工序，降低成本，提高液晶显示面板的集成度，并有利于实现面板的超窄边框及薄型化。但采用GOA架构会使电路驱动板(PCBA)上多出一颗电平移位芯片(Level Shift IC)，将低压驱动信号升压至高压驱动信号，以驱动液晶面板中的TFT进行工作。
请参阅图1，现有的用于GOA架构液晶面板的电平移位电路通常包括：一设于电路驱动板PCBA上的时序控制器(TCON)100，该时序控制器100用于产生和发送起始信号STV、时序信号CKVn等控制信号，n为正整数；一设于电路驱动板PCBA上的电平移位芯片200，该电平移位芯片200用于提升由时序控制器100发送来的起始信号STV、及时序信号CKVn的电压。经电平移位芯片200升压后的起始信号STV、及时序信号CKVn对GOA架构液晶面板300中的TFT进行驱动。
为使GOA架构液晶面板300中的TFT能够正常的逐行打开，一般需要4组时序信号CKV1～CKV4或更多的时序信号才能实现逐行扫描的显示效果。每个控制信号都需要时序控制器100和电平移位芯片200有对应的引脚来进行通信连接，如图1所示，当有4组时序信号CKV1～CKV4及一 起始信号STV时，总共需要5对一一对应的引脚用于时序控制器100和电平移位芯片200的通信连接，以提升每一控制信号的电压。
如图2所示，时序控制器100产生起始信号STV，并以起始信号STV的上升沿为基准，分别间隔T1、T2、T3、及T4时间后依次产生时序信号CKV1、CKV2、CKV3、及CKV4。所述起始信号STV及时序信号CKV1～CKV4的低电平为0V，高电平为3.3V，高电平持续时间为T5，周期时间为T6。如图3所示，经电平移位芯片200升压后的起始信号STV、及时序信号CKV1～CKV4的低电平为-6V，高电平为30V，时序信号CKV1～CKV4相对起始信号STV上升沿的时间间隔、高电平持续时间、及周期时间均不变。
上述用于GOA架构液晶面板的电平移位电路虽然能够实现提升每一控制信号的电压来驱动液晶面板中的TFT，但是当所需的时序信号CKVn越来越多的时候，时序控制器100和电平移位芯片200之间所需要的引脚就会越来越多，而每多出一个引脚都有可能会使时序控制器100和电平移位芯片200的封装型号(package)变大，而封装型号的大小直接影响到IC的成本高低。同时，走线越多亦会使PCBA尺寸变大，进一步导致成本增高。因此，当所需的时序信号CKVn数量较多时，会造成IC的成本和PCBA的成本明显增高，不利于采用GOA架构降低成本的初衷。
发明内容
本发明的目的在于提供一种用于GOA架构液晶面板的电平移位电路，能够减少时序控制器与电平移位芯片之间的引脚数，减小时序控制器与电平移位芯片的封装型号，减少时序控制器与电平移位芯片之间的走线总数，减小电路驱动板尺寸，降低生产成本。
本发明的目的还在于提供一种用于GOA架构液晶面板的电平移位方法，能够产生较多数量的时序信号，同时能够减少时序控制器与电平移位芯片之间的引脚数，减小时序控制器与电平移位芯片的封装型号，减少时序控制器与电平移位芯片之间的走线总数，减小电路驱动板尺寸，降低生产成本。
为实现上述目的，本发明首先提供一种用于GOA架构液晶面板的电平移位电路，包括：一时序控制器及一电平移位芯片；
所述电平移位芯片内包括一延时计算寄存模块；
所述时序控制器通过起始信号线和IIC总线与电平移位芯片通信连接；
所述时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块 进行初始化赋值，通过起始信号线发送起始信号给电平移位芯片；
所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压；升压后的起始信号及每一组时序信号分别通过一信号线传输至GOA架构液晶面板。
所述IIC总线包括用于传输串行数据信号的串行数据信号线和用于传输串行时序信号的串行时序信号线。
所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号的上升沿为基准，触发输出至少四组时序信号。
每一组时序信号的产生时间与起始信号的上升沿间隔相应的一初始化赋值。
所述至少四组时序信号的高电平持续时间及周期时间亦由所述延时计算寄存模块内的初始化赋值确定。
本发明还提供一种用于GOA架构液晶面板的电平移位电路，包括：一时序控制器及一电平移位芯片；
所述电平移位芯片内包括一延时计算寄存模块；
所述时序控制器通过起始信号线和IIC总线与电平移位芯片通信连接；
所述时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值，通过起始信号线发送起始信号给电平移位芯片；
所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压；升压后的起始信号及每一组时序信号分别通过一信号线传输至GOA架构液晶面板；
其中，所述IIC总线包括用于传输串行数据信号的串行数据信号线和用于传输串行时序信号的串行时序信号线；
其中，所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号的上升沿为基准，触发输出至少四组时序信号。
本发明还提供一种用于GOA架构液晶面板的电平移位方法，包括如下步骤：
步骤1、提供一GOA架构液晶面板、及用于GOA架构液晶面板的电平移位电路；
所述用于GOA架构液晶面板的电平移位电路包括一时序控制器及一电平移位芯片；所述电平移位芯片内包括一延时计算寄存模块；所述时序控制器通过起始信号线和IIC总线与电平移位芯片通信连接；
步骤2、所述时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值；
步骤3、所述时序控制器产生起始信号并通过起始信号线发送给电平移位芯片；
步骤4、所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压；再将升压后的起始信号及每一组时序信号分别通过一信号线传输至GOA架构液晶面板。
所述IIC总线包括用于传输串行数据信号的串行数据信号线和用于传输串行时序信号的串行时序信号线。
所述步骤2中根据串行数据信号与串行时序信号确定延时计算寄存模块内的初始化赋值。
所述步骤4中电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号的上升沿为基准，触发输出至少四组时序信号；每一组时序信号的产生时间与起始信号的上升沿间隔相应的一初始化赋值。
所述步骤4中，所述至少四组时序信号的高电平持续时间及周期时间亦由所述延时计算寄存模块内的初始化赋值确定。
本发明的有益效果：本发明提供的一种用于GOA架构液晶面板的电平移位电路及电平移位方法，在电平移位芯片内设置延时计算寄存模块，使用起始信号线和IIC总线对时序控制器与电平移位芯片进行通信连接。时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值，通过起始信号线发送起始信号给电平移位芯片；电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压，以对GOA架构液晶面板进行驱动，能够减少时序控制器与电平移位芯片之间的引脚数，减小时序控制器与电平移位芯片的封装型号，减少时序控制器与电平移位芯片之间的走线总数，减小电路驱动板尺寸，降低生产成本，实现在较低的成本下产生较多数量的时序信号。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图1为现有的用于GOA架构液晶面板的电平移位电路的的示意图；
图2为图1所示电路在升压前的时序图；
图3为图1所示电路在升压后的时序图；
图4为本发明用于GOA架构液晶面板的电平移位电路的示意图；
图5为图4所示电路在升压前的时序图；
图6为图4所示电路在升压后的时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图4、图5、及图6，本发明提供一种用于GOA架构液晶面板的电平移位电路。该用于GOA架构液晶面板的电平移位电路包括：一时序控制器10及一电平移位芯片20，所述时序控制器10及一电平移位芯片20设于电路驱动板PCBA上。
所述电平移位芯片20内包括一延时计算寄存模块201。
所述时序控制器10通过起始信号线30和IIC总线40与电平移位芯片20通信连接。
所述IIC总线40包括用于传输串行数据信号SDA的串行数据信号线和用于传输串行时序信号SCL的串行时序信号线。
所述时序控制器用于通过IIC总线40对电平移位芯片20内的延时计算寄存模块201进行初始化赋值T1～Tn，n为正整数，通过起始信号线30发送起始信号STV给电平移位芯片20。
所述电平移位芯片20用于根据延时计算寄存模块201内的初始化赋值T1～Tn以起始信号STV为基准，触发输出至少四组时序信号CKV1～CKVn，并提升所述起始信号STV及至少四组时序信号CKV1～CKVn的电压；升压后的起始信号STV及每一组时序信号分别通过一信号线传输至GOA架构液晶面板50。
相比于现有的用于GOA架构液晶面板的电平移位电路，本发明的用于GOA架构液晶面板的电平移位电路能够减少时序控制器10与电平移位芯片20之间的引脚数，减小时序控制器10与电平移位芯片20的封装型号，减少时序控制器10与电平移位芯片20之间的走线总数，减小电路驱动板PCBA的尺寸，降低生产成本。
进一步地，所述电平移位芯片20根据延时计算寄存模块201内的初始化赋值T1～Tn以起始信号STV的上升沿为基准，触发输出至少四组时序信号CKV1～CKVn。
每一组时序信号CKVn的产生时间与起始信号STV的上升沿间隔相应的一初始化赋值Tn。
所述至少四组时序信号CKV1～CKVn的高电平持续时间Tn+1及周期时间Tn+2亦由所述延时计算寄存模块201内的初始化赋值确定。
具体地，以电平移位芯片20输出四组时序信号CKV1～CKV4为例，结合图4、图5，所述时序控制器10分别通过IIC总线40的串行数据信号线及串行时序信号线向电平移位芯片20内的延时计算寄存模块201发送串行数据信号SDA及串行时序信号SCL，用于确定对延时计算寄存模块201的初始化赋值T1～T4，通过起始信号线30发送起始信号STV给电平移位芯片20。所述起始信号STV，串行数据信号SDA、及串行时序信号SCL的低电平均为0V，高电平均为3.3V。
结合图4、图6，所述电平移位芯片20正确识别到起始信号STV的上升沿，以起始信号STV的上升沿为基准，触发输出四组时序信号CKV1～CKV4，并对所述起始信号STV及四组时序信号CKV1～CKV4的电压进行提升。第一组时序信号CKV1的产生时间与起始信号STV的上升沿间隔初始化赋值T1所对应的时间，第二组时序信号CKV2的产生时间与起始信号STV的上升沿间隔初始化赋值T2所对应的时间，第三组时序信号CKV3的产生时间与起始信号STV的上升沿间隔初始化赋值T3所对应的时间，第四组时序信号CKV4的产生时间与起始信号STV的上升沿间隔初始化赋值T4所对应的时间。另外，该四组时序信号CKV1～CKV4的高电平持续时间T5、与周期时间T6亦由所述延时计算寄存模块201内的初始化赋值确定，针对不同解析度的液晶面板，所述高电平持续时间T5和周期时间T6可以通过不同的初始化赋值来设定。经过电平移位芯片20做电压提升后，所述起始信号STV、及第一、第二、第三、第四组时序信号CKV1、CKV2、CKV3、CKV4的低电平均为-6V，高电平均为30V，能够用于驱动GOA架构液晶面板50中的TFT，实现逐行扫描。本实施例仅以四组时序信号为例进行说明，但本发明并不局限于此，还可以适用于更多组时序信号的情况。GOA架构液晶面板50所需的时序信号数量越多，本发明能够减少时序控制器10与电平移位芯片20之间的引脚数，减小时序控制器10与电平移位芯片20的封装型号，减少时序控制器10与电平移位芯片20之间的走线总数，减小电路驱动板PCBA的尺寸，降低生产成本的作用越明 显。
请同时参阅图4、图5、及图6，本发明还提供一种用于GOA架构液晶面板的电平移位方法，包括如下步骤：
步骤1、提供一GOA架构液晶面板50、及用于GOA架构液晶面板的电平移位电路。
所述用于GOA架构液晶面板的电平移位电路包括一时序控制器10及一电平移位芯片20，所述时序控制器10及一电平移位芯片20设于电路驱动板PCBA上。所述电平移位芯片20内包括一延时计算寄存模块201。所述时序控制器10通过起始信号线30和IIC总线40与电平移位芯片20通信连接。
其中，所述IIC总线40包括用于传输串行数据信号SDA的串行数据信号线和用于传输串行时序信号SCL的串行时序信号线。
步骤2、所述时序控制器10通过IIC总线40对电平移位芯片20内的延时计算寄存模块201进行初始化赋值T1～Tn，n为正整数。
具体地，该步骤2根据串行数据信号SDA与串行时序信号SCL确定延时计算寄存模块201内的初始化赋值T1～Tn。
步骤3、所述时序控制器10产生起始信号STV并通过起始信号线30发送给电平移位芯片20。
具体地，结合图4，图5，所述起始信号STV、串行数据信号SDA、及串行时序信号SCL的低电平均为0V，高电平均为3.3V。
步骤4、所述电平移位芯片20根据延时计算寄存模块201内的初始化赋值T1～Tn以起始信号STV为基准，优选以起始信号STV的上升沿为基准，触发输出至少四组时序信号CKV1～CKVn，并提升所述起始信号STV及至少四组时序信号CKV1～CKVn的电压；再将升压后的起始信号STV及每一组时序信号分别通过一信号线传输至GOA架构液晶面板50。
进一步地，在该步骤4中，每一组时序信号CKVn的产生时间与起始信号STV的上升沿间隔相应的一初始化赋值Tn。所述至少四组时序信号CKV1～CKVn的高电平持续时间Tn+1及周期时间Tn+2亦由所述延时计算寄存模块201内的初始化赋值确定。
具体地，以电平移位芯片20输出四组时序信号CKV1～CKV4为例，结合图4、图6，所述电平移位芯片20正确识别到起始信号STV的上升沿，以起始信号STV的上升沿为基准，触发输出四组时序信号CKV1～CKV4，并对所述起始信号STV及四组时序信号CKV1～CKV4的电压进行提升。第一组时序信号CKV1的产生时间与起始信号STV的上升沿间隔初始化赋 值T1所对应的时间，第二组时序信号CKV2的产生时间与起始信号STV的上升沿间隔初始化赋值T2所对应的时间，第三组时序信号CKV3的产生时间与起始信号STV的上升沿间隔初始化赋值T3所对应的时间，第四组时序信号CKV4的产生时间与起始信号STV的上升沿间隔初始化赋值T4所对应的时间。另外，该四组时序信号CKV1～CKV4的高电平持续时间T5、与周期时间T6亦由所述延时计算寄存模块201内的初始化赋值确定，针对不同解析度的液晶面板，所述高电平持续时间T5和周期时间T6可以通过不同的初始化赋值来设定。经过电平移位芯片20做电压提升后，所述起始信号STV、及第一、第二、第三、第四组时序信号CKV1、CKV2、CKV3、CKV4的低电平均为-6V，高电平均为30V，能够用于驱动GOA架构液晶面板50中的TFT，实现逐行扫描。本实施例仅以四组时序信号为例进行说明，但本发明并不局限于此，还可以适用于更多组时序信号的情况。GOA架构液晶面板50所需的时序信号数量越多，本发明能够减少时序控制器10与电平移位芯片20之间的引脚数，减小时序控制器10与电平移位芯片20的封装型号，减少时序控制器10与电平移位芯片20之间的走线总数，减小电路驱动板PCBA的尺寸，降低生产成本的作用越明显。
综上所述，本发明的用于GOA架构液晶面板的电平移位电路及电平移位方法，在电平移位芯片内设置延时计算寄存模块，使用起始信号线和IIC总线对时序控制器与电平移位芯片进行通信连接。时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值，通过起始信号线发送起始信号给电平移位芯片；电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压，以对GOA架构液晶面板进行驱动，能够减少时序控制器与电平移位芯片之间的引脚数，减小时序控制器与电平移位芯片的封装型号，减少时序控制器与电平移位芯片之间的走线总数，减小电路驱动板PCBA的尺寸，降低生产成本，实现在较低的成本下产生较多数量的时序信号。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种用于GOA架构液晶面板的电平移位电路，包括：一时序控制器及一电平移位芯片；
    所述电平移位芯片内包括一延时计算寄存模块；
    所述时序控制器通过起始信号线和IIC总线与电平移位芯片通信连接；
    所述时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值，通过起始信号线发送起始信号给电平移位芯片；
    所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压；升压后的起始信号及每一组时序信号分别通过一信号线传输至GOA架构液晶面板。
  2. 如权利要求1所述的用于GOA架构液晶面板的电平移位电路，其中，所述IIC总线包括用于传输串行数据信号的串行数据信号线和用于传输串行时序信号的串行时序信号线。
  3. 如权利要求1所述的用于GOA架构液晶面板的电平移位电路，其中，所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号的上升沿为基准，触发输出至少四组时序信号。
  4. 如权利要求3所述的用于GOA架构液晶面板的电平移位电路，其中，每一组时序信号的产生时间与起始信号的上升沿间隔相应的一初始化赋值。
  5. 如权利要求4所述的用于GOA架构液晶面板电的平移位电路，其中，所述至少四组时序信号的高电平持续时间及周期时间亦由所述延时计算寄存模块内的初始化赋值确定。
  6. 一种用于GOA架构液晶面板的电平移位电路，包括：一时序控制器及一电平移位芯片；
    所述电平移位芯片内包括一延时计算寄存模块；
    所述时序控制器通过起始信号线和IIC总线与电平移位芯片通信连接；
    所述时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值，通过起始信号线发送起始信号给电平移位芯片；
    所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压；升压后的起始信号及每一组时序信号分别通过一信号线传 输至GOA架构液晶面板；
    其中，所述IIC总线包括用于传输串行数据信号的串行数据信号线和用于传输串行时序信号的串行时序信号线；
    其中，所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号的上升沿为基准，触发输出至少四组时序信号。
  7. 如权利要求6所述的用于GOA架构液晶面板的电平移位电路，其中，每一组时序信号的产生时间与起始信号的上升沿间隔相应的一初始化赋值。
  8. 如权利要求7所述的用于GOA架构液晶面板的电平移位电路，其中，所述至少四组时序信号的高电平持续时间及周期时间亦由所述延时计算寄存模块内的初始化赋值确定。
  9. 一种用于GOA架构液晶面板的电平移位方法，包括如下步骤：
    步骤1、提供一GOA架构液晶面板、及用于GOA架构液晶面板的电平移位电路；
    所述用于GOA架构液晶面板的电平移位电路包括一时序控制器及一电平移位芯片；所述电平移位芯片内包括一延时计算寄存模块；所述时序控制器通过起始信号线和IIC总线与电平移位芯片通信连接；
    步骤2、所述时序控制器通过IIC总线对电平移位芯片内的延时计算寄存模块进行初始化赋值；
    步骤3、所述时序控制器产生起始信号并通过起始信号线发送给电平移位芯片；
    步骤4、所述电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号为基准，触发输出至少四组时序信号，并提升所述起始信号及至少四组时序信号的电压；再将升压后的起始信号及每一组时序信号分别通过一信号线传输至GOA架构液晶面板。
  10. 如权利要求9所述的用于GOA架构液晶面板的电平移位方法，其中，所述IIC总线包括用于传输串行数据信号的串行数据信号线和用于传输串行时序信号的串行时序信号线。
  11. 如权利要求10所述的用于GOA架构液晶面板的电平移位方法，其中，所述步骤2中根据串行数据信号与串行时序信号确定延时计算寄存模块内的初始化赋值。
  12. 如权利要求9所述的用于GOA架构液晶面板的电平移位方法，其中，所述步骤4中电平移位芯片根据延时计算寄存模块内的初始化赋值以起始信号的上升沿为基准，触发输出至少四组时序信号；每一组时序信号 的产生时间与起始信号的上升沿间隔相应的一初始化赋值。
  13. 如权利要求12所述的用于GOA架构液晶面板的电平移位方法，其中，所述步骤4中，所述至少四组时序信号的高电平持续时间及周期时间亦由所述延时计算寄存模块内的初始化赋值确定。
PCT/CN2015/075694 2015-03-03 2015-04-01 用于goa架构液晶面板的电平移位电路及电平移位方法 WO2016138686A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/758,803 US20160335968A1 (en) 2015-03-03 2015-04-01 Level shift circuit and level shift method for goa structure liquid crystal panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510094520.8 2015-03-03
CN201510094520.8A CN104680991B (zh) 2015-03-03 2015-03-03 用于goa架构液晶面板的电平移位电路及电平移位方法

Publications (1)

Publication Number Publication Date
WO2016138686A1 true WO2016138686A1 (zh) 2016-09-09

Family

ID=53315949

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/075694 WO2016138686A1 (zh) 2015-03-03 2015-04-01 用于goa架构液晶面板的电平移位电路及电平移位方法

Country Status (3)

Country Link
US (1) US20160335968A1 (zh)
CN (1) CN104680991B (zh)
WO (1) WO2016138686A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934012B (zh) * 2015-07-20 2018-01-09 深圳市华星光电技术有限公司 一种多时序生成电路及液晶显示器
CN105390106B (zh) * 2015-12-07 2018-12-21 深圳市华星光电技术有限公司 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法
CN106448580A (zh) 2016-05-25 2017-02-22 深圳市华星光电技术有限公司 电平移位电路及具有该电平移位电路的显示面板
CN105810169A (zh) * 2016-05-25 2016-07-27 深圳市华星光电技术有限公司 液晶显示器的驱动系统及驱动方法
CN106297671B (zh) * 2016-10-10 2020-02-07 深圳市华星光电技术有限公司 显示面板及其扫描驱动电路
CN107481682A (zh) * 2017-07-21 2017-12-15 惠科股份有限公司 显示面板的驱动方法及驱动装置
CN107516500B (zh) * 2017-09-28 2019-12-10 深圳市华星光电技术有限公司 Goa电路的驱动方法及驱动装置
CN107689205B (zh) * 2017-10-25 2019-12-24 深圳市华星光电半导体显示技术有限公司 Goa电路
KR102396469B1 (ko) * 2017-12-22 2022-05-10 엘지디스플레이 주식회사 디스플레이 장치
CN108986757B (zh) 2018-07-17 2019-12-24 深圳市华星光电技术有限公司 Goa电路的驱动方法及goa电路的驱动装置
CN109166556A (zh) * 2018-10-29 2019-01-08 惠科股份有限公司 信号控制电路及包含信号控制电路的显示装置
CN109285525B (zh) * 2018-12-11 2020-12-22 惠科股份有限公司 电压信号产生电路、方法及显示装置
CN109300448B (zh) * 2018-12-18 2020-06-02 深圳市华星光电半导体显示技术有限公司 电平转换模块及信号转换方法
CN110085188B (zh) * 2019-05-05 2021-10-08 京东方科技集团股份有限公司 显示面板的电平转换装置及其控制方法和显示面板
CN110277984B (zh) * 2019-05-31 2021-08-03 Tcl华星光电技术有限公司 电平移位电路及时钟讯号电路
CN110930924A (zh) * 2019-11-28 2020-03-27 Tcl华星光电技术有限公司 驱动电路
CN111681621B (zh) * 2020-06-04 2022-04-08 Tcl华星光电技术有限公司 一种时序控制器与电源管理芯片的通讯方法及驱动结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100978608B1 (ko) * 2010-01-08 2010-08-27 주식회사 실리콘마이터스 표시 장치 및 그 주사 신호 생성 방법
CN102479494A (zh) * 2010-11-26 2012-05-30 乐金显示有限公司 液晶显示装置
CN103065599A (zh) * 2013-01-06 2013-04-24 友达光电股份有限公司 一种可消除关机残影的液晶显示器
CN103178829A (zh) * 2011-12-20 2013-06-26 中芯国际集成电路制造(上海)有限公司 电平移位电路
KR20130091600A (ko) * 2012-02-08 2013-08-19 삼성디스플레이 주식회사 액정 표시 장치
CN104204992A (zh) * 2012-03-29 2014-12-10 高通股份有限公司 具有内置电平移位器及可编程上升边缘和脉冲宽度的脉冲时钟产生逻辑

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050076924A (ko) * 2004-01-26 2005-07-29 삼성전자주식회사 양방향 통신이 가능한 ｉ2ｃ 통신시스템 및 그 방법
JP4654923B2 (ja) * 2006-01-26 2011-03-23 カシオ計算機株式会社 シフトレジスタ回路、及び表示駆動装置
US7737740B2 (en) * 2007-04-26 2010-06-15 Freescale Semiconductor, Inc. Integrated circuit with a programmable delay and a method thereof
CN102402957B (zh) * 2011-11-15 2014-01-22 深圳市华星光电技术有限公司 Lcd数据驱动ic输出补偿电路及补偿方法
CN103489425B (zh) * 2013-10-12 2015-11-25 合肥京东方光电科技有限公司 电平转换电路、阵列基板及显示装置
CN203982752U (zh) * 2014-06-18 2014-12-03 京东方科技集团股份有限公司 栅极驱动电路、阵列基板及显示装置
CN104183210B (zh) * 2014-09-17 2016-08-17 厦门天马微电子有限公司 一种栅极驱动电路及其驱动方法及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100978608B1 (ko) * 2010-01-08 2010-08-27 주식회사 실리콘마이터스 표시 장치 및 그 주사 신호 생성 방법
CN102479494A (zh) * 2010-11-26 2012-05-30 乐金显示有限公司 液晶显示装置
CN103178829A (zh) * 2011-12-20 2013-06-26 中芯国际集成电路制造(上海)有限公司 电平移位电路
KR20130091600A (ko) * 2012-02-08 2013-08-19 삼성디스플레이 주식회사 액정 표시 장치
CN104204992A (zh) * 2012-03-29 2014-12-10 高通股份有限公司 具有内置电平移位器及可编程上升边缘和脉冲宽度的脉冲时钟产生逻辑
CN103065599A (zh) * 2013-01-06 2013-04-24 友达光电股份有限公司 一种可消除关机残影的液晶显示器

Also Published As

Publication number Publication date
CN104680991B (zh) 2017-03-08
US20160335968A1 (en) 2016-11-17
CN104680991A (zh) 2015-06-03

Similar Documents

Publication Publication Date Title
WO2016138686A1 (zh) 用于goa架构液晶面板的电平移位电路及电平移位方法
US9576524B2 (en) Shift register unit, shift register circuit, array substrate and display device
US8749469B2 (en) Display device for reducing parasitic capacitance with a dummy scan line
TWI419127B (zh) 液晶顯示裝置
TWI690911B (zh) 一種顯示接面裝置
US8223097B2 (en) Pixel array structure, flat display panel and method for driving flat display panel thereof
US20120068994A1 (en) Display device
US8890785B2 (en) Display panel and gate driving circuit thereof
KR102202128B1 (ko) 액정표시장치와 그 구동방법
KR101661026B1 (ko) 표시장치
US9379697B2 (en) Gate driver circuit and display apparatus having the same
US8253651B2 (en) Display apparatus and method for driving display panel thereof
JP2015018064A (ja) 表示装置
US20110063278A1 (en) Tft-lcd driving circuit
US10319322B2 (en) Gate driver, display panel and display use the same
US20170178560A1 (en) Gate driving circuit and display device using the same
JP2008107579A (ja) 表示装置
CN110796992B (zh) 显示面板及显示装置
EP3040977B1 (en) Display device
WO2017201820A1 (zh) 电平移位电路及具有该电平移位电路的显示面板
JP2012098608A (ja) マトリクス表示装置およびその駆動方法
CN107731192B (zh) 液晶显示器的驱动系统及液晶显示器的驱动方法
KR102540315B1 (ko) 액정 표시 장치
US10304406B2 (en) Display apparatus with reduced flash noise, and a method of driving the display apparatus
KR101181964B1 (ko) 액정 표시 장치 및 그의 구동 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14758803

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15883743

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15883743

Country of ref document: EP

Kind code of ref document: A1