WO2017197685A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2017197685A1
WO2017197685A1 PCT/CN2016/085645 CN2016085645W WO2017197685A1 WO 2017197685 A1 WO2017197685 A1 WO 2017197685A1 CN 2016085645 W CN2016085645 W CN 2016085645W WO 2017197685 A1 WO2017197685 A1 WO 2017197685A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
level
gate
electrically connected
Prior art date
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Ceased
Application number
PCT/CN2016/085645
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English (en)
French (fr)
Inventor
龚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/124,302 priority Critical patent/US10446099B2/en
Publication of WO2017197685A1 publication Critical patent/WO2017197685A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a GOA circuit and a liquid crystal display.
  • Array substrate row driver (GOA, Gate Driver On Array or Gate On Array)
  • the circuit is an existing thin film transistor display device (TFT-LCD) array (Array) process to gate the gate (Gate)
  • TFT-LCD thin film transistor display device
  • Array array
  • Gate gate
  • the GOA circuit uses the level transfer signal to directly turn on the GOA circuit of the next stage.
  • the load caused by the level transfer signal is large, so the delay is easy to occur when the process or device characteristics are deviated, so that the delay of the level transfer signal is sequentially transmitted through the stage transfer, thereby affecting the work of the next level GOA circuit. And the effect of delays in the process of passing in turn will gradually increase.
  • the invention provides a GOA circuit, which can effectively solve the technical problem in the prior art that the load of the level-transmitted signal is large and the delay phenomenon is relatively easy, and the influence of the delay is gradually increased in the stage transmission process.
  • the present invention provides a GOA circuit comprising a cascaded multi-level GOA unit circuit, each stage GOA unit circuit comprising:
  • a forward-backward scanning control module configured to pass the level-transmitted signal of the upper-level GOA unit circuit to the level-transmitting signal enhancement module;
  • a step signal enhancement module for controlling the first constant voltage bit or the second constant voltage bit to be input to the input end of the level signal output module by the control of the level transmission signal of the upper stage GOA unit circuit;
  • a constant piezoelectric potential is a constant voltage low potential, the second constant piezoelectric potential is a constant voltage high potential;
  • a level value of the second constant piezoelectric potential is smaller than a level value of the first constant piezoelectric potential
  • the input end of the forward-reverse scan control module is electrically connected to the output end of the upper-level GOA unit circuit, and the output end of the forward-reverse scan control module is electrically connected to the control end of the level-transmitted signal enhancement module.
  • the first input end of the level signal enhancement module is connected to the first constant voltage position, the second input end is connected to the second constant voltage position, and the output end of the level transmission signal enhancement module is electrically connected At the input of the level signal output module.
  • the level signal enhancement module includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor;
  • a gate of the first thin film transistor is electrically connected to an output end of the forward and reverse scan control module, a source is connected to the first constant piezoelectric position, and a drain is electrically connected to the second thin film transistor.
  • a gate and a source of the second thin film transistor are connected to the second constant piezoelectric position
  • a gate of the third thin film transistor is electrically connected to a drain of the second thin film transistor, a source is connected to the first constant piezoelectric potential, and a drain is electrically connected to a drain of the fourth thin film transistor ;
  • a gate of the fourth thin film transistor is electrically connected to a gate of the first thin film transistor, a source is connected to the second constant voltage bit, and a drain is electrically connected to an input of the level signal output module end.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all N-type thin film transistors.
  • the forward and reverse scan control module includes a fifth thin film transistor and a sixth thin film transistor;
  • the source of the fifth thin film transistor is connected to the pass signal of the N-1th stage GOA unit circuit, the gate is connected to the forward scan signal, the drain is connected to the gate of the first thin film transistor, and the fourth a gate connection of the thin film transistor;
  • the source of the sixth thin film transistor is connected to the pass signal of the N+1th stage GOA unit circuit, the gate is connected to the reverse scan signal, the drain is connected to the gate of the first thin film transistor, and the fourth The gate of the thin film transistor is connected.
  • the source of the fifth thin film transistor is connected to the start signal of the circuit.
  • the source of the sixth thin film transistor is connected to the start signal of the circuit.
  • the present invention also provides a GOA circuit comprising cascaded multi-level GOA unit circuits, each stage GOA unit circuit comprising:
  • a forward-backward scanning control module configured to pass the level-transmitted signal of the upper-level GOA unit circuit to the level-transmitting signal enhancement module;
  • a step signal enhancement module for controlling the first constant voltage bit or the second constant voltage bit to be input to the input end of the level signal output module by the control of the level transmission signal of the upper stage GOA unit circuit;
  • the input end of the forward-reverse scan control module is electrically connected to the output end of the upper-level GOA unit circuit, and the output end of the forward-reverse scan control module is electrically connected to the control end of the level-transmitted signal enhancement module.
  • the first input end of the level signal enhancement module is connected to the first constant voltage position, the second input end is connected to the second constant voltage position, and the output end of the level transmission signal enhancement module is electrically connected At the input of the level signal output module.
  • the first constant piezoelectric potential is a constant voltage low potential
  • the second constant piezoelectric potential is a constant voltage high potential
  • the level value of the second constant voltage bit is smaller than the level value of the first constant voltage bit.
  • the level signal enhancement module includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor;
  • a gate of the first thin film transistor is electrically connected to an output end of the forward and reverse scan control module, a source is connected to the first constant piezoelectric position, and a drain is electrically connected to the second thin film transistor.
  • a gate and a source of the second thin film transistor are connected to the second constant piezoelectric position
  • a gate of the third thin film transistor is electrically connected to a drain of the second thin film transistor, a source is connected to the first constant piezoelectric potential, and a drain is electrically connected to a drain of the fourth thin film transistor ;
  • a gate of the fourth thin film transistor is electrically connected to a gate of the first thin film transistor, a source is connected to the second constant voltage bit, and a drain is electrically connected to an input of the level signal output module end.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all N-type thin film transistors.
  • the forward and reverse scan control module includes a fifth thin film transistor and a sixth thin film transistor;
  • the source of the fifth thin film transistor is connected to the pass signal of the N-1th stage GOA unit circuit, the gate is connected to the forward scan signal, the drain is connected to the gate of the first thin film transistor, and the fourth a gate connection of the thin film transistor;
  • the source of the sixth thin film transistor is connected to the pass signal of the N+1th stage GOA unit circuit, the gate is connected to the reverse scan signal, the drain is connected to the gate of the first thin film transistor, and the fourth The gate of the thin film transistor is connected.
  • the source of the fifth thin film transistor is connected to the start signal of the circuit.
  • the source of the sixth thin film transistor is connected to the start signal of the circuit.
  • the level signal output module includes an output unit, an output pull-down unit, a node input unit, a node control unit, a voltage stabilization unit, and a first capacitor;
  • the output unit includes a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the first node, the source is connected to the second clock signal, and the drain is electrically connected to the Nth stage GOA unit circuit. And a second capacitor, one end of the second capacitor is electrically connected to the first node, and the other end is electrically connected to an output end of the Nth stage GOA unit circuit;
  • the voltage stabilizing unit includes an eighth thin film transistor, a gate of the eighth thin film transistor is connected to the second constant voltage bit, a source is electrically connected to the third node, and a drain is electrically connected to the first node;
  • the output pull-down unit includes a fourteenth thin film transistor, a gate of the fourteenth thin film transistor is electrically connected to the second node, a source is connected to the first constant piezoelectric position, and a drain is electrically connected to the An output of the Nth stage GOA unit circuit;
  • the node input unit includes a seventh thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor;
  • the seventh thin film transistor source is electrically connected to the drain of the third thin film transistor and the fourth thin film a drain of the transistor, a gate of the seventh thin film transistor, a source of the twelfth thin film transistor, and a gate of the thirteenth thin film transistor are connected to the first clock signal, the seventh film a drain of the transistor and a gate of the twelfth thin film transistor are electrically connected to the third node, and a drain of the twelfth thin film transistor and a drain of the thirteenth thin film transistor are electrically connected to The second node, the source of the thirteenth thin film transistor is connected to the second constant piezoelectric position;
  • the node control unit includes a tenth thin film transistor and an eleventh thin film transistor; a gate of the eleventh thin film transistor is electrically connected to the second node, and a source is connected to the first constant voltage bit, and the drain
  • the gate of the tenth thin film transistor is electrically connected to the source of the tenth thin film transistor; the gate of the tenth thin film transistor is connected to the second clock signal, and the drain is electrically connected to the third node.
  • a liquid crystal display comprising a GOA circuit comprising cascaded multi-level GOA unit circuits, each stage GOA unit circuit comprising:
  • a forward-backward scanning control module configured to pass the level-transmitted signal of the upper-level GOA unit circuit to the level-transmitting signal enhancement module;
  • a step signal enhancement module for controlling the first constant voltage bit or the second constant voltage bit to be input to the input end of the level signal output module by the control of the level transmission signal of the upper stage GOA unit circuit;
  • the input end of the forward-reverse scan control module is electrically connected to the output end of the upper-level GOA unit circuit, and the output end of the forward-reverse scan control module is electrically connected to the control end of the level-transmitted signal enhancement module.
  • the first input end of the level signal enhancement module is connected to the first constant voltage position, the second input end is connected to the second constant voltage position, and the output end of the level transmission signal enhancement module is electrically connected At the input of the level signal output module.
  • the first constant piezoelectric potential is a constant voltage low potential
  • the second constant piezoelectric potential is a constant voltage high potential
  • the level value of the second constant voltage bit is smaller than the level value of the first constant voltage bit.
  • the level signal enhancement module includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor;
  • a gate of the first thin film transistor is electrically connected to an output end of the forward and reverse scan control module, a source is connected to the first constant piezoelectric position, and a drain is electrically connected to the second thin film transistor.
  • a gate and a source of the second thin film transistor are connected to the second constant piezoelectric position
  • a gate of the third thin film transistor is electrically connected to a drain of the second thin film transistor, a source is connected to the first constant piezoelectric potential, and a drain is electrically connected to a drain of the fourth thin film transistor ;
  • a gate of the fourth thin film transistor is electrically connected to a gate of the first thin film transistor, a source is connected to the second constant voltage bit, and a drain is electrically connected to an input of the level signal output module end.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all N-type thin film transistors.
  • the GOA circuit and the liquid crystal display provided by the invention provide a first-level signal enhancement module between the forward-reverse scanning control module and the level-transmitting signal output module, so that the level-transmitted signal passes through the level-transmitted signal enhancement module.
  • the delay will be reduced and the driving capability will be improved, so that the effect of the delay of the level-transmitted signal on the next-level GOA unit circuit can be effectively reduced.
  • FIG. 1 is a circuit diagram of an Nth stage GOA unit circuit of a GOA circuit of the present invention
  • FIG. 2 is a circuit diagram of a first stage GOA unit circuit of the GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a final stage GOA unit circuit of the GOA circuit of the present invention.
  • FIG. 4 is a waveform diagram of an input signal and a key node of the GOA circuit of the present invention.
  • FIG. 1 is a circuit diagram of an Nth stage GOA unit circuit of a GOA circuit of the present invention
  • the GOA circuit of the present invention includes: a cascaded multi-level GOA unit circuit, each stage of the GOA unit circuit includes: a forward and reverse scan control module 100, a level signal enhancement module 200, and a level signal output module 300;
  • N be a positive integer, in addition to the first stage GOA unit circuit and the last stage GOA unit circuit, in the Nth stage GOA unit circuit:
  • the input end of the forward-reverse scan control module 100 is electrically connected to the output end of the upper-level GOA unit circuit, and the output end of the forward-reverse scan control module 100 is electrically connected to the control end of the level-transmitted signal enhancement module. For transmitting the level-transmitted signal of the upper-level GOA unit circuit to the level-pass signal enhancement module 200;
  • the first input end of the level signal enhancement module 200 is connected to the first constant voltage position, the second input end is connected to the second constant voltage position, and the output end of the level signal enhancement module 200 is electrically connected to the
  • the input end of the level signal output module 300 is configured to output the first constant voltage bit or the second constant voltage bit to the level transmission signal by the control of the level transmission signal of the upper stage GOA unit circuit The input of the output module 300.
  • the first constant piezoelectric potential is a constant voltage low potential VGL
  • the second constant piezoelectric potential is a constant voltage high potential VGH.
  • the level value of the second constant voltage bit is smaller than the level value of the first constant voltage bit.
  • the level signal enhancement module 200 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4;
  • the gate of the first thin film transistor T1 is electrically connected to the output end of the forward and reverse scan control module 100, the source is connected to the first constant piezoelectric position, and the drain is electrically connected to the second thin film transistor T2. Drain
  • the gate and the source of the second thin film transistor T2 are connected to the second constant piezoelectric position
  • the gate of the third thin film transistor T3 is electrically connected to the drain of the second thin film transistor T2, the source is connected to the first constant piezoelectric position, and the drain is electrically connected to the fourth thin film transistor T4. Drain
  • the gate of the fourth thin film transistor T4 is electrically connected to the gate of the first thin film transistor T1, the source is connected to the second constant piezoelectric potential, and the drain is electrically connected to the level signal output module. 300 input.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are all N-type thin film transistors.
  • the forward and reverse scan control module includes a fifth thin film transistor T5 and a sixth thin film transistor T6;
  • the source of the fifth thin film transistor T5 is connected to the pass signal of the N-1th stage GOA unit, the gate is connected to the forward scan signal U2D, the drain is connected to the gate of the first thin film transistor T1, and the gate a gate connection of the fourth thin film transistor T4;
  • the source of the sixth thin film transistor T6 is connected to the pass signal of the N+1th GOA unit, the gate is connected to the reverse scan signal D2U, the drain is connected to the gate of the first thin film transistor T1, and the gate The gate of the fourth thin film transistor T4 is connected.
  • the forward scan signal U2D when the forward scan is performed, the forward scan signal U2D is at a high potential, and the reverse scan signal D2U is at a low potential; When scanning, the forward scan signal U2D is at a low potential, and the reverse scan signal D2U is at a high potential.
  • the forward scan signal U2D when the forward scan is performed, the forward scan signal U2D is at a low potential, and the reverse scan signal D2U is at a high potential; When scanning, the forward scan signal U2D is at a high potential, and the reverse scan signal D2U is at a low potential.
  • the level signal output module 300 includes an output unit 301, an output pull-down unit 302, a node input unit 303, a node control unit 304, a voltage stabilization unit 305, and a first capacitor C1;
  • the output unit 301 includes a ninth thin film transistor T9.
  • the gate of the ninth thin film transistor T9 is electrically connected to the first node Q(n), the source is connected to the second clock signal CK2, and the drain is electrically connected to the drain.
  • the voltage stabilizing unit 305 includes an eighth thin film transistor T8.
  • the gate of the eighth thin film transistor T8 is connected to the second constant voltage, and the source is electrically connected to the third node A(n). Connected to the first node Q(n);
  • the output pull-down unit 302 includes a fourteenth thin film transistor T14.
  • the gate of the fourteenth thin film transistor T14 is electrically connected to the second node P(n), and the source is connected to the first constant voltage bit. Very electrically connected to the output terminal G(n) of the Nth stage GOA unit circuit;
  • the node input unit includes a seventh thin film transistor T7, a twelfth thin film transistor T12, and a thirteenth thin film transistor T13; the seventh thin film transistor T7 is electrically connected to the drain of the third thin film transistor T3 and a drain of the fourth thin film transistor T4, a gate of the seventh thin film transistor T7, a source of the twelfth thin film transistor T12, and a gate of the thirteenth thin film transistor T13 are connected to the first a clock signal CK1, a drain of the seventh thin film transistor T7 and a gate of the twelfth thin film transistor T12 are electrically connected to the third node A(n), and the twelfth thin film transistor T12 The drain and the drain of the thirteenth thin film transistor T13 are electrically connected to the second node P(n), and the source of the thirteenth thin film transistor T13 is connected to the second constant voltage;
  • the node control unit 304 includes a tenth thin film transistor T10 and an eleventh thin film transistor T11; a gate of the eleventh thin film transistor T11 is electrically connected to the second node P(n), and the source access station a first constant piezoelectric position, a drain electrically connected to a source of the tenth thin film transistor T10; a gate of the tenth thin film transistor T10 is connected to the second clock signal CK2, and a drain is electrically connected to The third node A(n).
  • the first clock signal CK1 is opposite in phase to the second clock signal CK2.
  • the source of the fifth thin film transistor T5 is connected to the start signal STV of the circuit, the gate is connected to the forward scan signal U2D, and the drain and the drain are connected.
  • the gate of the first thin film transistor T1 and the gate of the fourth thin film transistor T4 are connected.
  • the source signal of the sixth thin film transistor T6 is connected to the start signal STV, the gate is connected to the reverse scan signal D2U, and the drain is connected to the first film.
  • the gate of the transistor T1 is connected to the gate of the fourth thin film transistor T4.
  • the thin film transistors shown in the figure are all N-type thin film transistors.
  • the working process of the GOA circuit of the present invention is: starting the first stage from the starting signal STV of the circuit.
  • the GOA circuit is sequentially driven by scanning. Scanning drive to the Nth stage GOA unit circuit, the stage pass signal G(n-1) of the upper N-1th stage GOA unit circuit is high, the forward scan signal is high, and the reverse scan signal is low
  • the fifth thin film transistor T5 is turned on, the sixth thin film transistor T6 is turned off, and the level transfer signal G(n-1) is transmitted to the level transfer signal enhancement module.
  • the first thin film transistor T1 and the second thin film transistor T2 are turned on, because the first constant piezoelectric potential is a constant voltage low potential, the second constant piezoelectric potential is a constant voltage high potential, and the first The level value of the second constant piezoelectric level is smaller than the level value of the first constant piezoelectric level, so that point C is low at this time, so that the third thin film transistor T3 is turned off, and the fourth thin film transistor T4 is turned on, thereby transmitting the signal.
  • the output terminal B of the enhancement module is pulled up to a high potential by the second constant piezoelectric position; when the level transmission signal G(n-1) of the upper N-1th stage GOA unit circuit is low, the fourth thin film transistor T4 is disconnected, since the second thin film transistor T2 is always turned on by the second constant piezoelectric position, so the point C is high, and the third thin film transistor T3 is turned on, and the output terminal B of the level signal enhancement module is firstly constant.
  • the piezoelectric position is pulled low to low.
  • the level-transmitted signal enhancement module 200 uses the level-transmitted signal of the upper-level GOA unit circuit as a control signal, thereby transmitting the constant-voltage bit to the level-transmitted signal output module 300, thereby achieving a signal enhancement effect.
  • the seventh thin film transistor T7 and the eighth thin film transistor T8 are turned on, and the first node Q(n) is raised to a high level.
  • the first clock signal CK1 is at a low potential, and when the second clock signal CK2 is at a high potential, the seventh thin film transistor T7 is turned off, and the first node Q(n) is maintained at a high potential through the capacitor C2, so that the ninth thin film transistor T9
  • the first clock signal CK1 is low and the second clock signal CK2 is high
  • the thirteenth thin film transistor T13 is turned on, and the first clock signal CK1 pulls P(n) low, so that the fourteenth thin film transistor T14 Disconnected;
  • the source of the ninth thin film transistor T9 is connected to the second clock signal CK2, so that the output terminal G(n) of the Nth stage GOA unit circuit is raised to a high potential by the second clock signal CK2.
  • the eleventh thin film transistor T11, the tenth thin film transistor T10, and the eighth thin film transistor T8 are turned on, and the first node Q(n) is subjected to a constant voltage. Low potential pull low.
  • the GOA circuit of the present invention has a first-stage signal enhancement module between the forward-reverse scan control module and the level-transmitted signal output module, so that the delay of the level-transmitted signal after the level-transmitted signal enhancement module is reduced, and the drive is driven.
  • the ability will also be improved, which can effectively reduce the impact of the delay of the level signal on the next level of GOA unit circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种GOA电路及液晶显示器，在第N级GOA单元电路中，增设一级传信号增强模块（200），该级传信号增强模块（200）的第一输入端接入第一恒压电位（VGL），第二输入端接入第二恒压电位（VGH），该级传信号增强模块（200）的输出端电性连接于该级传信号输出模块（300）的输入端，用于受上一级GOA单元电路的该级传信号的控制将该第一恒压电位（VGL）或该第二恒压电位（VGH）输出至该级传信号输出模块（300）的输入端。

Description

一种GOA电路及液晶显示器 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种GOA电路及液晶显示器。
 背景技术
阵列基板行驱动 (GOA，Gate Driver On Array 或 Gate On Array) 电路，是利用现有薄膜晶体管显示装置 (TFT-LCD) 阵列 (Array) 制程将栅线 (Gate) 行扫描驱动信号电路制作在阵列基板上，以实现对栅线逐行扫描的驱动方式的一项技术。其与传统的柔性电路板 (COF) 和玻璃电路板 (COG) 工艺相比，不仅节省了制作成本，而且还可以省去栅极方向绑定 (Bonding) 的工艺，对提升产能极为有利，并提高了显示装置的集成度。
目前大部分的 GOA电路都使用级传信号直接开启下一级的GOA电路。但是，由级传信号挂的负载较大，所以在工艺或器件特性偏差时很容易出现延迟，这样通过级传就会将级传信号的延迟依次传递下去，从而影响下一级GOA电路的工作，而在依次传递的过程中延迟的影响也会逐渐加大。
 技术问题
本发明提供一种GOA电路，可以有效的解决现有技术中因级传信号挂的负载较大，比较容易出现延迟现象，而在级传过程中延迟的影响会逐渐加大的技术问题。
 技术解决方案
为了解决上述技术问题，本发明提供一种GOA电路，包括级联的多级GOA单元电路，每一级GOA单元电路均包括：
正反向扫描控制模块，其用于将所述上一级GOA单元电路的级传信号传入到级传信号增强模块；
级传信号增强模块，其用于受上一级GOA单元电路的所述级传信号的控制将第一恒压电位或第二恒压电位输出至级传信号输出模块的输入端；所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位；所述第二恒压电位的电平值小于所述第一恒压电位的电平值
其中，所述正反向扫描控制模块的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块的输出端电性连接于级传信号增强模块的控制端；所述级传信号增强模块的第一输入端接入所述第一恒压电位，第二输入端接入所述第二恒压电位，所述级传信号增强模块的输出端电性连接于所述级传信号输出模块的输入端。
所述级传信号增强模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
所述第一薄膜晶体管的栅极电性连接于所述正反向扫描控制模块的输出端，源极接入所述第一恒压电位，漏极电性连接于所述第二薄膜晶体管的的漏极；
所述第二薄膜晶体管的栅极和源极接入所述第二恒压电位；
所述第三薄膜晶体管的栅极电性连接于所述第二薄膜晶体管的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管的漏极；
所述第四薄膜晶体管的栅极电性连接于所述第一薄膜晶体管的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块的输入端。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管及第四薄膜晶体管都是N型薄膜晶体管。
所述正反向扫描控制模块包括第五薄膜晶体管和第六薄膜晶体管；
所述第五薄膜晶体管的源极接入第N-1级GOA单元电路的级传信号，栅极接入正向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接；
所述第六薄膜晶体管的源极接入第N+1级GOA单元电路的级传信号，栅极接入反向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接。
在第一级GOA单元电路中，所述第五薄膜晶体管的源极接入电路的起始信号。
在最后一级GOA单元电路中，所述第六薄膜晶体管的源极接入电路的起始信号。
本发明还提供一种GOA电路，其包括级联的多级GOA单元电路，每一级GOA单元电路均包括：
正反向扫描控制模块，其用于将所述上一级GOA单元电路的级传信号传入到级传信号增强模块；
级传信号增强模块，其用于受上一级GOA单元电路的所述级传信号的控制将第一恒压电位或第二恒压电位输出至级传信号输出模块的输入端；
其中，所述正反向扫描控制模块的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块的输出端电性连接于级传信号增强模块的控制端；所述级传信号增强模块的第一输入端接入所述第一恒压电位，第二输入端接入所述第二恒压电位，所述级传信号增强模块的输出端电性连接于所述级传信号输出模块的输入端。
所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位。
所述第二恒压电位的电平值小于所述第一恒压电位的电平值。
所述级传信号增强模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
所述第一薄膜晶体管的栅极电性连接于所述正反向扫描控制模块的输出端，源极接入所述第一恒压电位，漏极电性连接于所述第二薄膜晶体管的的漏极；
所述第二薄膜晶体管的栅极和源极接入所述第二恒压电位；
所述第三薄膜晶体管的栅极电性连接于所述第二薄膜晶体管的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管的漏极；
所述第四薄膜晶体管的栅极电性连接于所述第一薄膜晶体管的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块的输入端。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管及第四薄膜晶体管都是N型薄膜晶体管。
所述正反向扫描控制模块包括第五薄膜晶体管和第六薄膜晶体管；
所述第五薄膜晶体管的源极接入第N-1级GOA单元电路的级传信号，栅极接入正向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接；
所述第六薄膜晶体管的源极接入第N+1级GOA单元电路的级传信号，栅极接入反向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接。
在第一级GOA单元电路中，所述第五薄膜晶体管的源极接入电路的起始信号。
在最后一级GOA单元电路中，所述第六薄膜晶体管的源极接入电路的起始信号。
所述级传信号输出模块包括输出单元、输出下拉单元、节点输入单元、节点控制单元、稳压单元以及第一电容；
所述输出单元包括第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极接入第二时钟信号，漏极电性连接于所述第N级GOA单元电路的输出端；以及第二电容，所述第二电容的一端电性连接于所述第一节点，另一端电性连接于所述第N级GOA单元电路的输出端；
所述稳压单元包括第八薄膜晶体管，所述第八薄膜晶体管的栅极接入所述第二恒压电位，源极电性连接于第三节点，漏极电性连接于所述第一节点；
所述输出下拉单元包括第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于第二节点，源极接入所述第一恒压电位，漏极电性连接于所述第N级GOA单元电路的输出端；
所述节点输入单元包括第七薄膜晶体管、第十二薄膜晶体管以及第十三薄膜晶体管；所述第七薄膜晶体管源极电性连接于所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的漏极，所述第七薄膜晶体管的栅极、所述第十二薄膜晶体管的源极和所述第十三薄膜晶体管的栅极接入所述第一时钟信号，所述第七薄膜晶体管的漏极和所述第十二薄膜晶体管的栅极电性连接于所述第三节点，所述第十二薄膜晶体管的漏极和所述第十三薄膜晶体管的漏极电性连接于所述第二节点，所述第十三薄膜晶体管的源极接入所述第二恒压电位；
所述节点控制单元包括第十薄膜晶体管和第十一薄膜晶体管；所述第十一薄膜晶体管的栅极电性连接于所述第二节点，源极接入所述第一恒压电位，漏极电性连接于所述第十薄膜晶体管的源极；所述第十薄膜晶体管的栅极接入所述第二时钟信号，漏极电性连接于所述第三节点。
依据本发明的上述目的，提出一种液晶显示器，所述液晶显示器包括一种GOA电路，其包括级联的多级GOA单元电路，每一级GOA单元电路均包括：
正反向扫描控制模块，其用于将所述上一级GOA单元电路的级传信号传入到级传信号增强模块；
级传信号增强模块，其用于受上一级GOA单元电路的所述级传信号的控制将第一恒压电位或第二恒压电位输出至级传信号输出模块的输入端；
其中，所述正反向扫描控制模块的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块的输出端电性连接于级传信号增强模块的控制端；所述级传信号增强模块的第一输入端接入所述第一恒压电位，第二输入端接入所述第二恒压电位，所述级传信号增强模块的输出端电性连接于所述级传信号输出模块的输入端。
所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位。
所述第二恒压电位的电平值小于所述第一恒压电位的电平值。
所述级传信号增强模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
所述第一薄膜晶体管的栅极电性连接于所述正反向扫描控制模块的输出端，源极接入所述第一恒压电位，漏极电性连接于所述第二薄膜晶体管的的漏极；
所述第二薄膜晶体管的栅极和源极接入所述第二恒压电位；
所述第三薄膜晶体管的栅极电性连接于所述第二薄膜晶体管的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管的漏极；
所述第四薄膜晶体管的栅极电性连接于所述第一薄膜晶体管的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块的输入端。
所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管及第四薄膜晶体管都是N型薄膜晶体管。
 有益效果
本发明所提供的GOA电路及液晶显示器通过在所述正反向扫描控制模块和级传信号输出模块之间设一级传信号增强模块，使得级传信号在经过所述级传信号增强模块后延迟会降低，驱动能力也会得到提升，从而可以有效降低级传信号的延迟对下一级GOA单元电路的影响。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明的GOA电路的第N级GOA单元电路的电路图；
图2为本发明的GOA电路的第一级GOA单元电路的电路图；
图3为本发明的GOA电路的最后一级GOA单元电路的电路图；
图4为为本发明的GOA电路的输入信号与关键节点的波形示意图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
参见图1，为本发明GOA电路的第N级GOA单元电路的电路图；
本发明的GOA电路，包括：级联的多级GOA单元电路，每一级GOA单元电路均包括：正反向扫描控制模块100、级传信号增强模块200和级传信号输出模块300；
设N为正整数，除第一级GOA单元电路与最后一级GOA单元电路以外，在第N级GOA单元电路中：
所述正反向扫描控制模块100的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块100的输出端电性连接于级传信号增强模块的控制端，用于将所述上一级GOA单元电路的级传信号传入到所述级传信号增强模块200；
所述级传信号增强模块200的第一输入端接入第一恒压电位，第二输入端接入第二恒压电位，所述级传信号增强模块200的输出端电性连接于所述级传信号输出模块300的输入端，用于受上一级GOA单元电路的所述级传信号的控制将所述第一恒压电位或所述第二恒压电位输出至所述级传信号输出模块300的输入端。
所述第一恒压电位为恒压低电位VGL，所述第二恒压电位为恒压高电位VGH。
所述第二恒压电位的电平值小于所述第一恒压电位的电平值。
所述级传信号增强模块200包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3以及第四薄膜晶体管T4；
所述第一薄膜晶体管T1的栅极电性连接于所述正反向扫描控制模块100的输出端，源极接入第一恒压电位，漏极电性连接于所述第二薄膜晶体管T2的漏极；
所述第二薄膜晶体管T2的栅极和源极接入所述第二恒压电位；
所述第三薄膜晶体管T3的栅极电性连接于所述第二薄膜晶体管T2的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管T4的漏极；
所述第四薄膜晶体管T4的栅极电性连接于所述第一薄膜晶体管T1的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块300的输入端。
所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3及第四薄膜晶体管T4都是N型薄膜晶体管。
所述正反向扫描控制模块包括第五薄膜晶体管T5和第六薄膜晶体管T6；
所述第五薄膜晶体管T5的源极接入第N-1级GOA单元的级传信号，栅极接入正向扫描信号U2D，漏极与所述第一薄膜晶体管T1的栅极和所述第四薄膜晶体管T4的栅极连接；
所述第六薄膜晶体管T6的源极接入第N+1级GOA单元的级传信号，栅极接入反向扫描信号D2U，漏极与所述第一薄膜晶体管T1的栅极和所述第四薄膜晶体管T4的栅极连接。
可选的，当第五薄膜晶体管T5和第六薄膜晶体管T6都是N型薄膜晶体管时，正向扫描时，所述正向扫描信号U2D为高电位，反向扫描信号D2U为低电位；反向扫描时，所述正向扫描信号U2D为低电位，反向扫描信号D2U为高电位。
可选的，当第五薄膜晶体管T5和第六薄膜晶体管T6都是P型薄膜晶体管时，正向扫描时，所述正向扫描信号U2D为低电位，反向扫描信号D2U为高电位；反向扫描时，所述正向扫描信号U2D为高电位，反向扫描信号D2U为低电位。
所述级传信号输出模块300包括输出单元301，输出下拉单元302、节点输入单元303、节点控制单元304、稳压单元305以及第一电容C1；
所述输出单元301包括第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第一节点Q(n)，源极接入第二时钟信号CK2，漏极电性连接于所述第N级GOA单元电路的输出端；以及第二电容C2，所述第二电容C2的一端电性连接于所述第一节点Q(n)，另一端电性连接于所述第N级GOA单元电路的输出端G(n)；
所述稳压单元305包括第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极接入所述第二恒压电位，源极电性连接于第三节点A(n），漏极电性连接于所述第一节点Q(n)；
所述输出下拉单元302包括第十四薄膜晶体管T14，所述第十四薄膜晶体管T14的栅极电性连接于第二节点P(n)，源极接入所述第一恒压电位，漏极电性连接于所述第N级GOA单元电路的输出端G(n)；
所述节点输入单元包括第七薄膜晶体管T7、第十二薄膜晶体管T12以及第十三薄膜晶体管T13；所述第七薄膜晶体管T7源极电性连接于所述第三薄膜晶体管T3的漏极和所述第四薄膜晶体管T4的漏极，所述第七薄膜晶体管T7的栅极、所述第十二薄膜晶体管T12的源极和所述第十三薄膜晶体管T13的栅极接入所述第一时钟信号CK1，所述第七薄膜晶体管T7的漏极和所述第十二薄膜晶体管T12的栅极电性连接于所述第三节点A(n），所述第十二薄膜晶体管T12的漏极和所述第十三薄膜晶体管T13的漏极电性连接于所述第二节点P(n)，所述第十三薄膜晶体管T13的源极接入所述第二恒压电位；
所述节点控制单元304包括第十薄膜晶体管T10和第十一薄膜晶体管T11；所述第十一薄膜晶体管T11的栅极电性连接于所述第二节点P(n)，源极接入所述第一恒压电位，漏极电性连接于所述第十薄膜晶体管T10的源极；所述第十薄膜晶体管T10的栅极接入所述第二时钟信号CK2，漏极电性连接于所述第三节点A(n）。
所述第一时钟信号CK1与所述第二时钟信号CK2的相位相反。
特别地，请参阅图2，在第一级GOA单元电路中，所述第五薄膜晶体管T5的源极接入电路的起始信号STV,栅极接入正向扫描信号U2D，漏极与所述第一薄膜晶体管T1的栅极和所述第四薄膜晶体管T4的栅极连接。
请参阅图3，最后一级GOA单元电路中，所述第六薄膜晶体管T6的源极接入电路的起始信号STV，栅极接入反向扫描信号D2U，漏极与所述第一薄膜晶体管T1的栅极和所述第四薄膜晶体管T4的栅极连接。
请同时参阅图1与图4，图中所示薄膜晶体管都是N型薄膜晶体管，下面以正向扫描为例，本发明GOA电路的工作过程为：自电路的起始信号STV启动第一级的GOA电路，依次逐级进行扫描驱动。扫描驱动至第N级GOA单元电路，上一级第N-1级GOA单元电路的级传信号G(n-1)为高电位，正向扫描信号为高电位，反向扫描信号为低电位时，第五薄膜晶体管T5导通，第六薄膜晶体管T6断开，将级传信号G(n-1)传到级传信号增强模块。具体地，此时第一薄膜晶体管T1和第二薄膜晶体管T2导通，由于所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位，并且所述第二恒压电位的电平值小于所述第一恒压电位的电平值，故此时C点为低电位，从而第三薄膜晶体管T3断开，第四薄膜晶体管T4导通，从而级传信号增强模块的输出端B被第二恒压电位拉升至高电位；当上一级第N-1级GOA单元电路的级传信号G(n-1)为低电位时，所述第四薄膜晶体管T4断开，由于第二薄膜晶体管T2受第二恒压电位作用，始终打开，故此时C点为高电位，从而第三薄膜晶体管T3打开，级传信号增强模块的输出端B被第一恒压电位拉低至低电位。
通过级传信号增强模块200，将上一级GOA单元电路的级传信号作为控制信号，从而将恒压电位传输至级传信号输出模块300，起到信号增强的效果。
接着，当第一时钟信号CK1为高电位，第二时钟信号CK2为低电位时，所述第七薄膜晶体管T7和所述第八薄膜晶体管T8导通，第一节点Q(n)被抬升至高电位，并对第二电容C2充电；当第一时钟信号CK1为高电位，第二时钟信号CK2为低电位时，所述第十三薄膜晶体管T13和所述第十二薄膜晶体管T12打开，第二节点P(n)被抬升至高电位，此时，第九薄膜晶体管T9和第十四薄膜晶体管打开，从而使第N级GOA单元电路的输出端G(n)被下拉至低电位。
然后，第一时钟信号CK1为低电位，第二时钟信号CK2为高电位时，第七薄膜晶体管T7断开，第一节点Q(n)通过电容C2维持在高电位，使得第九薄膜晶体管T9打开；当第一时钟信号CK1为低电位，第二时钟信号CK2为高电位时，第十三薄膜晶体管T13打开，第一时钟信号CK1将P(n)拉低，从而第十四薄膜晶体管T14断开；第九薄膜晶体管T9的源极接入第二时钟信号CK2，从而第N级GOA单元电路的输出端G(n)被第二时钟信号CK2抬升至高电位。
当P点为高电平，第二时钟信号CK2为高电平时，第十一薄膜晶体管T11、第十薄膜晶体管T10及第八薄膜晶体管T8打开，所述第一节点Q(n)被恒压低电位拉低。
本发明的GOA电路通过在所述正反向扫描控制模块和级传信号输出模块之间设一级传信号增强模块，使得级传信号在经过所述级传信号增强模块后延迟会降低，驱动能力也会得到提升，从而可以有效降低级传信号的延迟对下一级GOA单元电路的影响。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (20)

  1. 一种GOA电路，其包括级联的多级GOA单元电路，每一级GOA单元电路均包括：
    正反向扫描控制模块，其用于将所述上一级GOA单元电路的级传信号传入到级传信号增强模块；
    级传信号增强模块，其用于受上一级GOA单元电路的所述级传信号的控制将第一恒压电位或第二恒压电位输出至级传信号输出模块的输入端；所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位；所述第二恒压电位的电平值小于所述第一恒压电位的电平值
    其中，所述正反向扫描控制模块的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块的输出端电性连接于级传信号增强模块的控制端；所述级传信号增强模块的第一输入端接入所述第一恒压电位，第二输入端接入所述第二恒压电位，所述级传信号增强模块的输出端电性连接于所述级传信号输出模块的输入端。
  2. 根据权利要求1所述的GOA电路，其中所述级传信号增强模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
    所述第一薄膜晶体管的栅极电性连接于所述正反向扫描控制模块的输出端，源极接入所述第一恒压电位，漏极电性连接于所述第二薄膜晶体管的的漏极；
    所述第二薄膜晶体管的栅极和源极接入所述第二恒压电位；
    所述第三薄膜晶体管的栅极电性连接于所述第二薄膜晶体管的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管的漏极；
    所述第四薄膜晶体管的栅极电性连接于所述第一薄膜晶体管的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块的输入端。
  3. 根据权利要求2所述的GOA电路，其中所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管及第四薄膜晶体管都是N型薄膜晶体管。
  4. 根据权利要求3所述的GOA电路，其中所述正反向扫描控制模块包括第五薄膜晶体管和第六薄膜晶体管；
    所述第五薄膜晶体管的源极接入第N-1级GOA单元电路的级传信号，栅极接入正向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接；
    所述第六薄膜晶体管的源极接入第N+1级GOA单元电路的级传信号，栅极接入反向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接。
  5. 根据权利要求4所述的GOA电路，其中在第一级GOA单元电路中，所述第五薄膜晶体管的源极接入电路的起始信号。
  6. 根据权利要求4所述的GOA电路，其中在最后一级GOA单元电路中，所述第六薄膜晶体管的源极接入电路的起始信号。
  7. 一种GOA电路，其包括级联的多级GOA单元电路，每一级GOA单元电路均包括：
    正反向扫描控制模块，其用于将所述上一级GOA单元电路的级传信号传入到级传信号增强模块；
    级传信号增强模块，其用于受上一级GOA单元电路的所述级传信号的控制将第一恒压电位或第二恒压电位输出至级传信号输出模块的输入端；
    其中，所述正反向扫描控制模块的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块的输出端电性连接于级传信号增强模块的控制端；所述级传信号增强模块的第一输入端接入所述第一恒压电位，第二输入端接入所述第二恒压电位，所述级传信号增强模块的输出端电性连接于所述级传信号输出模块的输入端。
  8. 根据权利要求7所述的GOA电路，其中所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位。
  9. 根据权利要求7所述的GOA电路，其中所述第二恒压电位的电平值小于所述第一恒压电位的电平值。
  10. 根据权利要求7所述的GOA电路，其中所述级传信号增强模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
    所述第一薄膜晶体管的栅极电性连接于所述正反向扫描控制模块的输出端，源极接入所述第一恒压电位，漏极电性连接于所述第二薄膜晶体管的的漏极；
    所述第二薄膜晶体管的栅极和源极接入所述第二恒压电位；
    所述第三薄膜晶体管的栅极电性连接于所述第二薄膜晶体管的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管的漏极；
    所述第四薄膜晶体管的栅极电性连接于所述第一薄膜晶体管的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块的输入端。
  11. 根据权利要求10所述的GOA电路，其中所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管及第四薄膜晶体管都是N型薄膜晶体管。
  12. 根据权利要求11所述的GOA电路，其中所述正反向扫描控制模块包括第五薄膜晶体管和第六薄膜晶体管；
    所述第五薄膜晶体管的源极接入第N-1级GOA单元电路的级传信号，栅极接入正向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接；
    所述第六薄膜晶体管的源极接入第N+1级GOA单元电路的级传信号，栅极接入反向扫描信号，漏极与所述第一薄膜晶体管的栅极和所述第四薄膜晶体管的栅极连接。
  13. 根据权利要求12所述的GOA电路，其中在第一级GOA单元电路中，所述第五薄膜晶体管的源极接入电路的起始信号。
  14. 根据权利要求12所述的GOA电路，其中在最后一级GOA单元电路中，所述第六薄膜晶体管的源极接入电路的起始信号。
  15. 根据权利要求13或14所述的GOA电路，其中所述级传信号输出模块包括输出单元、输出下拉单元、节点输入单元、节点控制单元、稳压单元以及第一电容；
    所述输出单元包括第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极接入第二时钟信号，漏极电性连接于所述第N级GOA单元电路的输出端；以及第二电容，所述第二电容的一端电性连接于所述第一节点，另一端电性连接于所述第N级GOA单元电路的输出端；
    所述稳压单元包括第八薄膜晶体管，所述第八薄膜晶体管的栅极接入所述第二恒压电位，源极电性连接于第三节点，漏极电性连接于所述第一节点；
    所述输出下拉单元包括第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于第二节点，源极接入所述第一恒压电位，漏极电性连接于所述第N级GOA单元电路的输出端；
    所述节点输入单元包括第七薄膜晶体管、第十二薄膜晶体管以及第十三薄膜晶体管；所述第七薄膜晶体管源极电性连接于所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的漏极，所述第七薄膜晶体管的栅极、所述第十二薄膜晶体管的源极和所述第十三薄膜晶体管的栅极接入所述第一时钟信号，所述第七薄膜晶体管的漏极和所述第十二薄膜晶体管的栅极电性连接于所述第三节点，所述第十二薄膜晶体管的漏极和所述第十三薄膜晶体管的漏极电性连接于所述第二节点，所述第十三薄膜晶体管的源极接入所述第二恒压电位；
    所述节点控制单元包括第十薄膜晶体管和第十一薄膜晶体管；所述第十一薄膜晶体管的栅极电性连接于所述第二节点，源极接入所述第一恒压电位，漏极电性连接于所述第十薄膜晶体管的源极；所述第十薄膜晶体管的栅极接入所述第二时钟信号，漏极电性连接于所述第三节点。
  16. 一种液晶显示器，其特征在于，所述液晶显示器包括一种GOA电路，其包括级联的多级GOA单元电路，每一级GOA单元电路均包括：
    正反向扫描控制模块，其用于将所述上一级GOA单元电路的级传信号传入到级传信号增强模块；
    级传信号增强模块，其用于受上一级GOA单元电路的所述级传信号的控制将第一恒压电位或第二恒压电位输出至级传信号输出模块的输入端；
    其中，所述正反向扫描控制模块的输入端电性连接于上一级GOA单元电路的输出端，所述正反向扫描控制模块的输出端电性连接于级传信号增强模块的控制端；所述级传信号增强模块的第一输入端接入所述第一恒压电位，第二输入端接入所述第二恒压电位，所述级传信号增强模块的输出端电性连接于所述级传信号输出模块的输入端。
  17. 根据权利要求16所述的液晶显示器，其中所述第一恒压电位为恒压低电位，所述第二恒压电位为恒压高电位。
  18. 根据权利要求16所述的GOA电路，其中所述第二恒压电位的电平值小于所述第一恒压电位的电平值。
  19. 根据权利要求16所述的GOA电路，其中所述级传信号增强模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管；
    所述第一薄膜晶体管的栅极电性连接于所述正反向扫描控制模块的输出端，源极接入所述第一恒压电位，漏极电性连接于所述第二薄膜晶体管的的漏极；
    所述第二薄膜晶体管的栅极和源极接入所述第二恒压电位；
    所述第三薄膜晶体管的栅极电性连接于所述第二薄膜晶体管的漏极，源极接入所述第一恒压电位，漏极电性连接于所述第四薄膜晶体管的漏极；
    所述第四薄膜晶体管的栅极电性连接于所述第一薄膜晶体管的栅极，源极接入所述第二恒压电位，漏极电性连接于所述级传信号输出模块的输入端。
  20. 根据权利要求19所述的GOA电路，其中所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管及第四薄膜晶体管都是N型薄膜晶体管。
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