WO2022252053A1 - 行驱动信号增强电路、移位寄存器单元和显示面板 - Google Patents

行驱动信号增强电路、移位寄存器单元和显示面板 Download PDF

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Publication number
WO2022252053A1
WO2022252053A1 PCT/CN2021/097403 CN2021097403W WO2022252053A1 WO 2022252053 A1 WO2022252053 A1 WO 2022252053A1 CN 2021097403 W CN2021097403 W CN 2021097403W WO 2022252053 A1 WO2022252053 A1 WO 2022252053A1
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Prior art keywords
transistor
lead
sub
connection line
connection
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PCT/CN2021/097403
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English (en)
French (fr)
Inventor
李东升
范龙飞
吴谦
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001392.1A priority Critical patent/CN115885338A/zh
Priority to US17/918,590 priority patent/US20240221643A1/en
Priority to PCT/CN2021/097403 priority patent/WO2022252053A1/zh
Publication of WO2022252053A1 publication Critical patent/WO2022252053A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a row driving signal enhancement circuit, a shift register unit and a display panel.
  • the scan signal can be loaded to the pixel drive circuit through the gate lead; due to the load and impedance on the gate lead, when the scan signal reaches the pixel drive circuit, there will often be a certain delay and voltage loss.
  • silicon-based OLED organic electroluminescent diode
  • the delay and voltage drop loss of the scanning signal on the gate lead are relatively large, which will cause different data voltages written by different pixel drive circuits , thereby reducing the display uniformity of the silicon-based OLED display.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, and provide a row driving signal enhancement circuit, a shift register unit and a display panel.
  • a row driving signal enhancement circuit including:
  • control unit having a first control terminal and a second control terminal, configured to input a first power supply voltage to one of the first node and the second node under the control of the first control terminal and the second control terminal, and inputting the second power supply voltage to the other;
  • a first output unit connected to the first node and a first output terminal, for outputting one of the first power supply voltage and the second power supply voltage to the first power supply under the control of the first node output terminal;
  • a second output unit connected to the second node and a second output terminal, for outputting the other of the first power supply voltage and the second power supply voltage to the first power supply voltage under the control of the second node Two output terminals.
  • control unit includes:
  • the first control unit has the first control terminal and the second control terminal, and is used to output the first power supply voltage to the second control terminal under the control of the first control terminal and the second control terminal. a node or the second node;
  • a second control unit connected to the first node and the second node, and configured to output the second power supply voltage to the second node in response to the first power supply voltage loaded on the first node , and for outputting the second power supply voltage to the first node in response to the first power supply voltage loaded on the second node.
  • the second control unit has at least four transistors.
  • the first control unit includes:
  • the first transistor has a first terminal for loading the first power supply voltage, a second terminal connected to the first node, and a control terminal serving as the first control terminal; the first transistor is used for, in the outputting the first power supply voltage to the first node under the control of the control terminal of the first transistor;
  • the second transistor has a first terminal for loading the first power supply voltage, a second terminal connected to the second node, and a control terminal as the second control terminal; the second transistor is used for, in the outputting the first power supply voltage to the second node under the control of the control terminal of the second transistor;
  • the first transistor and the second transistor are of the same type.
  • the second control unit includes:
  • the third transistor has a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second node; the third transistor is used for loading outputting the second supply voltage to the second node under control of the first supply voltage on the first node;
  • the fourth transistor has a control terminal connected to the first node, a first terminal used for loading the second power supply voltage, and a second terminal connected to the second node; the fourth transistor is used for loading outputting the second supply voltage to the second node under control of the first supply voltage on the first node;
  • the fifth transistor has a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first node; the fifth transistor is used for loading outputting the second supply voltage to the first node under control of the first supply voltage on the second node;
  • a sixth transistor having a control terminal connected to the second node, a first terminal used to load the second power supply voltage, and a second terminal connected to the first node; the sixth transistor is used for loading outputting the second supply voltage to the first node under control of the first supply voltage on the second node;
  • the types of the third transistor to the sixth transistor are the same.
  • the first output unit includes:
  • a seventh transistor having a control terminal connected to the first node, a first terminal for loading the first power supply voltage, and a second terminal as the first output terminal;
  • An eighth transistor having a control terminal connected to the first node, a first terminal for loading the first power supply voltage, and a second terminal connected to the first output terminal;
  • a ninth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first output terminal;
  • a tenth transistor having a control terminal connected to the first node, a first terminal for loading the second power supply voltage, and a second terminal connected to the first output terminal;
  • the second output unit includes:
  • An eleventh transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal serving as the first output terminal;
  • a twelfth transistor having a control terminal connected to the second node, a first terminal for loading the second power supply voltage, and a second terminal connected to the second output terminal;
  • a thirteenth transistor having a control terminal connected to the second node, a first terminal for loading the first power supply voltage, and a second terminal connected to the second output terminal;
  • a fourteenth transistor having a control terminal connected to the second node, a first terminal for loading the first power supply voltage, and a second terminal connected to the second output terminal;
  • any one of the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth crystal is used to respond to the first power supply voltage and the second One of the power supply voltages is turned on, and any one of the ninth transistor to the twelfth transistor is used to respond to the other of the first power supply voltage and the second power supply voltage loaded on its control terminal And turn on.
  • a shift register unit including a shift register, an inverter, and the above-mentioned row drive signal enhancement circuit;
  • the shift register is used to output the initial scanning signal to the input terminal of the inverter and the first control terminal of the row driving signal enhancement circuit; the output terminal of the inverter is connected to the row driving signal The second control terminal of the enhancement circuit.
  • a display panel including the above-mentioned shift register unit.
  • a display panel includes a driving backplane and a display layer stacked on the driving backplane;
  • the driving backplane includes semiconductor substrates stacked in sequence , a gate insulating layer, a gate layer, an insulating dielectric layer and a metal wiring layer;
  • the display panel includes a display area and a peripheral area surrounding the display area, and a plurality of row driving signal enhancement areas are arranged in the peripheral area ;
  • the drive backplane is provided with a row drive signal enhancement circuit including a first transistor to a fourteenth transistor; wherein, the first transistor and the second transistor are of the same type; The seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor are of the same type; the ninth transistor to the twelfth transistor are of the same type, and are identical to the first
  • the types of the seven transistors are opposite; the types of the third transistor to the sixth transistor are the same; the active area of each transistor is formed on the semiconductor substrate, and the active area of any one transistor includes a channel area, a trench The source and drain on both sides of the channel region; the gate layer is formed with the gate of each transistor, and the gate insulating layer isolates the gate and channel region of any transistor; the insulating dielectric layer covers all the gate layer;
  • the metal wiring layer is provided with connecting leads, a first power lead, a second power lead, a first control lead, a second control lead, a first output lead and a second output lead;
  • the connection lead is electrically connected to the source, drain and gate of each transistor through the conductive column in the insulating medium layer; wherein, the connection lead connects the gate of the first transistor to the first The control lead is electrically connected, and the gate of the second transistor is electrically connected to the second control lead, and the source of the first transistor, the source of the second transistor, the seventh transistor.
  • the source of the eighth transistor, the source of the thirteenth transistor, and the source of the fourteenth transistor are electrically connected to the first power supply lead, and make the third transistor to
  • the source of the sixth transistor, the sources of the ninth transistor to the twelfth transistor are electrically connected to the second power lead, and make the drains of the seventh transistor to the tenth transistor are electrically connected to the first output lead, and make the drains of the eleventh transistor to the fourteen
  • the first transistor, the second transistor, the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor are all N-type Transistors
  • the ninth transistor to the twelfth transistor are all P-type transistors.
  • any one of the row driving signal enhancement regions includes a P-type substrate region and an N-type substrate region, and the P-type substrate region is located in the first direction of the N-type substrate region.
  • the first direction is a direction away from the display region; the N-type transistor is formed in the P-type substrate region, and the P-type transistor is formed in the N-type substrate region.
  • the N-type substrate region includes an N-type auxiliary doped region, and includes a first active region and a second active region respectively surrounded by the N-type auxiliary doped region;
  • the second active region is located on one side of the first active region in the first direction;
  • the first active region includes a first sub-active region and a second sub-active region arranged in sequence along the first direction; the ninth transistor and the eleventh transistor are located in the first sub-active region , the tenth transistor and the twelfth transistor are located in the second sub-active region;
  • the second active region includes a third sub-active region and a fourth sub-active region arranged in sequence along a second direction; the second direction is perpendicular to the first direction and parallel to the plane of the semiconductor substrate ;
  • the fifth transistor and the sixth transistor are located in the third sub-active area, and the third transistor and the fourth transistor are located in the fourth sub-active area.
  • the P-type substrate region includes a P-type auxiliary doped region, a third active region, and a fourth active region; the fourth active region is located in the third active region the first direction side of the zone;
  • the third active region is surrounded by the P-type auxiliary doped region, and includes a fifth sub-active region and a sixth sub-active region sequentially arranged along the first direction; the seventh transistor and the The thirteenth transistor is located in the fifth sub-active area, and the eighth transistor and the fourteenth transistor are located in the sixth sub-active area;
  • the fourth active region includes a seventh sub-active region and an eighth sub-active region arranged in sequence along the second direction and respectively surrounded by the P-type auxiliary doped region; the first transistor is located in the The seventh sub-active region, the second transistor is located in the eighth sub-active region.
  • the insulating dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer sequentially stacked on the gate layer
  • the metal wiring layer includes The first metal wiring layer between the dielectric layer and the second dielectric layer, the second metal wiring layer between the second dielectric layer and the third dielectric layer, and the third dielectric layer away from the a third metal wiring layer on the surface of the semiconductor substrate;
  • the conductive pillars include first conductive pillars penetrating the first dielectric layer, second conductive pillars penetrating the second dielectric layer, and third conductive pillars penetrating the third dielectric layer; the first metal wiring layer is connected to the semiconductor substrate and the gate layer through the first conductive pillar; the second metal wiring layer is connected to the first metal wiring layer through the second conductive pillar; the third The metal wiring layer is connected to the second metal wiring layer through the third conductive column;
  • the first metal wiring layer includes a part of connection leads; the connection leads located in the first metal wiring layer include the first connection lead to the sixth connection lead, and also include the first transistor to the tenth connection lead.
  • the respective gate connecting wires, source connecting wires and drain connecting wires of the four transistors are connected; the gate connecting wire corresponding to any transistor is connected to the gate of the transistor; the source connecting wire corresponding to any transistor is connected to the gate of the transistor.
  • the source of the transistor is connected; the drain connection line corresponding to any transistor is connected to the drain of the transistor;
  • the source connection line corresponding to the ninth transistor and the source connection line corresponding to the eleventh transistor are connected to the first connection lead;
  • the source connection line corresponding to the tenth transistor includes a first sub-connection line and a second sub-connection line;
  • the source connection line corresponding to the twelfth transistor includes a first sub-connection line and a second sub-connection line;
  • the source connecting wire corresponding to the fourth transistor is connected to the second connecting lead;
  • the drain connection line corresponding to the fifth transistor, the drain connection line corresponding to the sixth transistor, the gate connection line corresponding to the third transistor, the gate connection line corresponding to the fourth transistor and the The fourth connecting lead is connected;
  • the source connection line corresponding to the eighth transistor includes a first sub-connection line and a second sub-connection line;
  • the source connection line corresponding to the fourteenth transistor includes a first sub-connection line and a second sub-connection line;
  • the first sub-connection line of the source connection line corresponding to the eighth transistor, the first sub-connection line of the source connection line corresponding to the fourteenth transistor, the source connection line corresponding to the seventh transistor, the The source connection line corresponding to the thirteenth transistor, the source connection line corresponding to the first transistor, and the source connection line corresponding to the second transistor are connected to the fifth connection lead;
  • the source connection line corresponding to the third transistor and the source connection line corresponding to the sixth transistor are connected to the sixth connection lead;
  • the second metal wiring layer includes a first control lead, a second control lead, a first output lead, a second output lead and some connecting leads; the connecting leads located in the second metal wiring layer include a seventh connecting lead to the fifteenth connecting lead;
  • connection lead, the second connection lead are connected to the seventh connection lead, and the first connection lead, the second connection lead are connected to the eighth connection lead;
  • the fifth connecting lead is connected to the ninth connecting lead and the tenth connecting lead;
  • the gate connection line corresponding to the ninth transistor, the gate connection line corresponding to the tenth transistor, the drain connection line corresponding to the fifth transistor, the drain connection line corresponding to the sixth transistor, the The gate connection line corresponding to the seventh transistor, the gate connection line corresponding to the eighth transistor, and the drain connection line corresponding to the first transistor are connected to the eleventh connection lead;
  • the gate connection line corresponding to the thirteenth transistor, the gate connection line corresponding to the fourteenth transistor, and the drain connection line corresponding to the second transistor are connected to the twelfth connection lead;
  • the first connection lead, the source connection line corresponding to the ninth transistor, the source connection line corresponding to the eleventh transistor, the second sub-connection line of the source connection line corresponding to the tenth transistor, The second sub-connection line of the source connection line corresponding to the twelfth transistor, and the sixth connection lead are connected to the thirteenth connection lead;
  • the fifth connecting lead is connected to the fifteenth connecting lead
  • the drain connection line corresponding to the eleventh transistor, the drain connection line corresponding to the twelfth transistor, the drain connection line corresponding to the thirteenth transistor, and the drain connection line corresponding to the fourteenth transistor A line is connected to the second output lead;
  • the gate connection line corresponding to the first transistor is connected to the first control lead, and the gate connection line corresponding to the second transistor is connected to the second control lead;
  • the third metal wiring layer includes a first power supply lead for loading a first power supply voltage, and a second power supply lead for loading a second power supply voltage; the ninth connection lead, the tenth connection lead , the fourteenth connecting lead, the fifteenth connecting lead are connected to the first power lead; the seventh connecting lead, the eighth connecting lead, the thirteenth connecting lead are connected to the first Two power leads are connected.
  • the source connection lines and drain connection lines corresponding to each transistor extend along the first direction, and the gates of each transistor extend along the first direction. extending in the first direction.
  • the first connecting lead includes a first sub-lead, a second sub-lead and a third sub-lead connected in sequence; the first sub-lead of the first connecting lead, the first connecting lead The third sub-lead of the lead extends along the first direction and at least partially overlaps with the N-type auxiliary doped region; the second sub-lead of the first connection lead extends along the second direction and overlaps with the N-type auxiliary doping region; type auxiliary doped region overlaps at least partially; the first sub-lead of the first connection lead, the second sub-lead of the first connection lead and the third sub-lead of the first connection lead are all connected to the N-type The auxiliary doped region is connected; the first sub-active region is located in the space surrounded by the first connecting lead;
  • the source connection line corresponding to the ninth transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the ninth transistor and extending along the first direction;
  • the source connection line corresponding to a transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the eleventh transistor and extending along the first direction;
  • the ninth transistor corresponds to The opposite side of the second direction of the first sub-connection line of the source connection line is connected to the first sub-lead line of the first connection lead;
  • the first sub-connection line of the source connection line corresponding to the eleventh transistor One side of the connection line in the second direction is connected to the third sub-lead of the first connection lead;
  • the second sub-connection line of the source connection line corresponding to the ninth transistor is connected to the source corresponding to the eleventh transistor
  • the second sub-connection line of the line is the same lead, and extends along the direction opposite to the first direction to connect with the second sub-
  • connection lead is connected to the first sub-lead of the first connection lead; the eighth connection lead is connected to the third sub-lead of the first connection lead; the thirteenth connection lead is connected to the first connection lead A second sub-lead is connected to the lead.
  • the second connecting lead includes a first sub-lead, a third sub-lead, and a fourth sub-lead connected in sequence, and includes a second sub-lead; wherein, the second connecting lead of the second connecting lead A sub-lead and the fourth sub-lead of the second connection lead extend along the first direction and at least partially overlap with the N-type auxiliary doped region; the second sub-lead of the second connection lead, the The third sub-leads of the second connecting leads all extend along the second direction and at least partially overlap with the N-type auxiliary doped region; the first to fourth sub-leads of the second connecting leads all connected to the N-type auxiliary doped region;
  • the second sub-active area is located in a space surrounded by the first sub-lead of the second connection lead, the second sub-lead of the second connection lead, and the fourth sub-lead of the second connection lead,
  • the second active area is located on the first sub-lead of the second connecting lead, the second sub-lead of the second connecting lead, the third sub-lead of the second connecting lead and the In the space surrounded by the fourth sub-lead;
  • the first sub-connection line of the source connection line corresponding to the tenth transistor extends along the first direction, and the opposite side of the first direction is connected to the first sub-connection line of the second connection lead;
  • the first sub-connection line of the source connection line corresponding to the twelfth transistor extends along the first direction, and one side of the first direction is connected to the fourth sub-lead of the second connection lead;
  • the second sub-connection line of the source connection line corresponding to the tenth transistor and the second sub-connection line of the source connection line corresponding to the twelfth transistor are the same lead and extend along the first direction.
  • the fifth connecting lead includes a first sub-lead, a second sub-lead, a third sub-lead and a fourth sub-lead connected in sequence, and includes a fifth sub-lead and a sixth sub-lead;
  • the first sub-lead, the third sub-lead and the sixth sub-lead of the fifth connecting lead all extend along the first direction and at least partially overlap with the P-type auxiliary doped region; the fifth connection The sixth sub-lead of the lead is located between the first sub-lead and the third sub-lead, and the two ends are respectively connected to the fifth sub-lead and the fourth sub-lead;
  • the second sub-lead, the fourth sub-lead, and the fifth sub-lead of the fifth connection lead all extend in the second direction and at least partially overlap the P-type auxiliary doped region;
  • the fifth connection The fifth sub-lead of the lead is located between the second sub-lead and the fourth sub-lead, and the two ends are respectively connected to the first sub-lead and the third sub-lead;
  • the first sub-lead to the sixth sub-lead of the fifth connecting lead are all connected to the P-type auxiliary doped region;
  • the third active region is located in the space surrounded by the first sub-lead, the second sub-lead, the third sub-lead and the fifth sub-lead of the fifth connecting lead;
  • the seventh sub-active region is located in the In the space surrounded by the first sub-lead, the fifth sub-lead, the sixth sub-lead and the fourth sub-lead of the fifth connection lead;
  • the eighth sub-active region is located in the sixth sub-lead of the fifth connection lead , the fifth sub-lead, the third sub-lead and the space surrounded by the fourth sub-lead;
  • the source connection line corresponding to the seventh transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the seventh transistor and extending along the first direction;
  • the source connection lines corresponding to the three transistors include a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the thirteenth transistor and extending along the first direction;
  • the seventh transistor corresponds to The opposite side of the second direction of the first sub-connection line of the source connection line is connected to the first sub-lead line of the fifth connection lead;
  • the first sub-connection line of the source connection line corresponding to the thirteenth transistor One side of the connection line in the second direction is connected to the third sub-lead of the fifth connection lead;
  • the second sub-connection line of the source connection line corresponding to the seventh transistor is connected to the source corresponding to the thirteenth transistor
  • the second sub-connection line of the line is the same lead, and extends along the first direction to connect with the second sub-lead
  • the opposite side of the second direction of the first sub-connection line of the source connection line corresponding to the eighth transistor is connected to the first sub-lead line of the fifth connection lead; the source corresponding to the fourteenth transistor
  • the second direction side of the first sub-connection line of the connecting line is connected to the third sub-leading line of the fifth connecting lead; the second sub-connecting line of the source connecting line corresponding to the eighth transistor is connected to the fourteenth connecting line.
  • the second sub-connection line of the source connection line corresponding to the transistor is the same lead;
  • the source connection line corresponding to the first transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the first transistor and extending along the first direction;
  • the opposite side of the second direction of the first sub-connection line of the source connection line corresponding to the transistor is connected to the first sub-lead line of the fifth connection lead;
  • the second side of the source connection line corresponding to the first transistor One side of the sub-connection wire in the second direction is connected to the sixth sub-lead of the fifth connection lead;
  • the source connection line corresponding to the second transistor includes a first sub-connection line and a second sub-connection line respectively located on both sides of the gate corresponding to the second transistor and extending along the first direction;
  • the second direction side of the first sub-connection line of the source connection line corresponding to the transistor is connected to the third sub-connection line of the fifth connection lead;
  • the second sub-connection line of the source connection line corresponding to the second transistor The opposite side of the second direction is connected to the sixth sub-lead of the fifth connecting lead.
  • the third connection lead, the fourth connection lead and the sixth connection lead are located at the first sub-lead of the second connection lead and the first sub-lead of the second connection lead.
  • the third sub-lead of the second connection lead and the fourth sub-lead of the second connection lead are along the extending in a second direction, the sixth connecting lead extending along the first direction;
  • One side of the source connection line corresponding to the sixth transistor in the second direction is connected to the sixth connection lead, and the source connection line corresponding to the third transistor is connected to the second direction opposite side of the source connection line to the first Six connecting lead wire connections;
  • the drain connection line corresponding to the fifth transistor and the drain connection line corresponding to the sixth transistor are the same lead, and one end is connected to one end of the fourth connection lead;
  • the gate corresponding to the third transistor is connected to
  • the line and the gate connection line corresponding to the fourth transistor are the same lead, and one end is connected to the other end of the fourth connection lead;
  • the drain connection line corresponding to the third transistor and the drain connection line corresponding to the fourth transistor are the same lead, and one end is connected to one end of the third connection lead; the gate corresponding to the fifth transistor is connected to The line and the gate connecting wire corresponding to the sixth transistor are the same lead, and one end is connected to the other end of the third connecting lead.
  • the seventh connecting lead extends along the first direction, and is connected to the first sub-lead of the first connecting lead and the first sub-lead of the second connecting lead;
  • the eighth connecting lead extends along the first direction and is connected to the third sub-lead of the first connecting lead and the fourth sub-lead of the second connecting lead;
  • the ninth connecting lead extends along the first direction and is electrically connected to the first sub-lead of the fifth connecting lead;
  • the tenth connecting lead extends along the first direction and is connected to the third sub-lead of the fifth connecting lead;
  • the drain connection line corresponding to the fifth transistor and the drain connection line corresponding to the first transistor are located on the same straight line, and the orthographic projection of the extension axis on the semiconductor substrate is the same as that of the eleventh connection lead. coincident orthographic projections of the extension axes on said semiconductor substrate;
  • the drain connection line corresponding to the third transistor and the drain connection line corresponding to the second transistor are located on the same straight line, and the orthographic projection of the extension axis on the semiconductor substrate is the same as that of the twelfth connection lead. coincident orthographic projections of the extension axes on said semiconductor substrate;
  • the orthographic projection of the extension axis of the second sub-connection line of the source connection line corresponding to the seventh transistor on the semiconductor substrate, the extension of the second sub-connection line of the source connection line corresponding to the eighth transistor The orthographic projection of the axis on the semiconductor substrate, the orthographic projection of the extension axis of the sixth sub-lead of the fifth connection lead on the semiconductor substrate, the extension axis of the fourteenth connection lead in the The orthographic projection on the semiconductor substrate coincides with the orthographic projection of the extension axis of the fifteenth connection lead on the semiconductor substrate.
  • the first power lead covers the third active area and the fourth active area; the second power lead covers the first active area and the fourth active area. 2. Active area.
  • the display panel is further provided with a pixel driving circuit in the display area, and the pixel driving circuit includes a data writing unit, a storage capacitor and a driving transistor;
  • the data writing unit has a first control electrode and a second control electrode, the first control electrode of the data writing unit is connected to the first output lead, and the second control electrode of the data writing unit is connected to the The second output leads are connected, the input end of the data writing unit is connected to the data line of the display panel, and the output end of the data writing unit is connected to the third node;
  • the first electrode plate of the storage capacitor is connected to the third node, and the second electrode plate of the storage capacitor is used for applying a first driving voltage
  • the control terminal of the driving transistor is connected to the third node, the output terminal of the driving transistor is connected to the light emitting element of the display panel, and the input terminal of the driving transistor can be loaded with a second driving voltage.
  • the first power supply lead is used for loading the first driving voltage; the second power supply lead is used for loading the second driving voltage.
  • the display panel is further provided with a plurality of shift registers and a plurality of inverters corresponding to each of the row driving signal enhancement circuits in the peripheral area;
  • the row drive signal enhancement circuit In the row drive signal enhancement circuit, the shift register and the inverter corresponding to each other, the output terminal of the shift register and the input terminal of the inverter, the row drive signal enhancement circuit
  • the first control lead of the inverter is connected to the first control lead, and the output terminal of the inverter is connected to the second control lead of the row driving signal enhancement circuit.
  • FIG. 1 is a schematic structural diagram of a row driving signal enhancement circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a row driving signal enhancement circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a timing diagram of signals loaded on two control terminals of the row driving signal enhancement circuit in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of positions of active regions and auxiliary doped regions of a semiconductor substrate in a row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a gate layer in a row driving signal enhancement region in an embodiment of the present disclosure.
  • N-type doping of the semiconductor substrate in the row driving signal enhancement region in an embodiment of the present disclosure is a schematic structural diagram of N-type doping of the semiconductor substrate in the row driving signal enhancement region in an embodiment of the present disclosure; the shaded area filled with lines is the N-type doping area.
  • FIG. 8 is a schematic diagram of the location of the N-type doped region and each active region in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of P-type doping of the semiconductor substrate in the row driving signal enhancement region in an embodiment of the present disclosure; the shaded area filled with dots is the P-type doping area.
  • FIG. 10 is a schematic diagram of the location of the P-type doped region, the N-type doped region and each active region in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a P-type doped region, an N-type doped region, a gate layer and each active region in a row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of each first conductive column in the first dielectric layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of the first metal wiring layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 14 shows the P-type doped region, the N-type doped region, each active region, the gate layer, the first conductive column and the first Schematic diagram of the structure of the metal wiring layer.
  • FIG. 15 is a schematic structural diagram of each second conductive column in the second dielectric layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • Fig. 16 is an embodiment of the present disclosure, in the row driving signal enhancement region, the P-type doped region, the N-type doped region, each active region, the gate layer, the first conductive column, the first Schematic diagram of the structure of the metal wiring layer and the second conductive pillar.
  • FIG. 17 is a schematic structural diagram of the second metal wiring layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of the first metal wiring layer, the second conductive pillar and the second metal wiring layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of each third conductive column in the third dielectric layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 20 is a schematic structural diagram of the third metal wiring layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of the second metal wiring layer, the third conductive pillar and the third metal wiring layer in the row driving signal enhancement region in an embodiment of the present disclosure.
  • Fig. 22 is an embodiment of the present disclosure, in the row drive signal enhancement region, the P-type doped region, the N-type doped region, each active region, the gate layer, the first conductive column, the first Schematic diagram of the structure of the metal wiring layer, the second conductive column, the second metal wiring layer, the third conductive column, and the third metal wiring layer.
  • FIG. 23 is a schematic structural diagram of the drive backplane at the QQ' position in FIG. 22 in an embodiment of the present disclosure.
  • FIG. 24 is a schematic structural view of a plurality of row driving signal enhancement regions arranged in sequence on a semiconductor substrate in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and source (source terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows. In cases where transistors of opposite types are used, or when the direction of current changes during circuit operation, the functions of "source” and “drain” may be interchanged. Therefore, in the present disclosure, “source” and “drain” can be interchanged with each other.
  • a transistor can have a first terminal, a second terminal and a control terminal, wherein the gate of the transistor can be used as the control terminal (or control electrode) of the transistor; one of the source and the drain of the transistor can be used as the transistor’s first terminal, and the other can be used as the second terminal of the transistor.
  • the "on" state of a transistor refers to a state in which the source and drain of the transistor are electrically connected.
  • the “off” state of the transistor refers to a state in which the source and the drain of the transistor are electrically disconnected; it can be understood that when the transistor is turned off, leakage current may still exist.
  • two signals are anti-phase signals, it means that one of the signals is a high-level signal and the other signal is a low-level signal.
  • a row driving signal enhancement circuit including:
  • the control unit CRL has a first control terminal IN1 and a second control terminal IN2, and is used to input the first node A and the second node B under the control of the first control terminal IN1 and the second control terminal IN2. a power supply voltage V1, and input a second power supply voltage V2 to the other;
  • the first output unit 130 is connected to the first node A and the first output terminal OUT1, and is used to output one of the first power supply voltage V1 and the second power supply voltage V2 to the first output terminal OUT1 under the control of the first node A;
  • the second output unit 140 is connected to the second node B and the second output terminal OUT2, and is used to output the other of the first power supply voltage V1 and the second power supply voltage V2 to the second output terminal OUT2 under the control of the second node B .
  • the row drive signal enhancement circuit 101 can form a shift register unit with a shift register 102 and an inverter 103; wherein, the shift register 102 is used to output an initial scan signal (ie, the first initial scan signal) to the input terminal of the inverter 103 and the first control terminal IN1 of the row drive signal enhancement circuit 101; the output terminal of the inverter 103 is connected to the second control terminal IN2 of the row drive signal enhancement circuit 101, so that according to the first initial The scan signal generates a second initial scan signal which is an inverted phase of the first initial scan signal.
  • the shift register 102 and the inverter 103 can respectively input two inverted initial scanning signals (the first initial scan signal and the second initial scan signal).
  • the row driving signal enhancement circuit 101 can make the first output unit 130 and the second output unit 140 output two different Two power supply voltages (the first power supply voltage V1 and the second power supply voltage V2) are used as the scan signal of the display panel, that is, the scan signal formed by the first power supply voltage V1 and the second power supply voltage V2 is output.
  • the scanning signal formed by these two power supply voltages can replace the initial scanning signal generated by the shift register 102 and the inverter 103 to control the data writing unit of the pixel driving circuit.
  • the row drive signal enhancement circuit 101 provided in the present disclosure can convert the initial scan signal with weaker drive capability into a scan signal formed by the power supply voltage with stronger drive capability, and can overcome the problem of when the initial scan signal reaches the pixel drive circuit.
  • the row driving signal enhancement circuit 101 provided in the present disclosure is used for improving the row driving capability of a display panel, especially for improving the row driving capability of a silicon-based OLED display.
  • the row driving signal enhancement circuit 101 can generate two scan signals according to the two initial scan signals of the display panel.
  • the scan voltages of the two scan signals are different power supply voltages.
  • it has a greater signal transmission capability to meet the needs of each load on the scan lead, reducing the turn-on delay of each data writing unit. Therefore, the scanning signal generated by the row driving signal enhancement circuit 101 has a stronger driving capability.
  • control unit CRL may include:
  • the first control unit 110 has a first control terminal IN1 and a second control terminal IN2, and is used to output the first power supply voltage V1 to the first node A or the first node A under the control of the first control terminal IN1 and the second control terminal IN2.
  • the second control unit 120 is connected to the first node A and the second node B, and is used for outputting the second power supply voltage V2 to the second node B in response to the first power supply voltage V1 loaded on the first node A, and for responding to The first power supply voltage V1 loaded on the second node B outputs the second power supply voltage V2 to the first node A.
  • the first output unit 130 may further include a first input terminal and a second input terminal, the first input terminal of the first output unit 130 is loaded with the first power supply voltage V1, and the second input terminal of the first output unit 130 The second supply voltage V2 is applied.
  • the first input terminal of the first output unit 130 is connected to the power source providing the first power voltage V1 through wires, and the second input end of the first output unit 130 is connected to the power source providing the second power voltage V2 through wires.
  • the first output unit 130 can directly output any one of the loaded first power supply voltage V1 and the second power supply voltage V2 to the first output terminal OUT1, without generating the first power supply voltage V1 and the second power supply voltage V1 through voltage regulation.
  • the power supply voltage V2 can further ensure that the signal output by the first output terminal OUT1 is not only the first power supply voltage V1 or the second power supply voltage V2 in voltage, but also can ensure that the scanning signal output by the first output terminal OUT1 has stronger
  • the drive capability can meet the needs of each load on each scan lead.
  • the second output unit 140 may further include a first input terminal and a second input terminal, the first input terminal of the second output unit 140 is loaded with the first power supply voltage V1, and the second output unit 140 is loaded with the first power supply voltage V1.
  • the second input terminal of the second output unit 140 is loaded with the second power supply voltage V2.
  • the first input terminal of the second output unit 140 is connected to the power source providing the first power voltage V1 through the wire, and the second input end of the second output unit 140 is connected to the power source providing the second power voltage V2 through the wire.
  • the second output unit 140 can directly output any one of the loaded first power supply voltage V1 and the second power supply voltage V2 to the second output terminal OUT2, without generating the first power supply voltage V1 and the second power supply voltage V1 through voltage regulation.
  • the power supply voltage V2 can ensure that the signal output by the second output terminal OUT2 is not only the first power supply voltage V1 or the second power supply voltage V2 in voltage, but also can ensure that the scanning signal output by the second output terminal OUT2 has stronger
  • the drive capability can meet the needs of each load on each scan lead.
  • the second control unit 120 has at least two groups of transistors, and each group of transistors includes at least two transistors of the same type. That is, the second control unit 120 has at least four transistors. Among them, in a group of transistors, each transistor is connected in parallel, that is, the sources of each transistor in the same group are electrically connected to each other, the drains are electrically connected to each other, and the gates are electrically connected to each other; in this way, the signal delay (RC) of each transistor can be reduced. delay), increase the turn-on speed of each group of transistors and ensure the driving capability of each group of transistors, and reduce the signal delay of the second control unit 120.
  • RC signal delay
  • the type of a transistor refers to whether the transistor is an N-type transistor or a P-type transistor. Wherein, when two or more transistors are of the same type, it means that the two or more transistors are all N-type transistors, or both are P-type transistors.
  • the first control unit 110 may include:
  • the first transistor M1 has a first terminal for loading the first power supply voltage V1, a second terminal connected to the first node A, and a control terminal as the first control terminal IN1; the first transistor M1 is used for, in the first transistor Outputting the first power supply voltage V1 to the first node A under the control of the control terminal of M1;
  • the second transistor M2 has a first terminal for loading the first power supply voltage V1, a second terminal connected to the second node B, and a control terminal as the second control terminal IN2; the second transistor M2 is used for, in the second transistor Outputting the first power supply voltage V1 to the second node B under the control of the control terminal of M2;
  • Both the first transistor M1 and the second transistor M2 are N-type transistors or both are P-type transistors.
  • the first control terminal IN1 and the second control terminal IN2 of the first control unit 110 are respectively loaded with an inverted first initial scan signal and a second initial scan signal. Signal. Therefore, the control terminals of the first transistor M1 and the second transistor M2 are respectively loaded with two initial scan signals in opposite phases.
  • the first transistor M1 and the second transistor M2 are of the same type, for example, both are N-type transistors or both are P-type transistors, which not only facilitates the preparation of transistors, but also enables the first transistor M1 and the second transistor M2 to be turned on alternatively , so that the first control unit 110 alternatively outputs the first power supply voltage V1 to the first node A or the second node B.
  • the working process of the first control unit 110 make an introduction.
  • FIG. 3 is a timing diagram of two initial scan signals loaded on the first control terminal IN1 and the second control terminal IN2.
  • the first control terminal IN1 is loaded with a low-level base voltage during the T1 and T3 phases, and is loaded with a high-level first initial scan signal during the T2 phase.
  • the second control terminal IN2 is loaded with a high-level base voltage during the T1 and T3 phases, and is loaded with a low-level second initial scan signal during the T2 phase. Therefore, the signals on the first control terminal IN1 and the second control terminal IN2 keep inverse phase, and one is at a high level while the other is at a low level.
  • the first control terminal IN1 is loaded with a low-level signal and the second control terminal IN2 is loaded with a high-level signal, so that the second transistor M2 is turned on and the first transistor M1 is turned off, and the first control unit 110 outputs the first A supply voltage V1 to the second node B.
  • the first control terminal IN1 is loaded with a high-level signal and the second control terminal IN2 is loaded with a low-level signal, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and the first control unit 110 outputs the first power supply voltage V1 to the first node A.
  • the second control unit 120 may include:
  • the third transistor M3 has a control terminal connected to the first node A, a first terminal used to load the second power supply voltage V2, and a second terminal connected to the second node B; the third transistor M3 is used for loading the first Outputting the second power supply voltage V2 to the second node B under the control of the first power supply voltage V1 on the node A;
  • the fourth transistor M4 has a control terminal connected to the first node A, a first terminal used to load the second power supply voltage V2, and a second terminal connected to the second node B; the fourth transistor M4 is used to load the first Outputting the second power supply voltage V2 to the second node B under the control of the first power supply voltage V1 on the node A;
  • the fifth transistor M5 has a control terminal connected to the second node B, a first terminal used for loading the second power supply voltage V2, and a second terminal connected to the first node A; the fifth transistor M5 is used for loading the second power supply voltage V2 Outputting the second power supply voltage V2 to the first node A under the control of the first power supply voltage V1 on the node B;
  • the sixth transistor M6 has a control terminal connected to the second node B, a first terminal used to load the second power supply voltage V2, and a second terminal connected to the first node A; the sixth transistor M6 is used for loading the second power supply voltage V2 The second power supply voltage V2 is output to the first node A under the control of the first power supply voltage V1 on the node B.
  • the types of the third transistor M3 to the sixth transistor M6 are the same, all being N-type transistors or all being P-type transistors.
  • the first power supply voltage V1 is lower than the second power supply voltage V2, and the third transistor M3 to the sixth transistor M6 are P-type transistors; or, the first power supply voltage V1 is higher than the second power supply voltage V2, and the third transistor M3 to the sixth transistor M6 are P-type transistors;
  • the sixth transistor M6 is an N-type transistor. In other words, when the control terminal of any one of the third transistor M3 to the sixth transistor M6 is loaded with the first power supply voltage V1, the transistor can be turned on; the control of any one of the third transistor M3 to the sixth transistor M6 When the terminal is loaded with the second power supply voltage V2, the transistor can be turned off.
  • the working process of the second control unit 120 will be explained and illustrated by taking the first power supply voltage V1 lower than the second power supply voltage V2 and the third transistor M3 to the sixth transistor M6 being P-type transistors as an example.
  • the first control unit 110 applies the first power supply voltage V1 to the first node A
  • the first control unit 110 does not apply voltage to the second node B
  • the third transistor M3 and the fourth transistor M4 is turned on to output the second power supply voltage V2 to the second node B.
  • the first node A is loaded with the first power supply voltage V1
  • the second node B is loaded with the second power supply voltage V2.
  • the first control unit 110 applies the first power supply voltage V1 to the second node B
  • the first control unit 110 does not apply voltage to the first node A
  • the fifth transistor M5 and the second The six transistors M6 are turned on to output the second power supply voltage V2 to the first node A.
  • the second node B is loaded with the first power supply voltage V1
  • the first node A is loaded with the second power supply voltage V2. It can be seen from this that no matter what working state the first control unit 110 and the second control unit 120 are in, the first node A and the second node B are respectively loaded with two different power supply voltages, which are the first power supply voltage V1 and The second power supply voltage V2.
  • the first node A and the second node B can be respectively loaded with two Different power supply voltages, the principle and process of which will not be repeated in this disclosure.
  • the first output unit 130 may include:
  • the seventh transistor M7 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal serving as the first output terminal OUT1;
  • the eighth transistor M8 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the first output terminal OUT1;
  • the ninth transistor M9 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1;
  • the tenth transistor M10 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1;
  • the second output unit 140 includes:
  • the eleventh transistor M11 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal serving as the first output terminal OUT1;
  • the twelfth transistor M12 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the second output terminal OUT2;
  • the thirteenth transistor M13 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2;
  • the fourteenth transistor M14 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2;
  • any one of the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 is used for responding to one of the first power supply voltage V1 and the second power supply voltage V2 applied to its control terminal. is turned on, and any one of the ninth transistor M9 to the twelfth transistor M12 is used to be turned on in response to the other of the first power supply voltage V1 and the second power supply voltage V2 applied to its control terminal.
  • the types of the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are the same; the types of the ninth transistor M9 to the twelfth transistor M12 are the same; the seventh transistor M7, the eighth transistor M8 The types of the thirteenth transistor M13 and the fourteenth transistor M14 are different from those of the ninth transistor M9 to the twelfth transistor M12.
  • two different power supply voltages namely, the first power supply voltage V1 and the second power supply voltage V2
  • the first output unit 130 and the second output unit 140 respectively output two different power supply voltages (namely the first power supply voltage V1 and the second power supply voltage V2).
  • the seventh transistor M7 and the eighth transistor M8 of the first output unit 130 are arranged in parallel, and the ninth transistor M9 and the tenth transistor M10 are arranged in parallel; this can increase the magnitude of the current output by the first output unit 130 and further The driving capability of the first output unit 130 is guaranteed, and the RC delay of the first output unit 130 can be reduced.
  • the eleventh transistor M11 and the twelfth transistor M12 of the second output unit 140 are arranged in parallel, and the thirteenth transistor M13 and the fourteenth transistor M14 are arranged in parallel; this can increase the magnitude of the current output by the second output unit 140 Furthermore, the driving capability of the second output unit 140 is ensured, and the RC delay of the second output unit 140 can be reduced.
  • the first power supply voltage V1 may be a low-level signal
  • the second power supply voltage V2 may be a high-level signal
  • the third transistor M13 and the fourteenth transistor M14 may be N-type transistors
  • the ninth transistor M9 to the twelfth transistor M12 may be P-type transistors.
  • the seventh transistor M7 and the eighth transistor M8 are turned off while the ninth transistor M9 and the tenth transistor M10 are turned on, and the first output unit 130 outputs the second Supply voltage V2.
  • B is loaded with the second power supply voltage V2
  • the eleventh transistor M11 and the twelfth transistor M12 are turned off and the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, and the second output unit 140 outputs The first supply voltage V1.
  • the seventh transistor M7 and the eighth transistor M8 are turned on and the ninth transistor M9 and the tenth transistor M10 are turned off, and the first output unit 130 passes the first output terminal OUT1
  • the first power supply voltage V1 is output.
  • B is loaded with the first power supply voltage V1
  • the eleventh transistor M11 and the twelfth transistor M12 are turned on and the thirteenth transistor M13 and the fourteenth transistor M14 are turned off, and the second output unit 140 outputs the The second power supply voltage V2.
  • the first transistor M1 to the fourteenth transistor M14 may be MOS (Metal Oxide Semiconductor, metal oxide semiconductor) transistors.
  • a row driving signal enhancement circuit 101 and its working process are exemplarily introduced, so as to further explain and illustrate the principle, structure and effect of the row driving signal enhancement circuit 101 of the present disclosure.
  • the exemplary row driving signal enhancement circuit 101 includes a first control unit 110 , a second control unit 120 , a first output unit 130 and a second output unit 140 .
  • the first control unit 110 includes a first transistor M1 and a second transistor M2, and both the first transistor M1 and the second transistor M2 are N-type transistors.
  • the first transistor M1 has a first terminal for loading the first power supply voltage V1, a second terminal connected to the first node A, and a control terminal as the first control terminal IN1.
  • the second transistor M2 has a first terminal for loading the first power supply voltage V1, a second terminal connected to the second node B, and a control terminal as the second control terminal IN2.
  • the first control terminal IN1 and the second control terminal IN2 of the row driving signal enhancement circuit 101 can load two inverted initial scan signals, one of which is a high-level signal and the other is a low-level signal.
  • the first transistor M1 and the second transistor M2 can be turned on in response to a high-level signal applied to the respective control terminals, and can be turned off in response to a low-level signal applied to the respective control terminals.
  • the second control unit 120 includes a third transistor M3 to a sixth transistor M6, and the third transistor M3 to the sixth transistor M6 are all P-type transistors.
  • the third transistor M3 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2 and a second terminal connected to the second node B.
  • the fourth transistor M4 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2 and a second terminal connected to the second node B.
  • the fifth transistor M5 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2 and a second terminal connected to the first node A.
  • the sixth transistor M6 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2 and a second terminal connected to the first node A.
  • one of the first node A and the second node B is loaded with the first power supply voltage V1, and the other is loaded with the second power supply voltage V2; wherein, the first power supply voltage V1 can be Low level and the second power supply voltage V2 is high level, so that the third transistor M3 to the sixth transistor M6 can be turned on in response to the first power supply voltage V1 applied to the respective control terminals, and can respond to the voltage applied to the respective control terminals.
  • the second power supply voltage V2 is cut off.
  • the first output unit 130 includes a seventh transistor M7 to a tenth transistor M10, and the seventh transistor M7 and the eighth transistor M8 are N-type transistors, and the ninth transistor M9 and the tenth transistor M10 are P-type transistors.
  • the seventh transistor M7 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1, and a second terminal serving as the first output terminal OUT1.
  • the eighth transistor M8 has a control terminal connected to the first node A, a first terminal for loading the first power supply voltage V1 and a second terminal connected to the first output terminal OUT1.
  • the ninth transistor M9 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1.
  • the tenth transistor M10 has a control terminal connected to the first node A, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the first output terminal OUT1.
  • the second output unit 140 includes an eleventh transistor M11 to a fourteenth transistor M14, and the eleventh transistor M11 and the twelfth transistor M12 are P-type transistors, and the thirteenth transistor M13 and the fourteenth transistor M14 are N-type transistors .
  • the eleventh transistor M11 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal serving as the second output terminal OUT2.
  • the twelfth transistor M12 has a control terminal connected to the second node B, a first terminal for loading the second power supply voltage V2, and a second terminal connected to the second output terminal OUT2.
  • the thirteenth transistor M13 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2.
  • the fourteenth transistor M14 has a control terminal connected to the second node B, a first terminal for loading the first power supply voltage V1, and a second terminal connected to the second output terminal OUT2.
  • the first power supply voltage V1 is at a low level
  • the second power supply voltage V2 is at a high level
  • the first power supply voltage V1 and the second power supply voltage V2 are antiphase Two initial scan signals.
  • the control terminal of the N-type transistor is loaded with the first power supply voltage V1
  • the N-type transistor is turned off; when the control terminal of the N-type transistor is loaded with the second power supply voltage V2, the N-type transistor is turned on; when the control terminal of the P-type transistor
  • the first power supply voltage V1 is loaded, the N-type transistor is turned on; when the control terminal of the P-type transistor is loaded with the second power supply voltage V2, the P-type transistor is turned off.
  • the first output terminal OUT1 and the second output terminal OUT2 respectively output two inverted scan signals. Signal.
  • the first control terminal IN1 is loaded with the first power supply voltage V1 and the second control terminal IN2 is loaded with the second power supply voltage V2, the first transistor M1 is turned off and the second transistor M2 is turned on, so that The first supply voltage V1 is applied to B through the second transistor M2.
  • the fifth transistor M5 and the sixth transistor M6 are turned on in response to the first supply voltage V1 applied on B, so that the second supply voltage V2 is applied to A through the fifth transistor M5 and the sixth transistor M6.
  • the third transistor M3 and the fourth transistor M4 are turned off in response to the second power supply voltage V2 applied to A, so that the signal applied to B is locked to the first power supply voltage V1.
  • the seventh transistor M7 and the eighth transistor M8 are turned on in response to the second power supply voltage V2 applied to A, and the ninth transistor M9 and the tenth transistor M10 are turned off in response to the second power supply voltage V2 applied to A, so that the first The power supply voltage V1 is loaded to the first output terminal OUT1 through the seventh transistor M7 and the eighth transistor M8; that is, the first output terminal OUT1 of the row driving signal enhancement circuit 101 outputs the first power supply voltage V1.
  • the eleventh transistor M11 and the twelfth transistor M12 are turned on in response to the first power supply voltage V1 applied to B, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned off in response to the first power supply voltage V1 applied to B.
  • the first control terminal IN1 is loaded with the second power supply voltage V2 and the second control terminal IN2 is loaded with the first power supply voltage V1
  • the first transistor M1 is turned on and the second transistor M2 is turned off, so that The first power supply voltage V1 is loaded to A through the first transistor M1.
  • the third transistor M3 and the fourth transistor M4 are turned on in response to the first supply voltage V1 applied on A, so that the second supply voltage V2 is applied to B through the third transistor M3 and the fourth transistor M4.
  • the fifth transistor M5 and the sixth transistor M6 are turned off in response to the second power supply voltage V2 applied to B, so that the signal applied to A is locked to the first power supply voltage V1.
  • the seventh transistor M7 and the eighth transistor M8 are turned off in response to the first power supply voltage V1 applied to A, and the ninth transistor M9 and the tenth transistor M10 are turned on in response to the first power supply voltage V1 applied to A, so that the second The power supply voltage V2 is loaded to the first output terminal OUT1 through the ninth transistor M9 and the tenth transistor M10; that is, the first output terminal OUT1 of the row driving signal enhancement circuit 101 outputs the second power supply voltage V2.
  • the eleventh transistor M11 and the twelfth transistor M12 are turned off in response to the second power supply voltage V2 applied to B, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned on in response to the second power supply voltage V2 applied to B. , so that the first power supply voltage V1 is loaded to the second output terminal OUT2 through the thirteenth transistor M13 and the fourteenth transistor M14; that is, the second output terminal OUT2 of the row driving signal enhancement circuit 101 outputs the first power supply voltage V1.
  • one of the first power supply voltage V1 and the second power supply voltage V2 may be a ground voltage (GND), that is, a reference voltage of the display panel.
  • the other can be the voltage VDD applied to the source of the driving transistor by the pixel driving circuit during the light-emitting phase.
  • the embodiment of the present disclosure also provides a shift register unit.
  • the shift register unit includes any row drive signal enhancement circuit 101 described in the above embodiment of the row drive signal enhancement circuit 101 , and includes a shift register 102.
  • An inverter 103 is used to output the first initial scan signal to the input terminal of the inverter 103 and the first control terminal IN1 of the row drive signal enhancement circuit 101; the output terminal of the inverter 103 is connected to the row drive signal enhancement circuit 101 The second control terminal IN2.
  • the shift register unit can generate an initial scan signal (including an inverted first initial scan signal and a second initial scan signal), and then convert the initial scan signal to into a scanning signal; the scanning voltage and the base value voltage of the scanning signal are different power supply voltages (respectively the first power supply voltage V1 and the second power supply voltage V2), thereby improving the driving capability of the scanning signal and overcoming the problem of the scanning signal when scanning Defects of large delay and large voltage drop on the lead.
  • the shift register unit has any one of the row driving signal enhancing circuits 101 described in the row driving signal enhancing circuit implementation manner above, it has the same beneficial effect, and the present disclosure will not repeat them here.
  • Embodiments of the present disclosure also provide a display panel, which includes any shift register unit described in the above embodiment of the shift register unit.
  • the display panel can be an OLED (organic electroluminescent diode) display panel, a liquid crystal display panel, a Micro LED (micro light emitting diode) display panel or other types of display panels, especially a silicon-based OLED display panel, a silicon-based liquid crystal display panel. Since the display panel has any shift register unit described in the implementation manners of the above shift register unit, it has the same beneficial effect, and the present disclosure will not repeat them here.
  • the present disclosure also provides a display panel, which may include a driving backplane and a display layer stacked on the driving backplane.
  • the driving backplane includes a semiconductor substrate 310 , a gate insulating layer 320 , a gate layer 330 , an insulating dielectric layer 340 and a metal wiring layer 360 which are sequentially stacked.
  • the display panel includes a display area D and a peripheral area E located on at least one side of the display area D; referring to FIG. 24 , a plurality of row driving signal enhancement areas F are arranged in the peripheral area E.
  • the peripheral area E surrounds the display area D. As shown in FIG.
  • FIG. 5 is a schematic structural diagram of the semiconductor substrate 310 in the row driving signal enhancement region F. Referring to FIG. In FIG. 5 , only the positions of the respective active regions are shown, as well as the positions of the N-type substrate region F_Ndop and the P-type substrate region F_Pdop of the row driving signal enhancement region F, and the like.
  • the display panel is provided with a row driving signal enhancing circuit 101 including a first transistor M1 to a fourteenth transistor M14; wherein, the first transistor M1 and the second transistor M2 are of the same type; the fifth transistor The types of M5, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are the same; the types of the ninth transistor M9 to the twelfth transistor M12 are the same, and are opposite to the type of the fifth transistor M5; the third transistor M3 to the sixth transistor M6 are of the same type.
  • the active area of each transistor is formed on the semiconductor substrate 310, and the active area of any one transistor includes a channel area, source and drain on both sides of the channel area; the gate layer 330 is formed with the gate of each transistor, and The gate insulating layer 320 isolates the gate and channel regions of any one transistor. Referring to FIG. 23 , the insulating dielectric layer 340 covers the gate layer 330 .
  • the metal wiring layer 360 is provided with connection leads, first power lead 411, second power lead 412, first control lead 421, second control lead 422, first output lead 431 and second output leads 432 .
  • the connection lead is electrically connected to the source, drain and gate of each transistor through the conductive column located in the insulating medium layer 340; wherein, the connection lead makes the gate M1G of the first transistor M1 electrically connected to the first control lead 421, and The gate M2G of the second transistor M2 is electrically connected to the second control lead 422, and the source of the first transistor M1, the source of the second transistor M2, the source of the seventh transistor M7, and the source of the eighth transistor M8 pole, the source of the thirteenth transistor M13, and the source of the fourteenth transistor M14 are electrically connected to the first power lead 411, and make the sources of the third transistor M3 to the sixth transistor M6, the ninth transistor M9 to the tenth transistor
  • the source of the second transistor M12 is electrically connected to the second power lead 412
  • the equivalent circuit of the row driving signal enhancement circuit 101 is shown in FIG. 2 .
  • the working process and effects of the row driving signal enhancement circuit 101 have been introduced in detail in the above-mentioned implementation of the row driving signal enhancement circuit 101 , and will not be repeated here.
  • the display panel is provided with a row driving signal enhancement circuit 101, so the row driving capability of the display panel can be improved, and the display uniformity of the display panel can be improved.
  • the first power supply lead 411 may be loaded with the first power supply voltage V1
  • the second power supply lead 412 may be loaded with the second power supply voltage V2.
  • the first control lead 421 can serve as the first control terminal IN1 of the row driving signal enhancement circuit 101
  • the second control lead 422 can serve as the second control terminal IN2 of the row drive signal enhancement circuit 101 .
  • the first output lead 431 can serve as the first output terminal OUT1 of the row driving signal enhancement circuit 101
  • the second output lead 432 can serve as the second output terminal OUT2 of the row drive signal enhancement circuit 101 .
  • the first transistor M1, the second transistor M2, the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, and the fourteenth transistor M14 are N-type transistors;
  • the third transistor M3 , the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are P-type transistors.
  • each transistor can be formed by using a CMOS (Complementary Metal Oxide Semiconductor) process, without introducing an additional process to increase the cost of the display panel.
  • CMOS Complementary Metal Oxide Semiconductor
  • the semiconductor substrate 310 may be a silicon-based semiconductor substrate, especially a single crystal silicon semiconductor substrate 310 .
  • any one of the row drive signal enhancement regions F includes a P-type substrate region F_Pdop and an N-type substrate region F_Ndop, and the P-type substrate region F_Pdop is located in the first direction G of the N-type substrate region F_Ndop. side, the first direction G is a direction away from the display region D; the N-type transistor is formed in the P-type substrate region F_Pdop, and the P-type transistor is formed in the N-type substrate region F_Ndop.
  • the N-type substrate region F_Ndop includes an N-type auxiliary doped region F_Ndummy, and includes a first active region Act1 and a second active region respectively surrounded by an N-type auxiliary doped region F_Ndummy Act2; the second active region Act2 is located on the first direction G side of the first active region Act1;
  • the first active region Act1 includes a first sub-active region Act_sub1 and a second sub-active region Act_sub2 sequentially arranged along the first direction G; the ninth transistor M9 and the eleventh transistor M11 are located in the first sub-active region Act_sub1, The tenth transistor M10 and the twelfth transistor M12 are located in the second sub-active region Act_sub2;
  • the second active region Act2 includes a third sub-active region Act_sub3 and a fourth sub-active region Act_sub4 sequentially arranged along a second direction H; the second direction H is perpendicular to the first direction G and parallel to the plane of the semiconductor substrate 310;
  • the fifth transistor M5 and the sixth transistor M6 are located in the third sub-active area Act_sub3, and the third transistor M3 and the fourth transistor M4 are located in the fourth sub-active area Act_sub4.
  • the arrangement of the transistors can improve the compactness of the arrangement of the transistors, reduce the area ratio of the row driving signal enhancement circuit 101 and reduce the length of connecting leads, and reduce the power consumption of the row driving signal enhancement circuit 101 .
  • the N-type auxiliary doped region F_Ndummy can reduce the leakage of each transistor, and further reduce the power consumption of the row driving signal enhancement circuit 101 .
  • the N-type auxiliary doped region F_Ndummy may include a first N-type doped sub-region F_Nsub1 to a seventh N-type doped sub-region F_Nsub7 .
  • the first N-type doped sub-region F_Nsub1, the third N-type doped sub-region F_Nsub3, the fifth N-type doped sub-region F_Nsub5 and the seventh N-type doped sub-region F_Nsub7 extend along the first direction G
  • the second The N-type doped sub-region F_Nsub2 , the fourth N-type doped sub-region F_Nsub4 and the sixth N-type doped sub-region F_Nsub6 extend along the second direction H.
  • the first N-type doped sub-region F_Nsub1, the second N-type doped sub-region F_Nsub2, the third N-type doped sub-region F_Nsub3 and the fourth N-type doped sub-region F_Nsub4 are sequentially connected to form a closed ring
  • the first active Region Act1 is located in the space surrounded by the first N-type doped sub-region F_Nsub1, the second N-type doped sub-region F_Nsub2, the third N-type doped sub-region F_Nsub3 and the fourth N-type doped sub-region F_Nsub4
  • the N-type doped sub-region F_Nsub4, the fifth N-type doped sub-region F_Nsub5, the sixth N-type doped sub-region F_Nsub6 and the seventh N-type doped sub-region F_Nsub7 are sequentially connected to form a closed ring
  • the second active region Act2 Located in the space surrounded by the fourth N-type doped sub-region F_Nsub4
  • the fifth N-type doped sub-region F_Nsub5 is located on the first direction G side of the first N-type doped sub-region F_Nsub1, and is located on the extension line of the first N-type doped sub-region F_Nsub1 along the first direction G; the seventh The N-type doped sub-region F_Nsub7 is located on one side of the third N-type doped sub-region F_Nsub3 in the first direction G, and is located on the extension line of the third N-type doped sub-region F_Nsub3 along the first direction G.
  • the second N-type doped sub-region F_Nsub2 , the fourth N-type doped sub-region F_Nsub4 and the sixth N-type doped sub-region F_Nsub6 are arranged in sequence along the first direction G.
  • the size of the fifth N-type doped sub-region F_Nsub5 in the second direction H is smaller than the size of the first N-type doped sub-region F_Nsub1 in the second direction H, and the seventh N-type doped sub-region
  • the size of the sub-region F_Nsub7 in the second direction H is smaller than the size of the third N-type doped sub-region F_Nsub3 in the second direction H.
  • the size of the second active region Act2 in the second direction H can be increased, thereby facilitating the arrangement of the third sub-active region Act_sub3 and the fourth sub-active region arranged along the second direction H in the second active region Act2 Act_sub4.
  • the size of the first sub-active region Act_sub1 in the first direction G is the same as the size of the second sub-active region Act_sub2 in the first direction G; the first sub-active region Act_sub1 is in the second direction H
  • the size of is the same as the size of the second sub-active region Act_sub2 in the second direction H. This facilitates the size of the ninth transistor M9 and the tenth transistor M10 to be the same, and facilitates the size of the eleventh transistor M11 and the twelfth transistor M12 to be the same.
  • the size of the third sub-active region Act_sub3 in the first direction G is the same as the size of the fourth sub-active region Act_sub4 in the first direction G; the size of the third sub-active region Act_sub3 in the second direction H The size in the second direction H is the same as that of the fourth sub-active region Act_sub4. This facilitates making the sizes of the third transistor M3 to the sixth transistor M6 the same.
  • the size of the first sub-active region Act_sub1 is 3 to 5 times the size of the third sub-active region Act_sub3, and the size of the second sub-active region Act_sub2 is 3-5 times the size of the third sub-active region Act_sub3.
  • the channel regions of the ninth transistor M9 to the twelfth transistor M12 can have larger widths, and the current output capability of the ninth transistor M9 to the twelfth transistor M12 can be improved, thereby improving the driving of the row driving signal enhancement circuit 101 ability.
  • the third transistor M3 to the sixth transistor M6 can have a smaller size, especially a smaller channel region, which can increase the turn-on speed or turn-off speed of the third transistor M3 to the sixth transistor M6, and reduce The signal delay caused by the third transistor M3 to the sixth transistor M6 further reduces the signal delay of the row driving signal enhancement circuit 101 .
  • the P-type substrate region F_Pdop includes a P-type auxiliary doped region F_Pdummy, a third active region Act3 and a fourth active region Act4; the fourth active region Act4 is located in the third active region The first direction G side of the area Act3.
  • the third active region Act3 is surrounded by the P-type auxiliary doped region F_Pdummy, and includes the fifth sub-active region Act_sub5 and the sixth sub-active region Act_sub6 arranged in sequence along the first direction G; the seventh transistor M7 and the thirteenth transistor The transistor M13 is located in the fifth sub-active area Act_sub5, and the eighth transistor M8 and the fourteenth transistor M14 are located in the sixth sub-active area Act_sub6.
  • the fourth active region Act4 includes the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8 which are arranged in sequence along the second direction H and are respectively surrounded by the P-type auxiliary doped region F_Pdummy; the first transistor M1 is located in the seventh sub-active region In the active region Act_sub7, the second transistor M2 is located in the eighth sub-active region Act_sub8.
  • the arrangement of the transistors can improve the compactness of the arrangement of the transistors, reduce the area ratio of the row driving signal enhancement circuit 101 and reduce the length of connecting leads, and reduce the power consumption of the row driving signal enhancement circuit 101 .
  • the P-type auxiliary doped region F_Pdummy can reduce the leakage of each transistor, and further reduce the power consumption of the row driving signal enhancement circuit 101 .
  • the P-type auxiliary doped region F_Pdummy may include a first P-type doped sub-region F_Psub1 to an eighth P-type doped sub-region F_Psub8 .
  • the first P-type doped sub-region F_Psub1, the third P-type doped sub-region F_Psub3, the fifth P-type doped sub-region F_Psub5, the seventh P-type doped sub-region F_Psub7 and the eighth P-type doped sub-region F_Psub8 extends along the first direction G
  • the second P-type doped sub-region F_Psub2 , the fourth P-type doped sub-region F_Psub4 and the sixth P-type doped sub-region F_Psub6 extend along the second direction H.
  • the first P-type doped sub-region F_Psub1, the second P-type doped sub-region F_Psub2, the third P-type doped sub-region F_Psub3 and the fourth P-type doped sub-region F_Psub4 are sequentially connected to form a closed ring
  • the third active region Act3 is located in the space surrounded by the first P-type doped sub-region F_Psub1, the second P-type doped sub-region F_Psub2, the third P-type doped sub-region F_Psub3 and the fourth P-type doped sub-region F_Psub4 Inside; the fifth P-type doped sub-region F_Psub5, the sixth P-type doped sub-region F_Psub6, the seventh P-type doped sub-region F_Psub7 and the fourth P-type doped sub-region F_Psub4 are sequentially connected to form a closed ring, and the fourth The active region Act4 is located in a space surrounded by the fifth P-type doped sub-
  • Both ends of the eighth P-type doped sub-region F_Psub8 are respectively connected to the fourth P-type doped sub-region F_Psub4 and the sixth P-type doped sub-region F_Psub6, wherein the seventh sub-active region Act_sub7 is located in the fifth P-type doped sub-region.
  • the eighth sub-active region Act_sub8 is located in the eighth In the space surrounded by the P-type doped sub-region F_Psub8 , the sixth P-type doped sub-region F_Psub6 , the seventh P-type doped sub-region F_Psub7 and the fourth P-type doped sub-region F_Psub4 .
  • the fifth P-type doped sub-region F_Psub5 is located on one side of the first P-type doped sub-region F_Psub1 in the first direction G, and is located on the extension line of the first P-type doped sub-region F_Psub1 along the first direction G.
  • the seventh P-type doped sub-region F_Psub7 is located on the side of the third P-type doped sub-region F_Psub3 in the first direction G, and is located on the extension line of the third P-type doped sub-region F_Psub3 along the first direction G.
  • the second P-type doped sub-region F_Psub2, the fourth P-type doped sub-region F_Psub4 and the sixth P-type doped sub-region F_Psub6 are arranged in sequence along the first direction G, the fifth P-type doped sub-region F_Psub5, the eighth P-type doped sub-region The P-type doped sub-region F_Psub8 and the seventh P-type doped sub-region F_Psub7 are arranged in sequence along the second direction H.
  • the size of the fifth P-type doped sub-region F_Psub5 in the second direction H is smaller than the size of the first P-type doped sub-region F_Psub1 in the second direction H, and the seventh P-type doped sub-region F_Psub1
  • the size of the sub-region F_Psub7 in the second direction H is smaller than the size of the third P-type doped sub-region F_Psub3 in the second direction H.
  • the size of the fourth active region Act4 in the second direction H can be increased, more space can be provided for the arrangement of the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8, and it can also be used for the arrangement of the eighth P-type active region.
  • the doped sub-region F_Psub8 provides space.
  • the size of the fifth sub-active region Act_sub5 in the first direction G is the same as the size of the sixth sub-active region Act_sub6 in the first direction G; the sixth sub-active region Act_sub6 is in the second direction H
  • the size of is the same as the size of the fifth sub-active region Act_sub5 in the second direction H. This facilitates the size of the seventh transistor M7 and the eighth transistor M8 to be the same, and facilitates the size of the thirteenth transistor M13 and the fourteenth transistor M14 to be the same.
  • the size of the seventh sub-active region Act_sub7 in the first direction G is the same as the size of the eighth sub-active region Act_sub8 in the first direction G; the seventh sub-active region Act_sub7 is in the second direction H
  • the size of is the same as the size of the eighth sub-active region Act_sub8 in the second direction H. This facilitates making the size of the first transistor M1 and the second transistor M2 the same.
  • the size of the seventh sub-active region Act_sub7 is 1.5 to 2.5 times the size of the fifth sub-active region Act_sub5; the size of the seventh sub-active region Act_sub7 The size is the same as that of the eighth sub-active region Act_sub8; the size of the fifth sub-active region Act_sub5 is the same as that of the sixth sub-active region Act_sub6.
  • the gate layer 330 is formed with the gates of the first transistor M1 to the fourteenth transistor M14 , and the gate insulating layer 320 isolates the gate of any one of the transistors from the channel region.
  • the gates of the respective transistors extend along the first direction G.
  • each transistor when forming each transistor, a CMOS process may be used for fabrication.
  • each transistor of the row driving signal enhancing circuit 101 can be formed in the row driving signal enhancing region F by the following method.
  • a P-type semiconductor substrate 310 may first be provided, and the P-type semiconductor substrate 310 has a first region and a second region in the row driving signal enhancement region F.
  • the first region can be used as a P-type substrate region F_Pdop, which has a P well.
  • N-type ions can be implanted in the second region to form an N well in the second region, which is an N-type substrate region F_Ndop.
  • a gate insulating layer 320 (not shown in the figure) and a gate layer 330 may be formed, so that the gate insulating layer 320 and the gate layer 330 cover the channel regions of each transistor and expose The source and drain of each transistor.
  • the material of the gate insulating layer 320 may be inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride and the like.
  • the material of the gate layer 330 may be polysilicon.
  • N-type ion implantation can be performed on each active region of the P-type substrate region F_Pdop and the N-type auxiliary doped region F_Ndummy of the N-type substrate region F_Ndop.
  • the source and drain electrodes of each transistor located in the P-type substrate region F_Pdop are transformed into N-type doping, and then each N-type transistor is formed in the P-type substrate region F_Pdop; the doping of the N-type auxiliary doped region F_Ndummy
  • P-type ion implantation can be performed on each active region of the N-type substrate region F_Ndop and the P-type auxiliary doped region F_Pdummy of the P-type substrate region F_Pdop.
  • the source and drain electrodes of each transistor located in the N-type substrate region F_Ndop are transformed into P-type doping, and then each P-type transistor is formed in the N-type substrate region F_Ndop; the doping of the P-type auxiliary doped region F_Pdummy
  • the part of each active region overlapping with the gate can be used as the channel region of each transistor.
  • the gate can block the ion implantation of ions into the active region, thereby making it maintain semiconductor characteristics.
  • the gate M1G of the first transistor M1 includes a first gate M1G1 and a second gate M1G2, and the first gate M1G1 of the first transistor M1 and the first transistor M1
  • the second grids M1G2 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the seventh sub-active region Act_sub7 with the first gate M1G1 of the first transistor M1 and the second gate M1G2 of the first transistor M1 serves as a channel region of the first transistor M1.
  • the channel region of the first transistor M1 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the first transistor M1 overlaps with the first gate M1G1 of the first transistor M1 , the second channel region of the first transistor M1 overlaps with the second gate M1G2 of the first transistor M1.
  • the drain M1D of the first transistor M1 is located between the first channel region of the first transistor M1 and the second channel region of the first transistor M1, and the source M1S of the first transistor M1 is located in the first channel of the first transistor M1.
  • the channel region is located on a side away from the second channel region of the first transistor M1 and is located on a side of the second channel region of the first transistor M1 away from the first channel region of the first transistor M1 .
  • the source M1S of the first transistor M1 includes a first source M1S1 and a second source M1S2 arranged parallel to each other, and the first source M1S1 of the first transistor M1 is located far away from the first channel region of the first transistor M1.
  • the second source M1S2 of the first transistor M1 is located on the side of the second channel region of the first transistor M1 away from the first channel region of the first transistor M1.
  • the first source M1S1 of the first transistor M1, the first channel region of the first transistor M1, the drain M1D of the first transistor M1, the second channel region of the first transistor M1, and the first channel region of the first transistor M1 The two source electrodes M1S2 both extend along the first direction G and are arranged sequentially along the second direction H.
  • the gate M2G of the second transistor M2 includes a first gate M2G1 and a second gate M2G2, and the second gate M2G2 of the second transistor M2 and the second transistor M2
  • the first grids M2G1 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the eighth sub-active region Act_sub8 with the first gate M2G1 of the second transistor M2 and the second gate M2G2 of the second transistor M2 serves as a channel region of the second transistor M2.
  • the channel region of the second transistor M2 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the second transistor M2 overlaps with the first gate M2G1 of the second transistor M2 , the second channel region of the second transistor M2 overlaps with the second gate M2G2 of the second transistor M2.
  • the drain M2D of the second transistor M2 is located between the first channel region of the second transistor M2 and the second channel region of the second transistor M2, and the source M2S of the second transistor M2 is located in the first channel of the second transistor M2.
  • the channel region is located on a side away from the second channel region of the second transistor M2 and is located on a side of the second channel region of the second transistor M2 away from the first channel region of the second transistor M2 .
  • the source M2S of the second transistor M2 includes a first source M2S1 and a second source M2S2 arranged parallel to each other, and the first source M2S1 of the second transistor M2 is located far away from the first channel region of the second transistor M2.
  • the second source M2S2 of the second transistor M2 is located on the side of the second channel region of the second transistor M2 away from the first channel region of the second transistor M2.
  • a source electrode M2S1 extends along the first direction G and is arranged sequentially along the second direction H.
  • a gate M2G1 and the first source M2S1 of the second transistor M2 are arranged in sequence along the second direction H. In this way, the second transistor M2 is located on the side of the first transistor M1 in the second direction H.
  • the gate M5G of the fifth transistor M5, the gate M6G of the sixth transistor M6, the gate M3G of the third transistor M3, and the gate M4G of the fourth transistor M4 are along the The first direction G extends and is arranged in sequence along the second direction H, wherein the gate M5G of the fifth transistor M5 and the gate M6G of the sixth transistor M6 overlap with the third sub-active region Act_sub3, and the gate of the third transistor M3 The gate M3G and the gate M4G of the fourth transistor M4 overlap the fourth sub-active region Act_sub4.
  • the fifth transistor M5 , the sixth transistor M6 , the third transistor M3 and the fourth transistor M4 are arranged in sequence along the second direction H.
  • the overlapping portion of the fourth sub-active region Act_sub4 and the gate M3G of the third transistor M3 serves as a channel region of the third transistor M3.
  • the source M3S of the third transistor M3 is located on the opposite side of the second direction H of the channel region of the third transistor M3, and the drain M3D of the third transistor M3 is located in the second direction of the channel region of the third transistor M3 H side.
  • the source M3S of the third transistor M3 , the channel region of the third transistor M3 and the drain M3D of the third transistor M3 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the overlapping portion of the fourth sub-active region Act_sub4 and the gate M4G of the fourth transistor M4 serves as a channel region of the fourth transistor M4.
  • the source M4S of the fourth transistor M4 is located on the second direction H side of the channel region of the third transistor M4, and the drain M4D of the fourth transistor M4 is located on the opposite side of the second direction H of the channel region of the fourth transistor M4 direction side.
  • the drain M4D of the fourth transistor M4 , the channel region of the fourth transistor M4 and the source M4S of the fourth transistor M4 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the overlapping portion of the third sub-active region Act_sub3 and the gate M5G of the fifth transistor M5 serves as a channel region of the fifth transistor M5.
  • the source M5S of the fifth transistor M5 is located on the opposite side of the second direction H of the channel region of the fifth transistor M5, and the drain M5D of the fifth transistor M5 is located in the second direction of the channel region of the fifth transistor M5 H side.
  • the source M5S of the fifth transistor M5 , the channel region of the fifth transistor M5 and the drain M5D of the fifth transistor M5 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the overlapping portion of the third sub-active region Act_sub3 and the gate M6G of the sixth transistor M6 serves as a channel region of the sixth transistor M6.
  • the source M6S of the sixth transistor M6 is located on the second direction H side of the channel region of the sixth transistor M6, and the drain M6D of the sixth transistor M6 is located on the opposite side of the second direction H of the channel region of the sixth transistor M6 direction side.
  • the drain M6D of the sixth transistor M6 , the channel region of the sixth transistor M6 and the source M6S of the sixth transistor M6 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the drain M3D of the third transistor M3 coincides with the drain M4D of the fourth transistor M4.
  • the third transistor M3 and the fourth transistor M4 can share the drain, thereby simplifying the wiring arrangement of the row driving signal enhancing circuit 101, improving the compactness of the row driving signal enhancing circuit 101, and reducing the area occupied by the row driving signal enhancing circuit 101 .
  • the drain M5D of the fifth transistor M5 coincides with the drain M6D of the sixth transistor M6.
  • the fifth transistor M5 and the sixth transistor M6 can share the drain, thereby simplifying the wiring arrangement of the row driving signal enhancing circuit 101, improving the compactness of the row driving signal enhancing circuit 101, and reducing the area occupied by the row driving signal enhancing circuit 101 .
  • the gate M7G of the seventh transistor M7 includes a first gate M7G1 and a second gate M7G2, and the first gate M7G1 of the seventh transistor M7 and the seventh transistor M7
  • the second grids M7G2 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the fifth sub-active region Act_sub5 with the first gate M7G1 of the seventh transistor M7 and the second gate M7G2 of the seventh transistor M7 serves as a channel region of the seventh transistor M7.
  • the channel region of the seventh transistor M7 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the seventh transistor M7 overlaps with the first gate M7G1 of the seventh transistor M7 , the second channel region of the seventh transistor M7 overlaps with the second gate M7G2 of the seventh transistor M7.
  • the drain M7D of the seventh transistor M7 is located between the first channel region of the seventh transistor M7 and the second channel region of the seventh transistor M7, and the source M7S of the seventh transistor is located in the first channel of the seventh transistor M7 region away from the side of the second channel region of the seventh transistor M7 and located on a side of the second channel region of the seventh transistor M7 away from the first channel region of the seventh transistor M7.
  • the source M7S of the seventh transistor includes a first source M7S1 and a second source M7S2 arranged parallel to each other, and the first source M7S1 of the seventh transistor M7 is located far away from the first channel region of the seventh transistor M7 On one side of the second channel region of the transistor M7, the second source M7S2 of the seventh transistor M7 is located on a side of the second channel region of the seventh transistor M7 away from the first channel region of the seventh transistor M7.
  • the first source M7S1 of the seventh transistor M7, the first channel region of the seventh transistor M7, the drain M7D of the seventh transistor M7, the second channel region of the seventh transistor M7, and the first channel region of the seventh transistor M7 The two source electrodes M7S2 both extend along the first direction G and are arranged sequentially along the second direction H.
  • the gate M8G of the eighth transistor M8 includes a first gate M8G1 and a second gate M8G2, and the first gate M8G1 of the eighth transistor M8 and the eighth transistor M8
  • the second grids M8G2 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the sixth sub-active region Act_sub6 with the first gate M8G1 of the eighth transistor M8 and the second gate M8G2 of the eighth transistor M8 serves as a channel region of the eighth transistor M8.
  • the channel region of the eighth transistor M8 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the eighth transistor M8 overlaps with the first gate M8G1 of the eighth transistor M8 , the second channel region of the eighth transistor M8 overlaps the second gate M8G2 of the eighth transistor M8.
  • the drain M8D of the eighth transistor M8 is located between the first channel region of the eighth transistor M8 and the second channel region of the eighth transistor M8, and the source M8S of the eighth transistor is located in the first channel of the eighth transistor M8 region away from the side of the second channel region of the eighth transistor M8 and located on the side of the second channel region of the eighth transistor M8 away from the first channel region of the eighth transistor M8.
  • the source M8S of the eighth transistor includes a first source M8S1 and a second source M8S2 arranged parallel to each other, and the first source M8S1 of the eighth transistor M8 is located far away from the first channel region of the eighth transistor M8 On one side of the second channel region of the transistor M8, the second source M8S2 of the eighth transistor M8 is located on the side of the second channel region of the eighth transistor M8 away from the first channel region of the eighth transistor M8.
  • the first source M8S1 of the eighth transistor M8, the first channel region of the eighth transistor M8, the drain M8D of the eighth transistor M8, the second channel region of the eighth transistor M8, and the first channel region of the eighth transistor M8 The two source electrodes M8S2 both extend along the first direction G and are arranged sequentially along the second direction H.
  • the extension lines of the first source M8S1 of the eighth transistor M8 and the first source M7S1 of the seventh transistor M7 coincide in the first direction G, that is, the first source of the eighth transistor M8
  • the source M8S1 and the first source M7S1 of the seventh transistor M7 are linearly arranged along the first direction G.
  • the extension lines of the second source M8S2 of the eighth transistor M8 and the second source M7S2 of the seventh transistor M7 coincide in the first direction G, that is, the second source M8S2 of the eighth transistor M8 and the second source M7S2 of the seventh transistor M7
  • the two source electrodes M7S2 are linearly arranged along the first direction G.
  • the extension lines of the first gate M8G1 of the eighth transistor M8 and the first gate M7G1 of the seventh transistor M7 coincide in the first direction G, that is, the first gate M8G1 of the eighth transistor M8 and the first gate M7G1 of the seventh transistor M7
  • a grid M7G1 is linearly arranged along the first direction G.
  • the extension lines of the second gate M8G2 of the eighth transistor M8 and the second gate M7G2 of the seventh transistor M7 coincide in the first direction G, that is, the second gate M8G2 of the eighth transistor M8 and the second gate M7G2 of the seventh transistor M7
  • the two gates M7G2 are linearly arranged along the first direction G.
  • the extension lines of the drain M8D of the eighth transistor M8 and the drain M7D of the seventh transistor M7 coincide in the first direction G, that is, the drain M8D of the eighth transistor M8 and the drain M7D of the seventh transistor M7 are aligned along the first direction G.
  • G is arranged in a straight line.
  • the extension lines of the first channel region of the eighth transistor M8 and the first channel region of the seventh transistor M7 coincide in the first direction G, that is, the first channel region of the eighth transistor M8 and the first channel region of the seventh transistor M7 A channel region is arranged linearly along the first direction G.
  • the extension lines of the second channel region of the eighth transistor M8 and the second channel region of the seventh transistor M7 coincide in the first direction G, that is, the second channel region of the eighth transistor M8 and the second channel region of the seventh transistor M7
  • the two channel regions are arranged in a straight line along the first direction G. In this way, the eighth transistor M8 is located on the first direction G side of the seventh transistor M7.
  • the gate M13G of the thirteenth transistor M13 includes a first gate M13G1 and a second gate M13G2, and the second gate M13G2 of the thirteenth transistor M13 and the tenth
  • the first gates M13G1 of the three transistors M13 all extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the fifth sub-active region Act_sub5 with the first gate M13G1 of the thirteenth transistor M13 and the second gate M13G2 of the thirteenth transistor M13 serves as a channel region of the thirteenth transistor M13 .
  • the channel region of the thirteenth transistor M13 has a first channel region and a second channel region arranged parallel to each other, the first channel region of the thirteenth transistor M13 and the first gate of the thirteenth transistor M13 M13G1 overlaps, and the second channel region of the thirteenth transistor M13 overlaps with the second gate M13G2 of the thirteenth transistor M13.
  • the drain M13D of the thirteenth transistor M13 is located between the first channel region of the thirteenth transistor M13 and the second channel region of the thirteenth transistor M13, and the source M13S of the thirteenth transistor is located between the thirteenth transistor M13
  • the second channel region of M13 is away from the side of the first channel region of the thirteenth transistor M13.
  • the source M13S of the thirteenth transistor includes a first source M13S1 and a second source M13S2 arranged parallel to each other, and the first source M13S1 of the thirteenth transistor M13 is located in the first channel region of the thirteenth transistor M13 A side away from the second channel region of the thirteenth transistor M13, the second source M13S2 of the thirteenth transistor M13 is located in the second channel region of the thirteenth transistor M13 away from the first channel of the thirteenth transistor M13 side of the area.
  • the first sources M13S1 of the three transistors M13 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the gate M14G of the fourteenth transistor M14 includes a first gate M14G1 and a second gate M14G2, and the second gate M14G2 of the fourteenth transistor M14 and the tenth
  • the first gates M14G1 of the four transistors M14 all extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the sixth sub-active region Act_sub6 with the first gate M14G1 of the fourteenth transistor M14 and the second gate M14G2 of the fourteenth transistor M14 serves as a channel region of the fourteenth transistor M14 .
  • the channel region of the fourteenth transistor M14 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the fourteenth transistor M14 and the first gate of the fourteenth transistor M14 M14G1 overlaps, and the second channel region of the fourteenth transistor M14 overlaps with the second gate M14G2 of the fourteenth transistor M14.
  • the drain M14D of the fourteenth transistor M14 is located between the first channel region of the fourteenth transistor M14 and the second channel region of the fourteenth transistor M14, and the source M14S of the fourteenth transistor is located between the fourteenth transistor M14
  • the first channel region of the fourteenth transistor M14 is located on a side away from the second channel region of the fourteenth transistor M14 and the second channel region of the fourteenth transistor M14 is located on a side away from the first channel region of the fourteenth transistor M14.
  • the source M14S of the fourteenth transistor includes a first source M14S1 and a second source M14S2 arranged parallel to each other, and the first source M14S1 of the fourteenth transistor M14 is located in the first channel region of the fourteenth transistor M14 A side away from the second channel region of the fourteenth transistor M14, the second source M14S2 of the fourteenth transistor M14 is located in the second channel region of the fourteenth transistor M14 away from the first channel of the fourteenth transistor M14 side of the area.
  • the first sources M14S1 of the four transistors M14 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the extension lines of the first source M14S1 of the fourteenth transistor M14 and the first source M13S1 of the thirteenth transistor M13 in the first direction G overlap, that is, the fourteenth transistor M14
  • the first source M14S1 of the transistor M13 and the first source M13S1 of the thirteenth transistor M13 are linearly arranged along the first direction G.
  • the extension lines of the second source M14S2 of the fourteenth transistor M14 and the second source M13S2 of the thirteenth transistor M13 in the first direction G coincide, that is, the second source M14S2 of the fourteenth transistor M14 and the thirteenth transistor M14
  • the second source M13S2 of the transistor M13 is linearly arranged along the first direction G.
  • the extension lines of the first gate M14G1 of the fourteenth transistor M14 and the first gate M13G1 of the thirteenth transistor M13 coincide in the first direction G, that is, the first gate M14G1 of the fourteenth transistor M14 and the thirteenth transistor M14
  • the first gate M13G1 of the transistor M13 is linearly arranged along the first direction G.
  • the extension lines of the second gate M14G2 of the fourteenth transistor M14 and the second gate M13G2 of the thirteenth transistor M13 in the first direction G coincide, that is, the second gate M14G2 of the fourteenth transistor M14 and the thirteenth transistor M14
  • the second gate M13G2 of the transistor M13 is linearly arranged along the first direction G.
  • the first channel regions of the transistor M13 are linearly arranged along the first direction G.
  • the extension lines of the second channel region of the fourteenth transistor M14 and the second channel region of the thirteenth transistor M13 in the first direction G coincide, that is, the second channel region of the fourteenth transistor M14 and the thirteenth transistor M14
  • the second channel regions of the transistor M13 are linearly arranged along the first direction G. In this way, the fourteenth transistor M14 is located on the side of the thirteenth transistor M13 in the first direction G.
  • the first gate M13G1 of the transistor M13 and the first source M13S1 of the thirteenth transistor M13 are arranged in sequence along the second direction H. In this way, the thirteenth transistor M13 is located on the second direction H side of the seventh transistor M7.
  • the second source M7S2 of the seventh transistor M7 overlaps with the second source M13S2 of the thirteenth transistor M13.
  • the seventh transistor M7 and the thirteenth transistor M13 can share the source, thereby simplifying the wiring arrangement of the row driving signal enhancing circuit 101, improving the compactness of the row driving signal enhancing circuit 101, and reducing the occupation of the row driving signal enhancing circuit 101. area.
  • the first gate M14G1 of the transistor M14 and the first source M14S1 of the fourteenth transistor M14 are arranged in sequence along the second direction H. In this way, the fourteenth transistor M14 is located on the side of the eighth transistor M8 in the second direction H.
  • the second source M8S2 of the eighth transistor M8 overlaps with the second source M14S2 of the fourteenth transistor M14.
  • the eighth transistor M8 and the fourteenth transistor M14 can share the source, thereby simplifying the wiring arrangement of the row driving signal enhancing circuit 101, improving the compactness of the row driving signal enhancing circuit 101, and reducing the occupation of the row driving signal enhancing circuit 101. area.
  • the gate M9G of the ninth transistor M9 includes a first gate M9G1 and a second gate M9G2, and the first gate M9G1 of the ninth transistor M9 and the ninth transistor M9
  • the second grids M9G2 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the first sub-active region Act_sub1 with the first gate M9G1 of the ninth transistor M9 and the second gate M9G2 of the ninth transistor M9 serves as a channel region of the ninth transistor M9.
  • the channel region of the ninth transistor M9 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the ninth transistor M9 overlaps with the first gate M9G1 of the ninth transistor M9 , the second channel region of the ninth transistor M9 overlaps with the second gate M9G2 of the ninth transistor M9.
  • the drain M9D of the ninth transistor M9 is located between the first channel region of the ninth transistor M9 and the second channel region of the ninth transistor M9, and the source M9S of the ninth transistor is located in the first channel of the ninth transistor M9 region away from the side of the second channel region of the ninth transistor M9 and located on the side of the second channel region of the ninth transistor M9 away from the first channel region of the ninth transistor M9.
  • the source M9S of the ninth transistor includes a first source M9S1 and a second source M9S2 arranged parallel to each other, and the first source M9S1 of the ninth transistor M9 is located far away from the first channel region of the ninth transistor M9.
  • the second source M9S2 of the ninth transistor M9 is located on a side of the second channel region of the ninth transistor M9 away from the first channel region of the ninth transistor M9.
  • the first source M9S1 of the ninth transistor M9, the first channel region of the ninth transistor M9, the drain M9D of the ninth transistor M9, the second channel region of the ninth transistor M9, and the first channel region of the ninth transistor M9 both extend along the first direction G and are arranged sequentially along the second direction H.
  • the gate M10G of the tenth transistor M10 includes a first gate M10G1 and a second gate M10G2, and the first gate M10G1 of the tenth transistor M10 and the tenth transistor M10
  • the second grids M10G2 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the second sub-active region Act_sub2 with the first gate M10G1 of the tenth transistor M10 and the second gate M10G2 of the tenth transistor M10 serves as a channel region of the tenth transistor M10 .
  • the channel region of the tenth transistor M10 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the tenth transistor M10 overlaps with the first gate M10G1 of the tenth transistor M10 , the second channel region of the tenth transistor M10 overlaps with the second gate M10G2 of the tenth transistor M10.
  • the drain M10D of the tenth transistor M10 is located between the first channel region of the tenth transistor M10 and the second channel region of the tenth transistor M10, and the source M10S of the tenth transistor is located in the first channel of the tenth transistor M10 region away from the side of the second channel region of the tenth transistor M10 and located on a side of the second channel region of the tenth transistor M10 away from the first channel region of the tenth transistor M10 .
  • the source M10S of the tenth transistor includes a first source M10S1 and a second source M10S2 arranged parallel to each other, and the first source M10S1 of the tenth transistor M10 is located far away from the first channel region of the tenth transistor M10 On one side of the second channel region of the transistor M10, the second source M10S2 of the tenth transistor M10 is located on a side of the second channel region of the tenth transistor M10 away from the first channel region of the tenth transistor M10.
  • the first source M10S1 of the tenth transistor M10, the first channel region of the tenth transistor M10, the drain M10D of the tenth transistor M10, the second channel region of the tenth transistor M10, and the first channel region of the tenth transistor M10 both extend along the first direction G and are arranged in sequence along the second direction H.
  • the extension lines of the first source M10S1 of the tenth transistor M10 and the first source M9S1 of the ninth transistor M9 coincide in the first direction G, that is, the first source of the tenth transistor M10
  • the source M10S1 and the first source M9S1 of the ninth transistor M9 are linearly arranged along the first direction G.
  • the extension lines of the second source M10S2 of the tenth transistor M10 and the second source M9S2 of the ninth transistor M9 coincide in the first direction G, that is, the second source M10S2 of the tenth transistor M10 and the second source M10S2 of the ninth transistor M9
  • the two source electrodes M9S2 are linearly arranged along the first direction G.
  • the extension lines of the first gate M10G1 of the tenth transistor M10 and the first gate M9G1 of the ninth transistor M9 coincide in the first direction G, that is, the first gate M10G1 of the tenth transistor M10 and the first gate M10G1 of the ninth transistor M9
  • a grid M9G1 is linearly arranged along the first direction G.
  • the extension lines of the second gate M10G2 of the tenth transistor M10 and the second gate M9G2 of the ninth transistor M9 coincide in the first direction G, that is, the second gate M10G2 of the tenth transistor M10 and the second gate M9G2 of the ninth transistor M9
  • the two gates M9G2 are linearly arranged along the first direction G.
  • the extension lines of the drain M10D of the tenth transistor M10 and the drain M9D of the ninth transistor M9 coincide in the first direction G, that is, the drain M10D of the tenth transistor M10 and the drain M9D of the ninth transistor M9 are aligned along the first direction G.
  • G is arranged in a straight line.
  • the extension lines of the first channel region of the tenth transistor M10 and the first channel region of the ninth transistor M9 coincide in the first direction G, that is, the first channel region of the tenth transistor M10 and the first channel region of the ninth transistor M9
  • a channel region is arranged linearly along the first direction G.
  • the extension lines of the second channel region of the tenth transistor M10 and the second channel region of the ninth transistor M9 coincide in the first direction G, that is, the second channel region of the tenth transistor M10 and the first channel region of the ninth transistor M9
  • the two channel regions are arranged in a straight line along the first direction G. In this way, the tenth transistor M10 is located on the first direction G side of the ninth transistor M9.
  • the gate M11G of the eleventh transistor M11 includes a first gate M11G1 and a second gate M11G2 , and the second gate M11G2 of the eleventh transistor M11 and the tenth
  • the first gates M11G1 of a transistor M11 extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the first sub-active region Act_sub1 with the first gate M11G1 of the eleventh transistor M11 and the second gate M11G2 of the eleventh transistor M11 serves as a channel region of the eleventh transistor M11 .
  • the channel region of the eleventh transistor M11 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the eleventh transistor M11 and the first gate of the eleventh transistor M11 M11G1 overlaps, and the second channel region of the eleventh transistor M11 overlaps with the second gate M11G2 of the eleventh transistor M11 .
  • the drain M11D of the eleventh transistor M11 is located between the first channel region of the eleventh transistor M11 and the second channel region of the eleventh transistor M11, and the source M11S of the eleventh transistor M11 is located between the eleventh transistor M11
  • the first channel region of the eleventh transistor M11 is away from the side of the second channel region and the eleventh transistor
  • the second channel region of M11 is away from the side of the first channel region of the eleventh transistor M11.
  • the source M11S of the eleventh transistor includes a first source M11S1 and a second source M11S2 arranged parallel to each other, and the first source M11S1 of the eleventh transistor M11 is located in the first channel region of the eleventh transistor M11 The side away from the second channel region of the eleventh transistor M11, the second source M11S2 of the eleventh transistor M11 is located in the second channel region of the eleventh transistor M11 away from the first channel of the eleventh transistor M11 side of the area.
  • the first sources M11S1 of a transistor M11 all extend along the first direction G and are arranged in sequence along the second direction H.
  • the gate M12G of the twelfth transistor M12 includes a first gate M12G1 and a second gate M12G2, and the second gate M12G2 of the twelfth transistor M12 and the tenth
  • the first gates M12G1 of the two transistors M12 both extend along the first direction G and are arranged sequentially along the second direction H, and both have the same length.
  • the overlapping portion of the second sub-active region Act_sub2 with the first gate M12G1 of the twelfth transistor M12 and the second gate M12G2 of the twelfth transistor M12 serves as a channel region of the twelfth transistor M12 .
  • the channel region of the twelfth transistor M12 has a first channel region and a second channel region arranged parallel to each other, and the first channel region of the twelfth transistor M12 and the first gate of the twelfth transistor M12 M12G1 overlaps, and the second channel region of the twelfth transistor M12 overlaps with the second gate M12G2 of the twelfth transistor M12.
  • the drain M12D of the twelfth transistor M12 is located between the first channel region of the twelfth transistor M12 and the second channel region of the twelfth transistor M12, and the source M12S of the twelfth transistor is located between the twelfth transistor M12
  • the side of the first channel region of the twelfth transistor M12 away from the second channel region of the twelfth transistor M12 and the side of the second channel region of the twelfth transistor M12 away from the first channel region of the twelfth transistor M12 are located.
  • the source M12S of the twelfth transistor includes a first source M12S1 and a second source M12S2 arranged parallel to each other, and the first source M12S1 of the twelfth transistor M12 is located in the first channel region of the twelfth transistor M12 A side away from the second channel region of the twelfth transistor M12, the second source M12S2 of the twelfth transistor M12 is located in the second channel region of the twelfth transistor M12 away from the first channel of the twelfth transistor M12 side of the area.
  • the first sources M12S1 of the two transistors M12 both extend along the first direction G and are arranged in sequence along the second direction H.
  • the extension lines of the first source M12S1 of the twelfth transistor M12 and the first source M11S1 of the eleventh transistor M11 coincide in the first direction G, that is, the twelfth transistor M12
  • the first source M12S1 of the transistor M11 and the first source M11S1 of the eleventh transistor M11 are linearly arranged along the first direction G.
  • the extension lines of the second source M12S2 of the twelfth transistor M12 and the second source M11S2 of the eleventh transistor M11 in the first direction G coincide, that is, the second source M12S2 of the twelfth transistor M12 and the eleventh transistor M12
  • the second source M11S2 of the transistor M11 is linearly arranged along the first direction G.
  • the extension lines of the first gate M12G1 of the twelfth transistor M12 and the first gate M11G1 of the eleventh transistor M11 coincide in the first direction G, that is, the first gate M12G1 of the twelfth transistor M12 and the eleventh transistor M12
  • the first gate M11G1 of the transistor M11 is linearly arranged along the first direction G.
  • the extension lines of the second gate M12G2 of the twelfth transistor M12 and the second gate M11G2 of the eleventh transistor M11 coincide in the first direction G, that is, the second gate M12G2 of the twelfth transistor M12 and the eleventh transistor M12
  • the second gate M11G2 of the transistor M11 is linearly arranged along the first direction G.
  • the extension lines of the drain M12D of the twelfth transistor M12 and the drain M11D of the eleventh transistor M11 in the first direction G overlap, that is, the drain M12D of the twelfth transistor M12 and the drain M11D of the eleventh transistor M11 Arranged in a straight line along the first direction G.
  • the extension lines of the first channel region of the twelfth transistor M12 and the first channel region of the eleventh transistor M11 coincide in the first direction G, that is, the first channel region of the twelfth transistor M12 and the eleventh transistor M11
  • the first channel regions of the transistor M11 are linearly arranged along the first direction G.
  • the extension lines of the second channel region of the twelfth transistor M12 and the second channel region of the eleventh transistor M11 in the first direction G coincide, that is, the second channel region of the twelfth transistor M12 and the eleventh transistor M12
  • the second channel regions of the transistor M11 are linearly arranged along the first direction G. In this way, the twelfth transistor M12 is located on the side of the eleventh transistor M11 in the first direction G.
  • the first gate M11G1 of the first transistor M11 and the first source M11S1 of the eleventh transistor M11 are arranged in sequence along the second direction H. In this way, the eleventh transistor M11 is located on the side of the ninth transistor M9 in the second direction H.
  • the second source M9S2 of the ninth transistor M9 coincides with the second source M11S2 of the eleventh transistor M11.
  • the ninth transistor M9 and the eleventh transistor M11 can share the source, thereby simplifying the wiring arrangement of the row driving signal enhancing circuit 101, improving the compactness of the row driving signal enhancing circuit 101, and reducing the occupied space of the row driving signal enhancing circuit 101. area.
  • the first gate M12G1 of the transistor M12 and the first source M12S1 of the twelfth transistor M12 are arranged in sequence along the second direction H.
  • the twelfth transistor M12 is located on the side of the tenth transistor M10 in the second direction H. Further, the second source M10S2 of the tenth transistor M10 overlaps with the second source M12S2 of the twelfth transistor M12. In this way, the source of the twelfth transistor M12 and the tenth transistor M10 can be shared, thereby simplifying the wiring arrangement of the row driving signal enhancing circuit 101, improving the compactness of the row driving signal enhancing circuit 101, and reducing the occupied space of the row driving signal enhancing circuit 101. area.
  • the insulating dielectric layer 340 includes a first dielectric layer 341, a second dielectric layer 342, and a third dielectric layer 343 stacked on the gate layer 330 in sequence
  • the metal wiring layer 360 includes The first metal wiring layer 361 between the second dielectric layer 342, the second metal wiring layer 362 between the second dielectric layer 342 and the third dielectric layer 343, and the third dielectric layer 343 away from the semiconductor substrate 310 The third metal wiring layer 363 on the surface.
  • the conductive columns include a first conductive column 351 penetrating the first dielectric layer 341, a second conductive column 352 penetrating the second dielectric layer 342, and a third conductive column 353 penetrating the third dielectric layer 343; the first metal wiring layer 361 passes through the second A conductive column 351 is connected with the semiconductor substrate 310 and the gate layer 330; the second metal wiring layer 362 is connected with the first metal wiring layer 361 through the second conductive column 352; the third metal wiring layer 363 is connected with the third conductive column 353 The second metal wiring layer 362 is connected.
  • each conductive pillar penetrates the corresponding dielectric layer along a direction perpendicular to the semiconductor substrate 310 .
  • the first conductive pillar 351 penetrates the first dielectric layer 341 along a direction perpendicular to the semiconductor substrate 310 , so as to be connected to the semiconductor substrate 310 or the gate layer 330 .
  • the orthographic projection of the first conductive pillar 351 on the semiconductor substrate 310 does not overlap with the orthographic projection of the second conductive pillar 352 on the semiconductor substrate 310;
  • the orthographic projection on the substrate 310 does not overlap with the orthographic projection of the third conductive pillar 353 on the semiconductor substrate 310 .
  • each conductive column may be a metal column, such as a tungsten column.
  • the first metal wiring layer 361 includes some connection leads.
  • the connection leads located in the first metal wiring layer 361 include the first connection lead L01 to the sixth connection lead L06, and also include gate connection lines and source connection lines corresponding to the first transistor M1 to the fourteenth transistor M14 respectively. line and drain connection line.
  • the gate connection line corresponding to any transistor is connected to the gate of the transistor through the first conductive column 351; the source connection line corresponding to any transistor is connected to the source of the transistor through the first conductive column 351 The drain connection line corresponding to any transistor is connected to the drain of the transistor through the first conductive column 351 .
  • the source connection line corresponding to the ninth transistor M9 and the source connection line corresponding to the eleventh transistor M11 are connected to the first connection lead L01 .
  • the source connection line corresponding to the tenth transistor M10 includes the first sub-connection line M10SL1 and the second sub-connection line M10SL2; the source connection line corresponding to the twelfth transistor M12 includes the first sub-connection line M12SL1 and the second sub-connection line M12SL2 .
  • the source connection line corresponding to the eighth transistor M8 includes the first sub-connection line M8SL1 and the second sub-connection line M8SL2; the source connection line corresponding to the fourteenth transistor M14 includes the first sub-connection line M14SL1 and the second sub-connection line M14SL2 .
  • the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 includes the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14, the source connection line corresponding to the seventh transistor M7, the tenth
  • the source connection line corresponding to the third transistor M13 , the source connection line corresponding to the first transistor M1 , and the source connection line corresponding to the second transistor M2 are connected to the fifth connection lead L05 .
  • the source connection line M3SL corresponding to the third transistor M3 and the source connection line M6SL corresponding to the sixth transistor M6 are connected to the sixth connection lead and the sixth connection lead L06 .
  • the second metal wiring layer 362 includes a first control lead 421, a second control lead 422, a first output lead 431, a second output lead 432 and some connecting leads; the connecting leads at the second metal wiring layer 362 include The seventh connecting lead L07 to the fifteenth connecting lead L15. Referring to FIGS. 15 to 18 , the second metal wiring layer 362 is connected to the first metal wiring layer 361 through the second conductive pillar 352 .
  • connection lead L01, the second connection lead L02 are connected to the seventh connection lead L07, and the first connection lead L01, the second connection lead L02 are connected to the eighth connection lead L08.
  • the fifth connection lead L05 is connected to the ninth connection lead L09 and the tenth connection lead L10.
  • the gate connection line M7GL corresponding to the transistor M7, the gate connection line M8GL corresponding to the eighth transistor M8, and the drain connection line M1DL corresponding to the first transistor M1 are connected to the eleventh connection lead L11.
  • the gate connection line M13GL corresponding to the thirteenth transistor M13 , the gate connection line M14GL corresponding to the fourteenth transistor M14 , and the drain connection line M2DL corresponding to the second transistor M2 are connected to the twelfth connection lead L12 .
  • the first connection lead L01, the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9, the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10, and the source corresponding to the eleventh transistor M11 The second sub-connection line M11SL2 of the electrode connection line, the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12, the sixth connection lead L06, the second connection lead L02 and the thirteenth connection lead lead L13 connection.
  • the sub-connection line M13SL2 , the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14 , the fifth connection lead L05 are connected to the fourteenth connection lead L14 .
  • the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1, the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2, the fifth connection lead L05 and the fifteenth connection lead L15 are connected.
  • the drain connection line M7DL corresponding to the seventh transistor M7, the drain connection line M8DL corresponding to the eighth transistor M8, the drain connection line M9DL corresponding to the ninth transistor M9, and the drain connection line M10DL corresponding to the tenth transistor M10 are connected to the first The output lead 431 is connected.
  • the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13, and the drain connection line corresponding to the fourteenth transistor M14 M14DL is connected to the second output lead 432 .
  • the third metal wiring layer 363 includes a first voltage lead 411 for applying a first voltage, and includes a second power lead 412 for applying a second power voltage V2.
  • the ninth connecting lead L09, the tenth connecting lead L10, the fourteenth connecting lead L14, the fifteenth connecting lead L15 are connected to the first power lead 411 through the third conductive column; the seventh connecting lead L07 , the eighth connecting lead L08 , the thirteenth connecting lead L13 and the second power lead 412 are connected through the third conductive column.
  • the metal wiring layer 360 electrically connects each transistor in the row driving signal enhancing region F, so that the display panel forms a row driving signal enhancing circuit 101 in the row driving signal enhancing region F.
  • the second source M7S2 of the seventh transistor M7 coincides with the second source M13S2 of the thirteenth transistor M13 .
  • the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 coincides with the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13 , and are the same lead.
  • the second source M8S2 of the eighth transistor M8 coincides with the second source M14S2 of the fourteenth transistor M14 .
  • the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8 coincides with the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14 , and are the same lead.
  • the second source M9S2 of the ninth transistor M9 coincides with the second source M11S2 of the eleventh transistor M11 .
  • the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9 coincides with the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11 , and are the same lead.
  • the second source M10S2 of the tenth transistor M10 and the second source M12S2 of the twelfth transistor M12 overlap.
  • the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10 overlaps with the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12 , and are the same lead.
  • the drain M5D of the fifth transistor M5 coincides with the drain M6D of the sixth transistor M6 .
  • the drain connection line M5DL corresponding to the fifth transistor M5 overlaps with the drain connection line M6DL corresponding to the sixth transistor M6 , and they are the same lead.
  • the drain M3D of the third transistor M3 and the drain M4D of the fourth transistor M4 coincide.
  • the drain connection line M3DL corresponding to the third transistor M3 overlaps with the drain connection line M4DL corresponding to the fourth transistor M4 , and they are the same lead.
  • the source connection line corresponding to any one of the transistors overlaps with the source of the transistor, and the extension direction of the two is the same.
  • the extending direction of the source connection line corresponding to any one of the transistors is the first direction G.
  • the corresponding source connection lead of the transistor is connected to the source of the transistor through a plurality of first conductive pillars 351 sequentially arranged along the first direction G.
  • the drain connection line corresponding to any one of the transistors overlaps with the drain of the transistor, and the extension direction of the two is the same.
  • the extending direction of the drain connection line corresponding to any one of the transistors is the first direction G.
  • the corresponding drain connection lead of the transistor is connected to the drain of the transistor through two first conductive pillars 351 arranged along the first direction G.
  • the drain connection lines corresponding to each transistor have the same width as the drain connection lines.
  • the gate of any one of the transistors extends along the first direction G; the gate connection line corresponding to any one of the transistors extends along the second direction H, and is connected to the The ends of the gate are electrically connected through the first conductive pillar 351 . Further, the gate connection line corresponding to any transistor does not overlap with the active region.
  • the widths of the drain connection lines and the gate connection lines corresponding to each transistor are the same.
  • the gate connection line M1GL corresponding to the first transistor M1 is located on the side of the first direction G of the seventh sub-active region Act_sub7 and extends along the second direction H, and is connected to the first direction G of the first transistor M1.
  • a gate M1G1 is connected to an end on the first direction G side of the second gate M1G2 of the first transistor M1.
  • the gate connection line M2GL corresponding to the second transistor M2 is located on the side of the first direction G of the eighth sub-active region Act_sub8 and extends along the second direction H, and is connected to the first gate M2G1 of the second transistor M2, the second transistor The end portion of the second gate M2G2 of M2 on the first direction G side is connected.
  • the gate connection line M3GL corresponding to the third transistor M3 is located on the side of the first direction G of the fourth sub-active region Act_sub4 and extends along the second direction H, and is consistent with the first direction G of the gate M3G of the third transistor M3 side end connections.
  • the gate connection line M4GL corresponding to the fourth transistor M4 is located on the side of the first direction G of the fourth sub-active region Act_sub4 and extends along the second direction H, and is aligned with the first direction G of the gate M4G of the fourth transistor M4. side end connections.
  • the gate connection line M5GL corresponding to the fifth transistor M5 is located on the opposite side of the first direction G of the third sub-active region Act_sub3 and extends along the second direction H, and is connected to the first direction of the gate M5G of the fifth transistor M5. The end on the opposite side of G is connected.
  • the gate connection line M6GL corresponding to the sixth transistor M6 is located on the opposite side of the first direction G of the third sub-active region Act_sub3 and extends along the second direction H, and is connected to the first direction of the gate M6G of the sixth transistor M6. The end on the opposite side of G is connected.
  • the gate connection line M7GL corresponding to the seventh transistor M7 is located on the side of the first direction G of the fifth sub-active region Act_sub5 and extends along the second direction H, and is connected to the first gate M7G1 of the seventh transistor M7, the seventh transistor The end portion on the first direction G side of the second gate M7G2 of M7 is connected.
  • the gate connection line M8GL corresponding to the eighth transistor M8 is located on the side of the first direction G of the sixth sub-active region Act_sub6 and extends along the second direction H, and is connected to the first gate M8G1 of the eighth transistor M8, the eighth transistor M8 The end portion on the first direction G side of the second gate M8G2 of M8 is connected.
  • the gate connection line M9GL corresponding to the ninth transistor M9 is located on the side of the first direction G of the first sub-active region Act_sub1 and extends along the second direction H, and is connected to the first gate M9G1 of the ninth transistor M9, the ninth transistor The end portion on the first direction G side of the second gate M9G2 of M9 is connected.
  • the gate connection line M10GL corresponding to the tenth transistor M10 is located on the side of the first direction G of the second sub-active region Act_sub2 and extends along the second direction H, and is connected to the first gate M10G1 of the tenth transistor M10, the tenth transistor The end portion of the second gate M10G2 of the M10 on the first direction G side is connected.
  • the gate connection line M11GL corresponding to the eleventh transistor M11 is located on the side of the first sub-active region Act_sub1 in the first direction G and extends along the second direction H, and is connected to the first gate M11G1 and the first gate M11G1 of the eleventh transistor M11. The end portion on the first direction G side of the second gate M11G2 of the eleventh transistor M11 is connected.
  • the gate connection line M12GL corresponding to the twelfth transistor M12 is located on the side of the first direction G of the second sub-active region Act_sub2 and extends along the second direction H, and is connected to the first gate M12G1, the first gate M12G1 of the twelfth transistor M12 The end of the second gate M12G2 of the twelve transistor M12 on the first direction G side is connected.
  • the gate connection line M13GL corresponding to the thirteenth transistor M13 is located on the side of the first direction G of the fifth sub-active region Act_sub5 and extends along the second direction H, and is connected to the first gate M13G1 and the first gate M13G1 of the thirteenth transistor M13.
  • the end of the second gate M13G2 of the thirteen transistor M13 on the first direction G side is connected.
  • the gate connection line M14GL corresponding to the fourteenth transistor M14 is located on the side of the first direction G of the sixth sub-active region Act_sub6 and extends along the second direction H, and is connected to the first gate M14G1 and the first gate M14G1 of the fourteenth transistor M14. The end of the second gate M14G2 of the fourteenth transistor M14 on the first direction G side is connected.
  • the gate connection line M3GL corresponding to the third transistor M3 and the gate connection line M4GL corresponding to the fourth transistor M4 overlap and are the same lead.
  • the drain connection line M5DL corresponding to the fifth transistor M5 overlaps with the drain connection line M6DL corresponding to the sixth transistor M6, and they are the same lead.
  • the fourth connection lead L04 extends along the second direction H and is consistent with the extension direction of the gate connection line M3GL corresponding to the third transistor M3/the gate connection line M4GL corresponding to the fourth transistor M4, and is consistent with the extension direction of the gate connection line M4GL corresponding to the fifth transistor M5.
  • the end of the corresponding drain connection line M5DL/the sixth transistor M6 is connected in the first direction G to the corresponding drain connection line M6DL.
  • the gate connection line M4GL is an L-shaped lead line arranged along the first direction G and the second direction H.
  • the gate connection line M3GL corresponding to the third transistor M3/the gate connection line M4GL corresponding to the fourth transistor M4, and the fourth connection lead L04 are located between the sixth N-type doped sub-region F_Nsub6 and Between the third sub-active region Act_sub3 and the fourth sub-active region Act_sub4 and extending along the second direction H.
  • One end of the fourth connection lead L04 in the second direction H is connected to the gate connection line M3GL corresponding to the third transistor M3/the gate connection line M4GL corresponding to the fourth transistor M4, and the opposite direction of the second direction H of the fourth connection lead L04 One end is connected to the drain connection line M5DL corresponding to the fifth transistor M5/the drain connection line M6DL corresponding to the sixth transistor M6.
  • the gate connection line M5GL corresponding to the fifth transistor M5 and the gate connection line M6GL corresponding to the sixth transistor M6 overlap and are the same lead.
  • the drain connection line M3DL corresponding to the third transistor M3 overlaps with the drain connection line M4DL corresponding to the fourth transistor M4, and they are the same lead.
  • the third connection lead L03 extends along the second direction H and is consistent with the extension direction of the gate connection line M5GL corresponding to the fifth transistor M5, and is consistent with the first direction G of the drain connection line M3DL corresponding to the third transistor M3.
  • the gate connection line M6GL is an L-shaped lead line arranged along the first direction G and the second direction H.
  • the gate connection line M5GL corresponding to the fifth transistor M5/the gate connection line M6GL corresponding to the sixth transistor M6, and the third connection lead L03 are located between the fourth N-type doped sub-region F_Nsub4 and Between the third sub-active region Act_sub3 and the fourth sub-active region Act_sub4 and extending along the second direction H.
  • One end of the second direction H of the third connection lead L03 is connected to the drain connection line M3DL corresponding to the third transistor M3/the drain connection line M4DL corresponding to the fourth transistor M4, and the opposite direction of the second direction H of the third connection lead L03 One end is connected to the gate connection line M5GL corresponding to the fifth transistor M5/the gate connection line M6GL corresponding to the sixth transistor M6.
  • the second direction H of the gate connection line M9GL corresponding to the ninth transistor M9, the gate connection line M10GL corresponding to the tenth transistor M10, and the gate connection line M7GL corresponding to the seventh transistor M7 One end in the opposite direction of each is provided with a transfer line extending along the first direction G; the transfer line of the gate connection line M9GL corresponding to the ninth transistor M9, the transfer line of the gate connection line M10GL corresponding to the tenth transistor M10, the seventh transistor M10
  • the direction G is arranged in a straight line; the eleventh connection lead L11 is arranged in a straight line along the first direction G, and the transfer line of the gate connection line M9GL corresponding to the ninth transistor M9 and the
  • the eleventh connection lead L11 is respectively connected to the transition line of the gate connection line M9GL corresponding to the ninth transistor M9, the transition line of the gate connection line M10GL corresponding to the tenth transistor M10, and the transition line of the seventh transistor M7 through the second conductive column 352.
  • the drain connection line M1DL corresponding to M1 is connected.
  • the eleventh connection lead L11 may also be provided with a transition line extending toward the second direction H; the transition line of the eleventh connection lead L11 overlaps with the gate connection line M8GL corresponding to the eighth transistor M8, and passes through The second conductive column 352 is connected to the gate connection line M8GL corresponding to the eighth transistor M8.
  • the gate connection line M8GL corresponding to the eighth transistor M8 does not need to be provided with a transfer line, which can prevent the transfer line of the gate connection line M8GL corresponding to the eighth transistor M8 from occupying space in the first direction G, and reduce the row driving signal of the present disclosure.
  • the area of the circuit 101 is enhanced.
  • the gate connection line M11GL corresponding to the eleventh transistor M11, the gate connection line M12GL corresponding to the twelfth transistor M12, and the gate connection line M13GL corresponding to the thirteenth transistor M13 One end of the two directions H is provided with a transfer line extending along the first direction G, and the transfer line of the gate connection line M11GL corresponding to the eleventh transistor M11, the transfer line of the gate connection line M12GL corresponding to the twelfth transistor M12, The transfer line of the gate connection line M13GL corresponding to the thirteenth transistor M13, the drain connection line M3DL corresponding to the third transistor M3/the drain connection line M4DL corresponding to the fourth transistor M4, and the drain connection line corresponding to the second transistor M2
  • the M2DL is linearly arranged along the first direction G.
  • the twelfth connection lead L12 is arranged linearly along the first direction G, and the transition line of the gate connection line M11GL corresponding to the eleventh transistor M11, the transition line of the gate connection line M12GL corresponding to the twelfth transistor M12, the tenth transistor M12
  • the twelfth connection lead L12 is respectively connected to the transition line of the gate connection line M11GL corresponding to the eleventh transistor M11, the transition line of the gate connection line M12GL corresponding to the twelfth transistor M12, and the tenth connection line L12 through the second conductive column 352.
  • the transfer line of the gate connection line M13GL corresponding to the third transistor M13, the gate connection line M14GL corresponding to the fourteenth transistor M14, the drain connection line M3DL corresponding to the third transistor M3/the drain connection line M4DL corresponding to the fourth transistor M4 , and the drain connection line M2DL corresponding to the second transistor M2 is connected.
  • the twelfth connection lead L12 may also be provided with a transition line extending in the opposite direction to the second direction H; the transition line of the twelfth connection lead L12 intersects with the gate connection line M14GL corresponding to the fourteenth transistor M14 and connected to the gate connection line M14GL corresponding to the fourteenth transistor M14 through the second conductive pillar 352 .
  • the gate connection line M14GL corresponding to the fourteenth transistor M14 does not need to be provided with a transfer line, which can prevent the transfer line of the gate connection line M14GL corresponding to the fourteenth transistor M14 from occupying space in the first direction G, reducing the number of lines in the present disclosure.
  • the area of the driving signal enhancement circuit 101 is not need to be provided with a transfer line, which can prevent the transfer line of the gate connection line M14GL corresponding to the fourteenth transistor M14 from occupying space in the first direction G, reducing the number of lines in the present disclosure.
  • the first connection lead L01 includes a first sub-lead L011, a second sub-lead L012, and a third sub-lead L013 connected in sequence; the first sub-lead L011, the first The third sub-lead L013 of the connection lead L01 extends along the first direction G and at least partially overlaps with the N-type auxiliary doped region F_Ndummy; the second sub-lead L012 of the first connection lead L01 extends along the second direction H and overlaps with the N-type auxiliary doped region F_Ndummy; The doped region F_Ndummy at least partially overlaps; the first sub-active region Act_sub1 is located in the semi-open space surrounded by the first connection lead L01 .
  • the first connection lead L01 is located on the opposite side of the first direction G of the second connection lead L02 .
  • the extension direction of the first sub-lead L011 of the first connection lead L01 is consistent with the extension direction of the first N-type doped sub-region F_Nsub1, both of which are in the first direction G and at least partially overlap.
  • the extension direction of the second sub-lead L012 of the first connection lead L01 is consistent with the extension direction of the second N-type doped sub-region F_Nsub2, both of which are in the second direction H and at least partially overlap.
  • the extension direction of the third sub-lead L013 of the first connection lead L01 is consistent with the extension direction of the third N-type doped sub-region F_Nsub3, both of which are in the second direction H and at least partially overlap.
  • the first connection lead L01 forms a zigzag structure with an opening facing the first direction G, and the first sub-active region Act_sub1 is located in the space surrounded by the zigzag structure.
  • the first sub-lead L011 of the first connection lead L01, the second sub-lead L012 of the first connection lead L01, and the third sub-lead L013 of the first connection lead L01 are all mixed with the N-type auxiliary doped Miscellaneous region F_Ndummy connection.
  • the first sub-lead L011 of the first connection lead L01 is connected to the first N-type doped sub-region F_Nsub1 through a plurality of first conductive pillars 351 sequentially arranged along the first direction G;
  • the sub-lead L012 is connected to the second N-type doped sub-region F_Nsub2 through a plurality of first conductive pillars 351 arranged in sequence along the second direction H;
  • the plurality of first conductive pillars 351 are connected to the third N-type doped sub-region F_Nsub3.
  • the first sub-lead L011 of the first connection lead L01 is connected to the first N-type doped sub-region F_Nsub1 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes A plurality of first conductive pillars 351.
  • the third sub-lead L013 of the first connection lead L01 is connected to the third N-type doped sub-region F_Nsub3 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes A plurality of first conductive pillars 351 .
  • the second power supply voltage V2 applied to the first connecting lead L01 can be evenly applied to the N-type auxiliary doped region F_Ndummy overlapping with the first connecting lead L01, thereby reducing the number of the ninth transistor M9 and the eleventh transistor M11 leakage.
  • the orthographic projection of the first sub-lead L011 of the first connection lead L01 on the semiconductor substrate 310 is located within the range of the first N-type doped sub-region F_Nsub1; the second sub-lead of the first connection lead L01 The orthographic projection of L012 on the semiconductor substrate 310 is located within the range of the second N-type doped sub-region F_Nsub2; the orthographic projection of the third sub-lead L013 of the first connection lead L01 on the semiconductor substrate 310 is located in the third N-type within the range of the doped sub-region F_Nsub3.
  • the first sub-connection line L011 of the first connection lead L01 and the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9 both extend along the first direction G.
  • the local position of the first sub-lead L011 of the first connection lead L01 can also extend along the second direction H to form a protrusion, and the protrusion of the first sub-lead L011 of the first connection lead L01 is along the second direction H
  • the first sub-connection line M9SL1 extending to the source connection line corresponding to the ninth transistor M9 is connected so that the second direction H of the first sub-connection line M9SL1 corresponding to the source connection line of the ninth transistor M9 is opposite to the direction H.
  • the side is connected with the first sub-lead L011 of the first connecting lead L01. Further, the first sub-lead of the first connection lead L01
  • One end of the protruding part of L011 in the first direction G is flush with the end of the first direction G of the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9, and the first sub-lead L011 of the first connection lead L01
  • One end of the protruding portion in the opposite direction of the first direction G is flush with one end of the first sub-connection line M9SL1 of the corresponding source connection line of the ninth transistor M9 in the opposite direction of the first direction G.
  • the length of the protruding portion of the first sub-lead L011 of the first connection lead L01 in the first direction G is the length of the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9 in the first direction G. same length.
  • the setting of the protruding portion of the first sub-lead L011 of the first connection lead L01 can make the first source M9S1LN of the ninth transistor M9 and the first sub-lead L011 of the first connection lead L01 integrally structured.
  • the third sub-lead L013 of the first connecting lead L01 and the first sub-connecting line M11SL1 of the source connecting line corresponding to the eleventh transistor M11 both extend along the first direction G.
  • the local position of the third sub-lead L013 of the first connection lead L01 can also extend along the opposite direction of the second direction H to form a protrusion, and the protrusion of the third sub-lead L013 of the first connection lead L01 is along the second direction
  • the opposite direction of H extends to connect with the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11, so that the second sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11
  • the side in the direction H is connected to the third sub-lead L013 of the first connecting lead L01.
  • one end in the first direction G of the protruding portion of the third sub-lead L013 of the first connection lead L01 is aligned with one end in the first direction G of the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11 Flat, one end in the opposite direction of the first direction G of the protrusion of the third sub-lead L013 of the first connection lead L01 is connected to the first direction G of the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11 The end in the opposite direction is flush.
  • the length of the protruding portion of the third sub-lead L013 of the first connection lead L01 in the first direction G is the length of the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11 in the first direction G. same length.
  • the arrangement of the protruding part of the third sub-lead L013 of the first connection lead L01 can make the first source M11S1LN of the eleventh transistor M11 and the third sub-lead L013 of the first connection lead L01 integrally structured.
  • the second connecting lead L02 includes a first sub-lead L021 , a second sub-lead L022 , and a fourth sub-lead L024 connected in sequence, and includes a third sub-lead L023 .
  • both the first sub-lead L021 of the second connection lead L02 and the fourth sub-lead L024 of the second connection lead L02 extend along the first direction G, and at least partially overlap with the P-type auxiliary doped region F_Pdummy;
  • the second connection Both the second sub-lead L022 of the lead L02 and the third sub-lead L023 of the second connecting lead L02 extend along the second direction H, and at least partially overlap with the P-type auxiliary doped region F_Pdummy;
  • the second sub-active region Act_sub2 is located at the second In the space surrounded by the first sub-lead L021 of the second connection lead L02, the second sub-lead L022 of the second connection lead L02, and the fourth sub-lead L024 of the second connection lead L02,
  • the second active layer Act2 is located in the second connection In the space surrounded by the first sub-lead L021 of the lead L02, the second sub-lead L02
  • the second connecting lead L02 is located on one side of the first connecting lead L01 in the first direction G.
  • the extension direction of the first sub-lead L021 of the second connection lead L02 is consistent with that of the first sub-lead L011 of the first connection lead L01 and is not continuous with the first sub-lead L011 of the first connection lead L01.
  • the part of the first sub-lead L021 of the second connection lead L02 close to the opposite end of the first direction G may at least partially overlap with the first N-type doped sub-region F_Nsub1; the first sub-lead L021 of the second connection lead L02 A portion close to one end of the first direction G may at least partially overlap with the fifth N-type doped sub-region F_Nsub5.
  • the size of the overlapping part of the first sub-lead L021 of the second connection lead L02 and the fifth N-type doped sub-region F_Nsub5 in the second direction H may be smaller than the first sub-lead L021 of the second connection lead L02 and the first The size of the overlapping portion of the N-type doped sub-region F_Nsub1 in the second direction H.
  • the fourth sub-lead L024 of the second connection lead L02 extends in the same direction as the third sub-lead L013 of the first connection lead L01 and is discontinuous with the third sub-lead L013 of the first connection lead L01 .
  • the part of the fourth sub-lead L024 of the second connection lead L02 close to the opposite end of the first direction G may at least partially overlap with the third N-type doped sub-region F_Nsub3; the fourth sub-lead L024 of the second connection lead L02 A portion close to one end of the first direction G may at least partially overlap with the seventh N-type doped sub-region F_Nsub7.
  • the size of the overlapping part of the fourth sub-lead L024 of the second connection lead L02 and the seventh N-type doped sub-region F_Nsub7 in the second direction H may be smaller than the fourth sub-lead L024 of the second connection lead L02 and the third sub-region F_Nsub7.
  • the second sub-lead L022 of the second connection lead L02 extends along the second direction H, and its two ends are connected to the first sub-lead L021 of the second connection lead L02 and the fourth sub-lead L024 of the second connection lead L02 respectively.
  • the portion where the first sub-lead L021 of the second connection lead L02 overlaps the first N-type doped sub-region F_Nsub1, and the fourth sub-lead L024 of the second connection lead L02 overlaps the third N-type doped sub-region F_Nsub3 All are located on the opposite side of the first direction G of the second sub-lead L022 of the second connection lead L02; the first sub-lead L021 of the second connection lead L02 overlaps with the fifth N-type doped sub-region F_Nsub5 , and the overlapping portion of the fourth sub-lead L024 of the second connection lead L02 and the seventh N-type doped sub-region F_Nsub7 are located on the first direction G side of the second sub-lead L022 of the second connection lead L02 .
  • the second sub-lead L022 of the second connection lead L02 at least partially overlaps with the fourth N-type doped sub-region F_Nsub4.
  • the third sub-lead L023 of the second connection lead L02 extends along the second direction H, and its two ends are connected to the first sub-lead L021 of the second connection lead L02 and the fourth sub-lead L024 of the second connection lead L02 respectively.
  • the first sub-lead L021 of the second connection lead L02, the fourth sub-lead L024 of the second connection lead L02 and the second sub-lead L022 of the second connection lead L02 are located at the third sub-lead L023 of the second connection lead L02.
  • the third sub-lead L023 of the second connection lead L02 may at least partially overlap the sixth N-type doped sub-region F_Nsub6.
  • the first sub-lead L021 of the second connection lead L02, the second sub-lead L022 of the second connection lead L02 and the fourth sub-lead L024 of the second connection lead L02 surround an opening facing the opposite side of the first direction G. direction
  • the second sub-active region Act_sub2 may be located in the space.
  • the first sub-lead L021 of the second connection lead L02, the second sub-lead L022 of the second connection lead L02, the fourth sub-lead L024 of the second connection lead L02 and the third sub-lead L023 of the second connection lead L02 surround a closed space
  • the second active region Act2 may be located in the closed space.
  • the fourth sub-leads L024 are connected to the N-type auxiliary doped region F_Ndummy.
  • the first sub-lead L021 of the second connection lead L02 connects the first N-type doped sub-region F_Nsub1 and the fifth N-type doped
  • the heterogeneous sub-region F_Nsub5 is connected
  • the second sub-lead L022 of the second connection lead L02 is connected to the fourth N-type doped sub-region F_Nsub4 through a plurality of first conductive pillars 351 arranged in sequence along the second direction H
  • the second connection lead L02 The third sub-lead L023 of the second connection lead L02 is connected to the sixth N-type doped sub-region F_Nsub6 through a plurality of first conductive pillars 351 arranged in sequence along the second direction H
  • the fourth sub-lead L024 of the second connecting lead L02 is connected to the sixth N-type doped sub-region F_Nsub6 through A plurality of first conductive pillars 351 arranged in sequence are connected to the third N-type doped sub-region F_
  • the first sub-lead L021 of the second connection lead L02 is connected to the first N-type doped sub-region F_Nsub1 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes A plurality of first conductive pillars 351.
  • the fourth sub-lead L024 of the second connection lead L02 is connected to the third N-type doped sub-region F_Nsub3 through two rows of first conductive pillars 351, and each row of first conductive pillars 351 includes sequentially arranged along the first direction G. A plurality of first conductive pillars 351.
  • the second power supply voltage V2 applied to the second connecting lead L02 can evenly load the N-type auxiliary doped region F_Ndummy overlapping with the third connecting lead L03, thereby reducing the number of the tenth transistor M10, the twelfth transistor M12, Leakage of the fourth transistor M4 and the fifth transistor M5.
  • the first sub-connection line L021 of the second connection lead L02 and the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10 both extend along the first direction G.
  • the partial position of the first sub-lead L021 of the second connection lead L02 can also extend along the second direction H to form a first protrusion, and the first protrusion of the first sub-lead L021 of the second connection lead L02 is along the
  • the second direction H extends to connect with the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10, so that the second direction H of the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10
  • the side in the opposite direction is connected to the first sub-lead L021 of the second connection lead L02.
  • one end of the first protruding portion of the first sub-lead L021 of the second connection lead L02 in the first direction G is connected to the first direction G of the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10.
  • One end is flush with one end of the first protruding portion of the first sub-lead L021 of the second connection lead L02 in the opposite direction to the first direction G and the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10.
  • One end opposite to the first direction G is flush with each other.
  • the length of the first protruding portion of the first sub-lead L021 of the second connection lead L02 in the first direction G is the same as that of the first sub-connection line M10SL1 of the source connection line of the tenth transistor M10 in the first direction G. above are the same length.
  • the setting of the first protrusion of the first sub-lead L021 of the second connection lead L02 can make the first source M10S1LN of the tenth transistor M10 and the first sub-lead L021 of the second connection lead L02 integrally structured.
  • the fourth sub-lead L024 of the second connection lead L02 and the first sub-connection M12SL1 of the source connection line corresponding to the twelfth transistor M12 are both along the first direction G Extension; the local position of the fourth sub-lead L024 of the second connection lead L02 can also extend in the opposite direction of the second direction H to form a first protrusion, and the first part of the fourth sub-lead L024 of the second connection lead L02
  • the protrusion extends along the opposite direction of the second direction H to connect with the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12, so that the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12
  • the side of the sub-connection line M12SL1 in the second direction H is connected to the fourth sub-lead L024 of the second connection lead L02 .
  • one end of the first protruding portion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is aligned with the first direction of the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12.
  • One end of G is flush with one end of the first protruding portion of the fourth sub-lead L024 of the second connection lead L02 in the opposite direction to the first direction G and the first sub-connection line of the source connection line corresponding to the twelfth transistor M12
  • the end of the opposite direction of the first direction G of the M12SL1 is flush with each other.
  • the length of the first protruding portion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is the same as that of the first sub-connection line M12SL1 of the source connection line of the twelfth transistor M12 in the first direction.
  • G is the same length.
  • the setting of the first protrusion of the fourth sub-lead L024 of the second connection lead L02 can make the first source M12S1LN of the twelfth transistor M12 and the fourth sub-lead L024 of the second connection lead L02 integrally structured.
  • the width of the third connection lead L03 and the fourth connection lead L04 is the same as that of the drain connection line corresponding to each transistor.
  • the first sub-lead L021 of the second connection lead L02 and the source connection line M5SL corresponding to the fifth transistor M5 both extend along the first direction G; the second connection lead L02
  • the local position of the first sub-lead L021 of the second connection lead L02 can also extend along the second direction H to form a second protrusion, and the second protrusion of the first sub-lead L021 of the second connection lead L02 extends along the second direction H to
  • the source connection line M5SL corresponding to the fifth transistor M5 is connected so that the side of the source connection line M5SL corresponding to the fifth transistor M5 in the opposite direction of the second direction H is connected to the first sub-lead L021 of the second connection lead L02 connect.
  • one end in the first direction G of the second protruding portion of the first sub-lead L021 of the second connecting lead L02 is flush with the end in the first direction G of the source connecting line M5SL corresponding to the fifth transistor M5, and the second An end opposite to the first direction G of the second protruding portion of the first sub-lead L021 connecting the lead L02 is flush with an end opposite to the first direction G of the source connecting line M5SL corresponding to the fifth transistor M5 .
  • the length of the second protruding portion of the first sub-lead L021 of the second connection lead L02 in the first direction G is the same as the length of the source connection line M5SL corresponding to the fifth transistor M5 in the first direction G.
  • the arrangement of the second protruding portion of the first sub-lead L021 of the second connection lead L02 can make the source connection line M5SL corresponding to the fifth transistor M5 integrally structured with the first sub-lead L021 of the second connection lead L02.
  • both the sixth connection lead L06 and the source connection line M6SL corresponding to the sixth transistor M6 extend along the first direction G; at least a partial position of the sixth connection lead L06 can also be Extending in the opposite direction of the second direction H to form a first protrusion, the first protrusion of the sixth connection lead L06 extends in the opposite direction of the second direction H to the source connection line corresponding to the sixth transistor M6 M6SL is connected so that the side of the source connection line M6SL corresponding to the sixth transistor M6 in the second direction H is connected to the sixth connection lead L06 .
  • one end of the first protruding portion of the sixth connection lead L06 in the first direction G is flush with the end of the first direction G of the source connection line M6SL corresponding to the sixth transistor M6, and the first end of the sixth connection lead L06 An end opposite to the first direction G of the protruding portion is flush with an end opposite to the first direction G of the source connecting line M6SL corresponding to the sixth transistor M6 .
  • the length of the first protruding portion of the sixth connection lead L06 in the first direction G is the same as the length of the source connection line M6SL corresponding to the sixth transistor M6 in the first direction G.
  • the setting of the first protruding portion of the sixth connecting lead L06 can make the source connecting line M6SL corresponding to the sixth transistor M6 and the sixth connecting lead L06 integrally structured.
  • both the sixth connection lead L06 and the source connection line M3SL corresponding to the third transistor M3 extend along the first direction G; at least a partial position of the sixth connection lead L06 can also be Extending along the second direction H to form a second protrusion, the second protrusion of the sixth connection lead L06 extends along the second direction H to connect with the source connection line M3SL corresponding to the third transistor M3, so that the second The side of the source connection line M3SL corresponding to the three transistors M3 in the direction opposite to the second direction H is connected to the sixth connection lead L06 .
  • one end of the second protruding portion of the sixth connection lead L06 in the first direction G is flush with the end of the first direction G of the source connection line M3SL corresponding to the third transistor M3, and the second end of the sixth connection lead L06
  • One end of the protruding part in the opposite direction of the first direction G is flush with one end of the corresponding source connection line M3SL of the third transistor M3 in the opposite direction of the first direction G.
  • the length of the second protruding portion of the sixth connection lead L06 in the first direction G is the same as the length of the source connection line M3SL corresponding to the third transistor M3 in the first direction G.
  • the setting of the second protruding portion of the sixth connecting lead L06 can make the source connecting line M3SL corresponding to the third transistor M3 and the sixth connecting lead L06 integrally structured.
  • the width of the sixth connection lead L06 is greater than the width of the corresponding source connection lines of each transistor.
  • the sixth connection lead L06 is connected to the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10/the source corresponding to the twelfth transistor M12 along the axis in the first direction G.
  • the axis of the second sub-connection line M12SL2 of the line along the first direction G coincides.
  • the fourth sub-lead L024 of the second connection lead L02 and the source connection line M4SL corresponding to the fourth transistor M4 both extend along the first direction G; the second connection lead L02
  • the local position of the fourth sub-lead L024 of the second connection lead L02 can also extend along the opposite direction of the second direction H to form a second protrusion, and the second protrusion of the fourth sub-lead L024 of the second connection lead L02 is along the second direction
  • the opposite direction of H extends to connect with the source connection line M4SL corresponding to the fourth transistor M4, so that the side of the source connection line M4SL corresponding to the fourth transistor M4 in the second direction H is connected to the fourth side of the second connection lead L02.
  • Sub lead L024 connection Further, one end of the second protruding portion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is flush with the end of the first direction G of the source connection line M4SL corresponding to the fourth transistor M4, and the second An end opposite to the first direction G of the second protruding portion of the fourth sub-lead L024 connecting the lead L02 is flush with an end opposite to the first direction G of the source connecting line M4SL corresponding to the fourth transistor M4 .
  • the length of the second protruding portion of the fourth sub-lead L024 of the second connection lead L02 in the first direction G is the same as the length of the source connection line M4SL corresponding to the fourth transistor M4 in the first direction G.
  • the arrangement of the second protruding portion of the fourth sub-lead L024 of the second connection lead L02 can make the source connection line M4SL corresponding to the fourth transistor M4 and the fourth sub-lead L024 of the second connection lead L02 integrally structured.
  • the fifth connection lead L05 includes first sub-lead L051 , second sub-lead L052 , third sub-lead L053 and fourth sub-lead L054 connected in sequence, and includes fifth sub-lead L055 and Sixth sub-lead L056.
  • the first sub-lead L051 of the fifth connection lead L05, the third sub-lead L053 of the fifth connection lead L05, and the sixth sub-lead L056 of the fifth connection lead L05 all extend along the first direction G, and are all doped with the P-type auxiliary
  • the regions F_Pdummy at least partially overlap.
  • the sixth sub-lead L056 of the fifth connection lead L05 is located between the first sub-lead L051 of the fifth connection lead L05 and the third sub-lead L053 of the fifth connection lead L05, and both ends are respectively connected to the fifth sub-lead L05 of the fifth connection lead L05.
  • the fourth sub-lead L054 of the sub-lead L055 and the fifth connection lead L05 is connected; the second sub-lead L052 of the fifth connection lead L05, the fourth sub-lead L054 of the fifth connection lead L05, the fifth sub-lead L05 of the fifth connection lead L05
  • the lead lines L055 all extend along the second direction H, and at least partially overlap with the P-type auxiliary doped region F_Pdummy.
  • the fifth sub-lead L055 of the fifth connection lead L05 is located between the second sub-lead L052 of the fifth connection lead L05 and the fourth sub-lead L054 of the fifth connection lead L05, and both ends are connected to the fifth connection lead L05 respectively.
  • the first sub-lead L051 and the third sub-lead L053 of the fifth connection lead L05 are connected; the first sub-lead L051 to the sixth sub-lead L056 of the fifth connection lead L05 are all connected to the P-type auxiliary doped region F_Pdummy.
  • the third active region Act3 is located on the first sub-lead L051 of the fifth connection lead L05, the first sub-lead L052 of the fifth connection lead L05, the third sub-lead L053 of the fifth connection lead L05, and the fifth part of the fifth connection lead L05.
  • the seventh sub-active region Act_sub7 is located in the first sub-lead L051 of the fifth connection lead L05, the first sub-lead L055 of the fifth connection lead L05, and the sixth sub-lead of the fifth connection lead L05.
  • the eighth sub-active region Act_sub8 is located in the sixth sub-lead L056 of the fifth connection lead L05 and the first sub-lead of the fifth connection lead L05 In the space surrounded by the L055, the third sub-lead L053 of the fifth connection lead L05, and the fourth sub-lead L054 of the fifth connection lead L05.
  • the gate connection line M7GL corresponding to the seventh transistor M7 and the gate connection line M13GL corresponding to the thirteenth transistor M13 are located at the first sub-lead L051 of the fifth connection lead L05 and at the end of the fifth connection lead L05.
  • the third sub-lead L053 of the fifth connection lead L05, and the fifth sub-lead L055 of the fifth connection lead L05 and located in the fifth sub-active region Act_sub5 and the sixth sub-active region Between Act_sub6.
  • the gate connection line M8GL corresponding to the eighth transistor M8 and the gate connection line M14GL corresponding to the fourteenth transistor M14 are located on the first sub-lead L051 of the fifth connection lead L05, the second sub-lead L052 of the fifth connection lead L05, the second In the space surrounded by the third sub-lead L053 of the fifth connection lead L05 and the fifth sub-lead L055 of the fifth connection lead L05, and located between the sixth sub-active region Act_sub6 and the fifth sub-lead L055 of the fifth connection lead L05 .
  • the gate connection line M1GL corresponding to the first transistor M1 is located on the first sub-lead L051 of the fifth connection lead L05, the fifth sub-lead L055 of the fifth connection lead L05, and the first sub-lead L05 of the fifth connection lead L05.
  • the space surrounded by the sixth sub-lead L056 and the fourth sub-lead L054 of the fifth connection lead L05 is located between the seventh sub-active region Act_sub7 and the fourth sub-lead L054 of the fifth connection lead L05.
  • the gate connection line M2GL corresponding to the second transistor M2 is located at the third sub-lead L053 of the fifth connection lead L05, the fifth sub-lead L055 of the fifth connection lead L05, the sixth sub-lead L056 of the fifth connection lead L05 and the fifth connection
  • the space surrounded by the fourth sub-lead L054 of the lead L05 is located between the eighth sub-active region Act_sub8 and the fourth sub-lead L054 of the fifth connection lead L05.
  • the first sub-lead L051 of the fifth connection lead L05 extends along the first direction G and is connected to the first P-type doped sub-region F_Psub1, the fifth P-type doped sub-region The extension direction of the region F_Psub5 is the same.
  • the first sub-lead L051 of the fifth connection lead L05 includes a first portion located on one side of the first direction G and a second portion located on the opposite side of the first direction G, and the first sub-lead L051 of the fifth connection lead L05
  • the first part overlaps with the fifth P-type doped sub-region F_Psub5 and is electrically connected through a plurality of first conductive pillars 351 arranged in sequence along the first direction G;
  • the second of the first sub-lead L051 of the fifth connection lead L05 A portion overlaps with the first P-type doped sub-region F_Psub1 and is electrically connected through a plurality of first conductive pillars 351 arranged in sequence along the first direction G.
  • the second part of the first sub-lead L051 of the fifth connection lead L05 is electrically connected to the first P-type doped sub-region F_Psub1 through two rows of first conductive pillars 351, and any row of the first
  • the conductive pillars 351 include a plurality of first conductive pillars 351 sequentially arranged along the first direction G. As shown in FIG. Further, referring to FIG. 13, the connecting position of the first part and the second part of the first sub-lead L051 of the fifth connection lead L05 is opposite to the second direction H of the fifth sub-lead L055 of the fifth connection lead L05. connect.
  • the second part of the first sub-lead L051 of the fifth connection lead L05 and the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7 are both along the first sub-connection line M7SL1.
  • the partial position of the second part of the first sub-lead L051 of the fifth connection lead L05 can also extend along the second direction H to form a first protrusion, the first sub-lead of the fifth connection lead L05
  • the first protrusion of L051 extends along the second direction H to the first sub-connection line of the source connection line corresponding to the seventh transistor M7
  • M7SL1 is connected so that the side in the opposite direction of the second direction H of the first sub-connection line M7SL1 corresponding to the source connection line of the seventh transistor M7 is connected to the second part of the first sub-lead L051 of the fifth connection lead L05 . Further, one end in the first direction G of the first protruding portion of the first sub-lead L051 of the fifth connection lead L05 is connected to the first direction G of the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7.
  • One end is flush with one end of the first protruding portion of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction to the first direction G and the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7.
  • One end opposite to the first direction G is flush with each other.
  • the length of the first protruding portion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is the same as that of the first sub-connection line M7SL1 of the source connection line of the seventh transistor M7 in the first direction G. same length as above.
  • the setting of the first protrusion of the first sub-lead L051 of the fifth connection lead L05 can make the first sub-connection line M7SL1 of the source connection line corresponding to the seventh transistor M7 and the first sub-connection line M7SL1 of the fifth connection lead L05
  • the second part of the lead L051 is a one-piece structure.
  • the second part of the first sub-lead L051 of the fifth connection lead L05 and the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 are both along the first sub-connection line M8SL1.
  • the partial position of the second part of the first sub-lead L051 of the fifth connection lead L05 can also extend along the second direction H to form a second protrusion, the first sub-lead of the fifth connection lead L05
  • the second protrusion of L051 extends along the second direction H to connect with the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8, so that the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8
  • the opposite side of the connecting line M8SL1 in the second direction H is connected to the second portion of the first sub-lead L051 of the fifth connecting lead L05 .
  • one end of the first direction G of the second protrusion of the first sub-lead L051 of the fifth connection lead L05 is connected to the first direction G of the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8.
  • One end is flush with one end of the second protruding portion of the first sub-lead L051 of the fifth connection lead L05 in the opposite direction to the first direction G and the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8.
  • One end opposite to the first direction G is flush with each other.
  • the length of the second protruding portion of the first sub-lead L051 of the fifth connection lead L05 in the first direction G is the same as that of the first sub-connection line M8SL1 of the source connection line of the eighth transistor M8 in the first direction G. same length as above.
  • the setting of the second protrusion of the first sub-lead L051 of the fifth connection lead L05 can make the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 and the first sub-connection line M8SL1 of the fifth connection lead L05
  • the second part of the lead L051 is a one-piece structure.
  • the first part of the first sub-lead L051 of the fifth connection lead L05 and the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1 are both along the first The direction G extends; the local position of the first part of the first sub-lead L051 of the fifth connection lead L05 can also extend along the second direction H to form a third protrusion, the first sub-lead L051 of the fifth connection lead L05
  • the third protrusion extends along the second direction H to connect with the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1, so that the first sub-connection line of the source connection line corresponding to the first transistor M1
  • the opposite side of the second direction H of the M1SL1 is connected to the first portion of the first sub-lead L051 of the fifth connection lead L05 .
  • one end in the first direction G of the third protruding portion of the first sub-lead L051 of the fifth connection lead L05 is connected to the first direction G of the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1.
  • One end is flush, and the end opposite to the first direction G of the third protrusion of the first sub-lead L051 of the fifth connection lead L05 is connected to the fifth sub-lead L055 of the fifth connection lead L05.
  • the third protruding portion of the first sub-lead L051 of the fifth connection lead L05 exceeds the first sub-connection line M1SL1 of the corresponding source connection line of the first transistor M1 in the direction opposite to the first direction G.
  • the setting of the third protrusion of the first sub-lead L051 of the fifth connection lead L05 can make the first sub-connection line M1SL1 of the source connection line corresponding to the first transistor M1 and the first sub-connection line M1SL1 of the fifth connection lead L05
  • the first part of the lead L051 is a one-piece structure.
  • the second sub-lead L052 of the fifth connection lead L05 extends along the second direction H, and is consistent with the extending direction of the second P-type doped sub-region F_Psub2, both Can overlap.
  • the second sub-lead L052 of the fifth connection lead L05 is electrically connected to the second P-type doped sub-region F_Psub2 through a plurality of first conductive pillars 351 arranged in sequence along the second direction H.
  • the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7 coincides with the second sub-connection line M13SL2 of the source connection line corresponding to the thirteenth transistor M13, and along the opposite direction of the first direction G The direction extends to connect with the second sub-lead L052 of the fifth connection lead L05.
  • the third sub-lead L053 of the fifth connection lead L05 extends along the first direction G and is connected to the third P-type doped sub-region F_Psub3, the seventh P-type doped sub-region
  • the extension direction of F_Psub7 is the same.
  • the third sub-lead L053 of the fifth connection lead L05 includes a first part located on one side of the first direction G and a second part located on the opposite side of the first direction G, the first part of the third sub-lead L053 of the fifth connection lead L05 It overlaps with the seventh P-type doped sub-region F_Psub7 and is electrically connected through a plurality of first conductive pillars 351 arranged in sequence along the first direction G; the second part of the third sub-lead L053 of the fifth connection lead L05 is connected to the second The three P-type doped sub-regions F_Psub3 overlap and are electrically connected through a plurality of first conductive pillars 351 arranged in sequence along the first direction G.
  • the second part of the third sub-lead L053 of the fifth connection lead L05 is electrically connected to the third P-type doped sub-region F_Psub3 through two rows of first conductive pillars 351, and any row of first conductive pillars 351 includes A plurality of first conductive pillars 351 arranged sequentially in the first direction G. Further, referring to FIG. 13 , the connecting position of the first part and the second part of the third sub-lead L053 of the fifth connection lead L05 is connected to one end of the fifth sub-lead L055 of the fifth connection lead L05 in the second direction H.
  • the second part of the third sub-lead L053 of the fifth connection lead L05 and the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13 are both along the Extend in one direction G; the second part of the second part of the third sub-lead L053 of the fifth connection lead L05 can also extend along the opposite direction of the second direction H to form a first protrusion, the third sub-lead of the fifth connection lead L05
  • the first protruding portion of the lead L053 extends in the direction opposite to the second direction H to connect to the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13, so that the source corresponding to the thirteenth transistor M13
  • the side in the second direction H of the first sub-connection line M13SL1 of the connection line is connected to the second portion of the third sub-lead L053 of the fifth connection lead L05 .
  • one end of the first protruding portion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is connected to the first direction G of the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13.
  • One end is flush, and one end of the first protruding portion of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction to the first direction G is connected to the first sub-connection line M13SL1 of the source connection line corresponding to the thirteenth transistor M13.
  • One end opposite to the first direction G is flush with each other.
  • the length of the first protrusion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is the same as that of the first sub-connection line M13SL1 of the source connection line of the thirteenth transistor M13 in the first direction G. same length as above.
  • the setting of the first protrusion of the third sub-lead L053 of the fifth connecting lead L05 can make the first sub-connecting line M13SL1 of the source connecting line corresponding to the thirteenth transistor M13 and the third sub-leading line of the fifth connecting lead L05
  • the second part of L053 is a one-piece structure.
  • the second part of the third sub-lead L053 of the fifth connection lead L05 and the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 are both along the A direction G extends; the second part of the third sub-lead L053 of the fifth connection lead L05 can also be extended along the opposite direction of the second direction H to form a second protrusion, and the third sub-lead L05 of the fifth connection lead L05
  • the second protruding portion of the lead L053 extends in the direction opposite to the second direction H to connect to the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14, so that the source corresponding to the fourteenth transistor M14
  • the side in the second direction H of the first sub-connection line M14SL1 of the connection line is connected to the second portion of the third sub-lead L053 of the fifth connection lead L05 .
  • one end of the second protruding portion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is connected to the first direction G of the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14.
  • One end is flush, and one end of the second protruding portion of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction to the first direction G is connected to the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14.
  • One end opposite to the first direction G is flush with each other.
  • the length of the second protruding portion of the third sub-lead L053 of the fifth connection lead L05 in the first direction G is the same as that of the first sub-connection line M14SL1 of the source connection line of the fourteenth transistor M14 in the first direction G. same length as above.
  • the setting of the second protrusion of the third sub-lead L053 of the fifth connecting lead L05 can make the first sub-connecting line M14SL1 of the source connecting line corresponding to the fourteenth transistor M14 and the third sub-leading line of the fifth connecting lead L05
  • the second part of L053 is a one-piece structure.
  • the first part of the third sub-lead L053 of the fifth connection lead L05 and the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 are both along the first direction.
  • the local position of the first part of the third sub-lead L053 of the fifth connection lead L05 can also extend along the opposite direction of the second direction H to form a third protrusion, the third sub-lead L053 of the fifth connection lead L05
  • the third protrusion extends along the opposite direction of the second direction H to connect with the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2, so that the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2
  • the side of the sub-connection line M2SL1 in the second direction H is connected to the first portion of the third sub-lead L053 of the fifth connection lead L05 .
  • one end in the first direction G of the third protrusion of the third sub-lead L053 of the fifth connection lead L05 is connected to one end in the first direction G of the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2
  • one end of the third protruding portion of the third sub-lead L053 of the fifth connection lead L05 in the opposite direction to the first direction G is connected to the fifth sub-lead L055 of the fifth connection lead L05.
  • the third protruding portion of the third sub-lead L053 of the fifth connection lead L05 exceeds the first sub-connection line M2SL1 of the corresponding source connection line of the second transistor M2 in the direction opposite to the first direction G.
  • the setting of the third protrusion of the third sub-lead L053 of the fifth connection lead L05 can make the first sub-connection line M2SL1 of the source connection line corresponding to the second transistor M2 and the third sub-lead L053 of the fifth connection lead L05 The first part of the integral structure.
  • the fourth sub-lead L054 of the fifth connection lead L05 extends along the second direction H, and is consistent with the extension direction of the sixth P-type doped sub-region F_Psub6, both Can overlap.
  • the fourth sub-lead L054 of the fifth connecting lead L05 is electrically connected to the sixth P-type doped sub-region F_Psub6 through a plurality of first conductive pillars 351 sequentially arranged along the second direction H.
  • one end in the first direction G of the sixth sub-lead L056 of the fifth connection lead L05 is connected to the middle position of the fourth sub-lead L054 of the fifth connection lead L05.
  • the areas of the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8 can be basically the same.
  • the fifth sub-lead L055 of the fifth connection lead L05 extends along the second direction H, and is consistent with the extension direction of the fourth P-type doped sub-region F_Psub4, both Can overlap.
  • the fifth sub-lead L055 of the fifth connection lead L05 is electrically connected to the fourth P-type doped sub-region F_Psub4 through a plurality of first conductive pillars 351 sequentially arranged along the second direction H.
  • the opposite end of the first direction G of the sixth sub-lead L056 of the fifth connection lead L05 is connected to the middle position of the fifth sub-lead L055 of the fifth connection lead L05.
  • the areas of the seventh sub-active region Act_sub7 and the eighth sub-active region Act_sub8 can be basically the same.
  • the sixth sub-lead L056 of the fifth connecting lead L05 extends along the first direction G, and is consistent with the extending direction of the eighth P-type doped sub-region F_Psub8, and the two may overlap.
  • the sixth sub-lead L056 of the fifth connection lead L05 is electrically connected to the eighth P-type doped sub-region F_Psub8 through a plurality of first conductive pillars 351 arranged in sequence along the first direction G.
  • the sixth sub-lead L056 of the fifth connection lead L05 and the second sub-connection M1SL2 of the source connection line corresponding to the first transistor M1 both extend along the first direction G.
  • At least a partial position of the sixth sub-lead L056 of the fifth connection lead L05 can also extend along the opposite direction of the second direction H to form a first protrusion, and the first part of the sixth sub-lead L056 of the fifth connection lead L05
  • the protrusion extends along the opposite direction of the second direction H to connect with the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1, so that the second sub-connection of the source connection line corresponding to the first transistor M1
  • the side of the line M1SL2 in the second direction H is connected to the sixth sub-lead L056 of the fifth connection lead L05.
  • one end of the first protruding portion of the sixth sub-lead L056 of the fifth connection lead L05 in the first direction G is connected to the first direction G of the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1.
  • One end of the sixth sub-lead L056 of the fifth connecting lead L05 is connected to the fifth sub-lead L055 of the fifth connecting lead L05 in the opposite direction to the first direction G of the first protruding portion of the fifth connecting lead L05.
  • the setting of the first protruding part of the sixth sub-lead L056 of the fifth connection lead L05 can make the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1 and the sixth sub-connection line M1SL2 of the fifth connection lead L05
  • the lead wire L056 is an integral structure.
  • the sixth sub-lead L056 of the fifth connection lead L05 and the second sub-connection M2SL2 of the source connection line corresponding to the second transistor M2 both extend along the first direction G.
  • At least a partial position of the sixth sub-lead L056 of the fifth connection lead L05 can also extend along the second direction H to form a second protrusion, and the second protrusion of the sixth sub-lead L056 of the fifth connection lead L05
  • the second sub-connection line M2SL2 extending along the second direction H to the source connection line corresponding to the second transistor M2 is connected, so that the second direction of the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2
  • the opposite side of H is connected to the sixth sub-lead L056 of the fifth connecting lead L05.
  • one end in the first direction G of the second protruding portion of the sixth sub-lead L056 of the fifth connection lead L05 is connected to the first direction G of the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2.
  • One end is flush, and one end of the second protruding portion of the sixth sub-lead L056 of the fifth connection lead L05 in the opposite direction to the first direction G is connected to the fifth sub-lead L055 of the fifth connection lead L05.
  • the setting of the second protrusion of the sixth sub-lead L056 of the fifth connection lead L05 can make the second sub-connection line M2SL2 of the source connection line corresponding to the second transistor M2 and the sixth sub-connection line M2SL2 of the fifth connection lead L05
  • the lead wire L056 is an integral structure.
  • the width of the sixth sub-lead L056 of the fifth connection lead L05 is larger than the width of the corresponding source connection line of each transistor.
  • the sixth sub-lead L056 of the fifth connection lead L05 is along the axis of the first direction G, and the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8/the fourteenth transistor
  • the second sub-connection line M14SL2 of the source connection line corresponding to M14 coincides with the axis along the first direction G.
  • the drain connection line M9DL corresponding to the ninth transistor M9, the drain connection line M10DL corresponding to the tenth transistor M10, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line corresponding to the eighth transistor M8 The axes of M8DL along the first direction G coincide.
  • the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13, and the drain connection line M13DL corresponding to the fourteenth transistor M14 The axes of the drain connection lines M14DL along the first direction G coincide.
  • the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9/the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11, and the source connection corresponding to the tenth transistor M10 The second sub-connection line M10SL2 of the same line/the second sub-connection line M12SL2 of the source connection line corresponding to the twelfth transistor M12, the second sub-connection line M7SL2/the thirteenth transistor of the source connection line corresponding to the seventh transistor M7
  • the second sub-connection line M13SL2 of the source connection line corresponding to M13, the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8/the second sub-connection line of the source connection line corresponding to the fourteenth transistor M14 The M14SL2 , the sixth connection lead L06 , and the sixth sub-lead L056 of the fifth connection lead L05 are coincident along the axis of the first direction G.
  • the first sub-connection line M9SL1 of the source connection line corresponding to the ninth transistor M9, the first sub-connection line M10SL1 of the source connection line corresponding to the tenth transistor M10, and the source connection line corresponding to the seventh transistor M7 The first sub-connection line M7SL1 of the eighth transistor M8 and the first sub-connection line M8SL1 of the source connection line corresponding to the eighth transistor M8 coincide along the axis of the first direction G.
  • the first sub-connection line M11SL1 of the source connection line corresponding to the eleventh transistor M11, the first sub-connection line M12SL1 of the source connection line corresponding to the twelfth transistor M12, and the source connection line corresponding to the thirteenth transistor M13 The first sub-connection line M13SL1 of the electrode connection line and the first sub-connection line M14SL1 of the source connection line corresponding to the fourteenth transistor M14 coincide along the axis of the first direction G.
  • the second metal wiring layer 362 may include a first control lead 421 , a second control lead 422 , a first output lead 431 and a second output lead 432 , and include a portion of connection leads.
  • the connecting leads located on the second metal wiring layer 362 may include seventh connecting leads L07 to fifteenth connecting leads L15 .
  • the seventh connecting lead L07 extends along the first direction G and overlaps the first sub-lead L011 of the first connecting lead L01 and the first sub-lead L021 of the second connecting lead L02 .
  • extension lines of the seventh connection lead L07 , the first sub-lead L011 of the first connection lead L01 , and the first sub-lead L021 of the second connection lead L02 are substantially coincident.
  • the seventh connection lead L07 can be electrically connected to the first sub-lead L011 of the first connection lead L01 through a plurality of second conductive pillars 352 arranged along the first direction G, and the seventh connection lead L07 can pass through the first sub-lead L011 along the first direction G.
  • the arranged plurality of second conductive columns 352 is electrically connected to the first sub-lead L021 of the second connection lead L02. Further, each second conductive column 352 connected to the seventh connection lead L07 is arranged in a straight line along the first direction G. It can be understood that the second conductive pillar 352 may not be provided in the gap between the first sub-lead L011 of the first connection lead L01 and the first sub-lead L021 of the second connection lead L02 .
  • one end of the seventh connection lead L07 in the first direction G does not exceed one end of the first sub-lead L021 of the second connection lead L02 in the first direction G;
  • the opposite end of the first direction G of the seventh connecting lead L07 exceeds the opposite end of the first direction G of the first sub-lead L011 of the first connecting lead L01.
  • the eighth connecting lead L08 extends along the first direction G and overlaps the third sub-lead L013 of the first connecting lead L01 and the fourth sub-lead L024 of the second connecting lead L02 .
  • the extension lines of the eighth connection lead L08 , the third sub-lead L013 of the first connection lead L01 and the fourth sub-lead L024 of the second connection lead L02 are substantially coincident.
  • the eighth connection lead L08 can be electrically connected to the third sub-lead L013 of the first connection lead L01 through a plurality of second conductive pillars 352 arranged along the first direction G, and the eighth connection lead L08 can be arranged along the first direction G by
  • the plurality of second conductive pillars 352 are electrically connected to the fourth sub-lead L024 of the second connection lead L02.
  • each second conductive column 352 connected to the seventh connection lead L07 is arranged in a straight line along the first direction G. It can be understood that the second conductive pillar 352 may not be provided in the gap between the third sub-lead L013 of the first connection lead L01 and the fourth sub-lead L024 of the second connection lead L02 .
  • one end of the eighth connection lead L08 in the first direction G does not exceed one end of the first direction G of the fourth sub-lead L024 of the second connection lead L02;
  • the opposite end of the first direction G of the eighth connecting lead L08 exceeds the opposite end of the first direction G of the third sub-lead L013 of the first connecting lead L01.
  • the second power supply voltage V2 may be applied to the seventh connection lead L07 and the eighth connection lead L08 , and then the second power supply voltage V2 may be applied to the first connection lead L01 and the second connection lead L02 .
  • the ninth connection lead L09 extends along the first direction G and overlaps the first sub-lead L051 of the fifth connection lead L05 .
  • the extension lines of the ninth connecting lead L09 and the first sub-lead L051 of the fifth connecting lead L05 are substantially coincident.
  • the ninth connection lead L09 may be electrically connected to the first sub-lead L051 of the fifth connection lead L05 through the plurality of second conductive pillars 352 arranged along the first direction G.
  • one end of the ninth connection lead L09 in the first direction G does not exceed one end of the first sub-lead L051 of the fifth connection lead L05 in the first direction G;
  • the opposite end of the first direction G of the ninth connecting lead L09 exceeds the opposite end of the first direction G of the first sub-lead L051 of the fifth connecting lead L05.
  • one end of the ninth connecting lead L09 in the opposite direction to the first direction G is flush with the end of the fifth connecting lead L05 in the opposite direction to the first direction G of the first sub-lead L051; along the first direction G, the ninth One end of the connection lead L09 in the first direction G is flush with the first end G of the drain connection line M1DL corresponding to the first transistor M1.
  • the tenth connection lead L10 extends along the first direction G and overlaps the third sub-lead L053 of the fifth connection lead L05 .
  • the extension lines of the tenth connection lead L10 and the third sub-lead L053 of the fifth connection lead L05 are substantially coincident. In this way, the tenth connection lead L10 may be electrically connected to the third sub-lead L053 of the fifth connection lead L05 through the plurality of second conductive pillars 352 arranged along the first direction G.
  • one end of the tenth connection lead L10 in the first direction G does not exceed one end of the first direction G of the third sub-lead L053 of the fifth connection lead L05; along the opposite direction of the first direction G
  • the opposite end of the first direction G of the tenth connecting lead L10 is beyond the opposite end of the first direction G of the third sub-lead L053 of the fifth connecting lead L05 .
  • the opposite end of the first direction G of the tenth connection lead L10 is flush with the opposite end of the first direction G of the third sub-lead L053 of the fifth connection lead L05; along the first direction G, the tenth connection One end of the lead L10 in the first direction G is flush with the end of the first direction G of the drain connection line M2DL corresponding to the second transistor M2.
  • the ninth connecting lead L09 and the tenth connecting lead L10 may be loaded with the first power supply voltage V1, and then the fifth connecting lead L05 may be loaded with the first power supply voltage V1.
  • the seventh connecting lead L07 and the ninth connecting lead L09 are located on the same straight line, and the ninth connecting lead L09 is located on the side of the seventh connecting lead L07 in the first direction G.
  • the eighth connecting lead L08 and the tenth connecting lead L10 are located on the same straight line, and the tenth connecting lead L10 is located on the side of the eighth connecting lead L08 in the first direction G.
  • the seventh connecting lead L07 , the eighth connecting lead L08 , the ninth connecting lead L09 and the tenth connecting lead L10 have the same width (that is, the size in the second direction H) and are larger than each transistor The width of the corresponding source connection line. In this way, the impedance of the seventh connecting lead L07 , the eighth connecting lead L08 , the ninth connecting lead L09 and the tenth connecting lead L10 can be reduced, and the enhanced driving capability of the row driving signal can be improved.
  • the eleventh connection lead L11 extends along the first direction G, corresponding to the transition line of the gate connection line M9GL corresponding to the ninth transistor M9 and the tenth transistor M10
  • the drain connection line M1DL corresponding to a transistor M1 overlaps and is connected through the second conductive pillar 352 .
  • the eleventh connection lead L11 may also be provided with a transition line extending toward the second direction H; the transition line of the eleventh connection lead L11 overlaps with the gate connection line M8GL corresponding to the eighth transistor M8, and passes through The second conductive pillar 352 is connected.
  • one end of the first direction G of the drain connection line M1DL corresponding to the first transistor M1 is located on the side of the first direction G of the first end of the first direction G of the eleventh connection lead L11, and the tenth An end opposite to the first direction G of a connection lead L11 is flush with an end opposite to the first direction G of the gate connection line M9GL corresponding to the ninth transistor M9 .
  • the width of the eleventh connection lead L11 is the same as the width of the source connection line corresponding to each transistor.
  • the twelfth connection lead L12 is linearly arranged along the first direction G, and the transfer line of the gate connection line M11GL corresponding to the eleventh transistor M11 , the tenth The transition line of the gate connection line M12GL corresponding to the second transistor M12, the transition line of the gate connection line M13GL corresponding to the thirteenth transistor M13, the drain connection line M3DL corresponding to the third transistor M3/the drain corresponding to the fourth transistor M4 The connection line M4DL and the drain connection line M2DL corresponding to the second transistor M2 overlap and are connected through the second conductive pillar 352 .
  • the twelfth connection lead L12 may also be provided with a transition line extending in the opposite direction to the second direction H; the transition line of the twelfth connection lead L12 intersects with the gate connection line M14GL corresponding to the fourteenth transistor M14 stacked and connected through the second conductive pillar 352.
  • the first end G of the drain connection line M2DL corresponding to the second transistor M2 is located on the first direction G side of the first direction G end of the twelfth connection lead L12, and the tenth end
  • the opposite end of the first direction G of the two connection leads L12 is flush with the opposite end of the first direction G of the gate connection line M11GL corresponding to the eleventh transistor M11 .
  • the width of the twelfth connection lead L12 is the same as the width of the source connection line corresponding to each transistor.
  • the thirteenth connection lead L13 extends along the first direction G, and is sequentially corresponding to the second sub-lead L012 of the first connection lead L01 and the ninth transistor M9.
  • the second sub-connection line M9SL2 of the source connection line/the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11, the second sub-connection line M10SL2/the second sub-connection line of the source connection line corresponding to the tenth transistor M10 The second sub-connection line M12SL2 of the source connection line corresponding to the twelve transistors M12, the second sub-lead L022 of the second connection lead L02, the third connection lead L03, the sixth connection lead L06, the fourth connection lead L04, the second The third sub-lead L023 connecting the lead L02 overlaps.
  • one end of the thirteenth connection lead L13 in the first direction G does not exceed the third sub-lead L023 of the second connection lead L02, and one end of the thirteenth connection lead L13 in the opposite direction of the first direction G does not exceed The second sub-lead L012 beyond the first connection lead L01.
  • one end of the thirteenth connecting lead L13 in the first direction G is flush with the side of the third sub-lead L023 of the second connecting lead L02 in the first direction G
  • One end of the L13 in the opposite direction to the first direction G is flush with the side of the second sub-lead L012 of the first connection lead L01 in the opposite direction to the first direction G.
  • the thirteenth connection lead L13 is respectively connected to the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9/the eleventh transistor through the second conductive column 352
  • the second sub-connection line M11SL2 of the source connection line corresponding to M11, the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10/the second sub-connection line of the source connection line corresponding to the twelfth transistor M12 M12SL2 is electrically connected to the sixth connection lead L06.
  • the thirteenth connection lead L13 can load the second power supply voltage V2 on the first connection lead L01 to the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10/the source corresponding to the twelfth transistor M12
  • connection between the thirteenth connection lead L13 and the second sub-connection line M9SL2 of the source connection line corresponding to the ninth transistor M9/the second sub-connection line M11SL2 of the source connection line corresponding to the eleventh transistor M11 is passed along the A plurality of second conductive pillars 352 arranged sequentially in the first direction G are electrically connected, and the thirteenth connection lead L13 is connected to the second sub-connection line M10SL2 of the source connection line corresponding to the tenth transistor M10/the source corresponding to the twelfth transistor M12
  • the second sub-connection line M12SL2 of the pole connection line is electrically connected through a plurality of second conductive pillars 352 arranged in sequence along the first direction G, and the thirteenth connection lead L13 and the sixth connection lead L06 are connected electrically through a plurality of second conductive columns 352 arranged along the first direction G.
  • the plurality of second conductive pillars 352 arranged sequentially are electrically connected. Further, the thirteenth connection lead L13 is electrically connected to the second sub-lead L012 of the first connection lead L01 through a second conductive column 352, and the thirteenth connection lead L13 is connected to the second sub-lead L02 of the second connection lead L02. The L022 are electrically connected through a second conductive column 352 , and the thirteenth connection lead L13 is electrically connected with the third sub-lead L023 of the second connection lead L02 through a second conductive column 352 .
  • the gate connection line M9GL corresponding to the ninth transistor M9 and the gate connection line M11GL corresponding to the eleventh transistor M11 are respectively located at the thirteenth connection The two sides of the lead L13, and do not overlap with the thirteenth connection lead L13; the gate connection line M10GL corresponding to the tenth transistor M10 and the gate connection line M12GL corresponding to the twelfth transistor M12 are respectively located on the thirteenth connection lead L13 on both sides, and does not overlap with the thirteenth connection lead L13.
  • the width of the thirteenth connection lead L13 is the same as the width of the source connection line corresponding to each transistor.
  • the fourteenth connecting lead L14 and the fifteenth connecting lead L15 are connected to each other and both extend along the first direction G, and the fifteenth connecting lead L15 is located at the fourteenth Connect to one side of the first direction G of the lead wire L14.
  • the axes of the fourteenth connecting lead L14 and the fifteenth connecting lead L15 along the first direction G coincide.
  • the fourteenth connection lead L14 is sequentially connected to the second sub-lead L052 of the fifth connection lead L05, the second sub-connection line M7SL2 of the source connection line corresponding to the seventh transistor M7/the source connection line corresponding to the thirteenth transistor M13
  • the second sub-connection line M13SL2, the second sub-connection line M8SL2 of the source connection line corresponding to the eighth transistor M8/the second sub-connection line M14SL2 of the source connection line corresponding to the fourteenth transistor M14 overlap and are electrically connected. Referring to FIG.
  • the fourteenth connecting lead L14 and the second sub-lead L052 of the fifth connecting lead L05 may be electrically connected through a second conductive column 352 , or directly connected without the second conductive column 352 .
  • the second conductive column 352 directly connected to the fourteenth connection lead L14 and the second sub-lead L052 of the fifth connection lead L05 may also be located on the fourteenth connection lead L14 and the corresponding source connection line of the seventh transistor M7.
  • the width of the fourteenth connection lead L14 is the same as the width of the source connection line corresponding to each transistor.
  • the fifteenth connection lead L15 overlaps with the sixth sub-lead L056 of the fifth connection lead L05 and is electrically connected through the second conductive pillar 352 .
  • the fifteenth connection lead L15 is electrically connected to the sixth sub-lead L056 of the fifth connection lead L05 through a plurality of second conductive pillars 352 arranged along the first direction G.
  • the sixth sub-lead L056 of the fifth connection lead L05 has a first protrusion and a second protrusion, so that the local width of the sixth sub-lead L056 of the fifth connection lead L05 is larger than that of the fourteenth connection lead L14 width.
  • the width of the fifteenth connection lead L15 may be the same as the maximum width of the sixth sub-lead L056 of the fifth connection lead L05, and the fifteenth connection lead L15 and the sixth sub-lead L056 of the fifth connection lead L05 pass through
  • Two rows of second conductive pillars 352 are electrically connected, and any row of second conductive pillars 352 includes a plurality of second conductive pillars 352 arranged along the first direction G. Furthermore, among the two rows of second conductive pillars 352, one row of second conductive pillars 352 overlaps with the first protrusion of the fifteenth connection lead L15, and the other row of second conductive pillars 352 overlaps with the fifteenth connection lead L15. The second protrusion of L15 overlaps.
  • the opposite end of the first direction G of the fifteenth connection lead L15 overlaps with the fifth sub-lead L055 of the fifth connection lead L05, and connects with the fifth sub-lead L05 of the fifth connection lead L05 through the second conductive column 352.
  • the sub-lead L055 is electrically connected.
  • one end of the second sub-connection line M1SL2 of the source connection line corresponding to the first transistor M1 in the first direction G is located on the side of the first direction G of the end of the fifteenth connection lead L15 in the first direction G. Further, one end of the fifteenth connecting lead L15 in the first direction G is flush with one end of the eleventh connecting lead L11 and the twelfth connecting lead L12 in the first direction G.
  • the first output lead 431 extends along the first direction G, and the drain connecting line M9DL corresponding to the ninth transistor M9, the drain connecting line M10DL corresponding to the tenth transistor M10, the seventh
  • the drain connection line M7DL corresponding to the transistor M7 is electrically connected to the drain connection line M8DL corresponding to the eighth transistor M8 through the second conductive pillar 352 .
  • the drain connection line M9DL corresponding to the ninth transistor M9, the drain connection line M10DL corresponding to the tenth transistor M10, the drain connection line M7DL corresponding to the seventh transistor M7, the eighth transistor M8 The corresponding drain connection line M8DL extends straight along the first direction G and is located on the same straight line; the extension direction of the first output lead 431 is connected to the drain connection line M9DL corresponding to the ninth transistor M9 and the drain corresponding to the tenth transistor M10
  • the extension directions of the line M10DL, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line M8DL corresponding to the eighth transistor M8 coincide, and correspond to the drain connection line M9DL corresponding to the ninth transistor M9, and the tenth transistor M10.
  • the drain connection line M10DL of the seventh transistor M7, the drain connection line M7DL corresponding to the seventh transistor M7, and the drain connection line M8DL corresponding to the eighth transistor M8 overlap, and respectively pass through a plurality of second conductive pillars 352 arranged along the first direction G connection; these second conductive pillars 352 may be located on the same straight line.
  • one end of the first output lead 431 in the direction opposite to the first direction G exceeds the second sub-lead L012 of the first connection lead L01 , So that the first output lead 431 serves as the second output terminal OUT2 of the row driving signal enhancement circuit 101 to output the first scan signal to the display area D of the display panel.
  • the second output lead 432 extends along the first direction G, and connects the drain corresponding to the eleventh transistor M11 to the line M11DL, and the drain corresponding to the twelfth transistor M12
  • the connection line M12DL, the drain connection line M13DL corresponding to the thirteenth transistor M13 and the drain connection line M14DL corresponding to the fourteenth transistor M14 are electrically connected through the second conductive pillar 352 .
  • the drain connection line M11DL corresponding to the eleventh transistor M11, the drain connection line M12DL corresponding to the twelfth transistor M12, the drain connection line M13DL corresponding to the thirteenth transistor M13, and the drain connection line M13DL corresponding to the thirteenth transistor M13 extends straight along the first direction G and is located on the same straight line; the extension direction of the second output lead 432 is the same as that of the drain connection line M11DL corresponding to the eleventh transistor M11,
  • the extension directions of the drain connection line M12DL corresponding to the M12, the drain connection line M13DL corresponding to the thirteenth transistor M13, and the drain connection line M14DL corresponding to the fourteenth transistor M14 overlap, and are respectively passed through multiple transistors arranged along the first direction G.
  • the two second conductive pillars 352 are connected, and these second conductive pillars 352 can be located on the same straight line.
  • one end of the second output lead 432 in the opposite direction of the first direction G exceeds the second sub-lead L012 of the first connection lead L01, so that the second output lead 432 serves as a row driving signal
  • the second output terminal OUT2 of the enhancement circuit 101 outputs the second scanning signal to the display area D of the display panel.
  • the first control lead 421 is located on the first direction G side of the drain connection line M1DL corresponding to the first transistor M1, and the gate connection line M1GL corresponding to the first transistor M1 passes through the first direction G side.
  • the two conductive pillars 352 are electrically connected. In this way, the first control wire 421 can be used as the first input terminal IN1 of the row driving signal enhancing circuit 101 to input the first initial scan signal to the row driving signal enhancing circuit 101 .
  • the first control lead 421 extends along the first direction G, and its end in the first direction G is located on the side of the first direction G of the fourth sub-lead L054 of the fifth connection lead L05, so that it can receive the first initial scan signal.
  • An end opposite to the first direction G of the first control lead 421 is flush with the corresponding gate connection line M1GL of the first transistor M1 .
  • one end of the first control lead 421 in the direction opposite to the first direction G has a connection portion, and the connection portion of the first control lead 421 extends in the direction opposite to the second direction H and is connected to the corresponding gate of the first transistor M1
  • the line M1GL overlaps and is connected to the corresponding gate connection line M1GL of the first transistor M1 through the second conductive pillar 352 .
  • the conductive area between the first control lead 421 and the gate connection line M1GL corresponding to the first transistor M1 can be increased, thereby reducing the delay of the row driving signal enhancement circuit 101 .
  • the second control lead 422 is located on the first direction G side of the drain connection line M2DL corresponding to the second transistor M2, and the gate connection line M2GL corresponding to the second transistor M2 passes through the second transistor M2.
  • the two conductive pillars 352 are electrically connected. In this way, the second control wire 422 can be used as the second input terminal IN2 of the row driving signal enhancing circuit 101 to input the second initial scan signal to the row driving signal enhancing circuit 101 .
  • the second control lead 422 extends along the first direction G, and its end in the first direction G is located on the side of the first direction G of the fourth sub-lead L054 of the fifth connection lead L05, so that it can receive the second initial scan signal.
  • An end of the second control lead 422 opposite to the first direction G is flush with the gate connection line M2GL corresponding to the second transistor M2.
  • one end of the second control lead 422 in the direction opposite to the first direction G has a connection portion, and the connection portion of the second control lead 422 extends along the second direction H and intersects with the gate connection line M2GL corresponding to the second transistor M2. It is connected to the gate connection line M2GL corresponding to the second transistor M2 through the second conductive pillar 352 . In this way, the conductive area between the second control lead 422 and the gate connection line M2GL corresponding to the second transistor M2 can be increased, thereby reducing the delay of the row driving signal enhancement circuit 101 .
  • the second metal wiring layer 362 may also have a sixteenth connection lead L16 and a seventeenth connection lead L17, and a sixteenth connection lead L16 and a seventeenth connection lead L17. Extend along the first direction G and the extension axes of the two coincide.
  • the sixteenth connecting lead L16 runs through the N-type substrate region F_Ndop along the first direction G, and is located between the eighth connecting lead L08 and the twelfth connecting lead L12 .
  • the seventeenth connecting lead L17 runs through the P-type substrate region F_Pdop along the first direction G, and is located between the tenth connecting lead L10 and the twelfth connecting lead L12 .
  • the sixteenth connecting lead L16 and the seventeenth connecting lead L17 are not electrically connected to any second conductive column 352 and third conductive column 353, so that the sixteenth connecting lead L16 and the The seventeenth connection lead L17 is located in the row driving signal enhancing region F but does not constitute a part of the row driving signal enhancing circuit 101 .
  • the third metal wiring layer 363 may be provided with a first power lead 411 and a second power lead 412 .
  • the first power lead 411 overlaps the ninth connection lead L09 and the tenth connection lead L10 and is electrically connected through the third conductive column 353 . Further, the first power lead 411 overlaps with the fourteenth connection lead L14 and the fifteenth connection lead L15 , and is electrically connected through the third conductive column 353 .
  • the first power lead 411 covers the third active region Act3 and the fourth active region Act4 to shield external signals from the seventh transistor M7, the eighth transistor M8, and the thirteenth transistor M13. , the interference of the fourteenth transistor M14, the first transistor M1 and the second transistor M2.
  • the first power lead 411 has two opposite sides extending along the second direction H, wherein the side on the side of the first direction G is connected to the ninth connecting lead One end of the L09 in the first direction G is flush, and the side of the opposite side of the first direction G is flush with one end of the ninth connecting lead L09 in the opposite direction of the first direction G.
  • the display panel includes a plurality of row signal drive enhancement regions F arranged sequentially along the second direction H, and a row signal drive enhancement circuit is arranged in any row signal drive enhancement region F .
  • Each row signal driving enhancement circuit can share the same first power supply lead 411, and the first power supply lead 411 extends along the second direction H to cover the third active region Act3 and the fourth active region Act4 of each row signal driving enhancement region , and are electrically connected to the ninth connecting lead L09 , the tenth connecting lead L10 , the fourteenth connecting lead L14 and the fifteenth connecting lead L15 in the respective row signal driving enhanced regions F through the third conductive pillar 353 .
  • the second power lead 412 overlaps the seventh connecting lead L07 and the eighth connecting lead L08 and is electrically connected through the third conductive column 353 . Further, the second power lead 412 overlaps with the thirteenth connection lead L13 and is electrically connected through the third conductive column 353 . In one embodiment of the present disclosure, the second power lead 412 covers the first active region Act1 and the second active region Act2 to shield the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 from external signals. , the interference of the twelfth transistor M12, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6.
  • the display panel includes a plurality of row signal driving enhancement regions F arranged sequentially along the second direction H, and a row signal driving enhancement circuit is arranged in any row signal driving enhancement region.
  • Each row signal driving enhancement circuit can share the same second power supply lead 412, and the second power supply lead 412 extends along the second direction H to cover the first active region Act1 and the second active region of each row signal driving enhancement region Act2, and is electrically connected to the seventh connecting lead L07 , the eighth connecting lead L08 , and the fourteenth connecting lead L14 in each row signal driving enhanced region through the third conductive column 353 .
  • the number of the second power supply leads 412 is two, and the two second power supply leads 412 both extend along the second direction H.
  • the second power lead 412 on the side of the first direction G covers the second sub-active region Act_sub2 and the second active region Act2, and its edge on the side of the first direction G is in the third sub-region of the second connection lead L02
  • the side of the lead L023 in the first direction G, its edge in the opposite direction of the first direction G is on the side of the first sub-lead L021 of the second connecting lead L02 in the opposite direction of the first direction G.
  • the second power lead 412 on the opposite side of the first direction G overlaps the first sub-active region Act_sub1, and its edge on the side of the first direction G is connected to the drain connection line M9DL corresponding to the ninth transistor M9.
  • One end in the first direction G is flush, and its edge on the opposite side of the first direction G is flush with the edge opposite to the first direction G of the second sub-lead L012 of the first connecting lead L01 .
  • the two second power lead wires 412 both extend along the second direction H, so as to sequentially pass through a plurality of row signal driving enhancement regions F arranged in a straight line along the second direction H. As shown in FIG.
  • two adjacent row signal drive enhancement circuits along the second direction H may share part of the metal wiring layer and part of the conductive column; correspondingly, two adjacent row signal drive enhancement regions along the second direction H may share part of the area .
  • each row signal driving enhanced region F can be numbered sequentially along the second direction H, wherein the third N-type doped sub-region F_Nsub3 of the upper row signal driven enhanced region can be the same as the first N-type doped subregion F_Nsub3 of the next row signal driven enhanced region
  • the third N-type doped sub-region F_Nsub1 of the upper row of signal-driven enhancement region can be considered as the third N-type doped sub-region F_Nsub3 of the upper row of signal-driven enhancement region and the first N-type doped sub-region of the next row of signal-driven enhancement region.
  • the hetero subregion F_Nsub1 is the same N-type doped subregion.
  • the seventh N-type doped sub-region F_Nsub7 of the signal-driven enhancement region of the upper row can be connected with the fifth N-type doped sub-region F_Nsub5 of the lower row of signal-driven enhancement region to form an integral structure and be arranged axially symmetrically, or It can be considered that the seventh N-type doped sub-region F_Nsub7 of the signal-driven enhancement region in the upper row is the same N-type doped sub-region as the fifth N-type doped sub-region F_Nsub5 of the lower-row signal-driven enhanced region.
  • the third P-type doped sub-region F_Psub3 of the signal-driven enhancement region in the upper row can be connected with the first P-type doped sub-region F_Psub1 of the lower row of signal-driven enhancement region to form an integrated structure and be arranged axially symmetrically, or it can be considered that the upper
  • the third P-type doped sub-region F_Psub3 of a row of signal-driven enhancement regions is the same P-type doped sub-region as the first P-type doped sub-region F_Psub1 of the next row of signal-driven enhancement regions.
  • the seventh P-type doped sub-region F_Psub7 of the signal-driven enhancement region in the upper row can be connected with the fifth P-type doped sub-region F_Psub5 of the lower row of signal-driven enhanced region to form an integrated structure and be arranged axially symmetrically, or it can be considered that the upper
  • the seventh P-type doped sub-region F_Psub7 of a row of signal-driven enhancement regions is the same P-type doped sub-region as the fifth P-type doped sub-region F_Psub5 of the next row of signal-driven enhancement regions.
  • each row signal driving enhancement circuit may be numbered sequentially along the second direction H.
  • the third sub-lead L013 of the first connection lead L01 of the signal drive enhancement circuit in the previous row can be connected with the first sub-lead L011 of the first connection lead L01 of the signal drive enhancement circuit of the next row to form an integral structure and arranged axially symmetrically,
  • the third sub-lead L013 of the first connection lead L01 of the signal driving enhancement circuit in the last row is the same sub-lead as the first sub-lead L011 of the first connection lead L01 of the signal driving enhancement circuit of the next row.
  • the fourth sub-lead L024 of the second connection lead L02 of the signal drive enhancement circuit in the previous row can be connected with the first sub-lead L021 of the second connection lead L02 of the signal drive enhancement circuit in the next row to form an integral structure and be axially symmetrical. Or it can be considered that the fourth sub-lead L024 of the second connection lead L02 of the signal driving enhancement circuit in the previous row is the same sub-lead as the first sub-lead L021 of the second connection lead L02 of the signal driving enhancement circuit of the next row.
  • the third sub-lead L053 of the fifth connection lead L05 of the signal drive enhancement circuit in the previous row can be connected with the first sub-lead L051 of the fifth connection lead L05 of the signal drive enhancement circuit in the next row to form an integral structure and be arranged axially symmetrically, or It can be considered that the third sub-lead L053 of the fifth connection lead L05 of the signal driving enhancement circuit in the previous row is the same sub-lead as the first sub-lead L051 of the fifth connection lead L05 of the signal driving enhancement circuit in the next row.
  • the eighth connection lead L08 of the signal drive enhancement circuit in the upper row can be connected with the seventh connection lead L07 of the signal drive enhancement circuit in the next row to form an integral structure and arranged axially symmetrically, or it can be considered as the eighth connection lead of the signal drive enhancement circuit in the upper row.
  • the connecting lead L08 is the same lead as the seventh connecting lead L07 of the next row of signal driving enhancement circuits.
  • the tenth connection lead L10 of the signal drive enhancement circuit in the previous row can be connected with the ninth connection lead L09 of the signal drive enhancement circuit in the next row to form an integral structure and arranged axially symmetrically, or it can be considered as the tenth connection lead of the signal drive enhancement circuit in the previous row.
  • the connection lead L10 is the same lead as the ninth connection lead L09 of the next row of signal driving enhancement circuits.
  • the display panel is further provided with a pixel driving circuit 104 in the display area D, and the pixel driving circuit 104 includes a data writing unit 250 , a storage capacitor Cst and a driving transistor M03 .
  • the data writing unit has a first control electrode and a second control electrode, the first control electrode of the data writing unit is connected to the first output lead 431, the second control electrode of the data writing unit is connected to the second output lead 432, and the data The input end of the writing unit is connected to the data line of the display panel, and the output end of the data writing unit is connected to the third node C.
  • the first electrode plate of the storage capacitor Cst is connected to the third node C, and the second electrode plate of the storage capacitor Cst is loaded with the first driving voltage.
  • the control terminal of the driving transistor M03 is connected to the third node C, the output terminal of the driving transistor M03 is connected to the light-emitting elements of the display panel (such as OLED, liquid crystal pixel unit, LED, etc.), and the input terminal of the driving transistor M03 can be loaded with the second driving voltage.
  • the row driving signal enhancement circuit 101 can output a scan signal to control the on or off of the data writing unit.
  • the data voltage Vdata applied to the input terminal of the data writing unit may be applied to the third node C.
  • the data writing unit may include a first switching transistor M01 and a second switching transistor M02.
  • one of the first switching transistor M01 and the second switching transistor M02 is a P-type transistor, and the other is an N-type transistor; the P-type transistor can be turned on in response to the first power supply voltage V1 applied to its control terminal, and N The type transistor can be turned on in response to the second power supply voltage V2 applied to its control terminal.
  • the control terminal of the first switching transistor M01 can be used as the first control electrode of the data writing unit
  • the control terminal of the second switching transistor M02 can be used as the second control electrode of the data writing unit.
  • both the first switching transistor M01 and the second switching transistor M02 can be turned on; when the non-scanning signal is applied to the first control electrode of the data writing unit control electrode and the second control electrode, for example, when the base voltage on the first output terminal OUT1 and the second output terminal OUT2 of the row driving signal enhancement circuit 101 is applied to the first control electrode and the second control electrode of the data writing unit , the data writing units are all cut off.
  • the second power supply voltage of the row driving signal enhancing circuit 101 is the second power supply voltage V2 and the voltage of the scan signal is the first power supply voltage V1.
  • the first switch transistor M01 can be an N-type transistor
  • the second switch transistor M02 can be a P-type transistor.
  • the display area D is provided with a first gate lead and a second gate lead.
  • the first control electrode of the data writing unit is connected to the first gate lead, and the second control electrode of the data writing unit is connected to the second gate lead.
  • the first output lead 431 of the row driving signal enhancement circuit 101 is connected to the first gate lead, and the second output lead 432 of the row drive signal enhancement circuit 101 is connected to the second gate lead.
  • the first power lead 411 is used for loading the first driving voltage
  • the second power lead 412 is used for loading the second driving voltage. That is, the first driving voltage is the same as the first power supply voltage, and the second driving voltage is the same as the second power supply voltage.
  • the row driving signal enhancement circuit 101 provided by the present disclosure has the same power supply voltage specification as the scanning signal and the power supply voltage specification of the display area D, which not only simplifies the power supply specification setting and power supply distribution setting of the display panel, but also significantly Improve the driving ability of the scanning signal.
  • the display panel is further provided with a plurality of shift registers 102 and a plurality of inverters 103 in a one-to-one correspondence with each row driving signal enhancement circuit 101 in the peripheral area E.
  • the shift register 102 and the inverter 103 corresponding to each other, the output terminal of the shift register 102 and the input terminal of the inverter 103, the first control lead 421 of the row drive signal enhancement circuit 101
  • the output terminal of the inverter 103 is connected to the second control lead 422 of the row driving signal enhancement circuit 101 .
  • the shift register 102 can output the first initial scan signal, and the first initial scan signal can be loaded to the first control terminal IN1 of the row driving signal enhancement circuit 101 .
  • the inverter 103 can generate an opposite second preliminary scanning signal according to the first preliminary scanning signal, and the second preliminary scanning signal can be loaded to the second control terminal IN2 of the row driving signal enhancement circuit 101 .
  • the two control terminals of the row driving signal enhancement circuit 101 are respectively loaded with two different initial scan signals, and output the first scan signal and the second scan signal under the control of the two different initial scan signals, so as to Scan the pixel driver circuit.
  • the row driving signal enhancement circuit 101 can generate two opposite scanning signals formed by the first power supply voltage V1 and the second power supply voltage V2 according to the first preliminary scanning signal output by the shift register 102, thereby improving the scanning signal Drive capability.

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Abstract

公开了一种行驱动信号增强电路、移位寄存器单元和显示面板，属于显示技术领域。行驱动信号增强电路包括第一控制单元（110）、第二控制单元（120）、第一输出单元（130）和第二输出单元（140）。第一控制单元（110）用于在第一控制端（IN1）和第二控制端（IN2）的控制下输出第一电源电压（V1）至第一节点（A）或第二节点（B）；第二控制单元（120）用于响应第一节点上（A）的第一电源电压（V1）而输出第二电源电压（V2）至第二节点（B），且用于响应第二节点（B）上的第一电源电压（V1）而输出第二电源电压（V2）至第一节点（A）；第一输出单元（110）用于在第一节点（A）控制下输出第一电源电压（V1）和第二电源电压（V2）中的一个至第一输出端（OUT1）；第二输出单元（120）用于在第二节点（B）的控制下输出第一电源电压（V1）和第二电源电压（V2）中的另一个至第二输出端（OUT2）。该行驱动信号增强电路能增强行驱动信号的驱动能力。

Description

行驱动信号增强电路、移位寄存器单元和显示面板 技术领域
本公开涉及显示技术领域，具体而言，涉及一种行驱动信号增强电路、移位寄存器单元和显示面板。
背景技术
在显示面板中，可以通过栅极引线向像素驱动电路加载扫描信号；由于栅极引线上的负载以及阻抗等原因，当扫描信号抵达像素驱动电路时往往会出现一定的延迟和电压损失。在硅基OLED(有机电致发光二极管)显示器中，由于像素分辨率大，因此栅极引线上的扫描信号的延迟和压降损失较大，这会导致不同像素驱动电路写入的数据电压不同，进而降低了硅基OLED显示器的显示均一性。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种行驱动信号增强电路、移位寄存器单元和显示面板。
根据本公开的一个方面，提供一种行驱动信号增强电路，包括：
控制单元，具有第一控制端和第二控制端，用于在所述第一控制端和所述第二控制端的控制下，向第一节点和第二节点中的一个输入第一电源电压，且向另一个输入第二电源电压；
第一输出单元，连接所述第一节点和第一输出端，用于在所述第一节点的控制下输出所述第一电源电压和所述第二电源电压中的一个至所述第一输出端；
第二输出单元，连接所述第二节点和第二输出端，用于在所述第二节点的控制下输出所述第一电源电压和所述第二电源电压中的另一个至所述第二输出端。
根据本公开的一种实施方式，所述控制单元包括：
第一控制单元，具有所述第一控制端和所述第二控制端，用于在所述第一控制端和所述第二控制端的控制下，输出所述第一电源电压至所述第一节点或者所述第二节点；
第二控制单元，连接所述第一节点和所述第二节点，用于响应加载于所述 第一节点上的所述第一电源电压而输出所述第二电源电压至所述第二节点，且用于响应加载于所述第二节点上的所述第一电源电压而输出所述第二电源电压至所述第一节点。
根据本公开的一种实施方式，所述第二控制单元具有至少四个晶体管。
根据本公开的一种实施方式，所述第一控制单元包括：
第一晶体管，具有用于加载所述第一电源电压的第一端、连接所述第一节点的第二端和作为所述第一控制端的控制端；所述第一晶体管用于，在所述第一晶体管的控制端的控制下输出所述第一电源电压至所述第一节点；
第二晶体管，具有用于加载所述第一电源电压的第一端、连接所述第二节点的第二端和作为所述第二控制端的控制端；所述第二晶体管用于，在所述第二晶体管的控制端的控制下输出所述第一电源电压至所述第二节点；
所述第一晶体管和所述第二晶体管的类型相同。
根据本公开的一种实施方式，所述第二控制单元包括：
第三晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第二节点的第二端；所述第三晶体管用于，在加载于所述第一节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第二节点；
第四晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第二节点的第二端；所述第四晶体管用于，在加载于所述第一节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第二节点；
第五晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一节点的第二端；所述第五晶体管用于，在加载于所述第二节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第一节点；
第六晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一节点的第二端；所述第六晶体管用于，在加载于所述第二节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第一节点；
所述第三晶体管至所述第六晶体管的类型相同。
根据本公开的一种实施方式，所述第一输出单元包括：
第七晶体管，具有连接所述第一节点的控制端、用于加载所述第一电源电 压的第一端和作为所述第一输出端的第二端；
第八晶体管，具有连接所述第一节点的控制端、用于加载所述第一电源电压的第一端和连接所述第一输出端的第二端；
第九晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一输出端的第二端；
第十晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一输出端的第二端；
所述第二输出单元包括：
第十一晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和作为所述第一输出端的第二端；
第十二晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和连接所述第二输出端的第二端；
第十三晶体管，具有连接所述第二节点的控制端、用于加载所述第一电源电压的第一端和连接所述第二输出端的第二端；
第十四晶体管，具有连接所述第二节点的控制端、用于加载所述第一电源电压的第一端和连接所述第二输出端的第二端；
其中，所述第七晶体管、所述第八晶体管、所述第十三晶体管、所述第十四晶体中的任意一个用于响应加载于其控制端的所述第一电源电压和所述第二电源电压中的一个而导通，所述第九晶体管至所述第十二晶体管中的任意一个用于响应加载于其控制端的所述第一电源电压和所述第二电源电压中的另一个而导通。
根据本公开的另一个方面，提供一种移位寄存器单元，包括移位寄存器、反相器和上述的行驱动信号增强电路；
其中，所述移位寄存器用于输出初始扫描信号至所述反相器的输入端和所述行驱动信号增强电路的第一控制端；所述反相器的输出端连接所述行驱动信号增强电路的第二控制端。
根据本公开的另一个方面，提供一种显示面板，包括上述的移位寄存器单元。
根据本公开的另一个方面，提供一种显示面板，其中，所述显示面板包括驱动背板和层叠于所述驱动背板上的显示层；所述驱动背板包括依次层叠设置的半导体衬底、栅极绝缘层、栅极层、绝缘介质层和金属布线层；所述显示面板包括显示区和围绕所述显示区的外围区，且在所述外围区设置有多个行驱动信号增强区；
在任意一个所述行驱动信号增强区，所述驱动背板设置有包括第一晶体管至第十 四晶体管的行驱动信号增强电路；其中，所述第一晶体管和所述第二晶体管类型相同；所述第七晶体管、所述第八晶体管、所述第十三晶体管和所述第十四晶体管的类型相同；所述第九晶体管至所述第十二晶体管的类型相同，且与所述第七晶体管的类型相反；所述第三晶体管至所述第六晶体管的类型相同；所述半导体衬底形成有各个晶体管的有源区，任意一个晶体管的所述有源区包括沟道区、沟道区两侧的源极和漏极；所述栅极层形成有各个晶体管的栅极，且所述栅极绝缘层隔离任意一个晶体管的栅极和沟道区；所述绝缘介质层覆盖所述栅极层；
在一个所述行驱动信号增强区，所述金属布线层设置有连接引线、第一电源引线、第二电源引线、第一控制引线、第二控制引线、第一输出引线和第二输出引线；所述连接引线通过位于所述绝缘介质层中的导电柱与各个晶体管的源极、漏极和栅极电连接；其中，所述连接引线使得所述第一晶体管的栅极与所述第一控制引线电连接，且使得所述第二晶体管的栅极与所述第二控制引线电连接，且使得所述第一晶体管的源极、所述第二晶体管的源极、所述第七晶体管的源极、所述第八晶体管的源极、所述第十三晶体管的源极、所述第十四晶体管的源极与所述第一电源引线电连接，且使得所述第三晶体管至所述第六晶体管的源极、所述第九晶体管至所述第十二晶体管的源极与所述第二电源引线电连接，且使得所述第七晶体管至所述第十晶体管的漏极与所述第一输出引线电连接，且使得所述第十一晶体管至所述第十四晶体管的漏极与所述第二输出引线电连接，且使得所述第一晶体管的漏极、所述第五晶体管的漏极、所述第六晶体管的漏极、所述第三晶体管的栅极、所述第四晶体管的栅极、所述第七晶体管至所述第十晶体管的栅极相互电连接，且使得所述第二晶体管的漏极、所述第三晶体管的漏极、所述第四晶体管的漏极、所述第五晶体管的栅极、所述第六晶体管的栅极、所述第十一晶体管至所述第十四晶体管的栅极相互电连接。
根据本公开的一种实施方式，所述第一晶体管、所述第二晶体管、所述第七晶体管、所述第八晶体管、所述第十三晶体管、所述第十四晶体管均为N型晶体管，所述第三晶体管至所述第六晶体管、所述第九晶体管至所述第十二晶体管均为P型晶体管。
根据本公开的一种实施方式，任意一个所述行驱动信号增强区包括P型衬底区和N型衬底区，所述P型衬底区位于所述N型衬底区的第一方向一侧，所述第一方向为远离所述显示区的方向；所述N型晶体管形成于所述P型衬底区，且所述P型晶体管形成于所述N型衬底区。
根据本公开的一种实施方式，所述N型衬底区包括N型辅助掺杂区，以及包括分别被所述N型辅助掺杂区环绕的第一有源区和第二有源区；所述第二有源区位于所述第一有源区的第一方向一侧；
所述第一有源区包括沿所述第一方向依次排列的第一亚有源区和第二亚有源区；所述第九晶体管和第十一晶体管位于所述第一亚有源区，所述第十晶体管和所述第十 二晶体管位于所述第二亚有源区；
所述第二有源区包括沿第二方向依次排列的第三亚有源区和第四亚有源区；所述第二方向与所述第一方向垂直且平行于所述半导体衬底所在平面；所述第五晶体管和所述第六晶体管位于所述第三亚有源区，所述第三晶体管和所示第四晶体管位于所述第四亚有源区。
根据本公开的一种实施方式，所述P型衬底区包括P型辅助掺杂区、第三有源区和第四有源区；所述第四有源区位于所述第三有源区的第一方向一侧；
所述第三有源区被所述P型辅助掺杂区环绕，且包括沿所述第一方向依次排列的第五亚有源区和第六亚有源区；所述第七晶体管和所述第十三晶体管位于所述第五亚有源区，所述第八晶体管和所述第十四晶体管位于所述第六亚有源区；
所述第四有源区包括沿所述第二方向依次排列且分别被所述P型辅助掺杂区环绕的第七亚有源区和第八亚有源区；所述第一晶体管位于所述第七亚有源区，所述第二晶体管位于所述第八亚有源区。
根据本公开的一种实施方式，所述绝缘介质层包括依次层叠于所述栅极层的第一电介质层、第二电介质层和第三电介质层，所述金属布线层包括位于所述第一电介质层和所述第二电介质层之间的第一金属布线层、位于所述第二电介质层和所述第三电介质层之间的第二金属布线层和位于所述第三电介质层远离所述半导体衬底的表面的第三金属布线层；
所述导电柱包括贯穿所述第一电介质层的第一导电柱、贯穿所述第二电介质层的第二导电柱和贯穿所述第三电介质层的第三导电柱；所述第一金属布线层通过所述第一导电柱与所述半导体衬底和所述栅极层连接；所述第二金属布线层通过所述第二导电柱与所述第一金属布线层连接；所述第三金属布线层通过所述第三导电柱与所述第二金属布线层连接；
其中，所述第一金属布线层包括部分连接引线；位于所述第一金属布线层的所述连接引线包括第一连接引线至第六连接引线，还包括所述第一晶体管至所述第十四晶体管各自对应的栅极连接线、源极连接线和漏极连接线；任意一个晶体管对应的栅极连接线与所述晶体管的栅极连接；任意一个晶体管对应的源极连接线与所述晶体管的源极连接；任意一个晶体管对应的漏极连接线与所述晶体管的漏极连接；
所述第九晶体管对应的源极连接线和所述第十一晶体管对应的源极连接线与所述第一连接引线连接；
所述第十晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第十二晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第十晶体管对应的源极连接线的第一亚连接线、所述第十二晶体管对应的源极连接线的第一亚连接线、所述第五晶体管对应的源极连接线、所述第四晶体管对应的源极连接线与所述第二连接引线连接；
所述第三晶体管对应的漏极连接线、所述第四晶体管对应的漏极连接线、所述第五晶体管对应的栅极连接线、所述第六晶体管对应的栅极连接线与所述第三连接引线连接；
所述第五晶体管对应的漏极连接线、所述第六晶体管对应的漏极连接线、所述第三晶体管对应的栅极连接线、所述第四晶体管对应的栅极连接线与所述第四连接引线连接；
所述第八晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第十四晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第八晶体管对应的源极连接线的第一亚连接线、所述第十四晶体管对应的源极连接线的第一亚连接线、所述第七晶体管对应的源极连接线、所述第十三晶体管对应的源极连接线、所述第一晶体管对应的源极连接线、所述第二晶体管对应的源极连接线与所述第五连接引线连接；
所述第三晶体管对应的源极连接线、所述第六晶体管对应的源极连接线与所述第六连接引线连接；
所述第二金属布线层包括第一控制引线、第二控制引线、第一输出引线、第二输出引线和部分连接引线；位于所述第二金属布线层的所述连接引线包括第七连接引线至第十五连接引线；
所述第一连接引线、所述第二连接引线与所述第七连接引线连接，且所述第一连接引线、所述第二连接引线与所述第八连接引线连接；
所述第五连接引线与所述第九连接引线、所述第十连接引线连接；
所述第九晶体管对应的栅极连接线、所述第十晶体管对应的栅极连接线、所述第五晶体管对应的漏极连接线、所述第六晶体管对应的漏极连接线、所述第七晶体管对应的栅极连接线、所述第八晶体管对应的栅极连接线、所述第一晶体管对应的漏极连接线与所述第十一连接引线连接；
所述第十一晶体管对应的栅极连接线、所述第十二晶体管对应的栅极连接线、所述第三晶体管对应的漏极连接线、所述第四晶体管对应的漏极连接线、所述第十三晶体管对应的栅极连接线、所述第十四晶体管对应的栅极连接线、所述第二晶体管对应的漏极连接线与所述第十二连接引线连接；
所述第一连接引线、所述第九晶体管对应的源极连接线、所述第十一晶体管对应的源极连接线、所述第十晶体管对应的源极连接线的第二亚连接线、所述第十二晶体管对应的源极连接线的第二亚连接线、所述第六连接引线与所述第十三连接引线连接；
所述第七晶体管对应的源极连接线、所述第八晶体管对应的源极连接线的第二亚连接线、所述第十三晶体管对应的源极连接线、所述第十四晶体管对应的源极连接线的第二亚连接线、所述第五连接引线与所述第十四连接引线连接；
所述第五连接引线与所述第十五连接引线连接；
所述第七晶体管对应的漏极连接线、所述第八晶体管对应的漏极连接线、所述第九晶体管对应的漏极连接线、所述第十晶体管对应的漏极连接线与所述第一输出引线连接；
所述第十一晶体管对应的漏极连接线、所述第十二晶体管对应的漏极连接线、所述第十三晶体管对应的漏极连接线、所述第十四晶体管对应的漏极连接线与所述第二输出引线连接；
所述第一晶体管对应的栅极连接线与所述第一控制引线连接，所述第二晶体管对应的栅极连接线与所述第二控制引线连接；
所述第三金属布线层包括用于加载第一电源电压的第一电源引线，以及包括线用于加载第二电源电压的第二电源引线；所述第九连接引线、所述第十连接引线、所述第十四连接引线、所述第十五连接引线与所述第一电源引线连接；所述第七连接引线、所述第八连接引线、所述第十三连接引线与所述第二电源引线连接。
根据本公开的一种实施方式，在任意一个所述行驱动信号增强区，各个晶体管对应的源极连接线和漏极连接线均沿所述第一方向延伸，各个晶体管的栅极均沿所述第一方向延伸。
根据本公开的一种实施方式，所述第一连接引线包括依次连接的第一亚引线、第二亚引线和第三亚引线；所述第一连接引线的第一亚引线、所述第一连接引线的第三亚引线沿所述第一方向延伸且与所述N型辅助掺杂区至少部分交叠；所述第一连接引线的第二亚引线沿所述第二方向延伸且与所述N型辅助掺杂区至少部分交叠；所述第一连接引线的第一亚引线、所述第一连接引线的第二亚引线和所述第一连接引线的第三亚引线均与所述N型辅助掺杂区连接；所述第一亚有源区位于所述第一连接引线所环绕的空间内；
所述第九晶体管对应的源极连接线包括分别位于所述第九晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第十一晶体管对应的源极连接线包括分别位于所述第十一晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第九晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第一连接引线的第一亚引线连接；所述第十一晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第一连接引线的第三亚引线连接；所述第九晶体管对应的源极连接线的第二亚连接线和所述第十一晶体管对应的源极连接线的第二亚连接线为同一引线，且沿所述第一方向的相反方向延伸至与所述第一连接引线的第二亚引线连接；
所述第七连接引线与所述第一连接引线的第一亚引线连接；所述第八连接引线与所述第一连接引线的第三亚引线连接；所述第十三连接引线与所述第一连接引线的第二亚引线连接。
根据本公开的一种实施方式，所述第二连接引线包括依次连接的第一亚引线、 第三亚引线和第四亚引线，以及包括第二亚引线；其中，所述第二连接引线的第一亚引线、所述第二连接引线的第四亚引线均沿第一方向延伸，且与所述N型辅助掺杂区至少部分交叠；所述第二连接引线的第二亚引线、所述第二连接引线的第三亚引线均沿所述第二方向延伸，且与所述N型辅助掺杂区至少部分交叠；所述第二连接引线的第一亚引线至第四亚引线均与所述N型辅助掺杂区连接；
所述第二亚有源区位于所述第二连接引线的第一亚引线、所述第二连接引线的第二亚引线和所述第二连接引线的第四亚引线所环绕的空间内，所述第二有源区位于所述第二连接引线的第一亚引线、所述第二连接引线的第二亚引线、所述第二连接引线的第三亚引线和所述第二连接引线的第四亚引线所环绕的空间内；
所述第十晶体管对应的源极连接线的第一亚连接线沿所述第一方向延伸，且其第一方向的相反方向一侧与所述第二连接引线的第一亚引线连接；所述第十二晶体管对应的源极连接线的第一亚连接线沿所述第一方向延伸，且其第一方向的一侧与所述第二连接引线的第四亚引线连接；所述第十晶体管对应的源极连接线的第二亚连接线和所述第十二晶体管对应的源极连接线的第二亚连接线为同一引线，且沿所述第一方向延伸。
根据本公开的一种实施方式，所述第五连接引线包括依次连接的第一亚引线、第二亚引线、第三亚引线和第四亚引线，以及包括第五亚引线和第六亚引线；
所述第五连接引线的第一亚引线、第三亚引线和第六亚引线均沿所述第一方向延伸，且均与所述P型辅助掺杂区至少部分交叠；所述第五连接引线的第六亚引线位于第一亚引线和第三亚引线之间，且两端分别与第五亚引线、第四亚引线连接；
所述第五连接引线的第二亚引线、第四亚引线、第五亚引线均所述第二方向延伸，且均与所述P型辅助掺杂区至少部分交叠；所述第五连接引线的第五亚引线位于第二亚引线和第四亚引线之间，且两端分别与第一亚引线、第三亚引线连接；所述第五连接引线的第一亚引线至第六亚引线均与所述P型辅助掺杂区连接；
所述第三有源区位于所述第五连接引线的第一亚引线、第二亚引线、第三亚引线和第五亚引线所环绕的空间内；所述第七亚有源区位于所述第五连接引线的第一亚引线、第五亚引线、第六亚引线和第四亚引线所环绕的空间内；所述第八亚有源区位于所述第五连接引线的第六亚引线、第五亚引线、第三亚引线和第四亚引线所环绕的空间内；
所述第七晶体管对应的源极连接线包括分别位于所述第七晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第十三晶体管对应的源极连接线包括分别位于所述第十三晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第七晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第五连接引线的第一亚引线连接；所述第十三晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第五连接引线的第三亚引线连 接；所述第七晶体管对应的源极连接线的第二亚连接线和所述第十三晶体管对应的源极连接线的第二亚连接线为同一引线，且沿所述第一方向延伸至与所述第五连接引线的第二亚引线连接；
所述第八晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第五连接引线的第一亚引线连接；所述第十四晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第五连接引线的第三亚引线连接；所述第八晶体管对应的源极连接线的第二亚连接线和所述第十四晶体管对应的源极连接线的第二亚连接线为同一引线；
所述第一晶体管对应的源极连接线包括分别位于所述第一晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第一晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第五连接引线的第一亚引线连接；所述第一晶体管对应的源极连接线的第二亚连接线的第二方向一侧与所述第五连接引线的第六亚引线连接；
所述第二晶体管对应的源极连接线包括分别位于所述第二晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第二晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第五连接引线的第三亚引线连接；所述第二晶体管对应的源极连接线的第二亚连接线的第二方向的相反方向一侧与所述第五连接引线的第六亚引线连接。
根据本公开的一种实施方式，所述第三连接引线、所述第四连接引线和所述第六连接引线位于所述第二连接引线的第一亚引线、所述第二连接引线的第二亚引线、所述第二连接引线的第三亚引线和所述第二连接引线的第四亚引线所环绕的空间内；其中，所述第三连接引线和所述第四连接引线沿所述第二方向延伸，所述第六连接引线沿所述第一方向延伸；
所述第六晶体管对应的源极连接线的第二方向一侧与所述第六连接引线连接，所述第三晶体管对应的源极连接线的第二方向的相反方向一侧与所述第六连接引线连接；
所述第五晶体管对应的漏极连接线和所述第六晶体管对应的漏极连接线为同一引线，且一端与所述第四连接引线的一端连接；所述第三晶体管对应的栅极连接线和所述第四晶体管对应的栅极连接线为同一引线，且一端与所述第四连接引线的另一端连接；
所述第三晶体管对应的漏极连接线和所述第四晶体管对应的漏极连接线为同一引线，且一端与所述第三连接引线的一端连接；所述第五晶体管对应的栅极连接线和所述第六晶体管对应的栅极连接线为同一引线，且一端与所述第三连接引线的另一端连接。
根据本公开的一种实施方式，所述第七连接引线沿所述第一方向延伸，且与所述第一连接引线的第一亚引线、所示第二连接引线的第一亚引线连接；
所述第八连接引线沿所述第一方向延伸，且与所述第一连接引线的第三亚引线、所述第二连接引线的第四亚引线连接；
所述第九连接引线沿所述第一方向延伸，且与所述第五连接引线的第一亚引线电连接；
所述第十连接引线沿所述第一方向延伸，且与所述第五连接引线的第三亚引线连接；
所述第五晶体管对应的漏极连接线和所述第一晶体管对应的漏极连接线位于同一直线，且延伸轴线在所述半导体衬底上的正投影均与所述第十一连接引线的延伸轴线在所述半导体衬底上的正投影重合；
所述第三晶体管对应的漏极连接线和所述第二晶体管对应的漏极连接线位于同一直线，且延伸轴线在所述半导体衬底上的正投影均与所述第十二连接引线的延伸轴线在所述半导体衬底上的正投影重合；
所述第十三连接引线的延伸轴线在所述半导体衬底上的正投影、所述第九晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第十晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第六连接引的延伸轴线在所述半导体衬底上的正投影重合；
所述第七晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第八晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第五连接引线的第六亚引线的延伸轴线在所述半导体衬底上的正投影、所述第十四连接引线的延伸轴线在所述半导体衬底上的正投影和所述第十五连接引线的延伸轴线在所述半导体衬底上的正投影重合。
根据本公开的一种实施方式，所述第一电源引线覆盖所述第三有源区和所述第四有源区；所述第二电源引线覆盖所述第一有源区和所述第二有源区。
根据本公开的一种实施方式，所述显示面板在所述显示区还设置有像素驱动电路，所述像素驱动电路包括数据写入单元、存储电容和驱动晶体管；
所述数据写入单元具有第一控制电极和第二控制电极，所述数据写入单元的第一控制电极与所述第一输出引线连接，所述数据写入单元的第二控制电极与所述第二输出引线连接，所述数据写入单元的输入端与所述显示面板的数据线连接，所述数据写入单元的输出端与第三节点连接；
所述存储电容的第一电极板连接所述第三节点，所述存储电容的第二电极板用于加载第一驱动电压；
所述驱动晶体管的控制端连接所述第三节点，所述驱动晶体管的输出端连接所述显示面板的发光元件，所述驱动晶体管的输入端能够加载第二驱动电压。
根据本公开的一种实施方式，所述第一电源引线用于加载所述第一驱动电压；所述第二电源引线用于加载所述第二驱动电压。
根据本公开的一种实施方式，所述显示面板在外围区还设置有与各个所述行驱动信号增强电路一一对应设置的多个移位寄存器和多个反相器；
在相互对应的所述行驱动信号增强电路、所述移位寄存器和所述反相器中，所述移位寄存器的输出端与所述反相器的输入端、所述行驱动信号增强电路的第一控制引线连接，所述反相器的输出端与所述行驱动信号增强电路的第二控制引线连接。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式的行驱动信号增强电路的结构示意图。
图2为本公开一种实施方式的行驱动信号增强电路的结构示意图。
图3为本公开一种实施方式中加载于行驱动信号增强电路的两个控制端的信号的时序图。
图4为本公开一种实施方式中显示面板的结构示意图。
图5为本公开一种实施方式中，半导体衬底在行驱动信号增强区的各个有源区和辅助掺杂区的位置示意图。
图6为本公开一种实施方式中，栅极层在行驱动信号增强区的结构示意图。
图7为本公开一种实施方式中，在行驱动信号增强区，对半导体衬底进行N型掺杂的结构示意图；其中线条填充的阴影区域为进行N型掺杂的区域。
图8为本公开一种实施方式中，在行驱动信号增强区，进行N型掺杂的区域与各个有源区的位置示意图。
图9为本公开一种实施方式中，在行驱动信号增强区，对半导体衬底进行P型掺杂的结构示意图；其中点填充的阴影区域为进行P型掺杂的区域。
图10为本公开一种实施方式中，在行驱动信号增强区，进行P型掺杂的区域、进行N型掺杂的区域与各个有源区的位置示意图。
图11为本公开一种实施方式中，在行驱动信号增强区，进行P型掺杂的区域、进行N型掺杂的区域、栅极层与各个有源区的结构示意图。
图12为本公开一种实施方式中，在行驱动信号增强区，第一电介质层中各个第一导电柱的结构示意图。
图13为本公开一种实施方式中，在行驱动信号增强区，第一金属布线层的结构示意图。
图14为本公开一种实施方式中，在行驱动信号增强区，进行P型掺杂的区域、进行N型掺杂的区域、各个有源区、栅极层、第一导电柱和第一金属布线层的结构示意图。
图15为本公开一种实施方式中，在行驱动信号增强区，第二电介质层中各个第二导电柱的结构示意图。
图16为本公开一种实施方式中，在行驱动信号增强区，进行P型掺杂的区域、进行N型掺杂的区域、各个有源区、栅极层、第一导电柱、第一金属布线层和第二导电柱的结构示意图。
图17为本公开一种实施方式中，在行驱动信号增强区，第二金属布线层的结构示意图。
图18为本公开一种实施方式中，在行驱动信号增强区，第一金属布线层、第二导电柱和第二金属布线层的结构示意图。
图19为本公开一种实施方式中，在行驱动信号增强区，第三电介质层中各个第三导电柱的结构示意图。
图20为本公开一种实施方式中，在行驱动信号增强区，第三金属布线层的结构示意图。
图21为本公开一种实施方式中，在行驱动信号增强区，第二金属布线层、第三导电柱和第三金属布线层的结构示意图。
图22为本公开一种实施方式中，在行驱动信号增强区，进行P型掺杂的区域、进行N型掺杂的区域、各个有源区、栅极层、第一导电柱、第一金属布线层、第二导电柱、第二金属布线层、第三导电柱、第三金属布线层的结构示意图。
图23为本公开一种实施方式中，驱动背板在图22的QQ＇位置处的结构示意图。
图24为本公开一种实施方式中，半导体衬底上多个行驱动信号增强区依次排列的结构示意图。
附图标记说明：
101、行驱动信号增强电路；102、移位寄存器；103、反相器；104、像素驱动电路；CRL、控制单元；110、第一控制单元；120、第二控制单元；130、第一输出单元；140、第二输出单元；250、数据写入单元；M01、第一开关晶体管；M02、第二开关晶体管；Cst、存储电容；M03、驱动晶体管；310、半导体衬底；320、栅极绝缘层；330、栅极层；340、绝缘介质层；341、第一电介质层；342、第二电介质层；343、第三电介质层；351、第一导电柱；352、第二导电柱；353、第三导电柱；360、金属布线层；361、第一金属布线层；362、第二金属布线层；363、第三金属布线层；411、第一电源引线；412、第二电源引线；421、第一控制引线；422、第二控制引线；431、第一输出引线；432、第二输出引线；M1、第一晶体管；M2、第二晶体管；M3、第三晶体管；M4、第四晶体管；M5、第五晶体管；M6、第六晶体管；M7、第七晶体管； M8、第八晶体管；M9、第九晶体管；M10、第十晶体管；M11、第十一晶体管；M12、第十二晶体管；M13、第十三晶体管；M14、第十四晶体管；V1、第一电源电压；V2、第二电源电压；A、第一节点；B、第二节点；C、第三节点；IN1、第一控制端；IN2、第二控制端；OUT1、第一输出端；OUT2、第二输出端；D、显示区；E、外围区；F、行驱动信号增强区；G、第一方向；H、第二方向；Act1、第一有源区；Act2、第二有源区；Act3、第三有源区；Act4、第四有源区；Act_sub1、第一亚有源区；Act_sub2、第二亚有源区；Act_sub3、第三亚有源区；Act_sub4、第四亚有源区；Act_sub5、第五亚有源区；Act_sub6、第六亚有源区；Act_sub7、第七亚有源区；Act_sub8、第八亚有源区；F_Pdop、P型衬底区；F_Pdummy、P型辅助掺杂区；F_Psub1、第一P型掺杂亚区；F_Psub2、第二P型掺杂亚区；F_Psub3、第三P型掺杂亚区；F_Psub4、第四P型掺杂亚区；F_Psub5、第五P型掺杂亚区；F_Psub6、第六P型掺杂亚区；F_Psub7、第七P型掺杂亚区；F_Psub8、第八P型掺杂亚区；F_Ndop、N型衬底区；F_Ndummy、N型辅助掺杂区；F_Nsub1、第一N型掺杂亚区；F_Nsub2、第二N型掺杂亚区；F_Nsub3、第三N型掺杂亚区；F_Nsub4、第四N型掺杂亚区；F_Nsub5、第五N型掺杂亚区；F_Nsub6、第六N型掺杂亚区；F_Nsub7、第七N型掺杂亚区；M1S1、第一晶体管的第一源极；M1S2、第一晶体管的第二源极；M1D、第一晶体管的漏极；M1G、第一晶体管的栅极；M1G1、第一晶体管的第一栅极；M1G2、第一晶体管的第二栅极；M1SL1、第一晶体管对应的源极连接线的第一亚连接线；M1SL2、第一晶体管对应的源极连接线的第二亚连接线；M1DL、第一晶体管对应的漏极连接线；M1GL、第一晶体管对应的栅极连接线；M2S1、第二晶体管的第一源极；M2S2、第二晶体管的第二源极；M2D、第二晶体管的漏极；M2G、第二晶体管的栅极；M2G1、第二晶体管的第一栅极；M2G2、第二晶体管的第二栅极；M2SL1、第二晶体管对应的源极连接线的第一亚连接线；M2SL2、第二晶体管对应的源极连接线的第二亚连接线；M2DL、第二晶体管对应的漏极连接线；M2GL、第二晶体管对应的栅极连接线；M3S、第三晶体管的第二源极；M3D、第三晶体管的漏极；M3G、第三晶体管的栅极；M3SL、第三晶体管对应的源极连接线；M3DL、第三晶体管对应的漏极连接线；M3GL、第三晶体管对应的栅极连接线；M4S、第四晶体管的第二源极；M4D、第四晶体管的漏极；M4G、第四晶体管的栅极；M4SL、第四晶体管对应的源极连接线；M4DL、第四晶体管对应的漏极连接线；M4GL、第四晶体管对应的栅极连接线；M5S、第五晶体管的第二源极；M5D、第五晶体管的漏极；M5G、第五晶体管的栅极；M5SL、第五晶体管对应的源极连接线；M5DL、第五晶体管对应的漏极连接线；M5GL、第五晶体管对应的栅极连接线；M6S、第六晶体管的第二源极；M6D、第六晶体管的漏极；M6G、第六晶体管的栅极；M6SL、第六晶体管对应的源极连接线；M6DL、第六晶体管对应的漏极连接线；M6GL、第六晶体管对应的栅极连接线；M7S1、第七晶体管的第一源极；M7S2、第七晶体管的第二源极；M7D、第七晶体管的漏极；M7G、第七晶体管 的栅极；M7G1、第七晶体管的第一栅极；M7G2、第七晶体管的第二栅极；M7SL1、第七晶体管对应的源极连接线的第一亚连接线；M7SL2、第七晶体管对应的源极连接线的第二亚连接线；M7DL、第七晶体管对应的漏极连接线；M7GL、第七晶体管对应的栅极连接线；M8S1、第八晶体管的第一源极；M8S2、第八晶体管的第二源极；M8D、第八晶体管的漏极；M8G、第八晶体管的栅极；M8G1、第八晶体管的第一栅极；M8G2、第八晶体管的第二栅极；M8SL1、第八晶体管对应的源极连接线的第一亚连接线；M8SL2、第八晶体管对应的源极连接线的第二亚连接线；M8DL、第八晶体管对应的漏极连接线；M8GL、第八晶体管对应的栅极连接线；M9S1、第九晶体管的第一源极；M9S2、第九晶体管的第二源极；M9D、第九晶体管的漏极；M9G、第九晶体管的栅极；M9G1、第九晶体管的第一栅极；M9G2、第九晶体管的第二栅极；M9SL1、第九晶体管对应的源极连接线的第一亚连接线；M9SL2、第九晶体管对应的源极连接线的第二亚连接线；M9DL、第九晶体管对应的漏极连接线；M9GL、第九晶体管对应的栅极连接线；M10S1、第十晶体管的第一源极；M10S2、第十晶体管的第二源极；M10D、第十晶体管的漏极；M10G、第十晶体管的栅极；M10G1、第十晶体管的第一栅极；M10G2、第十晶体管的第二栅极；M10SL1、第十晶体管对应的源极连接线的第一亚连接线；M10SL2、第十晶体管对应的源极连接线的第二亚连接线；M10DL、第十晶体管对应的漏极连接线；M10GL、第十晶体管对应的栅极连接线；M11S1、第十一晶体管的第一源极；M11S2、第十一晶体管的第二源极；M11D、第十一晶体管的漏极；M11G、第十一晶体管的栅极；M11G1、第十一晶体管的第一栅极；M11G2、第十一晶体管的第二栅极；M11SL1、第十一晶体管对应的源极连接线的第一亚连接线；M11SL2、第十一晶体管对应的源极连接线的第二亚连接线；M11DL、第十一晶体管对应的漏极连接线；M11GL、第十一晶体管对应的栅极连接线；M12S1、第十二晶体管的第一源极；M12S2、第十二晶体管的第二源极；M12D、第十二晶体管的漏极；M12G、第十二晶体管的栅极；M12G1、第十二晶体管的第一栅极；M12G2、第十二晶体管的第二栅极；M12SL1、第十二晶体管对应的源极连接线的第一亚连接线；M12SL2、第十二晶体管对应的源极连接线的第二亚连接线；M12DL、第十二晶体管对应的漏极连接线；M12GL、第十二晶体管对应的栅极连接线；M13S1、第十三晶体管的第一源极；M13S2、第十三晶体管的第二源极；M13D、第十三晶体管的漏极；M13G、第十三晶体管的栅极；M13G1、第十三晶体管的第一栅极；M13G2、第十三晶体管的第二栅极；M13SL1、第十三晶体管对应的源极连接线的第一亚连接线；M13SL2、第十三晶体管对应的源极连接线的第二亚连接线；M13DL、第十三晶体管对应的漏极连接线；M13GL、第十三晶体管对应的栅极连接线；M14S1、第十四晶体管的第一源极；M14S2、第十四晶体管的第二源极；M14D、第十四晶体管的漏极；M14G、第十四晶体管的栅极；M14G1、第十四晶体管的第一栅极；M14G2、第十四晶体管的第二栅极；M14SL1、第十四晶体管对应的源极连接线的第一亚连接线； M14SL2、第十四晶体管对应的源极连接线的第二亚连接线；M14DL、第十四晶体管对应的漏极连接线；M14GL、第十四晶体管对应的栅极连接线；L01、第一连接引线；L011、第一连接引线的第一亚引线；L012、第一连接引线的第二亚引线；L013、第一连接引线的第三亚引线；L02、第二连接引线；L021、第二连接引线的第一亚引线；L022、第二连接引线的第二亚引线；L023、第二连接引线的第三亚引线；L024、第二连接引线的第四亚引线；L03、第三连接引线；L04、第四连接引线；L05、第五连接引线；L051、第五连接引线的第一亚引线；L052、第五连接引线的第二亚引线；L053、第五连接引线的第三亚引线；L054、第五连接引线的第四亚引线；L055、第五连接引线的第五亚引线；L056、第五连接引线的第六亚引线；L07、第七连接引线；L08、第八连接引线；L09、第九连接引线；L10、第十连接引线；L11、第十一连接引线；L12、第十二连接引线；L13、第十三连接引线；L14、第十四连接引线；L15、第十五连接引线；L16、第十六连接引线；L17、第十七连接引线。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本公开中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏极端子、漏区域或漏电极)与源极(源极端子、源区域或源电极)之间具有沟道区，并且电流可以流过漏极、沟道区以及源极。沟道区是指电流主要流过的区域。在使用类型相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本公开中，“源极”和“漏极”可以互相调换。从结构上，晶体管可以具有第一端、第二端和控制端，其中，晶体 管的栅极可以作为晶体管的控制端(或者控制电极)；晶体管的源极和漏极中的一个可以作为晶体管的第一端，另一个可以作为晶体管的第二端。
在本公开中，晶体管的“导通”状态，指的是晶体管的源极和漏极之间处于电性连接的状态。晶体管的“截止”状态，指的是晶体管的源极和漏极之间处于电性断路的状态；可以理解的是，当晶体管截止时，其依然可以存在漏电流。
在本公开中，当描述两个信号为反相信号时，指的是其中一个信号为高电平信号而另一个信号为低电平信号。
参见图1，本公开提供一种行驱动信号增强电路，包括：
控制单元CRL，具有第一控制端IN1和第二控制端IN2，用于在第一控制端IN1和第二控制端IN2的控制下，向第一节点A和第二节点B中的一个输入第一电源电压V1，且向另一个输入第二电源电压V2；
第一输出单元130，连接第一节点A和第一输出端OUT1，用于在第一节点A的控制下输出第一电源电压V1和第二电源电压V2中的一个至第一输出端OUT1；
第二输出单元140，连接第二节点B和第二输出端OUT2，用于在第二节点B的控制下输出第一电源电压V1和第二电源电压V2中的另一个至第二输出端OUT2。
参见图4，本公开提供的行驱动信号增强电路101，可以与移位寄存器102和反相器103组成移位寄存器单元；其中，移位寄存器102用于输出初始扫描信号(即第一初始扫描信号)至反相器103的输入端和行驱动信号增强电路101的第一控制端IN1；反相器103的输出端连接行驱动信号增强电路101的第二控制端IN2，以便根据第一初始扫描信号生成与第一初始扫描信号反相的第二初始扫描信号。如此，移位寄存器102和反相器103可以向行驱动信号增强电路101的控制单元CRL的两个控制端(第一控制端IN1和第二控制端IN2)分别输入两个反相的初始扫描信号(第一初始扫描信号和第二初始扫描信号)。该行驱动信号增强电路101可以根据第一控制端IN1和第二控制端IN2上所加载的两个反相的初始扫描信号，进而使得第一输出单元130和第二输出单元140输出不同的两个电源电压(第一电源电压V1和第二电源电压V2)作为显示面板的扫描信号，即输出由第一电源电压V1和第二电源电压V2形成的扫描信号。这两个电源电压所形成的扫描信号可以代替移位寄存器102和反相器103生成的初始扫描信号以控制像素驱动电路的数据写入单元。
由此，本公开提供的行驱动信号增强电路101，可以将驱动能力较弱的初始扫描信号转变为驱动能力更强的、由电源电压形成的扫描信号，能够克服初始扫描信号抵达像素驱动电路时存在较大延迟和电压损失的问题，能够提高显示面板的显示均一性，尤其是提高硅基OLED(有机电致发光二极管)显示器的显示均一性。
下面，结合附图对本公开的行驱动信号增强电路101的结构、原理和效果做进一步地解释和说明。
本公开提供的行驱动信号增强电路101，用于提高显示面板的行驱动能力，尤其是提高硅基OLED显示器的行驱动能力。该行驱动信号增强电路101能够根据显示面板的两个初始扫描信号生成两个扫描信号，该两个扫描信号的扫描电压为不同的电源电压，一方面在扫描引线上的传输过程中具有更小的压降，另一方面具有更大的信号传输能力以满足扫描引线上的各个负载的需求，降低各个数据写入单元的导通延迟。因此，该行驱动信号增强电路101所生成的扫描信号具有更强的驱动能力。
可选的，在行驱动信号增强电路101中，控制单元CRL可以包括：
第一控制单元110，具有第一控制端IN1和第二控制端IN2，用于在第一控制端IN1和第二控制端IN2的控制下，输出第一电源电压V1至第一节点A或者第二节点B；
第二控制单元120，连接第一节点A和第二节点B，用于响应加载于第一节点A上的第一电源电压V1而输出第二电源电压V2至第二节点B，且用于响应加载于第二节点B上的第一电源电压V1而输出第二电源电压V2至第一节点A。
可选地，第一输出单元130还可以包括第一输入端和第二输入端，第一输出单元130的第一输入端加载有第一电源电压V1，第一输出单元130的第二输入端加载有第二电源电压V2。换言之，第一输出单元130的第一输入端通过引线与提供第一电源电压V1的电源连接，第一输出单元130的第二输入端通过引线与提供第二电源电压V2的电源连接。这样，第一输出单元130可以将加载的第一电源电压V1和第二电源电压V2中的任意一个直接输出至第一输出端OUT1，无需通过调压的方法生成第一电源电压V1和第二电源电压V2，进而可以保证第一输出端OUT1所输出的信号不仅在电压上为第一电源电压V1或者第二电源电压V2，而且可以保证第一输出端OUT1所输出的扫描信号具有更强的驱动能力，能够满足各个扫描引线上各个负载的需求。
可选地，在行驱动信号增强电路101中，第二输出单元140还可以包括第一输入端和第二输入端，第二输出单元140的第一输入端加载有第一电源电压V1，第二输出单元140的第二输入端加载有第二电源电压V2。换言之，第二输出单元140的第一输入端通过引线与提供第一电源电压V1的电源连接，第二输出单元140的第二输入端通过引线与提供第二电源电压V2的电源连接。这样，第二输出单元140可以将加载的第一电源电压V1和第二电源电压V2中的任意一个直接输出至第二输出端OUT2，无需通过调压的方法生成第一电源电压V1和第二电源电压V2，进而可以保 证第二输出端OUT2所输出的信号不仅在电压上为第一电源电压V1或者第二电源电压V2，而且可以保证第二输出端OUT2所输出的扫描信号具有更强的驱动能力，能够满足各个扫描引线上各个负载的需求。
可选地，第二控制单元120具有至少两组晶体管，每组晶体管包括类型相同的至少两个晶体管。即，第二控制单元120具有至少四个晶体管。其中，在一组晶体管中，各个晶体管并联，即同一组中的各个晶体管的源极相互电连接，漏极相互电连接，栅极相互电连接；这样，可以降低各个晶体管的信号延时(RC delay)，提高各组晶体管的开启速度并保证各组晶体管的驱动能力，降低第二控制单元120的信号延时。
在本公开中，晶体管的类型指的是晶体管为N型晶体管或者P型晶体管。其中，当两个以上晶体管类型相同时，指的该两个以上晶体管均为N型晶体管，或者均为P型晶体管。
可选地，参见图2，第一控制单元110可以包括：
第一晶体管M1，具有用于加载第一电源电压V1的第一端、连接第一节点A的第二端和作为第一控制端IN1的控制端；第一晶体管M1用于，在第一晶体管M1的控制端的控制下输出第一电源电压V1至第一节点A；
第二晶体管M2，具有用于加载第一电源电压V1的第一端、连接第二节点B的第二端和作为第二控制端IN2的控制端；第二晶体管M2用于，在第二晶体管M2的控制端的控制下输出第一电源电压V1至第二节点B；
第一晶体管M1和第二晶体管M2均为N型晶体管或者均为P型晶体管。
参见图3，本公开的行驱动信号增强电路101在工作时，第一控制单元110的第一控制端IN1和第二控制端IN2分别加载反相的的第一初始扫描信号和第二初始扫描信号。因此，第一晶体管M1和第二晶体管M2的控制端分别加载反相的两个初始扫描信号。第一晶体管M1和第二晶体管M2的类型相同，例如均为N型晶体管或者均为P型晶体管，这不仅便于晶体管的制备，而且可以使得第一晶体管M1和第二晶体管M2择一地导通，使得第一控制单元110择一地输出第一电源电压V1至第一节点A或者第二节点B。
下面，以第一晶体管M1和第二晶体管M2均为N型晶体管为例，且以移位寄存器单元输出的第一初始扫描信号为高电平信号为例，对第一控制单元110的工作过程进行介绍。
图3为加载于第一控制端IN1和第二控制端IN2上的两个初始扫描信号的时序图。参见图3，第一控制端IN1在T1阶段和T3阶段加载有低电平的基值电压，且在T2阶段加载有高电平的第一初始扫描信号。第二控制端IN2在T1阶段和T3阶段加载 有高电平的基值电压，且在T2阶段加载有低电平的第二初始扫描信号。因此，第一控制端IN1和第二控制端IN2上的信号保持反相，一个为高电平时另一个为低电平。
在T1阶段和T3阶段，第一控制端IN1加载低电平信号且第二控制端IN2加载高电平信号，使得第二晶体管M2导通而第一晶体管M1截止，第一控制单元110输出第一电源电压V1至第二节点B。在T2阶段，第一控制端IN1加载高电平信号且第二控制端IN2加载低电平信号，使得第一晶体管M1导通而第二晶体管M2截止，第一控制单元110输出第一电源电压V1至第一节点A。
可选地，参见图2，第二控制单元120可以包括：
第三晶体管M3，具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第二节点B的第二端；第三晶体管M3用于，在加载于第一节点A上的第一电源电压V1的控制下输出第二电源电压V2至第二节点B；
第四晶体管M4，具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第二节点B的第二端；第四晶体管M4用于，在加载于第一节点A上的第一电源电压V1的控制下输出第二电源电压V2至第二节点B；
第五晶体管M5，具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和连接第一节点A的第二端；第五晶体管M5用于，在加载于第二节点B上的第一电源电压V1的控制下输出第二电源电压V2至第一节点A；
第六晶体管M6，具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和连接第一节点A的第二端；第六晶体管M6用于，在加载于第二节点B上的第一电源电压V1的控制下输出第二电源电压V2至第一节点A。
其中，第三晶体管M3至第六晶体管M6的类型相同，均为N型晶体管或者均为P型晶体管。
进一步地，第一电源电压V1低于第二电源电压V2，第三晶体管M3至第六晶体管M6为P型晶体管；或者，第一电源电压V1高于第二电源电压V2，第三晶体管M3至第六晶体管M6为N型晶体管。换言之，第三晶体管M3至第六晶体管M6中的任意一个晶体管的控制端加载有第一电源电压V1时，该晶体管能够导通；第三晶体管M3至第六晶体管M6中的任意一个晶体管的控制端加载有第二电源电压V2时，该晶体管能够截止。
下面，以第一电源电压V1低于第二电源电压V2，第三晶体管M3至第六晶体管M6为P型晶体管为例，对第二控制单元120的工作过程进行解释和说明。当第一控制单元110向第一节点A加载第一电源电压V1时，第一控制单元110不向第二节点B加载电压；在第一节点A的控制下，第三晶体管M3和第四晶体管M4导通而输出 第二电源电压V2至第二节点B。如此，第一节点A上加载有第一电源电压V1，且第二节点B上加载有第二电源电压V2。反之，当第一控制单元110向第二节点B加载第一电源电压V1时，第一控制单元110不向第一节点A加载电压；在第二节点B的控制下，第五晶体管M5和第六晶体管M6导通而输出第二电源电压V2至第一节点A。如此，第二节点B上加载有第一电源电压V1，且第一节点A上加载有第二电源电压V2。由此可知，无论第一控制单元110和第二控制单元120所处何种工作状态，第一节点A和第二节点B上分别加载两个不同的电源电压，分别为第一电源电压V1和第二电源电压V2。
同理，对于第一电源电压V1高于第二电源电压V2，且第三晶体管M3至第六晶体管M6为N型晶体管的情形，同样可以使得第一节点A和第二节点B上分别加载两个不同的电源电压，本公开对其原理和过程不再赘述。
可选地，参见图2，第一输出单元130可以包括：
第七晶体管M7，具有连接第一节点A的控制端、用于加载第一电源电压V1的第一端和作为第一输出端OUT1的第二端；
第八晶体管M8，具有连接第一节点A的控制端、用于加载第一电源电压V1的第一端和连接第一输出端OUT1的第二端；
第九晶体管M9，具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第一输出端OUT1的第二端；
第十晶体管M10，具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第一输出端OUT1的第二端；
第二输出单元140包括：
第十一晶体管M11，具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和作为第一输出端OUT1的第二端；
第十二晶体管M12，具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和连接第二输出端OUT2的第二端；
第十三晶体管M13，具有连接第二节点B的控制端、用于加载第一电源电压V1的第一端和连接第二输出端OUT2的第二端；
第十四晶体管M14，具有连接第二节点B的控制端、用于加载第一电源电压V1的第一端和连接第二输出端OUT2的第二端；
其中，第七晶体管M7、第八晶体管M8、第十三晶体管M13、第十四晶体管M14中的任意一个用于响应加载于其控制端的第一电源电压V1和第二电源电压V2中的一个而导通，第九晶体管M9至第十二晶体管M12中的任意一个 用于响应加载于其控制端的第一电源电压V1和第二电源电压V2中的另一个而导通。
换言之，第七晶体管M7、第八晶体管M8、第十三晶体管M13、第十四晶体管M14的类型相同；第九晶体管M9至第十二晶体管M12的类型相同；第七晶体管M7、第八晶体管M8、第十三晶体管M13、第十四晶体管M14的类型，与第九晶体管M9至第十二晶体管M12的类型不相同。如此，第一节点A和第二节点B上分别加载两个不同的电源电压(即第一电源电压V1和第二电源电压V2)，则第一输出单元130和第二输出单元140分别输出两个不同的电源电压(即第一电源电压V1和第二电源电压V2)。
在该实施方式中，第一输出单元130的第七晶体管M7和第八晶体管M8并联设置，第九晶体管M9和第十晶体管M10并联设置；这可以提高第一输出单元130输出的电流的大小进而保证第一输出单元130的驱动能力，并且可以降低第一输出单元130的RC延时。同理，第二输出单元140的第十一晶体管M11和第十二晶体管M12并联设置，第十三晶体管M13和第十四晶体管M14并联设置；这可以提高第二输出单元140输出的电流的大小进而保证第二输出单元140的驱动能力，并且可以降低第二输出单元140的RC延时。
示例性地，在本公开的一种实施方式中，第一电源电压V1可以为低电平信号，第二电源电压V2可以为高电平信号；第七晶体管M7、第八晶体管M8、第十三晶体管M13、第十四晶体管M14可以为N型晶体管，第九晶体管M9至第十二晶体管M12可以为P型晶体管。
当第一节点A加载第一电源电压V1时，第七晶体管M7和第八晶体管M8截止而第九晶体管M9和第十晶体管M10导通，第一输出单元130通过第一输出端OUT1输出第二电源电压V2。此时，B加载第二电源电压V2，第十一晶体管M11和第十二晶体管M12截止而第十三晶体管M13和第十四晶体管M14导通，第二输出单元140通过第二输出端OUT2输出第一电源电压V1。
同理，当第一节点A加载第二电源电压V2时，第七晶体管M7和第八晶体管M8导通而第九晶体管M9和第十晶体管M10截止，第一输出单元130通过第一输出端OUT1输出第一电源电压V1。此时，B加载第一电源电压V1，第十一晶体管M11和第十二晶体管M12导通而第十三晶体管M13和第十四晶体管M14截止，第二输出单元140通过第二输出端OUT2输出第二电源电压V2。
可选地，第一晶体管M1至第十四晶体管M14可以为MOS(Metal Oxide  Semiconductor，金属氧化物半导体)管。
下面，示例性地介绍一种行驱动信号增强电路101及其工作过程，以便对本公开的行驱动信号增强电路101的原理、结构和效果做进一步地解释和说明。
参见图2，该示例性的行驱动信号增强电路101包括第一控制单元110、第二控制单元120、第一输出单元130和第二输出单元140。
第一控制单元110包括第一晶体管M1和第二晶体管M2，且第一晶体管M1和第二晶体管M2均为N型晶体管。其中，第一晶体管M1具有用于加载第一电源电压V1的第一端、连接第一节点A的第二端和作为第一控制端IN1的控制端。第二晶体管M2具有用于加载第一电源电压V1的第一端、连接第二节点B的第二端和作为第二控制端IN2的控制端。行驱动信号增强电路101的第一控制端IN1和第二控制端IN2能够加载两个反相的初始扫描信号，其中一个初始扫描信号为高电平信号且另一个扫描信号为低电平信号。第一晶体管M1和第二晶体管M2能够响应加载于各自控制端的高电平信号而导通，且响应加载于各自控制端的低电平信号而截止。
第二控制单元120包括第三晶体管M3至第六晶体管M6，且第三晶体管M3至第六晶体管M6均为P型晶体管。其中，第三晶体管M3具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第二节点B的第二端。第四晶体管M4具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第二节点B的第二端。第五晶体管M5具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和连接第一节点A的第二端。第六晶体管M6具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和连接第一节点A的第二端。在行驱动信号增强电路101的工作过程中，第一节点A和第二节点B中的一个加载第一电源电压V1，且另一个加载第二电源电压V2；其中，第一电源电压V1可以为低电平且第二电源电压V2为高电平，使得第三晶体管M3至第六晶体管M6能够响应加载于各自的控制端的第一电源电压V1而导通，且能够响应加载于各自的控制端的第二电源电压V2而截止。
第一输出单元130包括第七晶体管M7至第十晶体管M10，且第七晶体管M7和第八晶体管M8为N型晶体管，第九晶体管M9和第十晶体管M10为P型晶体管。第七晶体管M7具有连接第一节点A的控制端、用于加载第一电源电压V1的第一端和作为第一输出端OUT1的第二端。第八晶体管M8具有连接第一节点A的控制端、用于加载第一电源电压V1的第一端和连接第一输出端OUT1的第二端。第九晶体管M9具有连接第一节点A的控制端、用于加载第二电源电 压V2的第一端和连接第一输出端OUT1的第二端。第十晶体管M10具有连接第一节点A的控制端、用于加载第二电源电压V2的第一端和连接第一输出端OUT1的第二端。
第二输出单元140包括第十一晶体管M11至第十四晶体管M14，且第十一晶体管M11和第十二晶体管M12为P型晶体管，第十三晶体管M13和第十四晶体管M14为N型晶体管。第十一晶体管M11具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和作为第二输出端OUT2的第二端。第十二晶体管M12具有连接第二节点B的控制端、用于加载第二电源电压V2的第一端和连接第二输出端OUT2的第二端。第十三晶体管M13具有连接第二节点B的控制端、用于加载第一电源电压V1的第一端和连接第二输出端OUT2的第二端。第十四晶体管M14，具有连接第二节点B的控制端、用于加载第一电源电压V1的第一端和连接第二输出端OUT2的第二端。
在该示例性地行驱动信号增强电路101中，第一电源电压V1为低电平，且第二电源电压V2为高电平，且第一电源电压V1和第二电源电压V2为反相的两个初始扫描信号。当N型晶体管的控制端加载有第一电源电压V1时，N型晶体管截止；当N型晶体管的控制端加载有第二电源电压V2时，N型晶体管导通；当P型晶体管的控制端加载有第一电源电压V1时，N型晶体管导通；当P型晶体管的控制端加载有第二电源电压V2时，P型晶体管截止。如此，在第一控制端IN1和第二控制端IN2上所分别加载的反相的两个初始扫描信号的控制下，第一输出端OUT1和第二输出端OUT2分别输出两个反相的扫描信号。
参见图3，在T1时间段内，第一控制端IN1加载有第一电源电压V1而第二控制端IN2加载有第二电源电压V2，第一晶体管M1截止且第二晶体管M2导通，使得第一电源电压V1通过第二晶体管M2加载至B。第五晶体管M5和第六晶体管M6响应B上加载的第一电源电压V1而导通，使得第二电源电压V2通过第五晶体管M5和第六晶体管M6加载至A。第三晶体管M3和第四晶体管M4响应加载于A上的第二电源电压V2而截止，进而使得B上加载的信号被锁定为第一电源电压V1。第七晶体管M7和第八晶体管M8响应加载于A上的第二电源电压V2而导通，第九晶体管M9和第十晶体管M10响应加载于A上的第二电源电压V2而截止，使得第一电源电压V1通过第七晶体管M7和第八晶体管M8加载至第一输出端OUT1；即行驱动信号增强电路101的第一输出端OUT1输出第一电源电压V1。第十一晶体管M11和第十二晶体管M12响应加载于B上的第一电源电压V1而导通，第十三晶体管M13和第十四晶体管M14响应加载于B上的第一电源电压V1而截止，使得第二 电源电压V2通过第十一晶体管M11和第十二晶体管M12加载至第二输出端OUT2；即行驱动信号增强电路101的第二输出端OUT2输出第二电源电压V2。
参见图3，在T2时间段内，第一控制端IN1加载有第二电源电压V2而第二控制端IN2加载有第一电源电压V1，第一晶体管M1导通且第二晶体管M2截止，使得第一电源电压V1通过第一晶体管M1加载至A。第三晶体管M3和第四晶体管M4响应A上加载的第一电源电压V1而导通，使得第二电源电压V2通过第三晶体管M3和第四晶体管M4加载至B。第五晶体管M5和第六晶体管M6响应加载于B上的第二电源电压V2而截止，进而使得A上加载的信号被锁定为第一电源电压V1。第七晶体管M7和第八晶体管M8响应加载于A上的第一电源电压V1而截止，第九晶体管M9和第十晶体管M10响应加载于A上的第一电源电压V1而导通，使得第二电源电压V2通过第九晶体管M9和第十晶体管M10加载至第一输出端OUT1；即行驱动信号增强电路101的第一输出端OUT1输出第二电源电压V2。第十一晶体管M11和第十二晶体管M12响应加载于B上的第二电源电压V2而截止，第十三晶体管M13和第十四晶体管M14响应加载于B上的第二电源电压V2而导通，使得第一电源电压V1通过第十三晶体管M13和第十四晶体管M14加载至第二输出端OUT2；即行驱动信号增强电路101的第二输出端OUT2输出第一电源电压V1。
可选的，在一些实施方式中，第一电源电压V1和第二电源电压V2中的一个可以为地线电压(GND)，即为显示面板的参考电压。另一个可以为像素驱动电路在发光阶段加载于驱动晶体管的源极上的电压VDD。
本公开实施方式还提供一种移位寄存器单元，参见图4，该移位寄存器单元包括上述行驱动信号增强电路101实施方式所描述的任意一种行驱动信号增强电路101，以及包括移位寄存器102、反相器103。其中，移位寄存器102用于输出第一初始扫描信号至反相器103的输入端和行驱动信号增强电路101的第一控制端IN1；反相器103的输出端连接行驱动信号增强电路101的第二控制端IN2。该移位寄存器单元可以生成初始扫描信号(包括反相的第一初始扫描信号和第二初始扫描信号)，然后利用电源电压(包括第一电源电压V1和第二电源电压V2)将初始扫描信号转变为扫描信号；该扫描信号的扫描电压和基值电压为不同的电源电压(分别为第一电源电压V1和第二电源电压V2)，进而提高该扫描信号的驱动能力，克服扫描信号在扫描引线上延迟大、压降大的缺陷。
由于该移位寄存器单元具有上述行驱动信号增强电路实施方式所描述的任意一种行驱动信号增强电路101，因此具有相同的有益效果，本公开在此不再赘述。
本公开实施方式还提供一种显示面板，该显示面板包括上述移位寄存器单元实施 方式所描述的任意一种移位寄存器单元。该显示面板可以为OLED(有机电致发光二极管)显示面板、液晶显示面板、Micro LED(微发光二极管)显示面板或者其他类型的显示面板，尤其是可以为硅基OLED显示面板、硅基液晶显示面板。由于该显示面板具有上述移位寄存器单元实施方式所描述的任意一种移位寄存器单元，因此具有相同的有益效果，本公开在此不再赘述。
本公开还提供一种显示面板，该显示面板可以包括驱动背板和层叠于驱动背板上的显示层。
参见图23，驱动背板包括依次层叠设置的半导体衬底310、栅极绝缘层320、栅极层330、绝缘介质层340和金属布线层360。参见图4，显示面板包括显示区D和位于显示区D至少一侧的外围区E；参见图24，在外围区E设置有多个行驱动信号增强区F。在本公开的一种实施方式中，外围区E围绕显示区D。
图5为半导体衬底310在行驱动信号增强区F的结构示意图。在图5中，仅仅示出了各个有源区的位置，以及示出了该行驱动信号增强区F的N型衬底区F_Ndop和P型衬底区F_Pdop等的位置。
在任意一个行驱动信号增强区F，显示面板设置有包括第一晶体管M1至第十四晶体管M14的行驱动信号增强电路101；其中，第一晶体管M1和第二晶体管M2类型相同；第五晶体管M5、第八晶体管M8、第十三晶体管M13和第十四晶体管M14的类型相同；第九晶体管M9至第十二晶体管M12的类型相同，且与第五晶体管M5的类型相反；第三晶体管M3至第六晶体管M6的类型相同。
半导体衬底310形成有各个晶体管的有源区，任意一个晶体管的有源区包括沟道区、沟道区两侧的源极和漏极；栅极层330形成有各个晶体管的栅极，且栅极绝缘层320隔离任意一个晶体管的栅极和沟道区。参见图23，绝缘介质层340覆盖栅极层330。
在一个行驱动信号增强区F，金属布线层360设置有连接引线、第一电源引线411、第二电源引线412、第一控制引线421、第二控制引线422、第一输出引线431和第二输出引线432。连接引线通过位于绝缘介质层340中的导电柱与各个晶体管的源极、漏极和栅极电连接；其中，连接引线使得第一晶体管M1的栅极M1G与第一控制引线421电连接，且使得第二晶体管M2的栅极M2G与第二控制引线422电连接，且使得第一晶体管M1的源极、第二晶体管M2的源极、第七晶体管M7的源极、第八晶体管M8的源极、第十三晶体管M13的源极、第十四晶体管M14的源极与第一电源引线411电连接，且使得第三晶体管M3至第六晶体管M6的源极、第九晶体管M9至第十二晶体管M12的源极与第二电源引线412电连接，且使得第七晶体管M7至第十晶体管M10的漏极与第一输出引线431电连接，且使得第十一晶体管M11至第十四晶体管M14的漏极与第二输出引线432电连接，且使得第一晶体管M1的漏极M1D、第五晶体管M5的漏极、第六晶体管M6的漏极、第三晶体管M3的栅极、第四晶体 管M4的栅极、第七晶体管M7至第十晶体管M10的栅极相互电连接，且使得第二晶体管M2的漏极M2D、第三晶体管M3的漏极、第四晶体管M4的漏极、第五晶体管M5的栅极、第六晶体管M6的栅极、第十一晶体管M11至第十四晶体管M14的栅极相互电连接。
如此，本公开的显示面板中，行驱动信号增强电路101的等效电路如图2所示。该行驱动信号增强电路101的工作过程和效果在上述的行驱动信号增强电路101实施方式中进行了详细介绍，在此不再赘述。该显示面板设置有行驱动信号增强电路101，因此能够提高显示面板的行驱动能力，提高显示面板显示的均一性。
在本公开提供的显示面板中，第一电源引线411可以加载有第一电源电压V1，第二电源引线412可以加载有第二电源电压V2。第一控制引线421可以作为行驱动信号增强电路101的第一控制端IN1，第二控制引线422可以作为行驱动信号增强电路101的第二控制端IN2。第一输出引线431可以作为行驱动信号增强电路101的第一输出端OUT1，第二输出引线432可以作为行驱动信号增强电路101的第二输出端OUT2。
在本公开的一种实施方式中，第一晶体管M1、第二晶体管M2、第七晶体管M7、第八晶体管M8、第十三晶体管M13、第十四晶体管M14为N型晶体管；第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12为P型晶体管。如此，可以采用CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)工艺形成各个晶体管，无需引入额外的制程而增加显示面板的成本。
可选地，半导体衬底310可以为硅基半导体衬底，尤其是可以为单晶硅半导体衬底310。
可选地，参见图5，任意一个行驱动信号增强区F包括P型衬底区F_Pdop和N型衬底区F_Ndop，P型衬底区F_Pdop位于N型衬底区F_Ndop的第一方向G一侧，第一方向G为远离显示区D的方向；N型晶体管形成于P型衬底区F_Pdop，且P型晶体管形成于N型衬底区F_Ndop。
在一些实施方式中，参见图5，N型衬底区F_Ndop包括N型辅助掺杂区F_Ndummy，以及包括分别被N型辅助掺杂区F_Ndummy环绕的第一有源区Act1和第二有源区Act2；第二有源区Act2位于第一有源区Act1的第一方向G一侧；
第一有源区Act1包括沿第一方向G依次排列的第一亚有源区Act_sub1和第二亚有源区Act_sub2；第九晶体管M9和第十一晶体管M11位于第一亚有源区Act_sub1，第十晶体管M10和第十二晶体管M12位于第二亚有源区Act_sub2；
第二有源区Act2包括沿第二方向H依次排列的第三亚有源区Act_sub3和第四亚 有源区Act_sub4；第二方向H与第一方向G垂直且平行于半导体衬底310所在平面；第五晶体管M5和第六晶体管M6位于第三亚有源区Act_sub3，第三晶体管M3和第四晶体管M4位于第四亚有源区Act_sub4。
如此，该晶体管的排布方式可以提高晶体管排布的紧凑性，降低行驱动信号增强电路101的面积占比以及减少连接引线的长度，降低行驱动信号增强电路101的功耗。不仅如此，N型辅助掺杂区F_Ndummy可以减小各个晶体管的漏电，进一步降低行驱动信号增强电路101的功耗。
在本公开的一种实施方式中，参见图5，N型辅助掺杂区F_Ndummy可以包括第一N型掺杂亚区F_Nsub1至第七N型掺杂亚区F_Nsub7。其中，第一N型掺杂亚区F_Nsub1、第三N型掺杂亚区F_Nsub3、第五N型掺杂亚区F_Nsub5和第七N型掺杂亚区F_Nsub7沿第一方向G延伸，第二N型掺杂亚区F_Nsub2、第四N型掺杂亚区F_Nsub4和第六N型掺杂亚区F_Nsub6沿第二方向H延伸。第一N型掺杂亚区F_Nsub1、第二N型掺杂亚区F_Nsub2、第三N型掺杂亚区F_Nsub3和第四N型掺杂亚区F_Nsub4依次连接而形成封闭环形，第一有源区Act1位于第一N型掺杂亚区F_Nsub1、第二N型掺杂亚区F_Nsub2、第三N型掺杂亚区F_Nsub3和第四N型掺杂亚区F_Nsub4所环绕的空间内；第四N型掺杂亚区F_Nsub4、第五N型掺杂亚区F_Nsub5、第六N型掺杂亚区F_Nsub6和第七N型掺杂亚区F_Nsub7依次连接而形成封闭环形，第二有源区Act2位于第四N型掺杂亚区F_Nsub4、第五N型掺杂亚区F_Nsub5、第六N型掺杂亚区F_Nsub6和第七N型掺杂亚区F_Nsub7所环绕的空间内。第五N型掺杂亚区F_Nsub5位于第一N型掺杂亚区F_Nsub1的第一方向G一侧，且位于第一N型掺杂亚区F_Nsub1沿第一方向G的延伸线上；第七N型掺杂亚区F_Nsub7位于第三N型掺杂亚区F_Nsub3的第一方向G一侧，且位于第三N型掺杂亚区F_Nsub3沿第一方向G的延伸线上。第二N型掺杂亚区F_Nsub2、第四N型掺杂亚区F_Nsub4和第六N型掺杂亚区F_Nsub6沿第一方向G依次排列。
可选地，参见图5，第五N型掺杂亚区F_Nsub5在第二方向H上的尺寸小于第一N型掺杂亚区F_Nsub1在第二方向H上的尺寸，第七N型掺杂亚区F_Nsub7在第二方向H上的尺寸小于第三N型掺杂亚区F_Nsub3在第二方向H上的尺寸。如此，可以提高第二有源区Act2在第二方向H上的尺寸，进而便于在第二有源区Act2内设置沿第二方向H排列的第三亚有源区Act_sub3和第四亚有源区Act_sub4。
可选地，第一亚有源区Act_sub1在第一方向G上的尺寸与第二亚有源区Act_sub2在第一方向G上的尺寸相同；第一亚有源区Act_sub1在第二方向H上的尺寸与第二亚有源区Act_sub2在第二方向H上的尺寸相同。如此便于使得第九晶体管M9和第十晶体管M10的尺寸相同，且便于使得第十一晶体管M11和第十二晶体管M12的尺寸相同。
可选地，第三亚有源区Act_sub3在第一方向G上的尺寸与第四亚有源区Act_sub4 在第一方向G上的尺寸相同；第三亚有源区Act_sub3在第二方向H上的尺寸与第四亚有源区Act_sub4在第二方向H上的尺寸相同。如此便于使得第三晶体管M3至第六晶体管M6的尺寸相同。
在本公开的一种实施方式中，沿第一方向G，第一亚有源区Act_sub1的尺寸为第三亚有源区Act_sub3的尺寸的3～5倍，第二亚有源区Act_sub2的尺寸为第三亚有源区Act_sub3的尺寸的3～5倍。如此，可以使得第九晶体管M9至第十二晶体管M12的沟道区具有较大的宽度，提高第九晶体管M9至第十二晶体管M12的电流输出能力，进而提高行驱动信号增强电路101的驱动能力。相应的，第三晶体管M3至第六晶体管M6可以具有较小的尺寸，尤其是具有较小的沟道区，这可以提高第三晶体管M3至第六晶体管M6的导通速度或者截止速度，减少第三晶体管M3至第六晶体管M6引起的信号延时，进而降低行驱动信号增强电路101的信号延时。
在一些实施方式中，参见图5，P型衬底区F_Pdop包括P型辅助掺杂区F_Pdummy、第三有源区Act3和第四有源区Act4；第四有源区Act4位于第三有源区Act3的第一方向G一侧。第三有源区Act3被P型辅助掺杂区F_Pdummy环绕，且包括沿第一方向G依次排列的第五亚有源区Act_sub5和第六亚有源区Act_sub6；第七晶体管M7和第十三晶体管M13位于第五亚有源区Act_sub5，第八晶体管M8和第十四晶体管M14位于第六亚有源区Act_sub6。第四有源区Act4包括沿第二方向H依次排列且分别被P型辅助掺杂区F_Pdummy环绕的第七亚有源区Act_sub7和第八亚有源区Act_sub8；第一晶体管M1位于第七亚有源区Act_sub7，第二晶体管M2位于第八亚有源区Act_sub8。
如此，该晶体管的排布方式可以提高晶体管排布的紧凑性，降低行驱动信号增强电路101的面积占比以及减少连接引线的长度，降低行驱动信号增强电路101的功耗。不仅如此，P型辅助掺杂区F_Pdummy可以减小各个晶体管的漏电，进一步降低行驱动信号增强电路101的功耗。
在本公开的一种实施方式中，P型辅助掺杂区F_Pdummy可以包括第一P型掺杂亚区F_Psub1至第八P型掺杂亚区F_Psub8。其中，第一P型掺杂亚区F_Psub1、第三P型掺杂亚区F_Psub3、第五P型掺杂亚区F_Psub5、第七P型掺杂亚区F_Psub7和第八P型掺杂亚区F_Psub8沿第一方向G延伸，第二P型掺杂亚区F_Psub2、第四P型掺杂亚区F_Psub4和第六P型掺杂亚区F_Psub6沿第二方向H延伸。参见图5，第一P型掺杂亚区F_Psub1、第二P型掺杂亚区F_Psub2、第三P型掺杂亚区F_Psub3和第四P型掺杂亚区F_Psub4依次连接而形成封闭环形，第三有源区Act3位于第一P型掺杂亚区F_Psub1、第二P型掺杂亚区F_Psub2、第三P型掺杂亚区F_Psub3和第四P型掺杂亚区F_Psub4所环绕的空间内；第五P型掺杂亚区F_Psub5、第六P型掺杂亚区F_Psub6、第七P型掺杂亚区F_Psub7和第四P型掺杂亚区F_Psub4依次连接而形成封闭环形，第四有源区Act4位于第五P型掺杂亚区F_Psub5、第六P型掺杂亚区F_Psub6、第七P型掺杂亚区F_Psub7和第四P型掺杂亚区F_Psub4所环绕的空间 内。第八P型掺杂亚区F_Psub8的两端分别连接第四P型掺杂亚区F_Psub4和第六P型掺杂亚区F_Psub6，其中，第七亚有源区Act_sub7位于第五P型掺杂亚区F_Psub5、第六P型掺杂亚区F_Psub6、第八P型掺杂亚区F_Psub8和第四P型掺杂亚区F_Psub4所围绕成的空间内，第八亚有源区Act_sub8位于第八P型掺杂亚区F_Psub8、第六P型掺杂亚区F_Psub6、第七P型掺杂亚区F_Psub7和第四P型掺杂亚区F_Psub4所围绕成的空间内。
第五P型掺杂亚区F_Psub5位于第一P型掺杂亚区F_Psub1的第一方向G一侧，且位于第一P型掺杂亚区F_Psub1沿第一方向G的延伸线上。第七P型掺杂亚区F_Psub7位于第三P型掺杂亚区F_Psub3的第一方向G一侧，且位于第三P型掺杂亚区F_Psub3沿第一方向G的延伸线上。第二P型掺杂亚区F_Psub2、第四P型掺杂亚区F_Psub4和第六P型掺杂亚区F_Psub6沿第一方向G依次排列，第五P型掺杂亚区F_Psub5、第八P型掺杂亚区F_Psub8和第七P型掺杂亚区F_Psub7沿第二方向H依次排列。
可选地，参见图5，第五P型掺杂亚区F_Psub5在第二方向H上的尺寸小于第一P型掺杂亚区F_Psub1在第二方向H上的尺寸，第七P型掺杂亚区F_Psub7在第二方向H上的尺寸小于第三P型掺杂亚区F_Psub3在第二方向H上的尺寸。如此，可以提高第四有源区Act4在第二方向H上的尺寸，为设置第七亚有源区Act_sub7和第八亚有源区Act_sub8提供更多空间，同时也可以为设置第八P型掺杂亚区F_Psub8提供空间。
可选地，第五亚有源区Act_sub5在第一方向G上的尺寸与第六亚有源区Act_sub6在第一方向G上的尺寸相同；第六亚有源区Act_sub6在第二方向H上的尺寸与第五亚有源区Act_sub5在第二方向H上的尺寸相同。如此便于使得第七晶体管M7和第八晶体管M8的尺寸相同，且便于使得第十三晶体管M13和第十四晶体管M14的尺寸相同。
可选地，第七亚有源区Act_sub7在第一方向G上的尺寸与第八亚有源区Act_sub8在第一方向G上的尺寸相同；第七亚有源区Act_sub7在第二方向H上的尺寸与第八亚有源区Act_sub8在第二方向H上的尺寸相同。如此便于使得第一晶体管M1和第二晶体管M2的尺寸相同。
在本公开的一种实施方式中，沿第一方向G，第七亚有源区Act_sub7的尺寸为第五亚有源区Act_sub5的尺寸的1.5～2.5倍；第七亚有源区Act_sub7的尺寸与第八亚有源区Act_sub8的尺寸相同；第五亚有源区Act_sub5的尺寸与第六亚有源区Act_sub6的尺寸相同。
参见图6、图11和图23，栅极层330形成有第一晶体管M1至第十四晶体管M14的栅极，且栅极绝缘层320隔离任意一个晶体管的栅极和沟道区。可选地，各个晶体 管的栅极沿第一方向G延伸。
在本公开的一种实施方式中，在形成各个晶体管时，可以采用CMOS工艺进行制备。示例性地，可以采用如下方法在行驱动信号增强区F形成行驱动信号增强电路101的各个晶体管。
参见图5和图23，可以先提供一P型半导体衬底310，P型半导体衬底310在行驱动信号增强区F具有第一区域和第二区域。其中，第一区域可以作为P型衬底区F_Pdop，其具有P阱。可以在第二区域注入N型离子而使得该第二区域形成N阱，作为N型衬底区F_Ndop。
然后，参见图6和图23，可以形成栅极绝缘层320(图中未示出)和栅极层330，使得栅极绝缘层320和栅极层330覆盖各个晶体管的沟道区，并暴露各个晶体管的源极和漏极。栅极绝缘层320的材料可以为氧化硅、氮化硅、氮氧化硅等无机绝缘材料。栅极层330的材料可以为多晶硅。
参见图7、图8和图11中线条填充部分，可以对P型衬底区F_Pdop的各个有源区和N型衬底区F_Ndop的N型辅助掺杂区F_Ndummy进行N型离子注入。如此，位于P型衬底区F_Pdop中的各个晶体管的源极和漏极转变为N型掺杂，进而在P型衬底区F_Pdop形成各个N型晶体管；N型辅助掺杂区F_Ndummy的掺杂浓度增大，具有更好的防漏电效果。
参见图9、图10和图11中点填充部分，可以对N型衬底区F_Ndop的各个有源区和P型衬底区F_Pdop的P型辅助掺杂区F_Pdummy进行P型离子注入。如此，位于N型衬底区F_Ndop中的各个晶体管的源极和漏极转变为P型掺杂，进而在N型衬底区F_Ndop形成各个P型晶体管；P型辅助掺杂区F_Pdummy的掺杂浓度增大，具有更好的防漏电效果。
根据上述的制备方法，各个有源区中与栅极交叠的部分，可以作为各个晶体管的沟道区。在N型离子注入或者P型离子注入的过程中，栅极可以阻挡离子向有源区的离子注入，进而使得其保持半导体特性。
在本公开的一种实施方式中，参见图11，第一晶体管M1的栅极M1G包括第一栅极M1G1和第二栅极M1G2，第一晶体管M1的第一栅极M1G1和第一晶体管M1的第二栅极M1G2均沿第一方向G延伸且沿第二方向H依次排列，两者的长度相同。第七亚有源区Act_sub7与第一晶体管M1的第一栅极M1G1和第一晶体管M1的第二栅极M1G2交叠的部分，作为第一晶体管M1的沟道区。换言之，第一晶体管M1的沟道区具有相互平行设置的第一沟道区和第二沟道区，第一晶体管M1的第一沟道区与第一晶体管M1的第一栅极M1G1交叠，第一晶体管M1的第二沟道区与第一晶 体管M1的第二栅极M1G2交叠。第一晶体管M1的漏极M1D位于第一晶体管M1的第一沟道区和第一晶体管M1的第二沟道区之间，第一晶体管M1的源极M1S位于第一晶体管M1的第一沟道区远离第一晶体管M1的第二沟道区的一侧以及位于第一晶体管M1的第二沟道区远离第一晶体管M1的第一沟道区的一侧。换言之，第一晶体管M1的源极M1S包括相互平行设置的第一源极M1S1和第二源极M1S2，第一晶体管M1的第一源极M1S1位于第一晶体管M1的第一沟道区远离第一晶体管M1的第二沟道区的一侧，第一晶体管M1的第二源极M1S2位于第一晶体管M1的第二沟道区远离第一晶体管M1的第一沟道区的一侧。如此，第一晶体管M1的第一源极M1S1、第一晶体管M1的第一沟道区、第一晶体管M1的漏极M1D、第一晶体管M1的第二沟道区和第一晶体管M1的第二源极M1S2均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，参见图11，第二晶体管M2的栅极M2G包括第一栅极M2G1和第二栅极M2G2，第二晶体管M2的第二栅极M2G2和第二晶体管M2的第一栅极M2G1均沿第一方向G延伸且沿第二方向H依次排列，两者的长度相同。第八亚有源区Act_sub8与第二晶体管M2的第一栅极M2G1和第二晶体管M2的第二栅极M2G2交叠的部分，作为第二晶体管M2的沟道区。换言之，第二晶体管M2的沟道区具有相互平行设置的第一沟道区和第二沟道区，第二晶体管M2的第一沟道区与第二晶体管M2的第一栅极M2G1交叠，第二晶体管M2的第二沟道区与第二晶体管M2的第二栅极M2G2交叠。第二晶体管M2的漏极M2D位于第二晶体管M2的第一沟道区和第二晶体管M2的第二沟道区之间，第二晶体管M2的源极M2S位于第二晶体管M2的第一沟道区远离第二晶体管M2的第二沟道区的一侧以及位于第二晶体管M2的第二沟道区远离第二晶体管M2的第一沟道区的一侧。换言之，第二晶体管M2的源极M2S包括相互平行设置的第一源极M2S1和第二源极M2S2，第二晶体管M2的第一源极M2S1位于第二晶体管M2的第一沟道区远离第二晶体管M2的第二沟道区的一侧，第二晶体管M2的第二源极M2S2位于第二晶体管M2的第二沟道区远离第二晶体管M2的第一沟道区的一侧。如此，第二晶体管M2的第二源极M2S2、第二晶体管M2的第二沟道区、第二晶体管M2的漏极M2D、第二晶体管M2的第一沟道区和第二晶体管M2的第一源极M2S1均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，第一晶体管M1的第一源极M1S1、第一晶体管M1的第一栅极M1G1、第一晶体管M1的漏极M1D、第一晶体管M1的第二栅极M1G2、第一晶体管M1的第二源极M1S2、第二晶体管M2的第二源极M2S2、第二 晶体管M2的第二栅极M2G2、第二晶体管M2的漏极M2D、第二晶体管M2的第一栅极M2G1和第二晶体管M2的第一源极M2S1沿第二方向H依次排列。如此，第二晶体管M2位于第一晶体管M1的第二方向H一侧。
在本公开的一种实施方式中，参见图11，第五晶体管M5的栅极M5G、第六晶体管M6的栅极M6G、第三晶体管M3的栅极M3G和第四晶体管M4的栅极M4G沿第一方向G延伸，且沿第二方向H依次排列，其中，第五晶体管M5的栅极M5G和第六晶体管M6的栅极M6G与第三亚有源区Act_sub3交叠，第三晶体管M3的栅极M3G和第四晶体管M4的栅极M4G与第四亚有源区Act_sub4交叠。如此，第五晶体管M5、第六晶体管M6、第三晶体管M3和第四晶体管M4沿第二方向H依次排列。
第四亚有源区Act_sub4与第三晶体管M3的栅极M3G交叠的部分作为第三晶体管M3的沟道区。第三晶体管M3的源极M3S位于第三晶体管M3的沟道区的第二方向H的相反方向一侧，且第三晶体管M3的漏极M3D位于第三晶体管M3的沟道区的第二方向H一侧。换言之，第三晶体管M3的源极M3S、第三晶体管M3的沟道区和第三晶体管M3的漏极M3D均沿第一方向G延伸，且沿第二方向H依次排列。
第四亚有源区Act_sub4与第四晶体管M4的栅极M4G交叠的部分作为第四晶体管M4的沟道区。第四晶体管M4的源极M4S位于第三晶体管M4的沟道区的第二方向H一侧，且第四晶体管M4的漏极M4D位于第四晶体管M4的沟道区的第二方向H的相反方向一侧。换言之，第四晶体管M4的漏极M4D、第四晶体管M4的沟道区和第四晶体管M4的源极M4S均沿第一方向G延伸，且沿第二方向H依次排列。
第三亚有源区Act_sub3与第五晶体管M5的栅极M5G交叠的部分作为第五晶体管M5的沟道区。第五晶体管M5的源极M5S位于第五晶体管M5的沟道区的第二方向H的相反方向一侧，且第五晶体管M5的漏极M5D位于第五晶体管M5的沟道区的第二方向H一侧。换言之，第五晶体管M5的源极M5S、第五晶体管M5的沟道区和第五晶体管M5的漏极M5D均沿第一方向G延伸，且沿第二方向H依次排列。
第三亚有源区Act_sub3与第六晶体管M6的栅极M6G交叠的部分作为第六晶体管M6的沟道区。第六晶体管M6的源极M6S位于第六晶体管M6的沟道区的第二方向H一侧，且第六晶体管M6的漏极M6D位于第六晶体管M6的沟道区的第二方向H的相反方向一侧。换言之，第六晶体管M6的漏极M6D、第六晶体管M6的沟道区和第六晶体管M6的源极M6S均沿第一方向G延伸，且沿第二方向H依次排列。
可选地，第三晶体管M3的漏极M3D和第四晶体管M4的漏极M4D重合。如此，第三晶体管M3和第四晶体管M4可以共用漏极，进而简化行驱动信号增强电路101 的布线设置，提高行驱动信号增强电路101的紧凑性，降低行驱动信号增强电路101所占用的面积。
可选地，第五晶体管M5的漏极M5D和第六晶体管M6的漏极M6D重合。如此，第五晶体管M5和第六晶体管M6可以共用漏极，进而简化行驱动信号增强电路101的布线设置，提高行驱动信号增强电路101的紧凑性，降低行驱动信号增强电路101所占用的面积。
在本公开的一种实施方式中，参见图11，第七晶体管M7的栅极M7G包括第一栅极M7G1和第二栅极M7G2，第七晶体管M7的第一栅极M7G1和第七晶体管M7的第二栅极M7G2均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第五亚有源区Act_sub5与第七晶体管M7的第一栅极M7G1和第七晶体管M7的第二栅极M7G2交叠的部分，作为第七晶体管M7的沟道区。换言之，第七晶体管M7的沟道区具有相互平行设置的第一沟道区和第二沟道区，第七晶体管M7的第一沟道区与第七晶体管M7的第一栅极M7G1交叠，第七晶体管M7的第二沟道区与第七晶体管M7的第二栅极M7G2交叠。第七晶体管M7的漏极M7D位于第七晶体管M7的第一沟道区和第七晶体管M7的第二沟道区之间，第七晶体管的源极M7S位于第七晶体管M7的第一沟道区远离第七晶体管M7的第二沟道区的一侧以及位于第七晶体管M7的第二沟道区远离第七晶体管M7的第一沟道区的一侧。换言之，第七晶体管的源极M7S包括相互平行设置的第一源极M7S1和第二源极M7S2，第七晶体管M7的第一源极M7S1位于第七晶体管M7的第一沟道区远离第七晶体管M7的第二沟道区的一侧，第七晶体管M7的第二源极M7S2位于第七晶体管M7的第二沟道区远离第七晶体管M7的第一沟道区的一侧。如此，第七晶体管M7的第一源极M7S1、第七晶体管M7的第一沟道区、第七晶体管M7的漏极M7D、第七晶体管M7的第二沟道区和第七晶体管M7的第二源极M7S2均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，参见图11，第八晶体管M8的栅极M8G包括第一栅极M8G1和第二栅极M8G2，第八晶体管M8的第一栅极M8G1和第八晶体管M8的第二栅极M8G2均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第六亚有源区Act_sub6与第八晶体管M8的第一栅极M8G1和第八晶体管M8的第二栅极M8G2交叠的部分，作为第八晶体管M8的沟道区。换言之，第八晶体管M8的沟道区具有相互平行设置的第一沟道区和第二沟道区，第八晶体管M8的第一沟道区与第八晶体管M8的第一栅极M8G1交叠，第八晶体管M8的第二沟道区与第八晶体管M8的第二栅极M8G2交叠。第八晶体管M8的漏极M8D位于第八晶体管M8 的第一沟道区和第八晶体管M8的第二沟道区之间，第八晶体管的源极M8S位于第八晶体管M8的第一沟道区远离第八晶体管M8的第二沟道区的一侧以及位于第八晶体管M8的第二沟道区远离第八晶体管M8的第一沟道区的一侧。换言之，第八晶体管的源极M8S包括相互平行设置的第一源极M8S1和第二源极M8S2，第八晶体管M8的第一源极M8S1位于第八晶体管M8的第一沟道区远离第八晶体管M8的第二沟道区的一侧，第八晶体管M8的第二源极M8S2位于第八晶体管M8的第二沟道区远离第八晶体管M8的第一沟道区的一侧。如此，第八晶体管M8的第一源极M8S1、第八晶体管M8的第一沟道区、第八晶体管M8的漏极M8D、第八晶体管M8的第二沟道区和第八晶体管M8的第二源极M8S2均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，第八晶体管M8的第一源极M8S1和第七晶体管M7的第一源极M7S1在第一方向G上的延伸线重合，即第八晶体管M8的第一源极M8S1和第七晶体管M7的第一源极M7S1沿第一方向G直线排列。第八晶体管M8的第二源极M8S2和第七晶体管M7的第二源极M7S2在第一方向G上的延伸线重合，即第八晶体管M8的第二源极M8S2和第七晶体管M7的第二源极M7S2沿第一方向G直线排列。第八晶体管M8的第一栅极M8G1和第七晶体管M7的第一栅极M7G1在第一方向G上的延伸线重合，即第八晶体管M8的第一栅极M8G1和第七晶体管M7的第一栅极M7G1沿第一方向G直线排列。第八晶体管M8的第二栅极M8G2和第七晶体管M7的第二栅极M7G2在第一方向G上的延伸线重合，即第八晶体管M8的第二栅极M8G2和第七晶体管M7的第二栅极M7G2沿第一方向G直线排列。第八晶体管M8的漏极M8D和第七晶体管M7的漏极M7D在第一方向G上的延伸线重合，即第八晶体管M8的漏极M8D和第七晶体管M7的漏极M7D沿第一方向G直线排列。第八晶体管M8的第一沟道区和第七晶体管M7的第一沟道区在第一方向G上的延伸线重合，即第八晶体管M8的第一沟道区和第七晶体管M7的第一沟道区沿第一方向G直线排列。第八晶体管M8的第二沟道区和第七晶体管M7的第二沟道区在第一方向G上的延伸线重合，即第八晶体管M8的第二沟道区和第七晶体管M7的第二沟道区沿第一方向G直线排列。如此，第八晶体管M8位于第七晶体管M7的第一方向G一侧。
在本公开的一种实施方式中，参见图11，第十三晶体管M13的栅极M13G包括第一栅极M13G1和第二栅极M13G2，第十三晶体管M13的第二栅极M13G2和第十三晶体管M13的第一栅极M13G1均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第五亚有源区Act_sub5与第十三晶体管M13的第一栅极M13G1 和第十三晶体管M13的第二栅极M13G2交叠的部分，作为第十三晶体管M13的沟道区。换言之，第十三晶体管M13的沟道区具有相互平行设置的第一沟道区和第二沟道区，第十三晶体管M13的第一沟道区与第十三晶体管M13的第一栅极M13G1交叠，第十三晶体管M13的第二沟道区与第十三晶体管M13的第二栅极M13G2交叠。第十三晶体管M13的漏极M13D位于第十三晶体管M13的第一沟道区和第十三晶体管M13的第二沟道区之间，第十三晶体管的源极M13S位于第十三晶体管M13的第一沟道区远离第十三晶体管M13的第二沟道区的一侧以及位于第十三晶体管
M13的第二沟道区远离第十三晶体管M13的第一沟道区的一侧。换言之，第十三晶体管的源极M13S包括相互平行设置的第一源极M13S1和第二源极M13S2，第十三晶体管M13的第一源极M13S1位于第十三晶体管M13的第一沟道区远离第十三晶体管M13的第二沟道区的一侧，第十三晶体管M13的第二源极M13S2位于第十三晶体管M13的第二沟道区远离第十三晶体管M13的第一沟道区的一侧。如此，第十三晶体管M13的第二源极M13S2、第十三晶体管M13的第二沟道区、第十三晶体管M13的漏极M13D、第十三晶体管M13的第一沟道区和第十三晶体管M13的第一源极M13S1均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，参见图11，第十四晶体管M14的栅极M14G包括第一栅极M14G1和第二栅极M14G2，第十四晶体管M14的第二栅极M14G2和第十四晶体管M14的第一栅极M14G1均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第六亚有源区Act_sub6与第十四晶体管M14的第一栅极M14G1和第十四晶体管M14的第二栅极M14G2交叠的部分，作为第十四晶体管M14的沟道区。换言之，第十四晶体管M14的沟道区具有相互平行设置的第一沟道区和第二沟道区，第十四晶体管M14的第一沟道区与第十四晶体管M14的第一栅极M14G1交叠，第十四晶体管M14的第二沟道区与第十四晶体管M14的第二栅极M14G2交叠。第十四晶体管M14的漏极M14D位于第十四晶体管M14的第一沟道区和第十四晶体管M14的第二沟道区之间，第十四晶体管的源极M14S位于第十四晶体管M14的第一沟道区远离第十四晶体管M14的第二沟道区的一侧以及位于第十四晶体管M14的第二沟道区远离第十四晶体管M14的第一沟道区的一侧。换言之，第十四晶体管的源极M14S包括相互平行设置的第一源极M14S1和第二源极M14S2，第十四晶体管M14的第一源极M14S1位于第十四晶体管M14的第一沟道区远离第十四晶体管M14的第二沟道区的一侧，第十四晶体管M14的第二源极M14S2位于第十四晶体管M14的第二沟道区远离第十四晶体管M14的第一沟道区的一侧。如此，第十四晶体管M14的第二源极M14S2、第十四晶体管M14的第二沟道区、第十四晶体管 M14的漏极M14D、第十四晶体管M14的第一沟道区和第十四晶体管M14的第一源极M14S1均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，第十四晶体管M14的第一源极M14S1和第十三晶体管M13的第一源极M13S1在第一方向G上的延伸线重合，即第十四晶体管M14的第一源极M14S1和第十三晶体管M13的第一源极M13S1沿第一方向G直线排列。第十四晶体管M14的第二源极M14S2和第十三晶体管M13的第二源极M13S2在第一方向G上的延伸线重合，即第十四晶体管M14的第二源极M14S2和第十三晶体管M13的第二源极M13S2沿第一方向G直线排列。第十四晶体管M14的第一栅极M14G1和第十三晶体管M13的第一栅极M13G1在第一方向G上的延伸线重合，即第十四晶体管M14的第一栅极M14G1和第十三晶体管M13的第一栅极M13G1沿第一方向G直线排列。第十四晶体管M14的第二栅极M14G2和第十三晶体管M13的第二栅极M13G2在第一方向G上的延伸线重合，即第十四晶体管M14的第二栅极M14G2和第十三晶体管M13的第二栅极M13G2沿第一方向G直线排列。第十四晶体管M14的漏极M14D和第十三晶体管M13的漏极M13D在第一方向G上的延伸线重合，即第十四晶体管M14的漏极M14D和第十三晶体管M13的漏极M13D沿第一方向G直线排列。第十四晶体管M14的第一沟道区和第十三晶体管M13的第一沟道区在第一方向G上的延伸线重合，即第十四晶体管M14的第一沟道区和第十三晶体管M13的第一沟道区沿第一方向G直线排列。第十四晶体管M14的第二沟道区和第十三晶体管M13的第二沟道区在第一方向G上的延伸线重合，即第十四晶体管M14的第二沟道区和第十三晶体管M13的第二沟道区沿第一方向G直线排列。如此，第十四晶体管M14位于第十三晶体管M13第一方向G一侧。
在本公开的一种实施方式中，第七晶体管M7的第一源极M7S1、第七晶体管M7的第一栅极M7G1、第七晶体管M7的漏极M7D、第七晶体管M7的第二栅极M7G2、第七晶体管M7的第二源极M7S2、第十三晶体管M13的第二源极M13S2、第十三晶体管M13的第二栅极M13G2、第十三晶体管M13的漏极M13D、第十三晶体管M13的第一栅极M13G1和第十三晶体管M13的第一源极M13S1沿第二方向H依次排列。如此，第十三晶体管M13位于第七晶体管M7的第二方向H一侧。进一步地，第七晶体管M7的第二源极M7S2和第十三晶体管M13的第二源极M13S2重合。如此，第七晶体管M7和第十三晶体管M13可以共用源极，进而简化行驱动信号增强电路101的布线设置，提高行驱动信号增强电路101的紧凑性，降低行驱动信号增强电路101所占用的面积。
在本公开的一种实施方式中，第八晶体管M8的第一源极M8S1、第八晶体管 M8的第一栅极M8G1、第八晶体管M8的漏极M8D、第八晶体管M8的第二栅极M8G2、第八晶体管M8的第二源极M8S2、第十四晶体管M14的第二源极M14S2、第十四晶体管M14的第二栅极M14G2、第十四晶体管M14的漏极M14D、第十四晶体管M14的第一栅极M14G1和第十四晶体管M14的第一源极M14S1沿第二方向H依次排列。如此，第十四晶体管M14位于第八晶体管M8的第二方向H一侧。进一步地，第八晶体管M8的第二源极M8S2和第十四晶体管M14的第二源极M14S2重合。如此，第八晶体管M8和第十四晶体管M14可以共用源极，进而简化行驱动信号增强电路101的布线设置，提高行驱动信号增强电路101的紧凑性，降低行驱动信号增强电路101所占用的面积。
在本公开的一种实施方式中，参见图11，第九晶体管M9的栅极M9G包括第一栅极M9G1和第二栅极M9G2，第九晶体管M9的第一栅极M9G1和第九晶体管M9的第二栅极M9G2均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第一亚有源区Act_sub1与第九晶体管M9的第一栅极M9G1和第九晶体管M9的第二栅极M9G2交叠的部分，作为第九晶体管M9的沟道区。换言之，第九晶体管M9的沟道区具有相互平行设置的第一沟道区和第二沟道区，第九晶体管M9的第一沟道区与第九晶体管M9的第一栅极M9G1交叠，第九晶体管M9的第二沟道区与第九晶体管M9的第二栅极M9G2交叠。第九晶体管M9的漏极M9D位于第九晶体管M9的第一沟道区和第九晶体管M9的第二沟道区之间，第九晶体管的源极M9S位于第九晶体管M9的第一沟道区远离第九晶体管M9的第二沟道区的一侧以及位于第九晶体管M9的第二沟道区远离第九晶体管M9的第一沟道区的一侧。换言之，第九晶体管的源极M9S包括相互平行设置的第一源极M9S1和第二源极M9S2，第九晶体管M9的第一源极M9S1位于第九晶体管M9的第一沟道区远离第九晶体管M9的第二沟道区的一侧，第九晶体管M9的第二源极M9S2位于第九晶体管M9的第二沟道区远离第九晶体管M9的第一沟道区的一侧。如此，第九晶体管M9的第一源极M9S1、第九晶体管M9的第一沟道区、第九晶体管M9的漏极M9D、第九晶体管M9的第二沟道区和第九晶体管M9的第二源极M9S2均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，参见图11，第十晶体管M10的栅极M10G包括第一栅极M10G1和第二栅极M10G2，第十晶体管M10的第一栅极M10G1和第十晶体管M10的第二栅极M10G2均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第二亚有源区Act_sub2与第十晶体管M10的第一栅极M10G1和第十晶体管M10的第二栅极M10G2交叠的部分，作为第十晶体管M10的沟道区。换言之， 第十晶体管M10的沟道区具有相互平行设置的第一沟道区和第二沟道区，第十晶体管M10的第一沟道区与第十晶体管M10的第一栅极M10G1交叠，第十晶体管M10的第二沟道区与第十晶体管M10的第二栅极M10G2交叠。第十晶体管M10的漏极M10D位于第十晶体管M10的第一沟道区和第十晶体管M10的第二沟道区之间，第十晶体管的源极M10S位于第十晶体管M10的第一沟道区远离第十晶体管M10的第二沟道区的一侧以及位于第十晶体管M10的第二沟道区远离第十晶体管M10的第一沟道区的一侧。换言之，第十晶体管的源极M10S包括相互平行设置的第一源极M10S1和第二源极M10S2，第十晶体管M10的第一源极M10S1位于第十晶体管M10的第一沟道区远离第十晶体管M10的第二沟道区的一侧，第十晶体管M10的第二源极M10S2位于第十晶体管M10的第二沟道区远离第十晶体管M10的第一沟道区的一侧。如此，第十晶体管M10的第一源极M10S1、第十晶体管M10的第一沟道区、第十晶体管M10的漏极M10D、第十晶体管M10的第二沟道区和第十晶体管M10的第二源极M10S2均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，第十晶体管M10的第一源极M10S1和第九晶体管M9的第一源极M9S1在第一方向G上的延伸线重合，即第十晶体管M10的第一源极M10S1和第九晶体管M9的第一源极M9S1沿第一方向G直线排列。第十晶体管M10的第二源极M10S2和第九晶体管M9的第二源极M9S2在第一方向G上的延伸线重合，即第十晶体管M10的第二源极M10S2和第九晶体管M9的第二源极M9S2沿第一方向G直线排列。第十晶体管M10的第一栅极M10G1和第九晶体管M9的第一栅极M9G1在第一方向G上的延伸线重合，即第十晶体管M10的第一栅极M10G1和第九晶体管M9的第一栅极M9G1沿第一方向G直线排列。第十晶体管M10的第二栅极M10G2和第九晶体管M9的第二栅极M9G2在第一方向G上的延伸线重合，即第十晶体管M10的第二栅极M10G2和第九晶体管M9的第二栅极M9G2沿第一方向G直线排列。第十晶体管M10的漏极M10D和第九晶体管M9的漏极M9D在第一方向G上的延伸线重合，即第十晶体管M10的漏极M10D和第九晶体管M9的漏极M9D沿第一方向G直线排列。第十晶体管M10的第一沟道区和第九晶体管M9的第一沟道区在第一方向G上的延伸线重合，即第十晶体管M10的第一沟道区和第九晶体管M9的第一沟道区沿第一方向G直线排列。第十晶体管M10的第二沟道区和第九晶体管M9的第二沟道区在第一方向G上的延伸线重合，即第十晶体管M10的第二沟道区和第九晶体管M9的第二沟道区沿第一方向G直线排列。如此，第十晶体管M10位于第九晶体管M9的第一方向G一侧。
在本公开的一种实施方式中，参见图11，第十一晶体管M11的栅极M11G包括 第一栅极M11G1和第二栅极M11G2，第十一晶体管M11的第二栅极M11G2和第十一晶体管M11的第一栅极M11G1均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第一亚有源区Act_sub1与第十一晶体管M11的第一栅极M11G1和第十一晶体管M11的第二栅极M11G2交叠的部分，作为第十一晶体管M11的沟道区。换言之，第十一晶体管M11的沟道区具有相互平行设置的第一沟道区和第二沟道区，第十一晶体管M11的第一沟道区与第十一晶体管M11的第一栅极M11G1交叠，第十一晶体管M11的第二沟道区与第十一晶体管M11的第二栅极M11G2交叠。第十一晶体管M11的漏极M11D位于第十一晶体管M11的第一沟道区和第十一晶体管M11的第二沟道区之间，第十一晶体管的源极M11S位于第十一晶体管M11的第一沟道区远离第十一晶体管M11的第二沟道区的一侧以及位于第十一晶体管
M11的第二沟道区远离第十一晶体管M11的第一沟道区的一侧。换言之，第十一晶体管的源极M11S包括相互平行设置的第一源极M11S1和第二源极M11S2，第十一晶体管M11的第一源极M11S1位于第十一晶体管M11的第一沟道区远离第十一晶体管M11的第二沟道区的一侧，第十一晶体管M11的第二源极M11S2位于第十一晶体管M11的第二沟道区远离第十一晶体管M11的第一沟道区的一侧。如此，第十一晶体管M11的第二源极M11S2、第十一晶体管M11的第二沟道区、第十一晶体管M11的漏极M11D、第十一晶体管M11的第一沟道区和第十一晶体管M11的第一源极M11S1均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，参见图11，第十二晶体管M12的栅极M12G包括第一栅极M12G1和第二栅极M12G2，第十二晶体管M12的第二栅极M12G2和第十二晶体管M12的第一栅极M12G1均沿第一方向G延伸且沿第二方向H排列依次，两者的长度相同。第二亚有源区Act_sub2与第十二晶体管M12的第一栅极M12G1和第十二晶体管M12的第二栅极M12G2交叠的部分，作为第十二晶体管M12的沟道区。换言之，第十二晶体管M12的沟道区具有相互平行设置的第一沟道区和第二沟道区，第十二晶体管M12的第一沟道区与第十二晶体管M12的第一栅极M12G1交叠，第十二晶体管M12的第二沟道区与第十二晶体管M12的第二栅极M12G2交叠。第十二晶体管M12的漏极M12D位于第十二晶体管M12的第一沟道区和第十二晶体管M12的第二沟道区之间，第十二晶体管的源极M12S位于第十二晶体管M12的第一沟道区远离第十二晶体管M12的第二沟道区的一侧以及位于第十二晶体管M12的第二沟道区远离第十二晶体管M12的第一沟道区的一侧。换言之，第十二晶体管的源极M12S包括相互平行设置的第一源极M12S1和第二源极M12S2，第十二晶体管M12的第一源极M12S1位于第十二晶体管M12的第一沟道区远离第十二晶 体管M12的第二沟道区的一侧，第十二晶体管M12的第二源极M12S2位于第十二晶体管M12的第二沟道区远离第十二晶体管M12的第一沟道区的一侧。如此，第十二晶体管M12的第二源极M12S2、第十二晶体管M12的第二沟道区、第十二晶体管M12的漏极M12D、第十二晶体管M12的第一沟道区和第十二晶体管M12的第一源极M12S1均沿第一方向G延伸，且沿第二方向H依次排列。
在本公开的一种实施方式中，第十二晶体管M12的第一源极M12S1和第十一晶体管M11的第一源极M11S1在第一方向G上的延伸线重合，即第十二晶体管M12的第一源极M12S1和第十一晶体管M11的第一源极M11S1沿第一方向G直线排列。第十二晶体管M12的第二源极M12S2和第十一晶体管M11的第二源极M11S2在第一方向G上的延伸线重合，即第十二晶体管M12的第二源极M12S2和第十一晶体管M11的第二源极M11S2沿第一方向G直线排列。第十二晶体管M12的第一栅极M12G1和第十一晶体管M11的第一栅极M11G1在第一方向G上的延伸线重合，即第十二晶体管M12的第一栅极M12G1和第十一晶体管M11的第一栅极M11G1沿第一方向G直线排列。第十二晶体管M12的第二栅极M12G2和第十一晶体管M11的第二栅极M11G2在第一方向G上的延伸线重合，即第十二晶体管M12的第二栅极M12G2和第十一晶体管M11的第二栅极M11G2沿第一方向G直线排列。第十二晶体管M12的漏极M12D和第十一晶体管M11的漏极M11D在第一方向G上的延伸线重合，即第十二晶体管M12的漏极M12D和第十一晶体管M11的漏极M11D沿第一方向G直线排列。第十二晶体管M12的第一沟道区和第十一晶体管M11的第一沟道区在第一方向G上的延伸线重合，即第十二晶体管M12的第一沟道区和第十一晶体管M11的第一沟道区沿第一方向G直线排列。第十二晶体管M12的第二沟道区和第十一晶体管M11的第二沟道区在第一方向G上的延伸线重合，即第十二晶体管M12的第二沟道区和第十一晶体管M11的第二沟道区沿第一方向G直线排列。如此，第十二晶体管M12位于第十一晶体管M11第一方向G一侧。
在本公开的一种实施方式中，第九晶体管M9的第一源极M9S1、第九晶体管M9的第一栅极M9G1、第九晶体管M9的漏极M9D、第九晶体管M9的第二栅极M9G2和、第九晶体管M9的第二源极M9S2、第十一晶体管M11的第二源极M11S2、第十一晶体管M11的第二栅极M11G2、第十一晶体管M11的漏极M11D、第十一晶体管M11的第一栅极M11G1和第十一晶体管M11的第一源极M11S1沿第二方向H依次排列。如此，第十一晶体管M11位于第九晶体管M9的第二方向H一侧。进一步地，第九晶体管M9的第二源极M9S2和第十一晶体管M11的第二源极M11S2重合。如此，第九晶体管M9和第十一晶体管M11可以共用源极，进而简化行驱动信 号增强电路101的布线设置，提高行驱动信号增强电路101的紧凑性，降低行驱动信号增强电路101所占用的面积。
在本公开的一种实施方式中，第十晶体管M10的第一源极M10S1、第十晶体管M10的第一栅极M10G1、第十晶体管M10的漏极M10D、第十晶体管M10的第二栅极M10G2、第十晶体管M10的第二源极M10S2、第十二晶体管M12的第二源极M12S2、第十二晶体管M12的第二栅极M12G2、第十二晶体管M12的漏极M12D、第十二晶体管M12的第一栅极M12G1和第十二晶体管M12的第一源极M12S1沿第二方向H依次排列。如此，第十二晶体管M12位于第十晶体管M10的第二方向H一侧。进一步地，第十晶体管M10的第二源极M10S2和第十二晶体管M12的第二源极M12S2重合。如此，第十二晶体管M12和第十晶体管M10可以共用源极，进而简化行驱动信号增强电路101的布线设置，提高行驱动信号增强电路101的紧凑性，降低行驱动信号增强电路101所占用的面积。
可选地，参见图23，绝缘介质层340包括依次层叠于栅极层330的第一电介质层341、第二电介质层342和第三电介质层343，金属布线层360包括位于第一电介质层341和第二电介质层342之间的第一金属布线层361、位于第二电介质层342和第三电介质层343之间的第二金属布线层362和位于第三电介质层343远离半导体衬底310的表面的第三金属布线层363。
导电柱包括贯穿第一电介质层341的第一导电柱351、贯穿第二电介质层342的第二导电柱352和贯穿第三电介质层343的第三导电柱353；第一金属布线层361通过第一导电柱351与半导体衬底310和栅极层330连接；第二金属布线层362通过第二导电柱352与第一金属布线层361连接；第三金属布线层363通过第三导电柱353与第二金属布线层362连接。
可选地，参见图23，各个导电柱沿垂直于半导体衬底310的方向贯穿对应的电介质层。示例性地，第一导电柱351沿垂直于半导体衬底310的方向贯穿第一电介质层341，以与半导体衬底310或者栅极层330连接。
在本公开的一种实施方式中，第一导电柱351在半导体衬底310上的正投影与第二导电柱352在半导体衬底310上的正投影不交叠；第二导电柱352在半导体衬底310上的正投影与第三导电柱353在半导体衬底310上的正投影不交叠。
可选地，各个导电柱可以为金属柱，例如可以为钨柱。
可选地，参见图13，第一金属布线层361包括部分连接引线。位于第一金属布线层361的连接引线包括第一连接引线L01至第六连接引线第六连接引线L06，还包括第一晶体管M1至第十四晶体管M14各自对应的栅极连接线、源极连接线和漏极连接线。参见图12～图14，任意一个晶体管对应的栅极连接线与晶体管的栅极通过第一导电柱351连接；任意一个晶体管对应的源极连接线与晶体管的源极通过第一导电柱351 连接；任意一个晶体管对应的漏极连接线与晶体管的漏极通过第一导电柱351连接。
第九晶体管M9对应的源极连接线和第十一晶体管M11对应的源极连接线与第一连接引线L01连接。第十晶体管M10对应的源极连接线包括第一亚连接线M10SL1和第二亚连接线M10SL2；第十二晶体管M12对应的源极连接线包括第一亚连接线M12SL1和第二亚连接线M12SL2。第十晶体管M10对应的源极连接线的第一亚连接线M10SL1、第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1、第五晶体管M5对应的源极连接线M5SL、第四晶体管M4对应的源极连接线M4SL与第二连接引线L02连接。
第三晶体管M3对应的漏极连接线M3DL、第四晶体管M4对应的漏极连接线M4DL、第五晶体管M5对应的栅极连接线M5GL、第六晶体管M6对应的栅极连接线M6GL与第三连接引线L03连接。
第五晶体管M5对应的漏极连接线M5DL、第六晶体管M6对应的漏极连接线M6DL、第三晶体管M3对应的栅极连接线M3GL、第四晶体管M4对应的栅极连接线M4GL与第四连接引线L04连接。
第八晶体管M8对应的源极连接线包括第一亚连接线M8SL1和第二亚连接线M8SL2；第十四晶体管M14对应的源极连接线包括第一亚连接线M14SL1和第二亚连接线M14SL2。第八晶体管M8对应的源极连接线的第一亚连接线M8SL1、第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1、第七晶体管M7对应的源极连接线、第十三晶体管M13对应的源极连接线、第一晶体管M1对应的源极连接线、第二晶体管M2对应的源极连接线与第五连接引线L05连接。
第三晶体管M3对应的源极连接线M3SL、第六晶体管M6对应的源极连接线M6SL与第六连接引线第六连接引线L06连接。
参见图17，第二金属布线层362包括第一控制引线421、第二控制引线422、第一输出引线431、第二输出引线432和部分连接引线；位于第二金属布线层362的连接引线包括第七连接引线L07至第十五连接引线L15。参见图15～图18，第二金属布线层362通过第二导电柱352与第一金属布线层361连接。
其中，第一连接引线L01、第二连接引线L02与第七连接引线L07连接，且第一连接引线L01、第二连接引线L02与第八连接引线L08连接。第五连接引线L05与第九连接引线L09、第十连接引线L10连接。
第九晶体管M9对应的栅极连接线M9GL、第十晶体管M10对应的栅极连接线M10GL、第五晶体管M5对应的漏极连接线M5DL、第六晶体管M6对应的漏极连接线M6DL、第七晶体管M7对应的栅极连接线M7GL、第八晶体管M8对应的栅极连接线M8GL、第一晶体管M1对应的漏极连接线M1DL与第十一连接引线L11连接。
第十一晶体管M11对应的栅极连接线M11GL、第十二晶体管M12对应的栅极连接线M12GL、第三晶体管M3对应的漏极连接线M3DL、第四晶体管M4对应的漏极 连接线M4DL、第十三晶体管M13对应的栅极连接线M13GL、第十四晶体管M14对应的栅极连接线M14GL、第二晶体管M2对应的漏极连接线M2DL与第十二连接引线L12连接。
第一连接引线L01、第九晶体管M9对应的源极连接线的第二亚连接线M9SL2、第十晶体管M10对应的源极连接线的第二亚连接线M10SL2、第十一晶体管M11对应的源极连接线的第二亚连接线M11SL2、第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2、第六连接引线第六连接引线L06、第二连接引线L02与第十三连接引线L13连接。
第七晶体管M7对应的源极连接线的第二亚连接线M7SL2、第八晶体管M8对应的源极连接线的第二亚连接线M8SL2、第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2、第十四晶体管M14对应的源极连接线的第二亚连接线M14SL2、第五连接引线L05与第十四连接引线L14连接。
第一晶体管M1对应的源极连接线的第二亚连接线M1SL2、第二晶体管M2对应的源极连接线的第二亚连接线M2SL2、第五连接引线L05与第十五连接引线L15连接。
第七晶体管M7对应的漏极连接线M7DL、第八晶体管M8对应的漏极连接线M8DL、第九晶体管M9对应的漏极连接线M9DL、第十晶体管M10对应的漏极连接线M10DL与第一输出引线431连接。第十一晶体管M11对应的漏极连接线M11DL、第十二晶体管M12对应的漏极连接线M12DL、第十三晶体管M13对应的漏极连接线M13DL、第十四晶体管M14对应的漏极连接线M14DL与第二输出引线432连接。
参见图20，第三金属布线层363包括用于加载第一电压的第一电压引线411，以及包括线用于加载第二电源电压V2的第二电源引线412。参见图19～图22，第九连接引线L09、第十连接引线L10、第十四连接引线L14、第十五连接引线L15与第一电源引线411通过第三导电柱连接；第七连接引线L07、第八连接引线L08、第十三连接引线L13与第二电源引线412通过第三导电柱连接。
如此，本公开的显示面板中，金属布线层360在行驱动信号增强区F将各个晶体管电连接，进而使得显示面板在行驱动信号增强区F形成行驱动信号增强电路101。
在本公开的一种实施方式中，参见图11，第七晶体管M7的第二源极M7S2和第十三晶体管M13的第二源极M13S2重合。参见图13，第七晶体管M7对应的源极连接线的第二亚连接线M7SL2与第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2重合，为同一引线。
在本公开的一种实施方式中，参见图11，第八晶体管M8的第二源极M8S2和第十四晶体管M14的第二源极M14S2重合。参见图13，第八晶体管M8对应的源极连接线的第二亚连接线M8SL2与第十四晶体管M14对应的源极连接线的第二亚连接线M14SL2重合，为同一引线。
在本公开的一种实施方式中，参见图11，第九晶体管M9的第二源极M9S2和第十一晶体管M11的第二源极M11S2重合。参见图13，第九晶体管M9对应的源极连接线的第二亚连接线M9SL2与第十一晶体管M11对应的源极连接线的第二亚连接线M11SL2重合，为同一引线。
在本公开的一种实施方式中，参见图11，第十晶体管M10的第二源极M10S2和第十二晶体管M12的第二源极M12S2重合。参见图13，第十晶体管M10对应的源极连接线的第二亚连接线M10SL2与第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2重合，为同一引线。
在本公开的一种实施方式中，参见图11，第五晶体管M5的漏极M5D和第六晶体管M6的漏极M6D重合。参见图13，第五晶体管M5对应的漏极连接线M5DL与第六晶体管M6对应的漏极连接线M6DL重合，为同一引线。
在本公开的一种实施方式中，参见图11，第三晶体管M3的漏极M3D和第四晶体管M4的漏极M4D重合。参见图13，第三晶体管M3对应的漏极连接线M3DL与第四晶体管M4对应的漏极连接线M4DL重合，为同一引线。
可选地，第一晶体管M1至第十四晶体管M14中，任意一个晶体管对应的源极连接线与该晶体管的源极交叠，且两者的延伸方向一致。在本公开的一种实施方式中，第一晶体管M1至第十四晶体管M14中，任意一个晶体管对应的源极连接线的延伸方向为第一方向G。进一步可选地，对于任意一个晶体管，该晶体管对应的源极连接引线与该晶体管的源极之间，通过沿第一方向G依次排列的多个第一导电柱351连接。
可选地，第一晶体管M1至第十四晶体管M14中，任意一个晶体管对应的漏极连接线与该晶体管的漏极交叠，且两者的延伸方向一致。在本公开的一种实施方式中，第一晶体管M1至第十四晶体管M14中，任意一个晶体管对应的漏极连接线的延伸方向为第一方向G。进一步可选地，对于任意一个晶体管，该晶体管对应的漏极连接引线与该晶体管的漏极之间，通过沿第一方向G排列的两个第一导电柱351连接。
可选地，各个晶体管对应的漏极连接线和漏极连接线的宽度相同。
可选地，第一晶体管M1至第十四晶体管M14中，任意一个晶体管的栅极沿第一方向G延伸；任意一个晶体管对应的栅极连接线沿第二方向H延伸，且与该晶体管的栅极的末端通过第一导电柱351电连接。进一步地，任意一个晶体管对应的栅极连接线与有源区之间不交叠。
可选地，各个晶体管对应的漏极连接线和栅极连接线的宽度相同。
示例性地，参见图13，第一晶体管M1对应的栅极连接线M1GL位于第七亚有源区Act_sub7的第一方向G一侧且沿第二方向H延伸，且与第一晶体管M1的第一栅极M1G1、第一晶体管M1的第二栅极M1G2的第一方向G一侧的端部连接。
第二晶体管M2对应的栅极连接线M2GL位于第八亚有源区Act_sub8的第一方向 G一侧且沿第二方向H延伸，且与第二晶体管M2的第一栅极M2G1、第二晶体管M2的第二栅极M2G2的第一方向G一侧的端部连接。
第三晶体管M3对应的栅极连接线M3GL位于第四亚有源区Act_sub4的第一方向G一侧且沿第二方向H延伸，且与第三晶体管M3的栅极M3G的第一方向G一侧的端部连接。
第四晶体管M4对应的栅极连接线M4GL位于第四亚有源区Act_sub4的第一方向G一侧且沿第二方向H延伸，且与第四晶体管M4的栅极M4G的第一方向G一侧的端部连接。
第五晶体管M5对应的栅极连接线M5GL位于第三亚有源区Act_sub3的第一方向G的相反方向一侧且沿第二方向H延伸，且与第五晶体管M5的栅极M5G的第一方向G的相反方向一侧的端部连接。
第六晶体管M6对应的栅极连接线M6GL位于第三亚有源区Act_sub3的第一方向G的相反方向一侧且沿第二方向H延伸，且与第六晶体管M6的栅极M6G的第一方向G的相反方向一侧的端部连接。
第七晶体管M7对应的栅极连接线M7GL位于第五亚有源区Act_sub5的第一方向G一侧且沿第二方向H延伸，且与第七晶体管M7的第一栅极M7G1、第七晶体管M7的第二栅极M7G2的第一方向G一侧的端部连接。
第八晶体管M8对应的栅极连接线M8GL位于第六亚有源区Act_sub6的第一方向G一侧且沿第二方向H延伸，且与第八晶体管M8的第一栅极M8G1、第八晶体管M8的第二栅极M8G2的第一方向G一侧的端部连接。
第九晶体管M9对应的栅极连接线M9GL位于第一亚有源区Act_sub1的第一方向G一侧且沿第二方向H延伸，且与第九晶体管M9的第一栅极M9G1、第九晶体管M9的第二栅极M9G2的第一方向G一侧的端部连接。
第十晶体管M10对应的栅极连接线M10GL位于第二亚有源区Act_sub2的第一方向G一侧且沿第二方向H延伸，且与第十晶体管M10的第一栅极M10G1、第十晶体管M10的第二栅极M10G2的第一方向G一侧的端部连接。
第十一晶体管M11对应的栅极连接线M11GL位于第一亚有源区Act_sub1的第一方向G一侧且沿第二方向H延伸，且与第十一晶体管M11的第一栅极M11G1、第十一晶体管M11的第二栅极M11G2的第一方向G一侧的端部连接。
第十二晶体管M12对应的栅极连接线M12GL位于第二亚有源区Act_sub2的第一方向G一侧且沿第二方向H延伸，且与第十二晶体管M12的第一栅极M12G1、第十二晶体管M12的第二栅极M12G2的第一方向G一侧的端部连接。
第十三晶体管M13对应的栅极连接线M13GL位于第五亚有源区Act_sub5的第一方向G一侧且沿第二方向H延伸，且与第十三晶体管M13的第一栅极M13G1、第十三晶体管M13的第二栅极M13G2的第一方向G一侧的端部连接。
第十四晶体管M14对应的栅极连接线M14GL位于第六亚有源区Act_sub6的第一方向G一侧且沿第二方向H延伸，且与第十四晶体管M14的第一栅极M14G1、第十四晶体管M14的第二栅极M14G2的第一方向G一侧的端部连接。
在本公开的一种实施方式中，参见图13，第三晶体管M3对应的栅极连接线M3GL和第四晶体管M4对应的栅极连接线M4GL重合，为同一引线。第五晶体管M5对应的漏极连接线M5DL和第六晶体管M6对应的漏极连接线M6DL重合，为同一引线。进一步地，第四连接引线L04沿第二方向H延伸且与第三晶体管M3对应的栅极连接线M3GL/第四晶体管M4对应的栅极连接线M4GL的延伸方向一致，并与第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL的第一方向G的端部连接。如此，第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL、第四连接引线L04、第三晶体管M3对应的栅极连接线M3GL/第四晶体管M4对应的栅极连接线M4GL呈沿第一方向G和第二方向H设置的L型引线。示例性地，沿第一方向G，第三晶体管M3对应的栅极连接线M3GL/第四晶体管M4对应的栅极连接线M4GL、第四连接引线L04位于第六N型掺杂亚区F_Nsub6与第三亚有源区Act_sub3、第四亚有源区Act_sub4之间，且沿第二方向H延伸。第四连接引线L04的第二方向H一端与第三晶体管M3对应的栅极连接线M3GL/第四晶体管M4对应的栅极连接线M4GL连接，第四连接引线L04的第二方向H的相反方向一端与第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL连接。
在本公开的一种实施方式中，参见图13，第五晶体管M5对应的栅极连接线M5GL和第六晶体管M6对应的栅极连接线M6GL重合，为同一引线。第三晶体管M3对应的漏极连接线M3DL和第四晶体管M4对应的漏极连接线M4DL重合，为同一引线。进一步地，第三连接引线L03沿第二方向H延伸且与第五晶体管M5对应的栅极连接线M5GL的延伸方向一致，并与第三晶体管M3对应的漏极连接线M3DL的第一方向G的相反方向一侧的端部连接。如此，第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL、第三连接引线L03、第五晶体管M5对应的栅极连接线M5GL/第六晶体管M6对应的栅极连接线M6GL呈沿第一方向G和第二方向H设置的L型引线。示例性地，沿第一方向G，第五晶体管M5对应的栅极连接线M5GL/第六晶体管M6对应的栅极连接线M6GL、第三连接引线L03位于第四N型掺杂亚区F_Nsub4与第三亚有源区Act_sub3、第四亚有源区Act_sub4之间，且沿第二方向H延伸。第三连接引线L03的第二方向H一端与第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL连接，第三连接引线L03的第二方向H的相反方向一端与第五晶体管M5对应的栅极连接线M5GL/第六晶体管M6对应的栅极连接线M6GL连接。
在本公开的一种实施方式中，第九晶体管M9对应的栅极连接线M9GL、第十晶 体管M10对应的栅极连接线M10GL、第七晶体管M7对应的栅极连接线M7GL的第二方向H的相反方向一端均设置有沿第一方向G延伸的转接线；第九晶体管M9对应的栅极连接线M9GL的转接线、第十晶体管M10对应的栅极连接线M10GL的转接线、第七晶体管M7对应的栅极连接线M7GL的转接线、第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL、第一晶体管M1对应的漏极连接线M1DL沿第一方向G直线设置；第十一连接引线L11沿第一方向G直线设置，且与第九晶体管M9对应的栅极连接线M9GL的转接线、第十晶体管M10对应的栅极连接线M10GL的转接线、第七晶体管M7对应的栅极连接线M7GL的转接线、第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL、第一晶体管M1对应的漏极连接线M1DL交叠。其中，第十一连接引线L11通过第二导电柱352分别与第九晶体管M9对应的栅极连接线M9GL的转接线、第十晶体管M10对应的栅极连接线M10GL的转接线、第七晶体管M7对应的栅极连接线M7GL的转接线、第八晶体管M8对应的栅极连接线M8GL、第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL、第一晶体管M1对应的漏极连接线M1DL连接。可选地，第十一连接引线L11还可以设置有朝第二方向H延伸的转接线；第十一连接引线L11的转接线与第八晶体管M8对应的栅极连接线M8GL交叠，并通过第二导电柱352与第八晶体管M8对应的栅极连接线M8GL连接。如此，第八晶体管M8对应的栅极连接线M8GL无需设置转接线，能够避免第八晶体管M8对应的栅极连接线M8GL的转接线在第一方向G上占用空间，减少本公开的行驱动信号增强电路101的面积。
在本公开的一种实施方式中，第十一晶体管M11对应的栅极连接线M11GL、第十二晶体管M12对应的栅极连接线M12GL、第十三晶体管M13对应的栅极连接线M13GL的第二方向H一端均设置有沿第一方向G延伸的转接线，且第十一晶体管M11对应的栅极连接线M11GL的转接线、第十二晶体管M12对应的栅极连接线M12GL的转接线、第十三晶体管M13对应的栅极连接线M13GL的转接线、第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL、第二晶体管M2对应的漏极连接线M2DL沿第一方向G直线设置。第十二连接引线L12沿第一方向G直线设置，且与第十一晶体管M11对应的栅极连接线M11GL的转接线、第十二晶体管M12对应的栅极连接线M12GL的转接线、第十三晶体管M13对应的栅极连接线M13GL的转接线、第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL、第二晶体管M2对应的漏极连接线M2DL交叠。其中，第十二连接引线L12通过第二导电柱352分别与第十一晶体管M11对应的栅极连接线M11GL的转接线、第十二晶体管M12对应的栅极连接线M12GL的转接线、第十三晶体管M13对应的栅极连接线M13GL的转接线、第十四晶体管M14对应的栅极连接线M14GL、第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL、 第二晶体管M2对应的漏极连接线M2DL连接。可选地，第十二连接引线L12还可以设置有朝第二方向H的相反方向延伸的转接线；第十二连接引线L12的转接线与第十四晶体管M14对应的栅极连接线M14GL交叠，并通过第二导电柱352与第十四晶体管M14对应的栅极连接线M14GL连接。如此，第十四晶体管M14对应的栅极连接线M14GL无需设置转接线，能够避免第十四晶体管M14对应的栅极连接线M14GL的转接线在第一方向G上占用空间，减少本公开的行驱动信号增强电路101的面积。
在一些实施方式中，参见图13，第一连接引线L01包括依次连接的第一亚引线L011、第二亚引线L012和第三亚引线L013；第一连接引线L01的第一亚引线L011、第一连接引线L01的第三亚引线L013沿第一方向G延伸且与N型辅助掺杂区F_Ndummy至少部分交叠；第一连接引线L01的第二亚引线L012沿第二方向H延伸且与N型辅助掺杂区F_Ndummy至少部分交叠；第一亚有源区Act_sub1位于第一连接引线L01所环绕而成的半开放空间内。
示例性地，第一连接引线L01位于第二连接引线L02的第一方向G的相反方向一侧。其中，第一连接引线L01的第一亚引线L011的延伸方向与第一N型掺杂亚区F_Nsub1的延伸方向一致，均为第一方向G且两者至少部分交叠。第一连接引线L01的第二亚引线L012的延伸方向与第二N型掺杂亚区F_Nsub2的延伸方向一致，均为第二方向H且两者至少部分交叠。第一连接引线L01的第三亚引线L013的延伸方向与第三N型掺杂亚区F_Nsub3的延伸方向一致，均为第二方向H且两者至少部分交叠。如此，第一连接引线L01形成一个具有朝向第一方向G的开口的凵字形结构，第一亚有源区Act_sub1位于该凵字形结构所环绕的空间内。
在本公开的一种实施方式中，第一连接引线L01的第一亚引线L011、第一连接引线L01的第二亚引线L012和第一连接引线L01的第三亚引线L013均与N型辅助掺杂区F_Ndummy连接。具体的，第一连接引线L01的第一亚引线L011通过沿第一方向G依次排列的多个第一导电柱351与第一N型掺杂亚区F_Nsub1连接；第一连接引线L01的第二亚引线L012通过沿第二方向H依次排列的多个第一导电柱351与第二N型掺杂亚区F_Nsub2连接；第一连接引线L01的第三亚引线L013通过沿第一方向G依次排列的多个第一导电柱351与第三N型掺杂亚区F_Nsub3连接。可选地，第一连接引线L01的第一亚引线L011通过两行第一导电柱351与第一N型掺杂亚区F_Nsub1连接，每行第一导电柱351包括沿第一方向G依次设置的多个第一导电柱351。可选地，第一连接引线L01的第三亚引线L013通过两行第一导电柱351与第三N型掺杂亚区F_Nsub3连接，每行第一导电柱351包括沿第一方向G依次设置的多个第一导电柱351。
如此，加载于第一连接引线L01上的第二电源电压V2能够均匀地加载至与第一连接引线L01交叠的N型辅助掺杂区F_Ndummy，进而减少第九晶体管M9和第十一晶体管M11的漏电。更进一步地的，第一连接引线L01的第一亚引线L011在半导体 衬底310上的正投影，位于第一N型掺杂亚区F_Nsub1的范围内；第一连接引线L01的第二亚引线L012在半导体衬底310上的正投影，位于第二N型掺杂亚区F_Nsub2的范围内；第一连接引线L01的第三亚引线L013在半导体衬底310上的正投影，位于第三N型掺杂亚区F_Nsub3的范围内。
在本公开的一种实施方式中，参见图13，第一连接引线L01的第一亚引线L011与第九晶体管M9对应的源极连接线的第一亚连接线M9SL1均沿第一方向G延伸；第一连接引线L01的第一亚引线L011的局部位置还可以沿第二方向H延伸以形成一凸出部，第一连接引线L01的第一亚引线L011的凸出部沿第二方向H延伸至与第九晶体管M9对应的源极连接线的第一亚连接线M9SL1连接，以使得第九晶体管M9对应的源极连接线的第一亚连接线M9SL1的第二方向H的相反方向的侧边与第一连接引线L01的第一亚引线L011连接。进一步地，第一连接引线L01的第一亚引线
L011的凸出部的第一方向G的一端与第九晶体管M9对应的源极连接线的第一亚连接线M9SL1的第一方向G一端齐平，第一连接引线L01的第一亚引线L011的凸出部的第一方向G的相反方向的一端与第九晶体管M9对应的源极连接线的第一亚连接线M9SL1的第一方向G的相反方向的一端齐平。如此，第一连接引线L01的第一亚引线L011的凸出部在第一方向G上的长度与第九晶体管M9对应的源极连接线的第一亚连接线M9SL1在第一方向G上的长度相同。该第一连接引线L01的第一亚引线L011的凸出部的设置，可以使得第九晶体管M9的第一源极M9S1LN与第一连接引线L01的第一亚引线L011为一体结构。
在本公开的一种实施方式中，参见图13，第一连接引线L01的第三亚引线L013与第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1均沿第一方向G延伸；第一连接引线L01的第三亚引线L013的局部位置还可以沿第二方向H的相反方向延伸以形成一凸出部，第一连接引线L01的第三亚引线L013的凸出部沿第二方向H的相反方向延伸至与第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1连接，以使得第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1的第二方向H的侧边与第一连接引线L01的第三亚引线L013连接。进一步地，第一连接引线L01的第三亚引线L013的凸出部的第一方向G的一端与第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1的第一方向G一端齐平，第一连接引线L01的第三亚引线L013的凸出部的第一方向G的相反方向的一端与第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1的第一方向G的相反方向的一端齐平。如此，第一连接引线L01的第三亚引线L013的凸出部在第一方向G上的长度与第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1在第一方向G上的长度相 同。该第一连接引线L01的第三亚引线L013的凸出部的设置，可以使得第十一晶体管M11的第一源极M11S1LN与第一连接引线L01的第三亚引线L013为一体结构。
可选地，参见图13，第二连接引线L02包括依次连接的第一亚引线L021、第二亚引线L022和第四亚引线L024，以及包括第三亚引线L023。其中，第二连接引线L02的第一亚引线L021、第二连接引线L02的第四亚引线L024均沿第一方向G延伸，且与P型辅助掺杂区F_Pdummy至少部分交叠；第二连接引线L02的第二亚引线L022、第二连接引线L02的第三亚引线L023均沿第二方向H延伸，且与P型辅助掺杂区F_Pdummy至少部分交叠；第二亚有源区Act_sub2位于第二连接引线L02的第一亚引线L021、第二连接引线L02的第二亚引线L022和第二连接引线L02的第四亚引线L024所环绕的空间内，第二有源层Act2位于第二连接引线L02的第一亚引线L021、所第二连接引线L02的第二亚引线L022、第二连接引线L02的第三亚引线L023和第二连接引线L02的第四亚引线L024所环绕的空间内。
示例性地，参见图13，第二连接引线L02位于第一连接引线L01的第一方向G一侧。其中，第二连接引线L02的第一亚引线L021与第一连接引线L01的第一亚引线L011的延伸方向一致且与第一连接引线L01的第一亚引线L011不连续。第二连接引线L02的第一亚引线L021靠近第一方向G的相反方向一端的部分，可以与第一N型掺杂亚区F_Nsub1至少部分交叠；第二连接引线L02的第一亚引线L021靠近第一方向G一端的部分，可以与第五N型掺杂亚区F_Nsub5至少部分交叠。第二连接引线L02的第一亚引线L021与第五N型掺杂亚区F_Nsub5交叠的部分在第二方向H上的尺寸，可以小于第二连接引线L02的第一亚引线L021与第一N型掺杂亚区F_Nsub1交叠的部分在第二方向H上的尺寸。
第二连接引线L02的第四亚引线L024与第一连接引线L01的第三亚引线L013的延伸方向一致且与第一连接引线L01的第三亚引线L013不连续。第二连接引线L02的第四亚引线L024靠近第一方向G的相反方向一端的部分，可以与第三N型掺杂亚区F_Nsub3至少部分交叠；第二连接引线L02的第四亚引线L024靠近第一方向G一端的部分，可以与第七N型掺杂亚区F_Nsub7至少部分交叠。第二连接引线L02的第四亚引线L024与第七N型掺杂亚区F_Nsub7交叠的部分在第二方向H上的尺寸，可以小于第二连接引线L02的第四亚引线L024与第三N型掺杂亚区F_Nsub3交叠的部分在第二方向H上的尺寸。
第二连接引线L02的第二亚引线L022沿第二方向H延伸，且两端分别与第二连接引线L02的第一亚引线L021、第二连接引线L02的第四亚引线L024连接。第二连接引线L02的第一亚引线L021与第一N型掺杂亚区F_Nsub1交叠的部分，以及第二连接引线L02的第四亚引线L024与第三N型掺杂亚区F_Nsub3交叠的部分，均位于第二连接引线L02的第二亚引线L022的第一方向G的相反方向一侧；第二连接引线L02的第一亚引线L021与第五N型掺杂亚区F_Nsub5交叠的部分，以及第二连接引 线L02的第四亚引线L024与第七N型掺杂亚区F_Nsub7交叠的部分，均位于第二连接引线L02的第二亚引线L022的第一方向G一侧。其中，第二连接引线L02的第二亚引线L022与第四N型掺杂亚区F_Nsub4至少部分交叠。
第二连接引线L02的第三亚引线L023沿第二方向H延伸，且两端分别与第二连接引线L02的第一亚引线L021、第二连接引线L02的第四亚引线L024连接。其中，第二连接引线L02的第一亚引线L021、第二连接引线L02的第四亚引线L024和第二连接引线L02的第二亚引线L022均位于第二连接引线L02的第三亚引线L023的第一方向G的相反方向一侧。第二连接引线L02的第三亚引线L023可以与第六N型掺杂亚区F_Nsub6至少部分交叠。
参见图13，第二连接引线L02的第一亚引线L021、第二连接引线L02的第二亚引线L022和第二连接引线L02的第四亚引线L024围绕出一个开口朝向第一方向G的相反方向的空间，第二亚有源区Act_sub2可以位于该空间内。第二连接引线L02的第一亚引线L021、第二连接引线L02的第二亚引线L022、第二连接引线L02的第四亚引线L024和第二连接引线L02的第三亚引线L023围绕出一个封闭空间，第二有源区Act2可以位于该封闭空间内。
在本公开的一种实施方式中，第二连接引线L02的第一亚引线L021、第二连接引线L02的第二亚引线L022、第二连接引线L02的第三亚引线L023和第二连接引线L02的第四亚引线L024均与N型辅助掺杂区F_Ndummy连接。参见图12～图14，第二连接引线L02的第一亚引线L021通过沿第一方向G依次排列的多个第一导电柱351与第一N型掺杂亚区F_Nsub1和第五N型掺杂亚区F_Nsub5连接，第二连接引线L02的第二亚引线L022通过沿第二方向H依次排列的多个第一导电柱351与第四N型掺杂亚区F_Nsub4连接，第二连接引线L02的第三亚引线L023通过沿第二方向H依次排列的多个第一导电柱351与第六N型掺杂亚区F_Nsub6连接，第二连接引线L02的第四亚引线L024通过沿第一方向G依次排列的多个第一导电柱351与第三N型掺杂亚区F_Nsub3和第七N型掺杂亚区F_Nsub7连接。可选地，第二连接引线L02的第一亚引线L021通过两行第一导电柱351与第一N型掺杂亚区F_Nsub1连接，每行第一导电柱351包括沿第一方向G依次设置的多个第一导电柱351。可选地，第二连接引线L02的第四亚引线L024通过两行第一导电柱351与第三N型掺杂亚区F_Nsub3连接，每行第一导电柱351包括沿第一方向G依次设置的多个第一导电柱351。如此，加载于第二连接引线L02上的第二电源电压V2能够均匀地加载与第三连接引线L03交叠的N型辅助掺杂区F_Ndummy，进而减少第十晶体管M10、第十二晶体管M12、第四晶体管M4、第五晶体管M5的漏电。
在本公开的一种实施方式中，参见图13，第二连接引线L02的第一亚引线L021与第十晶体管M10对应的源极连接线的第一亚连接线M10SL1均沿第一方向G延伸； 第二连接引线L02的第一亚引线L021的局部位置还可以沿第二方向H延伸以形成一第一凸出部，第二连接引线L02的第一亚引线L021的第一凸出部沿第二方向H延伸至与第十晶体管M10对应的源极连接线的第一亚连接线M10SL1连接，以使得第十晶体管M10对应的源极连接线的第一亚连接线M10SL1的第二方向H的相反方向的侧边与第二连接引线L02的第一亚引线L021连接。进一步地，第二连接引线L02的第一亚引线L021的第一凸出部的第一方向G的一端与第十晶体管M10对应的源极连接线的第一亚连接线M10SL1的第一方向G一端齐平，第二连接引线L02的第一亚引线L021的第一凸出部的第一方向G的相反方向的一端与第十晶体管M10对应的源极连接线的第一亚连接线M10SL1的第一方向G的相反方向的一端齐平。如此，第二连接引线L02的第一亚引线L021的第一凸出部在第一方向G上的长度与第十晶体管M10对应的源极连接线的第一亚连接线M10SL1在第一方向G上的长度相同。该第二连接引线L02的第一亚引线L021的第一凸出部的设置，可以使得第十晶体管M10的第一源极M10S1LN与第二连接引线L02的第一亚引线L021为一体结构。
在本公开的一种实施方式中，参见图13，第二连接引线L02的第四亚引线L024与第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1均沿第一方向G延伸；第二连接引线L02的第四亚引线L024的局部位置还可以沿第二方向H的相反方向延伸以形成一第一凸出部，第二连接引线L02的第四亚引线L024的第一凸出部沿第二方向H的相反方向延伸至与第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1连接，以使得第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1的第二方向H的侧边与第二连接引线L02的第四亚引线L024连接。进一步地，第二连接引线L02的第四亚引线L024的第一凸出部的第一方向G的一端与第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1的第一方向G一端齐平，第二连接引线L02的第四亚引线L024的第一凸出部的第一方向G的相反方向的一端与第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1的第一方向G的相反方向的一端齐平。如此，第二连接引线L02的第四亚引线L024的第一凸出部在第一方向G上的长度与第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1在第一方向G上的长度相同。该第二连接引线L02的第四亚引线L024的第一凸出部的设置，可以使得第十二晶体管M12的第一源极M12S1LN与第二连接引线L02的第四亚引线L024为一体结构。
在一些实施方式中，参见图13，第三连接引线L03、第四连接引线L04、第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL、第三晶体管M3对应的栅极连接线M3GL/第四晶体管M4对应的栅极连接线M4GL、第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL、第五晶 体管M5对应的栅极连接线M5GL/第六晶体管M6对应的栅极连接线M6GL、第六连接引线L06、第五晶体管M5对应的源极连接线M5SL、第六晶体管M6对应的源极连接线M6SL、第三晶体管M3对应的源极连接线M3SL和第四晶体管M4对应的源极连接线M4SL均位于第二连接引线L02的第一亚引线L021、第二连接引线L02的第二亚引线L022、第二连接引线L02的第四亚引线L024和第二连接引线L02的第三亚引线L023围绕出的封闭空间内。
可选地，第三连接引线L03、第四连接引线L04的宽度与各个晶体管对应的漏极连接线的宽度相同。
在本公开的一种实施方式中，参见图13，第二连接引线L02的第一亚引线L021与第五晶体管M5对应的源极连接线M5SL均沿第一方向G延伸；第二连接引线L02的第一亚引线L021的局部位置还可以沿第二方向H延伸以形成一第二凸出部，第二连接引线L02的第一亚引线L021的第二凸出部沿第二方向H延伸至与第五晶体管M5对应的源极连接线M5SL连接，以使得第五晶体管M5对应的源极连接线M5SL的第二方向H的相反方向的侧边与第二连接引线L02的第一亚引线L021连接。进一步地，第二连接引线L02的第一亚引线L021的第二凸出部的第一方向G的一端与第五晶体管M5对应的源极连接线M5SL的第一方向G一端齐平，第二连接引线L02的第一亚引线L021的第二凸出部的第一方向G的相反方向的一端与第五晶体管M5对应的源极连接线M5SL的第一方向G的相反方向的一端齐平。如此，第二连接引线L02的第一亚引线L021的第二凸出部在第一方向G上的长度与第五晶体管M5对应的源极连接线M5SL在第一方向G上的长度相同。该第二连接引线L02的第一亚引线L021的第二凸出部的设置，可以使得第五晶体管M5对应的源极连接线M5SL与第二连接引线L02的第一亚引线L021为一体结构。
在本公开的一种实施方式中，参见图13，第六连接引线L06与第六晶体管M6对应的源极连接线M6SL均沿第一方向G延伸；第六连接引线L06的至少局部位置还可以沿第二方向H的相反方向延伸以形成一第一凸出部，第六连接引线L06的第一凸出部沿第二方向H的相反方向延伸至与第六晶体管M6对应的源极连接线M6SL连接，以使得第六晶体管M6对应的源极连接线M6SL的第二方向H的侧边与第六连接引线L06连接。进一步地，第六连接引线L06的第一凸出部的第一方向G的一端与第六晶体管M6对应的源极连接线M6SL的第一方向G一端齐平，第六连接引线L06的第一凸出部的第一方向G的相反方向的一端与第六晶体管M6对应的源极连接线M6SL的第一方向G的相反方向的一端齐平。如此，第六连接引线L06的第一凸出部在第一方向G上的长度与第六晶体管M6对应的源极连接线M6SL在第一方向G上的长度相同。该第六连接引线L06的第一凸出部的设置，可以使得第六晶体管M6对应的源极连接 线M6SL与第六连接引线L06为一体结构。
在本公开的一种实施方式中，参见图13，第六连接引线L06与第三晶体管M3对应的源极连接线M3SL均沿第一方向G延伸；第六连接引线L06的至少局部位置还可以沿第二方向H延伸以形成一第二凸出部，第六连接引线L06的第二凸出部沿第二方向H延伸至与第三晶体管M3对应的源极连接线M3SL连接，以使得第三晶体管M3对应的源极连接线M3SL的第二方向H的相反方向的侧边与第六连接引线L06连接。进一步地，第六连接引线L06的第二凸出部的第一方向G的一端与第三晶体管M3对应的源极连接线M3SL的第一方向G一端齐平，第六连接引线L06的第二凸出部的第一方向G的相反方向的一端与第三晶体管M3对应的源极连接线M3SL的第一方向G的相反方向的一端齐平。如此，第六连接引线L06的第二凸出部在第一方向G上的长度与第三晶体管M3对应的源极连接线M3SL在第一方向G上的长度相同。该第六连接引线L06的第二凸出部的设置，可以使得第三晶体管M3对应的源极连接线M3SL与第六连接引线L06为一体结构。
可选地，第六连接引线L06的宽度大于各个晶体管对应的源极连接线的宽度。
可选地，参见图13，第六连接引线L06沿第一方向G的轴线，与第十晶体管M10对应的源极连接线的第二亚连接线M10SL2/第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2沿第一方向G的轴线重合。
在本公开的一种实施方式中，参见图13，第二连接引线L02的第四亚引线L024与第四晶体管M4对应的源极连接线M4SL均沿第一方向G延伸；第二连接引线L02的第四亚引线L024的局部位置还可以沿第二方向H的相反方向延伸以形成一第二凸出部，第二连接引线L02的第四亚引线L024的第二凸出部沿第二方向H的相反方向延伸至与第四晶体管M4对应的源极连接线M4SL连接，以使得第四晶体管M4对应的源极连接线M4SL的第二方向H的侧边与第二连接引线L02的第四亚引线L024连接。进一步地，第二连接引线L02的第四亚引线L024的第二凸出部的第一方向G的一端与第四晶体管M4对应的源极连接线M4SL的第一方向G一端齐平，第二连接引线L02的第四亚引线L024的第二凸出部的第一方向G的相反方向的一端与第四晶体管M4对应的源极连接线M4SL的第一方向G的相反方向的一端齐平。如此，第二连接引线L02的第四亚引线L024的第二凸出部在第一方向G上的长度与第四晶体管M4对应的源极连接线M4SL在第一方向G上的长度相同。该第二连接引线L02的第四亚引线L024的第二凸出部的设置，可以使得第四晶体管M4对应的源极连接线M4SL与第二连接引线L02的第四亚引线L024为一体结构。
在一些实施方式中，参见图15，第五连接引线L05包括依次连接的第一亚引线L051、第二亚引线L052、第三亚引线L053和第四亚引线L054，以及包括第五亚引 线L055和第六亚引线L056。
第五连接引线L05的第一亚引线L051、第五连接引线L05的第三亚引线L053、第五连接引线L05的第六亚引线L056均沿第一方向G延伸，且均与P型辅助掺杂区F_Pdummy至少部分交叠。
第五连接引线L05的第六亚引线L056位于第五连接引线L05的第一亚引线L051和第五连接引线L05的第三亚引线L053之间，且两端分别与第五连接引线L05的第五亚引线L055、第五连接引线L05的第四亚引线L054连接；第五连接引线L05的第二亚引线L052、第五连接引线L05的第四亚引线L054、第五连接引线L05的第五亚引线L055均沿第二方向H延伸，且均与P型辅助掺杂区F_Pdummy至少部分交叠。第五连接引线L05的第五亚引线L055位于第五连接引线L05的第二亚引线L052和第五连接引线L05的第四亚引线L054之间，且两端分别与第五连接引线L05的第一亚引线L051、第五连接引线L05的第三亚引线L053连接；第五连接引线L05的第一亚引线L051至第六亚引线L056均与P型辅助掺杂区F_Pdummy连接。第三有源区Act3位于第五连接引线L05的第一亚引线L051、第五连接引线L05的第一亚引线L052、第五连接引线L05的第三亚引线L053和第五连接引线L05的第五亚引线L055所环绕的空间内；第七亚有源区Act_sub7位于第五连接引线L05的第一亚引线L051、第五连接引线L05的第一亚引线L055、第五连接引线L05的第六亚引线L056和第五连接引线L05的第四亚引线L054所环绕的空间内；第八亚有源区Act_sub8位于第五连接引线L05的第六亚引线L056、第五连接引线L05的第一亚引线L055、第五连接引线L05的第三亚引线L053和第五连接引线L05的第四亚引线L054所环绕的空间内。
进一步地，参见图13，第七晶体管M7对应的栅极连接线M7GL、第十三晶体管M13对应的栅极连接线M13GL位于第五连接引线L05的第一亚引线L051、第五连接引线L05的第二亚引线L052、第五连接引线L05的第三亚引线L053和第五连接引线L05的第五亚引线L055所环绕的空间内，且位于第五亚有源区Act_sub5和第六亚有源区Act_sub6之间。第八晶体管M8对应的栅极连接线M8GL、第十四晶体管M14对应的栅极连接线M14GL位于第五连接引线L05的第一亚引线L051、第五连接引线L05的第二亚引线L052、第五连接引线L05的第三亚引线L053和第五连接引线L05的第五亚引线L055所环绕的空间内，且位于第六亚有源区Act_sub6与第五连接引线L05的第五亚引线L055之间。
进一步地，参见图13，第一晶体管M1对应的栅极连接线M1GL位于第五连接引线L05的第一亚引线L051、第五连接引线L05的第五亚引线L055、第五连接引线L05的第六亚引线L056和第五连接引线L05的第四亚引线L054所环绕的空间内，且位于第七亚有源区Act_sub7与第五连接引线L05的第四亚引线L054之间。第二晶体管M2对应的栅极连接线M2GL位于第五连接引线L05的第三亚引线L053、第五连接引线L05的第五亚引线L055、第五连接引线L05的第六亚引线L056和第五连接引线L05 的第四亚引线L054所环绕的空间内，且位于第八亚有源区Act_sub8与第五连接引线L05的第四亚引线L054之间。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第一亚引线L051沿第一方向G延伸且与第一P型掺杂亚区F_Psub1、第五P型掺杂亚区F_Psub5的延伸方向一致。第五连接引线L05的第一亚引线L051包括位于第一方向G一侧的第一部分和位于第一方向G的相反方向一侧的第二部分，第五连接引线L05的第一亚引线L051的第一部分与第五P型掺杂亚区F_Psub5之间交叠且通过沿第一方向G依次排列的多个第一导电柱351电连接；第五连接引线L05的第一亚引线L051的第二部分与第一P型掺杂亚区F_Psub1之间交叠且通过沿第一方向G依次排列的多个第一导电柱351电连接。进一步地，参见图12，第五连接引线L05的第一亚引线L051的第二部分与第一P型掺杂亚区F_Psub1之间通过两行第一导电柱351电连接，且任意一行第一导电柱351包括沿第一方向G依次排列的多个第一导电柱351。进一步地，参见图13，第五连接引线L05的第一亚引线L051的第一部分和第二部分的连接位置，与第五连接引线L05的第五亚引线L055的第二方向H的相反方向一端连接。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第一亚引线L051的第二部分与第七晶体管M7对应的源极连接线的第一亚连接线M7SL1均沿第一方向G延伸；第五连接引线L05的第一亚引线L051的第二部分的局部位置还可以沿第二方向H延伸以形成一第一凸出部，第五连接引线L05的第一亚引线L051的第一凸出部沿第二方向H延伸至与第七晶体管M7对应的源极连接线的第一亚连接线
M7SL1连接，以使得第七晶体管M7对应的源极连接线的第一亚连接线M7SL1的第二方向H的相反方向的侧边与第五连接引线L05的第一亚引线L051的第二部分连接。进一步地，第五连接引线L05的第一亚引线L051的第一凸出部的第一方向G的一端与第七晶体管M7对应的源极连接线的第一亚连接线M7SL1的第一方向G一端齐平，第五连接引线L05的第一亚引线L051的第一凸出部的第一方向G的相反方向的一端与第七晶体管M7对应的源极连接线的第一亚连接线M7SL1的第一方向G的相反方向的一端齐平。如此，第五连接引线L05的第一亚引线L051的第一凸出部在第一方向G上的长度与第七晶体管M7对应的源极连接线的第一亚连接线M7SL1在第一方向G上的长度相同。该第五连接引线L05的第一亚引线L051的第一凸出部的设置，可以使得第七晶体管M7对应的源极连接线的第一亚连接线M7SL1与第五连接引线L05的第一亚引线L051的第二部分为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第一亚引线L051的第二部分与第八晶体管M8对应的源极连接线的第一亚连接线M8SL1均沿第一方 向G延伸；第五连接引线L05的第一亚引线L051的第二部分的局部位置还可以沿第二方向H延伸以形成一第二凸出部，第五连接引线L05的第一亚引线L051的第二凸出部沿第二方向H延伸至与第八晶体管M8对应的源极连接线的第一亚连接线M8SL1连接，以使得第八晶体管M8对应的源极连接线的第一亚连接线M8SL1的第二方向H的相反方向的侧边与第五连接引线L05的第一亚引线L051的第二部分连接。进一步地，第五连接引线L05的第一亚引线L051的第二凸出部的第一方向G的一端与第八晶体管M8对应的源极连接线的第一亚连接线M8SL1的第一方向G一端齐平，第五连接引线L05的第一亚引线L051的第二凸出部的第一方向G的相反方向的一端与第八晶体管M8对应的源极连接线的第一亚连接线M8SL1的第一方向G的相反方向的一端齐平。如此，第五连接引线L05的第一亚引线L051的第二凸出部在第一方向G上的长度与第八晶体管M8对应的源极连接线的第一亚连接线M8SL1在第一方向G上的长度相同。该第五连接引线L05的第一亚引线L051的第二凸出部的设置，可以使得第八晶体管M8对应的源极连接线的第一亚连接线M8SL1与第五连接引线L05的第一亚引线L051的第二部分为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第一亚引线L051的第一部分与第一晶体管M1对应的源极连接线的第一亚连接线M1SL1均沿第一方向G延伸；第五连接引线L05的第一亚引线L051的第一部分的局部位置还可以沿第二方向H延伸以形成一第三凸出部，第五连接引线L05的第一亚引线L051的第三凸出部沿第二方向H延伸至与第一晶体管M1对应的源极连接线的第一亚连接线M1SL1连接，以使得第一晶体管M1对应的源极连接线的第一亚连接线M1SL1的第二方向H的相反方向的侧边与第五连接引线L05的第一亚引线L051的第一部分连接。进一步地，第五连接引线L05的第一亚引线L051的第三凸出部的第一方向G的一端与第一晶体管M1对应的源极连接线的第一亚连接线M1SL1的第一方向G一端齐平，第五连接引线L05的第一亚引线L051的第三凸出部的第一方向G的相反方向的一端与第五连接引线L05的第五亚引线L055连接。如此，第五连接引线L05的第一亚引线L051的第三凸出部在第一方向G的相反方向上超出第一晶体管M1对应的源极连接线的第一亚连接线M1SL1。该第五连接引线L05的第一亚引线L051的第三凸出部的设置，可以使得第一晶体管M1对应的源极连接线的第一亚连接线M1SL1与第五连接引线L05的第一亚引线L051的第一部分为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第二亚引线L052沿第二方向H延伸，且与第二P型掺杂亚区F_Psub2的延伸方向一致，两者可以交叠。其中，第五连接引线L05的第二亚引线L052通过沿第二方向H依次排列的多个 第一导电柱351与第二P型掺杂亚区F_Psub2电连接。
可选地，第七晶体管M7对应的源极连接线的第二亚连接线M7SL2和第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2重合，且沿第一方向G的相反方向延伸至与第五连接引线L05的第二亚引线L052连接。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第三亚引线L053沿第一方向G延伸且与第三P型掺杂亚区F_Psub3、第七P型掺杂亚区F_Psub7的延伸方向一致。第五连接引线L05的第三亚引线L053包括位于第一方向G一侧的第一部分和位于第一方向G的相反方向一侧的第二部分，第五连接引线L05的第三亚引线L053的第一部分与第七P型掺杂亚区F_Psub7之间交叠且通过沿第一方向G依次排列的多个第一导电柱351电连接；第五连接引线L05的第三亚引线L053的第二部分与第三P型掺杂亚区F_Psub3之间交叠且通过沿第一方向G依次排列的多个第一导电柱351电连接。进一步地，第五连接引线L05的第三亚引线L053的第二部分与第三P型掺杂亚区F_Psub3之间通过两行第一导电柱351电连接，且任意一行第一导电柱351包括沿第一方向G依次排列的多个第一导电柱351。进一步地，参见图13，第五连接引线L05的第三亚引线L053的第一部分和第二部分的连接位置，与第五连接引线L05的第五亚引线L055的第二方向H的一端连接。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第三亚引线L053的第二部分与第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1均沿第一方向G延伸；第五连接引线L05的第三亚引线L053的第二部分的局部位置还可以沿第二方向H的相反方向延伸以形成一第一凸出部，第五连接引线L05的第三亚引线L053的第一凸出部沿第二方向H的相反方向延伸至与第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1连接，以使得第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1的第二方向H的侧边与第五连接引线L05的第三亚引线L053的第二部分连接。进一步地，第五连接引线L05的第三亚引线L053的第一凸出部的第一方向G的一端与第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1的第一方向G一端齐平，第五连接引线L05的第三亚引线L053的第一凸出部的第一方向G的相反方向的一端与第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1的第一方向G的相反方向的一端齐平。如此，第五连接引线L05的第三亚引线L053的第一凸出部在第一方向G上的长度与第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1在第一方向G上的长度相同。该第五连接引线L05的第三亚引线L053的第一凸出部的设置，可以使得第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1与第五连接引线L05的第三亚引线L053的第二部 分为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第三亚引线L053的第二部分与第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1均沿第一方向G延伸；第五连接引线L05的第三亚引线L053的第二部分的局部位置还可以沿第二方向H的相反方向延伸以形成一第二凸出部，第五连接引线L05的第三亚引线L053的第二凸出部沿第二方向H的相反方向延伸至与第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1连接，以使得第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1的第二方向H的侧边与第五连接引线L05的第三亚引线L053的第二部分连接。进一步地，第五连接引线L05的第三亚引线L053的第二凸出部的第一方向G的一端与第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1的第一方向G一端齐平，第五连接引线L05的第三亚引线L053的第二凸出部的第一方向G的相反方向的一端与第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1的第一方向G的相反方向的一端齐平。如此，第五连接引线L05的第三亚引线L053的第二凸出部在第一方向G上的长度与第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1在第一方向G上的长度相同。该第五连接引线L05的第三亚引线L053的第二凸出部的设置，可以使得第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1与第五连接引线L05的第三亚引线L053的第二部分为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第三亚引线L053的第一部分与第二晶体管M2对应的源极连接线的第一亚连接线M2SL1均沿第一方向G延伸；第五连接引线L05的第三亚引线L053的第一部分的局部位置还可以沿第二方向H的相反方向延伸以形成一第三凸出部，第五连接引线L05的第三亚引线L053的第三凸出部沿第二方向H的相反方向延伸至与第二晶体管M2对应的源极连接线的第一亚连接线M2SL1连接，以使得第二晶体管M2对应的源极连接线的第一亚连接线M2SL1的第二方向H的侧边与第五连接引线L05的第三亚引线L053的第一部分连接。进一步地，第五连接引线L05的第三亚引线L053的第三凸出部的第一方向G的一端与第二晶体管M2对应的源极连接线的第一亚连接线M2SL1的第一方向G一端齐平，第五连接引线L05的第三亚引线L053的第三凸出部的第一方向G的相反方向的一端与第五连接引线L05的第五亚引线L055连接。如此，第五连接引线L05的第三亚引线L053的第三凸出部在第一方向G的相反方向上超出第二晶体管M2对应的源极连接线的第一亚连接线M2SL1。该第五连接引线L05的第三亚引线L053的第三凸出部的设置，可以使得第二晶体管M2对应的源极连接线的第一亚连接线M2SL1 与第五连接引线L05的第三亚引线L053的第一部分为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第四亚引线L054沿第二方向H延伸，且与第六P型掺杂亚区F_Psub6的延伸方向一致，两者可以交叠。其中，第五连接引线L05的第四亚引线L054通过沿第二方向H依次排列的多个第一导电柱351与第六P型掺杂亚区F_Psub6电连接。进一步地，第五连接引线L05的第六亚引线L056的第一方向G一端与第五连接引线L05的第四亚引线L054的中间位置连接。如此，可以使得第七亚有源区Act_sub7与第八亚有源区Act_sub8的面积基本一致。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第五亚引线L055沿第二方向H延伸，且与第四P型掺杂亚区F_Psub4的延伸方向一致，两者可以交叠。其中，第五连接引线L05的第五亚引线L055通过沿第二方向H依次排列的多个第一导电柱351与第四P型掺杂亚区F_Psub4电连接。进一步地，第五连接引线L05的第六亚引线L056的第一方向G的相反方向一端与第五连接引线L05的第五亚引线L055的中间位置连接。如此，可以使得第七亚有源区Act_sub7与第八亚有源区Act_sub8的面积基本一致。
在本公开的一种实施方式中，第五连接引线L05的第六亚引线L056沿第一方向G延伸，且与第八P型掺杂亚区F_Psub8的延伸方向一致，两者可以交叠。其中，第五连接引线L05的第六亚引线L056通过沿第一方向G依次排列的多个第一导电柱351与第八P型掺杂亚区F_Psub8电连接。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第六亚引线L056与第一晶体管M1对应的源极连接线的第二亚连接线M1SL2均沿第一方向G延伸；第五连接引线L05的第六亚引线L056的至少局部位置还可以沿第二方向H的相反方向延伸以形成一第一凸出部，第五连接引线L05的第六亚引线L056的第一凸出部沿第二方向H的相反方向延伸至与第一晶体管M1对应的源极连接线的第二亚连接线M1SL2连接，以使得第一晶体管M1对应的源极连接线的第二亚连接线M1SL2的第二方向H的侧边与第五连接引线L05的第六亚引线L056连接。进一步地，第五连接引线L05的第六亚引线L056的第一凸出部的第一方向G的一端与第一晶体管M1对应的源极连接线的第二亚连接线M1SL2的第一方向G一端齐平，第五连接引线L05的第六亚引线L056的第一凸出部的第一方向G的相反方向的一端与第五连接引线L05的第五亚引线L055连接。该第五连接引线L05的第六亚引线L056的第一凸出部的设置，可以使得第一晶体管M1对应的源极连接线的第二亚连接线M1SL2与第五连接引线L05的第六亚引线L056为一体结构。
在本公开的一种实施方式中，参见图13，第五连接引线L05的第六亚引线L056 与第二晶体管M2对应的源极连接线的第二亚连接线M2SL2均沿第一方向G延伸；第五连接引线L05的第六亚引线L056的至少局部位置还可以沿第二方向H延伸以形成一第二凸出部，第五连接引线L05的第六亚引线L056的第二凸出部沿第二方向H延伸至与第二晶体管M2对应的源极连接线的第二亚连接线M2SL2连接，以使得第二晶体管M2对应的源极连接线的第二亚连接线M2SL2的第二方向H的相反方向的侧边与第五连接引线L05的第六亚引线L056连接。进一步地，第五连接引线L05的第六亚引线L056的第二凸出部的第一方向G的一端与第二晶体管M2对应的源极连接线的第二亚连接线M2SL2的第一方向G一端齐平，第五连接引线L05的第六亚引线L056的第二凸出部的第一方向G的相反方向的一端与第五连接引线L05的第五亚引线L055连接。该第五连接引线L05的第六亚引线L056的第二凸出部的设置，可以使得第二晶体管M2对应的源极连接线的第二亚连接线M2SL2与第五连接引线L05的第六亚引线L056为一体结构。
可选地，第五连接引线L05的第六亚引线L056的宽度大于各个晶体管对应的源极连接线的宽度。
可选地，参见图13，第五连接引线L05的第六亚引线L056沿第一方向G的轴线，与第八晶体管M8对应的源极连接线的第二亚连接线M8SL2/第十四晶体管M14对应的源极连接线的第二亚连接线M14SL2沿第一方向G的轴线重合。
可选地，第九晶体管M9对应的漏极连接线M9DL、第十晶体管M10对应的漏极连接线M10DL、第七晶体管M7对应的漏极连接线M7DL和第八晶体管M8对应的漏极连接线M8DL沿第一方向G的轴线重合。
可选地，第十一晶体管M11对应的漏极连接线M11DL、第十二晶体管M12对应的漏极连接线M12DL、第十三晶体管M13对应的漏极连接线M13DL和第十四晶体管M14对应的漏极连接线M14DL沿第一方向G的轴线重合。
可选地，第九晶体管M9对应的源极连接线的第二亚连接线M9SL2/第十一晶体管M11对应的源极连接线的第二亚连接线M11SL2、第十晶体管M10对应的源极连接线的第二亚连接线M10SL2/第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2、第七晶体管M7对应的源极连接线的第二亚连接线M7SL2/第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2、第八晶体管M8对应的源极连接线的第二亚连接线M8SL2/第十四晶体管M14对应的源极连接线的第二亚连接线M14SL2、第六连接引线L06、第五连接引线L05的第六亚引线L056沿第一方向G的轴线重合。
可选地，第九晶体管M9对应的源极连接线的第一亚连接线M9SL1、第十晶体 管M10对应的源极连接线的第一亚连接线M10SL1、第七晶体管M7对应的源极连接线的第一亚连接线M7SL1、第八晶体管M8对应的源极连接线的第一亚连接线M8SL1沿第一方向G的轴线重合。
可选地，第十一晶体管M11对应的源极连接线的第一亚连接线M11SL1、第十二晶体管M12对应的源极连接线的第一亚连接线M12SL1、第十三晶体管M13对应的源极连接线的第一亚连接线M13SL1、第十四晶体管M14对应的源极连接线的第一亚连接线M14SL1沿第一方向G的轴线重合。
参见图17，第二金属布线层362可以包括第一控制引线421、第二控制引线422、第一输出引线431和第二输出引线432，以及包括部分连接引线。位于第二金属布线层362的连接引线可以包括第七连接引线L07至第十五连接引线L15。
第七连接引线L07沿第一方向G延伸，且与第一连接引线L01的第一亚引线L011、第二连接引线L02的第一亚引线L021交叠。参见图13、图17和图18，第七连接引线L07、第一连接引线L01的第一亚引线L011和第二连接引线L02的第一亚引线L021的延伸线基本重合。如此，第七连接引线L07可以通过沿第一方向G排列的多个第二导电柱352与第一连接引线L01的第一亚引线L011电连接，第七连接引线L07可以通过沿第一方向G排列的多个第二导电柱352与第二连接引线L02的第一亚引线L021电连接。进一步地的，与第七连接引线L07连接的各个第二导电柱352，沿第一方向G直线排列。可以理解的是，在第一连接引线L01的第一亚引线L011和第二连接引线L02的第一亚引线L021之间的间隙，可以不设置有第二导电柱352。
可选地，沿第一方向G，第七连接引线L07的第一方向G的一端不超出第二连接引线L02的第一亚引线L021的第一方向G的一端；沿第一方向G的相反方向，第七连接引线L07的第一方向G的相反方向一端超出第一连接引线L01的第一亚引线L011的第一方向G的相反方向一端。
第八连接引线L08沿第一方向G延伸，且与第一连接引线L01的第三亚引线L013、第二连接引线L02的第四亚引线L024交叠。第八连接引线L08、第一连接引线L01的第三亚引线L013和第二连接引线L02的第四亚引线L024的延伸线基本重合。如此，第八连接引线L08可以通过沿第一方向G排列的多个第二导电柱352与第一连接引线L01的第三亚引线L013电连接，第八连接引线L08可以通过沿第一方向G排列的多个第二导电柱352与第二连接引线L02的第四亚引线L024电连接。进一步地的，与第七连接引线L07连接的各个第二导电柱352，沿第一方向G直线排列。可以理解的是，在第一连接引线L01的第三亚引线L013和第二连接引线L02的第四亚引线L024之间的间隙，可以不设置有第二导电柱352。
可选地，沿第一方向G，第八连接引线L08的第一方向G的一端不超出第二连接引线L02的第四亚引线L024的第一方向G的一端；沿第一方向G的相反方向，第八连接引线L08的第一方向G的相反方向一端超出第一连接引线L01的第三亚引线L013的第一方向G的相反方向一端。
在本公开的一种实施方式中，第七连接引线L07和第八连接引线L08上可以加载第二电源电压V2，进而向第一连接引线L01和第二连接引线L02加载第二电源电压V2。
参见图13、图15和图17，第九连接引线L09沿第一方向G延伸，且与第五连接引线L05的第一亚引线L051交叠。第九连接引线L09、第五连接引线L05的第一亚引线L051的延伸线基本重合。如此，第九连接引线L09可以通过沿第一方向G排列的多个第二导电柱352与第五连接引线L05的第一亚引线L051电连接。
可选地，沿第一方向G，第九连接引线L09的第一方向G的一端不超出第五连接引线L05的第一亚引线L051的第一方向G的一端；沿第一方向G的相反方向，第九连接引线L09的第一方向G的相反方向一端超出第五连接引线L05的第一亚引线L051的第一方向G的相反方向一端。进一步地的，第九连接引线L09的第一方向G的相反方向一端与第五连接引线L05的第一亚引线L051的第一方向G的相反方向一端齐平；沿第一方向G，第九连接引线L09的第一方向G的一端与第一晶体管M1对应的漏极连接线M1DL的第一方向G一端齐平。
参见图13、图15和图17，第十连接引线L10沿第一方向G延伸，且与第五连接引线L05的第三亚引线L053交叠。第十连接引线L10、第五连接引线L05的第三亚引线L053的延伸线基本重合。如此，第十连接引线L10可以通过沿第一方向G排列的多个第二导电柱352与第五连接引线L05的第三亚引线L053电连接。
可选地，沿第一方向G，第十连接引线L10的第一方向G的一端不超出第五连接引线L05的第三亚引线L053的第一方向G的一端；沿第一方向G的相反方向，第十连接引线L10的第一方向G的相反方向一端超出第五连接引线L05的第三亚引线L053的第一方向G的相反方向一端。进一步地的，第十连接引线L10的第一方向G的相反方向一端与第五连接引线L05的第三亚引线L053的第一方向G的相反方向一端齐平；沿第一方向G，第十连接引线L10的第一方向G的一端与第二晶体管M2对应的漏极连接线M2DL的第一方向G一端齐平。
在本公开的一种实施方式中，第九连接引线L09和第十连接引线L10上可以加载第一电源电压V1，进而向第五连接引线L05加载第一电源电压V1。
可选地，参见图17，第七连接引线L07和第九连接引线L09位于同一直线，第 九连接引线L09位于第七连接引线L07的第一方向G一侧。第八连接引线L08和第十连接引线L10位于同一直线，第十连接引线L10位于第八连接引线L08的第一方向G一侧。
可选地，参见图17，第七连接引线L07、第八连接引线L08、第九连接引线L09和第十连接引线L10的宽度(即在第二方向H上的尺寸)相同，且大于各个晶体管对应的源极连接线的宽度。如此，可以减小第七连接引线L07、第八连接引线L08、第九连接引线L09和第十连接引线L10的阻抗，提高行驱动信号增强的驱动能力。
在一些实施方式中，参见图13、图15和图17，第十一连接引线L11沿第一方向G延伸，与第九晶体管M9对应的栅极连接线M9GL的转接线、第十晶体管M10对应的栅极连接线M10GL的转接线、第七晶体管M7对应的栅极连接线M7GL的转接线、第五晶体管M5对应的漏极连接线M5DL/第六晶体管M6对应的漏极连接线M6DL、第一晶体管M1对应的漏极连接线M1DL交叠，并通过第二导电柱352连接。可选地，第十一连接引线L11还可以设置有朝第二方向H延伸的转接线；第十一连接引线L11的转接线与第八晶体管M8对应的栅极连接线M8GL交叠，并通过第二导电柱352连接。
可选地，沿第一方向G，第一晶体管M1对应的漏极连接线M1DL的第一方向G一端位于第十一连接引线L11的第一方向G一端的第一方向G一侧，第十一连接引线L11的第一方向G的相反方向一端与第九晶体管M9对应的栅极连接线M9GL的第一方向G的相反方向一端齐平。
可选地，第十一连接引线L11的宽度与各个晶体管对应的源极连接线的宽度相同。
在一些实施方式中，参见图13、图15和图17，第十二连接引线L12沿第一方向G直线设置，且与第十一晶体管M11对应的栅极连接线M11GL的转接线、第十二晶体管M12对应的栅极连接线M12GL的转接线、第十三晶体管M13对应的栅极连接线M13GL的转接线、第三晶体管M3对应的漏极连接线M3DL/第四晶体管M4对应的漏极连接线M4DL、第二晶体管M2对应的漏极连接线M2DL交叠，且通过第二导电柱352连接。可选地，第十二连接引线L12还可以设置有朝第二方向H的相反方向延伸的转接线；第十二连接引线L12的转接线与第十四晶体管M14对应的栅极连接线M14GL交叠，并通过第二导电柱352连接。
可选地，沿第一方向G，第二晶体管M2对应的漏极连接线M2DL的第一方向G一端位于第十二连接引线L12的第一方向G一端的第一方向G一侧，第十二连接引线L12的第一方向G的相反方向一端与第十一晶体管M11对应的栅极连接线M11GL的第一方向G的相反方向一端齐平。
可选地，第十二连接引线L12的宽度与各个晶体管对应的源极连接线的宽度相同。
在一些实施方式中，参见图13、图15和图17，第十三连接引线L13沿第一方向G延伸，且依次与第一连接引线L01的第二亚引线L012、第九晶体管M9对应的源极连接线的第二亚连接线M9SL2/第十一晶体管M11对应的源极连接线的第二亚连接线M11SL2、第十晶体管M10对应的源极连接线的第二亚连接线M10SL2/第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2、第二连接引线L02的第二亚引线L022、第三连接引线L03、第六连接引线L06、第四连接引线L04、第二连接引线L02的第三亚引线L023交叠。其中，沿第一方向G，第十三连接引线L13的第一方向G的一端不超出第二连接引线L02的第三亚引线L023，第十三连接引线L13的第一方向G的相反方向一端不超出第一连接引线L01的第二亚引线L012。示例性地，沿第一方向G，第十三连接引线L13的第一方向G的一端与第二连接引线L02的第三亚引线L023的第一方向G的侧边齐平，第十三连接引线L13的第一方向G的相反方向一端与第一连接引线L01的第二亚引线L012的第一方向G的相反方向的侧边齐平。
可选地，参见图13、图15和图17，第十三连接引线L13通过第二导电柱352分别与第九晶体管M9对应的源极连接线的第二亚连接线M9SL2/第十一晶体管M11对应的源极连接线的第二亚连接线M11SL2、第十晶体管M10对应的源极连接线的第二亚连接线M10SL2/第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2和第六连接引线L06电连接。如此，第十三连接引线L13可以将第一连接引线L01上的第二电源电压V2加载至第十晶体管M10对应的源极连接线的第二亚连接线M10SL2/第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2和第六连接引线L06。进一步地，第十三连接引线L13与第九晶体管M9对应的源极连接线的第二亚连接线M9SL2/第十一晶体管M11对应的源极连接线的第二亚连接线M11SL2之间通过沿第一方向G依次排列的多个第二导电柱352电连接，第十三连接引线L13与第十晶体管M10对应的源极连接线的第二亚连接线M10SL2/第十二晶体管M12对应的源极连接线的第二亚连接线M12SL2之间通过沿第一方向G依次排列的多个第二导电柱352电连接，第十三连接引线L13与第六连接引线L06之间通过沿第一方向G依次排列的多个第二导电柱352电连接。进一步地，第十三连接引线L13与第一连接引线L01的第二亚引线L012之间通过一个第二导电柱352电连接，第十三连接引线L13与第二连接引线L02的第二亚引线L022之间通过一个第二导电柱352电连接，第十三连接引线L13与第二连接引线L02的第三亚引线L023之间通过一个第二导电柱352电连接。
在本公开的一种实施方式中，参见图13、图15和图17，第九晶体管M9对应的栅极连接线M9GL和第十一晶体管M11对应的栅极连接线M11GL分别位于第十三连接引线L13的两侧，且与第十三连接引线L13不交叠；第十晶体管M10对应的栅极连接线M10GL和第十二晶体管M12对应的栅极连接线M12GL分别位于第十三连接引线L13的两侧，且与第十三连接引线L13不交叠。
可选地，第十三连接引线L13的宽度与各个晶体管对应的源极连接线的宽度相同。
在一些实施方式中，参见图13、图15和图17，第十四连接引线L14和第十五连接引线L15相互连接且均沿第一方向G延伸，第十五连接引线L15位于第十四连接引线L14的第一方向G一侧。其中，第十四连接引线L14和第十五连接引线L15沿第一方向G的轴线重合。
第十四连接引线L14依次与第五连接引线L05的第二亚引线L052、第七晶体管M7对应的源极连接线的第二亚连接线M7SL2/第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2、第八晶体管M8对应的源极连接线的第二亚连接线M8SL2/第十四晶体管M14对应的源极连接线的第二亚连接线M14SL2交叠并电连接。参见图15，第十四连接引线L14与第七晶体管M7对应的源极连接线的第二亚连接线M7SL2/第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2之间通过沿第一方向G依次排列的多个第二导电柱352电连接，第十四连接引线L14与第八晶体管M8对应的源极连接线的第二亚连接线M8SL2/第十四晶体管M14对应的源极连接线的第二亚连接线M14SL2之间通过沿第一方向G依次排列的多个第二导电柱352电连接。第十四连接引线L14与第五连接引线L05的第二亚引线L052之间，既可以通过一个第二导电柱352电连接，也可以不通过第二导电柱352直接连接。当然地，直接连接第十四连接引线L14和第五连接引线L05的第二亚引线L052的第二导电柱352，也可以位于第十四连接引线L14和第七晶体管M7对应的源极连接线的第二亚连接线M7SL2/第十三晶体管M13对应的源极连接线的第二亚连接线M13SL2的连接处。
可选地，第十四连接引线L14的宽度与各个晶体管对应的源极连接线的宽度相同。
第十五连接引线L15与第五连接引线L05的第六亚引线L056交叠，且通过第二导电柱352电连接。示例性地，第十五连接引线L15与第五连接引线L05的第六亚引线L056之间通过沿第一方向G排列的多个第二导电柱352电连接。可选地，第五连接引线L05的第六亚引线L056具有第一凸出部和第二凸出部，使得第五连接引线L05的第六亚引线L056的局部宽度大于第十四连接引线L14的宽度。此时，第十五连接引线L15的宽度可以与第五连接引线L05的第六亚引线L056的最大宽度相同，第十五连接引线L15与第五连接引线L05的第六亚引线L056之间通过两行第二导电柱352电连接，任意一行第二导电柱352包括沿第一方向G排列的多个第二导电柱352。更进一步地，该两行第二导电柱352中，其中一行第二导电柱352与第十五连接引线L15的第一凸出部交叠，另一行第二导电柱352与第十五连接引线L15的第二凸出部交叠。
可选地，第十五连接引线L15的第一方向G的相反方向一端与第五连接引线L05的第五亚引线L055交叠，且通过第二导电柱352与第五连接引线L05的第五亚引线L055电连接。
可选地，第一晶体管M1对应的源极连接线的第二亚连接线M1SL2的第一方向G的一端位于第十五连接引线L15的第一方向G的一端的第一方向G一侧。进一步地， 第十五连接引线L15的第一方向G一端与第十一连接引线L11、第十二连接引线L12的第一方向G一端齐平。
参见图13、图15和图17，第一输出引线431沿第一方向G延伸，且与第九晶体管M9对应的漏极连接线M9DL、第十晶体管M10对应的漏极连接线M10DL、第七晶体管M7对应的漏极连接线M7DL和第八晶体管M8对应的漏极连接线M8DL通过第二导电柱352电连接。在本公开的一种实施方式中，第九晶体管M9对应的漏极连接线M9DL、第十晶体管M10对应的漏极连接线M10DL、第七晶体管M7对应的漏极连接线M7DL、第八晶体管M8对应的漏极连接线M8DL沿第一方向G直线延伸，且位于同一直线；第一输出引线431的延伸方向与第九晶体管M9对应的漏极连接线M9DL、第十晶体管M10对应的漏极连接线M10DL、第七晶体管M7对应的漏极连接线M7DL、第八晶体管M8对应的漏极连接线M8DL的延伸方向重合，且与第九晶体管M9对应的漏极连接线M9DL、第十晶体管M10对应的漏极连接线M10DL、第七晶体管M7对应的漏极连接线M7DL、第八晶体管M8对应的漏极连接线M8DL交叠，并分别通过沿第一方向G排列的多个第二导电柱352连接；这些第二导电柱352可以位于同一直线。
可选地，参见图13、图15和图17，沿第一方向G的相反方向，第一输出引线431的第一方向G的相反方向一端超出第一连接引线L01的第二亚引线L012，以便第一输出引线431作为行驱动信号增强电路101的第二输出端OUT2，向显示面板的显示区D输出第一扫描信号。
可选地，参见图13、图15和图17，第二输出引线432沿第一方向G延伸，且与第十一晶体管M11对应的漏极连接线M11DL、第十二晶体管M12对应的漏极连接线M12DL、第十三晶体管M13对应的漏极连接线M13DL和第十四晶体管M14对应的漏极连接线M14DL通过第二导电柱352电连接。在本公开的一种实施方式中，第十一晶体管M11对应的漏极连接线M11DL、第十二晶体管M12对应的漏极连接线M12DL、第十三晶体管M13对应的漏极连接线M13DL和第十四晶体管M14对应的漏极连接线M14DL沿第一方向G直线延伸，且位于同一直线；第二输出引线432的延伸方向与第十一晶体管M11对应的漏极连接线M11DL、第十二晶体管M12对应的漏极连接线M12DL、第十三晶体管M13对应的漏极连接线M13DL、第十四晶体管M14对应的漏极连接线M14DL的延伸方向重合，且分别通过沿第一方向G排列的多个第二导电柱352连接，且这些第二导电柱352可以位于同一直线。
可选地，沿第一方向G的相反方向，第二输出引线432的第一方向G的相反方向一端超出第一连接引线L01的第二亚引线L012，以便第二输出引线432作为行驱动信号增强电路101的第二输出端OUT2，向显示面板的显示区D输出第二扫描信号。
参见图13、图15和图17，第一控制引线421位于第一晶体管M1对应的漏极连接线M1DL的第一方向G一侧，且与第一晶体管M1对应的栅极连接线M1GL通过第 二导电柱352电连接。如此，第一控制引线421可以作为行驱动信号增强电路101的第一输入端IN1，向行驱动信号增强电路101输入第一初始扫描信号。
可选地，第一控制引线421沿第一方向G延伸，其第一方向G的一端位于第五连接引线L05的第四亚引线L054的第一方向G一侧，以便其能够接收第一初始扫描信号。第一控制引线421的第一方向G的相反方向一端与第一晶体管M1对应的栅极连接线M1GL齐平。进一步地，第一控制引线421的第一方向G的相反方向一端具有一个连接部，第一控制引线421的连接部沿第二方向H的相反方向延伸且与第一晶体管M1对应的栅极连接线M1GL交叠，其通过第二导电柱352与第一晶体管M1对应的栅极连接线M1GL连接。如此，可以提高第一控制引线421与第一晶体管M1对应的栅极连接线M1GL之间的导电面积，进而减小行驱动信号增强电路101的延迟。
参见图13、图15和图17，第二控制引线422位于第二晶体管M2对应的漏极连接线M2DL的第一方向G一侧，且与第二晶体管M2对应的栅极连接线M2GL通过第二导电柱352电连接。如此，第二控制引线422可以作为行驱动信号增强电路101的第二输入端IN2，向行驱动信号增强电路101输入第二初始扫描信号。
可选地，第二控制引线422沿第一方向G延伸，其第一方向G的一端位于第五连接引线L05的第四亚引线L054的第一方向G一侧，以便其能够接收第二初始扫描信号。第二控制引线422的第一方向G的相反方向一端与第二晶体管M2对应的栅极连接线M2GL齐平。进一步地，第二控制引线422的第一方向G的相反方向一端具有一个连接部，第二控制引线422的连接部沿第二方向H延伸且与第二晶体管M2对应的栅极连接线M2GL交叠，其通过第二导电柱352与第二晶体管M2对应的栅极连接线M2GL连接。如此，可以提高第二控制引线422与第二晶体管M2对应的栅极连接线M2GL之间的导电面积，进而减小行驱动信号增强电路101的延迟。
可以理解的是，在行驱动信号增强区F，还可以设置有其他引线或者导电结构，这些引线或者导电结构可以不构成行驱动信号增强电路101而仅仅穿过该行驱动信号增强区F，或者调整行驱动信号增强电路101中不同位置处的寄生电容、寄生电阻等。示例性地，参见图13、图15和图17，第二金属布线层362还可以具有第十六连接引线L16和第十七连接引线L17，第十六连接引线L16和第十七连接引线L17沿第一方向G延伸且两者的延伸轴线重合。其中，第十六连接引线L16沿第一方向G贯穿N型衬底区F_Ndop，且位于第八连接引线L08和第十二连接引线L12之间。第十七连接引线L17沿第一方向G贯穿P型衬底区F_Pdop，且位于第十连接引线L10和第十二连接引线L12之间。其中，在行驱动信号增强区F，第十六连接引线L16和第十七连接引线L17不与任何第二导电柱352和第三导电柱353电连接，以使得第十六连接引线L16和第十七连接引线L17位于行驱动信号增强区F却不构成行驱动信号增强电 路101的一部分。
参见图17、图19和图20，第三金属布线层363可以设置有第一电源引线411和第二电源引线412。第一电源引线411与第九连接引线L09和第十连接引线L10交叠，且通过第三导电柱353电连接。进一步地，第一电源引线411与第十四连接引线L14、第十五连接引线L15交叠，且通过第三导电柱353电连接。在本公开的一种实施方式中，第一电源引线411覆盖第三有源区Act3和第四有源区Act4，以屏蔽外部信号对第七晶体管M7、第八晶体管M8、第十三晶体管M13、第十四晶体管M14、第一晶体管M1和第二晶体管M2的干扰。
示例性地，参见图19、图20和图21，第一电源引线411具有相对设置且沿第二方向H延伸的两个侧边，其中第一方向G一侧的侧边与第九连接引线L09的第一方向G一端齐平，第一方向G的相反方向一侧的侧边与第九连接引线L09的第一方向G的相反方向的一端齐平。在本公开的一种实施方式中，参见图24，显示面板包括沿第二方向H依次排列的多个行信号驱动增强区F，任意一个行信号驱动增强区F内设置有行信号驱动增强电路。各个行信号驱动增强电路可以共用同一第一电源引线411，该第一电源引线411沿第二方向H延伸，以覆盖各个行信号驱动增强区的第三有源区Act3和第四有源区Act4，且与各个行信号驱动增强区F内的第九连接引线L09、第十连接引线L10、第十四连接引线L14和第十五连接引线L15通过第三导电柱353电连接。
参见图19、图20和图21，第二电源引线412与第七连接引线L07和第八连接引线L08交叠，且通过第三导电柱353电连接。进一步地，第二电源引线412与第十三连接引线L13交叠，且通过第三导电柱353电连接。在本公开的一种实施方式中，第二电源引线412覆盖第一有源区Act1和第二有源区Act2，以屏蔽外部信号对第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6的干扰。
在本公开的一种实施方式中，参见图24，显示面板包括沿第二方向H依次排列的多个行信号驱动增强区F，任意一个行信号驱动增强区内设置有行信号驱动增强电路。各个行信号驱动增强电路可以共用相同的第二电源引线412，该第二电源引线412沿第二方向H延伸，以覆盖各个行信号驱动增强区的第一有源区Act1和第二有源区Act2，且与各个行信号驱动增强区内的第七连接引线L07、第八连接引线L08、第十四连接引线L14通过第三导电柱353电连接。
在本公开的一种实施方式中，第二电源引线412的数量为两个，两个第二电源引线412均沿第二方向H延伸。其中，在第一方向G一侧的第二电源引线412覆盖第二亚有源区Act_sub2和第二有源区Act2，其在第一方向G一侧的边缘在第二连接引线L02的第三亚引线L023的第一方向G一侧，其在第一方向G的相反方向的边缘在第二连接引线L02的第一亚引线L021的第一方向G的相反方向一侧。在第一方向G的 相反方向一侧的第二电源引线412与第一亚有源区Act_sub1交叠，其在第一方向G一侧的边缘与第九晶体管M9对应的漏极连接线M9DL的第一方向G的一端齐平，其在第一方向G的相反方向一侧的边缘与第一连接引线L01的第二亚引线L012的第一方向G的相反方向的边缘齐平。其中，两个第二电源引线412均沿第二方向H延伸，以依次贯穿沿第二方向H直线排列的多个行信号驱动增强区F。
可选地，沿第二方向H相邻两个行信号驱动增强电路可以共用部分金属布线层和部分导电柱；相应的，沿第二方向H相邻两个行信号驱动增强区可以共用部分区域。
举例而言，各个行信号驱动增强区F可以沿第二方向H依次编号，其中，上一行信号驱动增强区的第三N型掺杂亚区F_Nsub3可以与下一行信号驱动增强区的第一N型掺杂亚区F_Nsub1连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强区的第三N型掺杂亚区F_Nsub3与下一行信号驱动增强区的第一N型掺杂亚区F_Nsub1为同一N型掺杂亚区。相应的，上一行信号驱动增强区的第七N型掺杂亚区F_Nsub7可以与下一行信号驱动增强区的第五N型掺杂亚区F_Nsub5连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强区的第七N型掺杂亚区F_Nsub7与下一行信号驱动增强区的第五N型掺杂亚区F_Nsub5为同一N型掺杂亚区。上一行信号驱动增强区的第三P型掺杂亚区F_Psub3可以与下一行信号驱动增强区的第一P型掺杂亚区F_Psub1连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强区的第三P型掺杂亚区F_Psub3与下一行信号驱动增强区的第一P型掺杂亚区F_Psub1为同一P型掺杂亚区。上一行信号驱动增强区的第七P型掺杂亚区F_Psub7可以与下一行信号驱动增强区的第五P型掺杂亚区F_Psub5连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强区的第七P型掺杂亚区F_Psub7与下一行信号驱动增强区的第五P型掺杂亚区F_Psub5为同一P型掺杂亚区。
再举例而言，各个行信号驱动增强电路可以沿第二方向H依次编号。其中，上一行信号驱动增强电路的第一连接引线L01的第三亚引线L013可以与下一行信号驱动增强电路的第一连接引线L01的第一亚引线L011连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强电路的第一连接引线L01的第三亚引线L013与下一行信号驱动增强电路的第一连接引线L01的第一亚引线L011为同一亚引线。
上一行信号驱动增强电路的第二连接引线L02的第四亚引线L024可以与下一行信号驱动增强电路的第二连接引线L02的第一亚引线L021连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强电路的第二连接引线L02的第四亚引线L024与下一行信号驱动增强电路的第二连接引线L02的第一亚引线L021为同一亚引线。
上一行信号驱动增强电路的第五连接引线L05的第三亚引线L053可以与下一行信号驱动增强电路的第五连接引线L05的第一亚引线L051连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强电路的第五连接引线L05的第三亚引线 L053与下一行信号驱动增强电路的第五连接引线L05的第一亚引线L051为同一亚引线。
上一行信号驱动增强电路的第八连接引线L08可以与下一行信号驱动增强电路的第七连接引线L07连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强电路的第八连接引线L08与下一行信号驱动增强电路的第七连接引线L07为同一引线。
上一行信号驱动增强电路的第十连接引线L10可以与下一行信号驱动增强电路的第九连接引线L09连接而成一体结构且呈轴对称设置，亦或可以认为上一行信号驱动增强电路的第十连接引线L10与下一行信号驱动增强电路的第九连接引线L09为同一引线。
在本公开的一种实施方式中，参见图4，显示面板在显示区D还设置有像素驱动电路104，像素驱动电路104包括数据写入单元250、存储电容Cst和驱动晶体管M03。数据写入单元具有第一控制电极和第二控制电极，数据写入单元的第一控制电极与第一输出引线431连接，数据写入单元的第二控制电极与第二输出引线432连接，数据写入单元的输入端与显示面板的数据线连接，数据写入单元的输出端与第三节点C连接。存储电容Cst的第一电极板连接第三节点C，存储电容Cst的第二电极板加载有第一驱动电压。驱动晶体管M03的控制端连接第三节点C，驱动晶体管M03的输出端连接显示面板的发光元件(例如OLED、液晶像素单元、LED等)，驱动晶体管M03的输入端能够加载第二驱动电压。
如此，行驱动信号增强电路101可以输出扫描信号，以控制数据写入单元的导通或者截止。当数据写入单元导通时，加载于数据写入单元的输入端上的数据电压Vdata可以加载至第三节点C。
优选地，数据写入单元可以包括第一开关晶体管M01和第二开关晶体管M02。其中，第一开关晶体管M01和第二开关晶体管M02中的一个为P型晶体管，另一个为N型晶体管；P型晶体管能够响应加载于其控制端上的第一电源电压V1而导通，N型晶体管能够响应加载于其控制端上的第二电源电压V2而导通。如此，第一开关晶体管M01的控制端可以作为数据写入单元的第一控制电极，第二开关晶体管M02的控制端可以作为数据写入单元的第二控制电极。当扫描信号加载至数据写入单元的第一控制电极和第二控制电极时，第一开关晶体管M01和第二开关晶体管M02均可以导通；当非扫描信号加载至数据写入单元的第一控制电极和第二控制电极时，例如当行驱动信号增强电路101的第一输出端OUT1和第二输出端OUT2上的基值电压加载至数据写入单元的第一控制电极和第二控制电极时，数据写入单元均截止。
示例性地，如果行驱动信号增强电路101的第一输出端OUT1输出的基值电压为第一电源电压V1且扫描信号的电压为第二电源电压V2时，行驱动信号增强电路101的第二输出端OUT2输出的基值电压为第二电源电压V2且扫描信号的电压为第一电 源电压V1。则第一开关晶体管M01可以为N型晶体管，且第二开关晶体管M02可以为P型晶体管。
进一步地，显示区D设置有第一栅极引线和第二栅极引线。数据写入单元的第一控制电极连接第一栅极引线，数据写入单元的第二控制电极连接第二栅极引线。行驱动信号增强电路101的第一输出引线431连接第一栅极引线，行驱动信号增强电路101的第二输出引线432连接第二栅极引线。
进一步地，第一电源引线411用于加载第一驱动电压；第二电源引线412用于加载第二驱动电压。即，第一驱动电压和第一电源电压相同，第二驱动电压和第二电源电压相同。如此，本公开提供的行驱动信号增强电路101，其作为扫描信号的电源电压的规格与显示区D的电源电压的规格一致，不仅能够简化显示面板的电源规格设置和电源分布设置，而且能够显著的提高扫描信号的驱动能力。
可选地，参见图4，显示面板在外围区E还设置有与各个行驱动信号增强电路101一一对应设置的多个移位寄存器102和多个反相器103。在相互对应的行驱动信号增强电路101、移位寄存器102和反相器103中，移位寄存器102的输出端与反相器103的输入端、行驱动信号增强电路101的第一控制引线421连接，反相器103的输出端与行驱动信号增强电路101的第二控制引线422连接。
如此，移位寄存器102可以输出第一初扫描信号，该第一初始扫描信号可以加载至行驱动信号增强电路101的第一控制端IN1。反相器103可以根据该第一初扫描信号而生成相反的第二初扫描信号，该第二初扫描信号可以加载至行驱动信号增强电路101的第二控制端IN2。由此，该行驱动信号增强电路101的两个控制端分别加载两个不同的初始扫描信号，并在该两个不同的初始扫描信号的控制下输出第一扫描信号和第二扫描信号，以扫描像素驱动电路。如此，行驱动信号增强电路101能够根据移位寄存器102输出的第一初扫描信号而生成两个相反的、由第一电源电压V1和第二电源电压V2形成的扫描信号，进而提高扫描信号的驱动能力。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (23)

  1. 一种行驱动信号增强电路，包括：
    控制单元，具有第一控制端和第二控制端，用于在所述第一控制端和所述第二控制端的控制下，向第一节点和第二节点中的一个输入第一电源电压，且向另一个输入第二电源电压；
    第一输出单元，连接所述第一节点和第一输出端，用于在所述第一节点的控制下输出所述第一电源电压和所述第二电源电压中的一个至所述第一输出端；
    第二输出单元，连接所述第二节点和第二输出端，用于在所述第二节点的控制下输出所述第一电源电压和所述第二电源电压中的另一个至所述第二输出端。
  2. 根据权利要求1所述的行驱动信号增强电路，其中，所述控制单元包括：
    第一控制单元，具有所述第一控制端和所述第二控制端，用于在所述第一控制端和所述第二控制端的控制下，输出所述第一电源电压至所述第一节点或者所述第二节点；
    第二控制单元，连接所述第一节点和所述第二节点，用于响应加载于所述第一节点上的所述第一电源电压而输出所述第二电源电压至所述第二节点，且用于响应加载于所述第二节点上的所述第一电源电压而输出所述第二电源电压至所述第一节点。
  3. 根据权利要求2所述的行驱动信号增强电路，其中，所述第二控制单元具有至少四个晶体管。
  4. 根据权利要求2所述的行驱动信号增强电路，其中，所述第一控制单元包括：
    第一晶体管，具有用于加载所述第一电源电压的第一端、连接所述第一节点的第二端和作为所述第一控制端的控制端；所述第一晶体管用于，在所述第一晶体管的控制端的控制下输出所述第一电源电压至所述第一节点；
    第二晶体管，具有用于加载所述第一电源电压的第一端、连接所述第二节点的第二端和作为所述第二控制端的控制端；所述第二晶体管用于，在所述第二晶体管的控制端的控制下输出所述第一电源电压至所述第二节点；
    所述第一晶体管和所述第二晶体管的类型相同；
    所述第二控制单元包括：
    第三晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第二节点的第二端；所述第三晶体管用于，在加载于所述第一节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第二节点；
    第四晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第二节点的第二端；所述第四晶体管用于，在加载于所述第一节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第二节点；
    第五晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一节点的第二端；所述第五晶体管用于，在加载于所述第二节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第一节点；
    第六晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一节点的第二端；所述第六晶体管用于，在加载于所述第二节点上的所述第一电源电压的控制下输出所述第二电源电压至所述第一节点；
    所述第三晶体管至所述第六晶体管的类型相同。
  5. 根据权利要求1所述的行驱动信号增强电路，其中，所述第一输出单元包括：
    第七晶体管，具有连接所述第一节点的控制端、用于加载所述第一电源电压的第一端和作为所述第一输出端的第二端；
    第八晶体管，具有连接所述第一节点的控制端、用于加载所述第一电源电压的第一端和连接所述第一输出端的第二端；
    第九晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一输出端的第二端；
    第十晶体管，具有连接所述第一节点的控制端、用于加载所述第二电源电压的第一端和连接所述第一输出端的第二端；
    所述第二输出单元包括：
    第十一晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和作为所述第一输出端的第二端；
    第十二晶体管，具有连接所述第二节点的控制端、用于加载所述第二电源电压的第一端和连接所述第二输出端的第二端；
    第十三晶体管，具有连接所述第二节点的控制端、用于加载所述第一电源电压的第一端和连接所述第二输出端的第二端；
    第十四晶体管，具有连接所述第二节点的控制端、用于加载所述第一电源电压的第一端和连接所述第二输出端的第二端；
    其中，所述第七晶体管、所述第八晶体管、所述第十三晶体管、所述第十四晶体中的任意一个用于响应加载于其控制端的所述第一电源电压和所述第二电源电压中的一个而导通，所述第九晶体管至所述第十二晶体管中的任意一个用于响应加载于其控制端的所述第一电源电压和所述第二电源电压中的另一个而导通。
  6. 一种移位寄存器单元，包括移位寄存器、反相器和权利要求1～5任意一项所述的行驱动信号增强电路；
    其中，所述移位寄存器用于输出初始扫描信号至所述反相器的输入端和所述行驱动信号增强电路的第一控制端；所述反相器的输出端连接所述行驱动信号增强电路的第二控制端。
  7. 一种显示面板，包括权利要求6所述的移位寄存器单元。
  8. 一种显示面板，其中，所述显示面板包括驱动背板和层叠于所述驱动背板上的显示层；所述驱动背板包括依次层叠设置的半导体衬底、栅极绝缘层、栅极层、绝缘介质层和金属布线层；所述显示面板包括显示区和围绕所述显示区的外围区，且在所述外围区设置有多个行驱动信号增强区；
    在任意一个所述行驱动信号增强区，所述驱动背板设置有包括第一晶体管至第十四晶体管的行驱动信号增强电路；其中，所述第一晶体管和所述第二晶体管类型相同；所述第七晶体管、所述第八晶体管、所述第十三晶体管和所述第十四晶体管的类型相同；所述第九晶体管至所述第十二晶体管的类型相同，且与所述第七晶体管的类型相反；所述第三晶体管至所述第六晶体管的类型相同；所述半导体衬底形成有各个晶体管的有源区，任意一个晶体管的所述有源区包括沟道区、沟道区两侧的源极和漏极；所述栅极层形成有各个晶体管的栅极，且所述栅极绝缘层隔离任意一个晶体管的栅极和沟道区；所述绝缘介质层覆盖所述栅极层；
    在一个所述行驱动信号增强区，所述金属布线层设置有连接引线、第一电源引线、第二电源引线、第一控制引线、第二控制引线、第一输出引线和第二输出引线；所述连接引线通过位于所述绝缘介质层中的导电柱与各个晶体管的源极、漏极和栅极电连接；其中，所述连接引线使得所述第一晶体管的栅极与所述第一控制引线电连接，且使得所述第二晶体管的栅极与所述第二控制引线电连接，且使得所述第一晶体管的源极、所述第二晶体管的源极、所述第七晶体管的源极、所述第八晶体管的源极、所述 第十三晶体管的源极、所述第十四晶体管的源极与所述第一电源引线电连接，且使得所述第三晶体管至所述第六晶体管的源极、所述第九晶体管至所述第十二晶体管的源极与所述第二电源引线电连接，且使得所述第七晶体管至所述第十晶体管的漏极与所述第一输出引线电连接，且使得所述第十一晶体管至所述第十四晶体管的漏极与所述第二输出引线电连接，且使得所述第一晶体管的漏极、所述第五晶体管的漏极、所述第六晶体管的漏极、所述第三晶体管的栅极、所述第四晶体管的栅极、所述第七晶体管至所述第十晶体管的栅极相互电连接，且使得所述第二晶体管的漏极、所述第三晶体管的漏极、所述第四晶体管的漏极、所述第五晶体管的栅极、所述第六晶体管的栅极、所述第十一晶体管至所述第十四晶体管的栅极相互电连接。
  9. 根据权利要求8所述的显示面板，其中，所述第一晶体管、所述第二晶体管、所述第七晶体管、所述第八晶体管、所述第十三晶体管、所述第十四晶体管均为N型晶体管，所述第三晶体管至所述第六晶体管、所述第九晶体管至所述第十二晶体管均为P型晶体管。
  10. 根据权利要求9所述的显示面板，其中，任意一个所述行驱动信号增强区包括P型衬底区和N型衬底区，所述P型衬底区位于所述N型衬底区的第一方向一侧，所述第一方向为远离所述显示区的方向；所述N型晶体管形成于所述P型衬底区，且所述P型晶体管形成于所述N型衬底区。
  11. 根据权利要求10所述的显示面板，其中，所述N型衬底区包括N型辅助掺杂区，以及包括分别被所述N型辅助掺杂区环绕的第一有源区和第二有源区；所述第二有源区位于所述第一有源区的第一方向一侧；
    所述第一有源区包括沿所述第一方向依次排列的第一亚有源区和第二亚有源区；所述第九晶体管和第十一晶体管位于所述第一亚有源区，所述第十晶体管和所述第十二晶体管位于所述第二亚有源区；
    所述第二有源区包括沿第二方向依次排列的第三亚有源区和第四亚有源区；所述第二方向与所述第一方向垂直且平行于所述半导体衬底所在平面；所述第五晶体管和所述第六晶体管位于所述第三亚有源区，所述第三晶体管和所示第四晶体管位于所述第四亚有源区。
  12. 根据权利要求11所述的显示面板，其中，所述P型衬底区包括P型辅助掺杂区、第三有源区和第四有源区；所述第四有源区位于所述第三有源区的第一方向一侧；
    所述第三有源区被所述P型辅助掺杂区环绕，且包括沿所述第一方向依次排列的第五亚有源区和第六亚有源区；所述第七晶体管和所述第十三晶体管位于所述第五亚有源区，所述第八晶体管和所述第十四晶体管位于所述第六亚有源区；
    所述第四有源区包括沿所述第二方向依次排列且分别被所述P型辅助掺杂区环绕的第七亚有源区和第八亚有源区；所述第一晶体管位于所述第七亚有源区，所述第二 晶体管位于所述第八亚有源区。
  13. 根据权利要求12所述的显示面板，其中，所述绝缘介质层包括依次层叠于所述栅极层的第一电介质层、第二电介质层和第三电介质层，所述金属布线层包括位于所述第一电介质层和所述第二电介质层之间的第一金属布线层、位于所述第二电介质层和所述第三电介质层之间的第二金属布线层和位于所述第三电介质层远离所述半导体衬底的表面的第三金属布线层；
    所述导电柱包括贯穿所述第一电介质层的第一导电柱、贯穿所述第二电介质层的第二导电柱和贯穿所述第三电介质层的第三导电柱；所述第一金属布线层通过所述第一导电柱与所述半导体衬底和所述栅极层连接；所述第二金属布线层通过所述第二导电柱与所述第一金属布线层连接；所述第三金属布线层通过所述第三导电柱与所述第二金属布线层连接；
    其中，所述第一金属布线层包括部分连接引线；位于所述第一金属布线层的所述连接引线包括第一连接引线至第六连接引线，还包括所述第一晶体管至所述第十四晶体管各自对应的栅极连接线、源极连接线和漏极连接线；任意一个晶体管对应的栅极连接线与所述晶体管的栅极连接；任意一个晶体管对应的源极连接线与所述晶体管的源极连接；任意一个晶体管对应的漏极连接线与所述晶体管的漏极连接；
    所述第九晶体管对应的源极连接线和所述第十一晶体管对应的源极连接线与所述第一连接引线连接；
    所述第十晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第十二晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第十晶体管对应的源极连接线的第一亚连接线、所述第十二晶体管对应的源极连接线的第一亚连接线、所述第五晶体管对应的源极连接线、所述第四晶体管对应的源极连接线与所述第二连接引线连接；
    所述第三晶体管对应的漏极连接线、所述第四晶体管对应的漏极连接线、所述第五晶体管对应的栅极连接线、所述第六晶体管对应的栅极连接线与所述第三连接引线连接；
    所述第五晶体管对应的漏极连接线、所述第六晶体管对应的漏极连接线、所述第三晶体管对应的栅极连接线、所述第四晶体管对应的栅极连接线与所述第四连接引线连接；
    所述第八晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第十四晶体管对应的源极连接线包括第一亚连接线和第二亚连接线；所述第八晶体管对应的源极连接线的第一亚连接线、所述第十四晶体管对应的源极连接线的第一亚连接线、所述第七晶体管对应的源极连接线、所述第十三晶体管对应的源极连接线、所述第一晶体管对应的源极连接线、所述第二晶体管对应的源极连接线与所述第五连接引线连接；
    所述第三晶体管对应的源极连接线、所述第六晶体管对应的源极连接线与所述第六连接引线连接；
    所述第二金属布线层包括第一控制引线、第二控制引线、第一输出引线、第二输出引线和部分连接引线；位于所述第二金属布线层的所述连接引线包括第七连接引线至第十五连接引线；
    所述第一连接引线、所述第二连接引线与所述第七连接引线连接，且所述第一连接引线、所述第二连接引线与所述第八连接引线连接；
    所述第五连接引线与所述第九连接引线、所述第十连接引线连接；
    所述第九晶体管对应的栅极连接线、所述第十晶体管对应的栅极连接线、所述第五晶体管对应的漏极连接线、所述第六晶体管对应的漏极连接线、所述第七晶体管对应的栅极连接线、所述第八晶体管对应的栅极连接线、所述第一晶体管对应的漏极连接线与所述第十一连接引线连接；
    所述第十一晶体管对应的栅极连接线、所述第十二晶体管对应的栅极连接线、所述第三晶体管对应的漏极连接线、所述第四晶体管对应的漏极连接线、所述第十三晶体管对应的栅极连接线、所述第十四晶体管对应的栅极连接线、所述第二晶体管对应的漏极连接线与所述第十二连接引线连接；
    所述第一连接引线、所述第九晶体管对应的源极连接线、所述第十一晶体管对应的源极连接线、所述第十晶体管对应的源极连接线的第二亚连接线、所述第十二晶体管对应的源极连接线的第二亚连接线、所述第六连接引线与所述第十三连接引线连接；
    所述第七晶体管对应的源极连接线、所述第八晶体管对应的源极连接线的第二亚连接线、所述第十三晶体管对应的源极连接线、所述第十四晶体管对应的源极连接线的第二亚连接线、所述第五连接引线与所述第十四连接引线连接；
    所述第五连接引线与所述第十五连接引线连接；
    所述第七晶体管对应的漏极连接线、所述第八晶体管对应的漏极连接线、所述第九晶体管对应的漏极连接线、所述第十晶体管对应的漏极连接线与所述第一输出引线连接；
    所述第十一晶体管对应的漏极连接线、所述第十二晶体管对应的漏极连接线、所述第十三晶体管对应的漏极连接线、所述第十四晶体管对应的漏极连接线与所述第二输出引线连接；
    所述第一晶体管对应的栅极连接线与所述第一控制引线连接，所述第二晶体管对应的栅极连接线与所述第二控制引线连接；
    所述第三金属布线层包括用于加载第一电源电压的第一电源引线，以及包括线用于加载第二电源电压的第二电源引线；所述第九连接引线、所述第十连接引线、所述第十四连接引线、所述第十五连接引线与所述第一电源引线连接；所述第七连接引线、所述第八连接引线、所述第十三连接引线与所述第二电源引线连接。
  14. 根据权利要求13所述的显示面板，其中，在任意一个所述行驱动信号增强区，各个晶体管对应的源极连接线和漏极连接线均沿所述第一方向延伸，各个晶体管的栅极均沿所述第一方向延伸。
  15. 根据权利要求14所述的显示面板，其中，所述第一连接引线包括依次连接的第一亚引线、第二亚引线和第三亚引线；所述第一连接引线的第一亚引线、所述第一连接引线的第三亚引线沿所述第一方向延伸且与所述N型辅助掺杂区至少部分交叠；所述第一连接引线的第二亚引线沿所述第二方向延伸且与所述N型辅助掺杂区至少部分交叠；所述第一连接引线的第一亚引线、所述第一连接引线的第二亚引线和所述第一连接引线的第三亚引线均与所述N型辅助掺杂区连接；所述第一亚有源区位于所述第一连接引线所环绕的空间内；
    所述第九晶体管对应的源极连接线包括分别位于所述第九晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第十一晶体管对应的源极连接线包括分别位于所述第十一晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第九晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第一连接引线的第一亚引线连接；所述第十一晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第一连接引线的第三亚引线连接；所述第九晶体管对应的源极连接线的第二亚连接线和所述第十一晶体管对应的源极连接线的第二亚连接线为同一引线，且沿所述第一方向的相反方向延伸至与所述第一连接引线的第二亚引线连接；
    所述第七连接引线与所述第一连接引线的第一亚引线连接连接；所述第八连接引线与所述第一连接引线的第三亚引线连接；所述第十三连接引线与所述第一连接引线的第二亚引线连接。
  16. 根据权利要求15所述的显示面板，其中，所述第二连接引线包括依次连接的第一亚引线、第三亚引线和第四亚引线，以及包括第二亚引线；其中，所述第二连接引线的第一亚引线、所述第二连接引线的第四亚引线均沿第一方向延伸，且与所述N型辅助掺杂区至少部分交叠；所述第二连接引线的第二亚引线、所述第二连接引线的第三亚引线均沿所述第二方向延伸，且与所述N型辅助掺杂区至少部分交叠；所述第二连接引线的第一亚引线至第四亚引线均与所述N型辅助掺杂区连接；
    所述第二亚有源区位于所述第二连接引线的第一亚引线、所述第二连接引线的第二亚引线和所述第二连接引线的第四亚引线所环绕的空间内，所述第二有源区位于所述第二连接引线的第一亚引线、所述第二连接引线的第二亚引线、所述第二连接引线的第三亚引线和所述第二连接引线的第四亚引线所环绕的空间内；
    所述第十晶体管对应的源极连接线的第一亚连接线沿所述第一方向延伸，且其第一方向的相反方向一侧与所述第二连接引线的第一亚引线连接；所述第十二晶体管对应的源极连接线的第一亚连接线沿所述第一方向延伸，且其第一方向的一侧与所述第 二连接引线的第四亚引线连接；所述第十晶体管对应的源极连接线的第二亚连接线和所述第十二晶体管对应的源极连接线的第二亚连接线为同一引线，且沿所述第一方向延伸。
  17. 根据权利要求16所述的显示面板，其中，所述第五连接引线包括依次连接的第一亚引线、第二亚引线、第三亚引线和第四亚引线，以及包括第五亚引线和第六亚引线；
    所述第五连接引线的第一亚引线、第三亚引线和第六亚引线均沿所述第一方向延伸，且均与所述P型辅助掺杂区至少部分交叠；所述第五连接引线的第六亚引线位于第一亚引线和第三亚引线之间，且两端分别与第五亚引线、第四亚引线连接；
    所述第五连接引线的第二亚引线、第四亚引线、第五亚引线均所述第二方向延伸，且均与所述P型辅助掺杂区至少部分交叠；所述第五连接引线的第五亚引线位于第二亚引线和第四亚引线之间，且两端分别与第一亚引线、第三亚引线连接；所述第五连接引线的第一亚引线至第六亚引线均与所述P型辅助掺杂区连接；
    所述第三有源区位于所述第五连接引线的第一亚引线、第二亚引线、第三亚引线和第五亚引线所环绕的空间内；所述第七亚有源区位于所述第五连接引线的第一亚引线、第五亚引线、第六亚引线和第四亚引线所环绕的空间内；所述第八亚有源区位于所述第五连接引线的第六亚引线、第五亚引线、第三亚引线和第四亚引线所环绕的空间内；
    所述第七晶体管对应的源极连接线包括分别位于所述第七晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第十三晶体管对应的源极连接线包括分别位于所述第十三晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第七晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第五连接引线的第一亚引线连接；所述第十三晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第五连接引线的第三亚引线连接；所述第七晶体管对应的源极连接线的第二亚连接线和所述第十三晶体管对应的源极连接线的第二亚连接线为同一引线，且沿所述第一方向延伸至与所述第五连接引线的第二亚引线连接；
    所述第八晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第五连接引线的第一亚引线连接；所述第十四晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第五连接引线的第三亚引线连接；所述第八晶体管对应的源极连接线的第二亚连接线和所述第十四晶体管对应的源极连接线的第二亚连接线为同一引线；
    所述第一晶体管对应的源极连接线包括分别位于所述第一晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第一晶体管对应的源极连接线的第一亚连接线的第二方向的相反方向一侧与所述第五连接引线的第一亚引线 连接；所述第一晶体管对应的源极连接线的第二亚连接线的第二方向一侧与所述第五连接引线的第六亚引线连接；
    所述第二晶体管对应的源极连接线包括分别位于所述第二晶体管对应的栅极两侧且沿所述第一方向延伸的第一亚连接线和第二亚连接线；所述第二晶体管对应的源极连接线的第一亚连接线的第二方向一侧与所述第五连接引线的第三亚引线连接；所述第二晶体管对应的源极连接线的第二亚连接线的第二方向的相反方向一侧与所述第五连接引线的第六亚引线连接。
  18. 根据权利要求17所述的显示面板，其中，所述第三连接引线、所述第四连接引线和所述第六连接引线位于所述第二连接引线的第一亚引线、所述第二连接引线的第二亚引线、所述第二连接引线的第三亚引线和所述第二连接引线的第四亚引线所环绕的空间内；其中，所述第三连接引线和所述第四连接引线沿所述第二方向延伸，所述第六连接引线沿所述第一方向延伸；
    所述第六晶体管对应的源极连接线的第二方向一侧与所述第六连接引线连接，所述第三晶体管对应的源极连接线的第二方向的相反方向一侧与所述第六连接引线连接；
    所述第五晶体管对应的漏极连接线和所述第六晶体管对应的漏极连接线为同一引线，且一端与所述第四连接引线的一端连接；所述第三晶体管对应的栅极连接线和所述第四晶体管对应的栅极连接线为同一引线，且一端与所述第四连接引线的另一端连接；
    所述第三晶体管对应的漏极连接线和所述第四晶体管对应的漏极连接线为同一引线，且一端与所述第三连接引线的一端连接；所述第五晶体管对应的栅极连接线和所述第六晶体管对应的栅极连接线为同一引线，且一端与所述第三连接引线的另一端连接。
  19. 根据权利要求18所述的显示面板，其中，所述第七连接引线沿所述第一方向延伸，且与所述第一连接引线的第一亚引线、所示第二连接引线的第一亚引线连接；
    所述第八连接引线沿所述第一方向延伸，且与所述第一连接引线的第三亚引线、所述第二连接引线的第四亚引线连接；
    所述第九连接引线沿所述第一方向延伸，且与所述第五连接引线的第一亚引线电连接；
    所述第十连接引线沿所述第一方向延伸，且与所述第五连接引线的第三亚引线连接；
    所述第五晶体管对应的漏极连接线和所述第一晶体管对应的漏极连接线位于同一直线，且延伸轴线在所述半导体衬底上的正投影均与所述第十一连接引线的延伸轴线在所述半导体衬底上的正投影重合；
    所述第三晶体管对应的漏极连接线和所述第二晶体管对应的漏极连接线位于同一直线，且延伸轴线在所述半导体衬底上的正投影均与所述第十二连接引线的延伸轴线 在所述半导体衬底上的正投影重合；
    所述第十三连接引线的延伸轴线在所述半导体衬底上的正投影、所述第九晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第十晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第六连接引的延伸轴线在所述半导体衬底上的正投影重合；
    所述第七晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第八晶体管对应的源极连接线的第二亚连接线的延伸轴线在所述半导体衬底上的正投影、所述第五连接引线的第六亚引线的延伸轴线在所述半导体衬底上的正投影、所述第十四连接引线的延伸轴线在所述半导体衬底上的正投影和所述第十五连接引线的延伸轴线在所述半导体衬底上的正投影重合。
  20. 根据权利要求13所述的显示面板，其中，所述第一电源引线覆盖所述第三有源区和所述第四有源区；所述第二电源引线覆盖所述第一有源区和所述第二有源区。
  21. 根据权利要求8所述的显示面板，其中，所述显示面板在所述显示区还设置有像素驱动电路，所述像素驱动电路包括数据写入单元、存储电容和驱动晶体管；
    所述数据写入单元具有第一控制电极和第二控制电极，所述数据写入单元的第一控制电极与所述第一输出引线连接，所述数据写入单元的第二控制电极与所述第二输出引线连接，所述数据写入单元的输入端与所述显示面板的数据线连接，所述数据写入单元的输出端与第三节点连接；
    所述存储电容的第一电极板连接所述第三节点，所述存储电容的第二电极板用于加载第一驱动电压；
    所述驱动晶体管的控制端连接所述第三节点，所述驱动晶体管的输出端连接所述显示面板的发光元件，所述驱动晶体管的输入端能够加载第二驱动电压。
  22. 根据权利要求21所述的显示面板，其中，所述第一电源引线用于加载所述第一驱动电压；所述第二电源引线用于加载所述第二驱动电压。
  23. 根据权利要求8所述的显示面板，其中，所述显示面板在外围区还设置有与各个所述行驱动信号增强电路一一对应设置的多个移位寄存器和多个反相器；
    在相互对应的所述行驱动信号增强电路、所述移位寄存器和所述反相器中，所述移位寄存器的输出端与所述反相器的输入端、所述行驱动信号增强电路的第一控制引线连接，所述反相器的输出端与所述行驱动信号增强电路的第二控制引线连接。
PCT/CN2021/097403 2021-05-31 2021-05-31 行驱动信号增强电路、移位寄存器单元和显示面板 WO2022252053A1 (zh)

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